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recipes-kernel/linux: Add linux_4.19.76.bb/bbappend

Browse source 
Add the latest linux available
from https://github.com/armbian/build
commit de58ac1faac92724c6449db12c22affaeb003875,
tag: sunxi-5.3, alongside all the patches
that it comes with.

Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
This commit is contained in:
Vicentiu Galanopulo 2019-10-03 18:58:06 +02:00
parent e3c4b204de
commit b167421e55
362 changed files with 1225418 additions and 0 deletions
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55
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0001-clk-sunxi-ng-Set-maximum-M-1-for-H3-pll-cpux-clock.patch Normal file
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@ -0,0 +1,55 @@
From 5b367397da1947fcbf6ed1091c351808218e59bc Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 12 Jan 2017 16:34:57 +0100
Subject: [PATCH 01/82] clk: sunxi-ng: Set maximum M = 1 for H3 pll-cpux clock
When using M factor greater than 1 system is experiencing
occasional lockups.
This change was verified to fix lockups with PLL stress
tester available at https://github.com/megous/h3-firmware.
Note that M factor must not be used outside the kernel
either, so for example u-boot needs a similar patch.
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 77ed0b0ba681..8d47742def49 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -30,15 +30,21 @@
#include "ccu-sun8i-h3.h"
-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
- "osc24M", 0x000,
- 8, 5, /* N */
- 4, 2, /* K */
- 0, 2, /* M */
- 16, 2, /* P */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static struct ccu_nkmp pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT(8, 5),
+ .k = _SUNXI_CCU_MULT(4, 2),
+ .m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
+ .p = _SUNXI_CCU_DIV(16, 2),
+ .common = {
+ .reg = 0x000,
+ .hw.init = CLK_HW_INIT("pll-cpux",
+ "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
--
2.20.1

76
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0002-clk-sunxi-ng-Allow-to-limit-the-use-of-NKMP-clock-s-.patch Normal file
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@ -0,0 +1,76 @@
From 9b15c5248e430f418621414f876170f08ca0a2cd Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 12 Jan 2017 16:37:24 +0100
Subject: [PATCH 02/82] clk: sunxi-ng: Allow to limit the use of NKMP clock's P
factor
Some SoCs mandate the maximum clock rate for which the use
of postdivider P factor is allowed. Allow to configure maximum
clock rate.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 13 ++++++++-----
drivers/clk/sunxi-ng/ccu_nkmp.h | 1 +
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 1ad53d1016a3..080bf4a4ace6 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -33,16 +33,19 @@ static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
}
static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
- struct _ccu_nkmp *nkmp)
+ struct _ccu_nkmp *nkmp, struct ccu_nkmp *_nkmp)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
- unsigned long _n, _k, _m, _p;
+ unsigned long _n, _k, _m, _p, _max_p;
+
+ _max_p = (_nkmp->max_rate_for_p == 0 || rate <= _nkmp->max_rate_for_p) ?
+ nkmp->max_p : nkmp->min_p;
for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) {
- for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
+ for (_p = nkmp->min_p; _p <= _max_p; _p <<= 1) {
unsigned long tmp_rate;
tmp_rate = ccu_nkmp_calc_rate(parent,
@@ -146,7 +149,7 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
- ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
+ ccu_nkmp_find_best(*parent_rate, rate, &_nkmp, nkmp);
rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
_nkmp.m, _nkmp.p);
@@ -177,7 +180,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
- ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
+ ccu_nkmp_find_best(parent_rate, rate, &_nkmp, nkmp);
if (nkmp->n.width)
n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index 6940503e7fc4..bbea3e5ed6fb 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -33,6 +33,7 @@ struct ccu_nkmp {
struct ccu_mult_internal k;
struct ccu_div_internal m;
struct ccu_div_internal p;
+ unsigned long max_rate_for_p;
unsigned int fixed_post_div;
--
2.20.1

29
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0003-clk-sunxi-ng-Limit-pll_cpux-P-factor-for-rates-288MH.patch Normal file
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@ -0,0 +1,29 @@
From d46f1f53618ceffa33a5920802a9247337fd3ff3 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 5 Apr 2017 15:43:48 +0200
Subject: [PATCH 03/82] clk: sunxi-ng: Limit pll_cpux P factor for rates >
288MHz on H3
Datasheet for H3 mandates that CPUX PLL must not use postdivider
(P factor must be 1) for clock rates above 288MHz.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 8d47742def49..7cc9467f373f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -37,6 +37,7 @@ static struct ccu_nkmp pll_cpux_clk = {
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
.p = _SUNXI_CCU_DIV(16, 2),
+ .max_rate_for_p = 288000000,
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux",
--
2.20.1

295
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0004-thermal-sun8i_ths-Add-support-for-the-thermal-sensor.patch Normal file
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@ -0,0 +1,295 @@
From e4092ba9553a4680f2b28334f87e2c97a084f95e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 25 Jun 2016 21:51:05 +0200
Subject: [PATCH 04/82] thermal: sun8i_ths: Add support for the thermal sensor
on Allwinner H3
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds support for the sun8i thermal sensor on
Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman <megous@megous.com>
---
drivers/thermal/Kconfig | 7 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/sun8i_ths.c | 239 ++++++++++++++++++++++++++++++++++++
3 files changed, 247 insertions(+)
create mode 100644 drivers/thermal/sun8i_ths.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 0e69edc77d18..5125c5e8f7ce 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -420,6 +420,13 @@ depends on ARCH_BCM || ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
source "drivers/thermal/broadcom/Kconfig"
endmenu
+config SUN8I_THS
+ tristate "Thermal sensor driver for Allwinner H3"
+ depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+ depends on OF
+ help
+ Enable this to support thermal reporting on some newer Allwinner SoCs.
+
menu "Texas Instruments thermal drivers"
depends on ARCH_HAS_BANDGAP || COMPILE_TEST
depends on HAS_IOMEM
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 610344eb3e03..dc8a24fddba9 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -61,3 +61,4 @@ obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o
+obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o
diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
new file mode 100644
index 000000000000..cfe7d1073b8c
--- /dev/null
+++ b/drivers/thermal/sun8i_ths.c
@@ -0,0 +1,239 @@
+/*
+ * Thermal sensor driver for Allwinner H3 SoC
+ *
+ * Copyright (C) 2016 Ondřej Jirman
+ * Based on the work of Josef Gajdusek <atx@atx.name>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+#include <linux/printk.h>
+
+#define THS_H3_CTRL0 0x00
+#define THS_H3_CTRL2 0x40
+#define THS_H3_INT_CTRL 0x44
+#define THS_H3_STAT 0x48
+#define THS_H3_FILTER 0x70
+#define THS_H3_CDATA 0x74
+#define THS_H3_DATA 0x80
+
+#define THS_H3_CTRL0_SENSOR_ACQ0(x) (x)
+#define THS_H3_CTRL2_SENSE_EN BIT(0)
+#define THS_H3_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
+#define THS_H3_INT_CTRL_DATA_IRQ_EN BIT(8)
+#define THS_H3_INT_CTRL_THERMAL_PER(x) ((x) << 12)
+#define THS_H3_STAT_DATA_IRQ_STS BIT(8)
+#define THS_H3_FILTER_TYPE(x) ((x) << 0)
+#define THS_H3_FILTER_EN BIT(2)
+
+#define THS_H3_CLK_IN 40000000 /* Hz */
+#define THS_H3_DATA_PERIOD 330 /* ms */
+
+#define THS_H3_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
+#define THS_H3_FILTER_DIV (1 << (THS_H3_FILTER_TYPE_VALUE + 1))
+#define THS_H3_INT_CTRL_THERMAL_PER_VALUE \
+ (THS_H3_DATA_PERIOD * (THS_H3_CLK_IN / 1000) / THS_H3_FILTER_DIV / 4096 - 1)
+#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
+#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+
+struct sun8i_ths_data {
+ struct reset_control *reset;
+ struct clk *clk;
+ struct clk *busclk;
+ void __iomem *regs;
+ struct thermal_zone_device *tzd;
+ u32 temp;
+};
+
+static int sun8i_ths_get_temp(void *_data, int *out)
+{
+ struct sun8i_ths_data *data = _data;
+
+ if (data->temp == 0)
+ return -EBUSY;
+
+ /* Formula and parameters from the Allwinner 3.4 kernel */
+ *out = 217000 - (int)((data->temp * 1000000) / 8253);
+ return 0;
+}
+
+static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data)
+{
+ struct sun8i_ths_data *data = _data;
+
+ writel(THS_H3_STAT_DATA_IRQ_STS, data->regs + THS_H3_STAT);
+
+ data->temp = readl(data->regs + THS_H3_DATA);
+ if (data->temp)
+ thermal_zone_device_update(data->tzd, THERMAL_EVENT_TEMP_SAMPLE);
+
+ return IRQ_HANDLED;
+}
+
+static void sun8i_ths_h3_init(struct sun8i_ths_data *data)
+{
+ writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE),
+ data->regs + THS_H3_CTRL0);
+ writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE),
+ data->regs + THS_H3_FILTER);
+ writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) |
+ THS_H3_CTRL2_SENSE_EN,
+ data->regs + THS_H3_CTRL2);
+ writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) |
+ THS_H3_INT_CTRL_DATA_IRQ_EN,
+ data->regs + THS_H3_INT_CTRL);
+}
+
+static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
+ .get_temp = sun8i_ths_get_temp,
+};
+
+static int sun8i_ths_probe(struct platform_device *pdev)
+{
+ struct sun8i_ths_data *data;
+ struct resource *res;
+ int ret;
+ int irq;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no memory resources defined\n");
+ return -EINVAL;
+ }
+
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs)) {
+ ret = PTR_ERR(data->regs);
+ dev_err(&pdev->dev, "failed to ioremap THS registers: %d\n", ret);
+ return ret;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ sun8i_ths_irq_thread, IRQF_ONESHOT,
+ dev_name(&pdev->dev), data);
+ if (ret)
+ return ret;
+
+ data->busclk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(data->busclk)) {
+ ret = PTR_ERR(data->busclk);
+ dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret);
+ return ret;
+ }
+
+ data->clk = devm_clk_get(&pdev->dev, "ths");
+ if (IS_ERR(data->clk)) {
+ ret = PTR_ERR(data->clk);
+ dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret);
+ return ret;
+ }
+
+ data->reset = devm_reset_control_get(&pdev->dev, "ahb");
+ if (IS_ERR(data->reset)) {
+ ret = PTR_ERR(data->reset);
+ dev_err(&pdev->dev, "failed to get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(data->reset);
+ if (ret) {
+ dev_err(&pdev->dev, "reset deassert failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(data->busclk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret);
+ goto err_assert_reset;
+ }
+
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret);
+ goto err_disable_bus;
+ }
+
+ ret = clk_set_rate(data->clk, THS_H3_CLK_IN);
+ if (ret)
+ goto err_disable_ths;
+
+ data->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, data,
+ &sun8i_ths_thermal_ops);
+ if (IS_ERR(data->tzd)) {
+ ret = PTR_ERR(data->tzd);
+ dev_err(&pdev->dev, "failed to register thermal zone: %d\n",
+ ret);
+ goto err_disable_ths;
+ }
+
+ sun8i_ths_h3_init(data);
+
+ platform_set_drvdata(pdev, data);
+ return 0;
+
+err_disable_ths:
+ clk_disable_unprepare(data->clk);
+err_disable_bus:
+ clk_disable_unprepare(data->busclk);
+err_assert_reset:
+ reset_control_assert(data->reset);
+ return ret;
+}
+
+static int sun8i_ths_remove(struct platform_device *pdev)
+{
+ struct sun8i_ths_data *data = platform_get_drvdata(pdev);
+
+ reset_control_assert(data->reset);
+ clk_disable_unprepare(data->clk);
+ clk_disable_unprepare(data->busclk);
+ return 0;
+}
+
+static const struct of_device_id sun8i_ths_id_table[] = {
+ { .compatible = "allwinner,sun8i-h3-ths", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sun8i_ths_id_table);
+
+static struct platform_driver sun8i_ths_driver = {
+ .probe = sun8i_ths_probe,
+ .remove = sun8i_ths_remove,
+ .driver = {
+ .name = "sun8i_ths",
+ .of_match_table = sun8i_ths_id_table,
+ },
+};
+
+module_platform_driver(sun8i_ths_driver);
+
+MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
+MODULE_DESCRIPTION("Thermal sensor driver for Allwinner H3 SoC");
+MODULE_LICENSE("GPL v2");
--
2.20.1

498
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0005-thermal-sun8i-Add-support-for-A83T-thermal-sensors.patch Normal file
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@ -0,0 +1,498 @@
From 9da4c28e6a7963f67e2ca05098683445a1571538 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 17:15:54 +0100
Subject: [PATCH 05/82] thermal: sun8i: Add support for A83T thermal sensors
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/thermal/sun8i_ths.c | 371 ++++++++++++++++++++++++++----------
1 file changed, 274 insertions(+), 97 deletions(-)
diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
index cfe7d1073b8c..2fda940da4cc 100644
--- a/drivers/thermal/sun8i_ths.c
+++ b/drivers/thermal/sun8i_ths.c
@@ -1,5 +1,5 @@
/*
- * Thermal sensor driver for Allwinner H3 SoC
+ * Thermal sensor driver for Allwinner SUN8I SoC
*
* Copyright (C) 2016 Ondřej Jirman
* Based on the work of Josef Gajdusek <atx@atx.name>
@@ -26,79 +26,174 @@
#include <linux/thermal.h>
#include <linux/printk.h>
-#define THS_H3_CTRL0 0x00
-#define THS_H3_CTRL2 0x40
-#define THS_H3_INT_CTRL 0x44
-#define THS_H3_STAT 0x48
-#define THS_H3_FILTER 0x70
-#define THS_H3_CDATA 0x74
-#define THS_H3_DATA 0x80
-
-#define THS_H3_CTRL0_SENSOR_ACQ0(x) (x)
-#define THS_H3_CTRL2_SENSE_EN BIT(0)
-#define THS_H3_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
-#define THS_H3_INT_CTRL_DATA_IRQ_EN BIT(8)
-#define THS_H3_INT_CTRL_THERMAL_PER(x) ((x) << 12)
-#define THS_H3_STAT_DATA_IRQ_STS BIT(8)
-#define THS_H3_FILTER_TYPE(x) ((x) << 0)
-#define THS_H3_FILTER_EN BIT(2)
-
-#define THS_H3_CLK_IN 40000000 /* Hz */
-#define THS_H3_DATA_PERIOD 330 /* ms */
-
-#define THS_H3_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
-#define THS_H3_FILTER_DIV (1 << (THS_H3_FILTER_TYPE_VALUE + 1))
-#define THS_H3_INT_CTRL_THERMAL_PER_VALUE \
- (THS_H3_DATA_PERIOD * (THS_H3_CLK_IN / 1000) / THS_H3_FILTER_DIV / 4096 - 1)
-#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
-#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+#define THS_SUN8I_CTRL0 0x00
+#define THS_SUN8I_CTRL2 0x40
+#define THS_SUN8I_INT_CTRL 0x44
+#define THS_SUN8I_STAT 0x48
+#define THS_SUN8I_FILTER 0x70
+#define THS_SUN8I_CDATA01 0x74
+#define THS_SUN8I_CDATA2 0x78
+#define THS_SUN8I_DATA0 0x80
+#define THS_SUN8I_DATA1 0x84
+#define THS_SUN8I_DATA2 0x88
+
+#define THS_SUN8I_CTRL0_SENSOR_ACQ0(x) (x)
+#define THS_SUN8I_CTRL2_SENSE_EN0 BIT(0)
+#define THS_SUN8I_CTRL2_SENSE_EN1 BIT(1)
+#define THS_SUN8I_CTRL2_SENSE_EN2 BIT(2)
+#define THS_SUN8I_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
+#define THS_SUN8I_INT_CTRL_DATA0_IRQ_EN BIT(8)
+#define THS_SUN8I_INT_CTRL_DATA1_IRQ_EN BIT(9)
+#define THS_SUN8I_INT_CTRL_DATA2_IRQ_EN BIT(10)
+#define THS_SUN8I_INT_CTRL_THERMAL_PER(x) ((x) << 12)
+#define THS_SUN8I_STAT_DATA0_IRQ_STS BIT(8)
+#define THS_SUN8I_STAT_DATA1_IRQ_STS BIT(9)
+#define THS_SUN8I_STAT_DATA2_IRQ_STS BIT(10)
+#define THS_SUN8I_STAT_CLEAR 0x777
+#define THS_SUN8I_FILTER_TYPE(x) ((x) << 0)
+#define THS_SUN8I_FILTER_EN BIT(2)
+
+#define THS_SUN8I_CLK_IN 40000000 /* Hz */
+#define THS_SUN8I_DATA_PERIOD 330 /* ms */
+#define THS_SUN8I_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
+
+//XXX: this formula doesn't work for A83T very well
+//XXX: A83T is getting slower readings out of this (1s interval?)
+//perhaps configure this in sun8i_ths_desc
+#define THS_SUN8I_FILTER_DIV (1 << (THS_SUN8I_FILTER_TYPE_VALUE + 1))
+#define THS_SUN8I_INT_CTRL_THERMAL_PER_VALUE \
+ (THS_SUN8I_DATA_PERIOD * (THS_SUN8I_CLK_IN / 1000) / \
+ THS_SUN8I_FILTER_DIV / 4096 - 1)
+
+#define THS_SUN8I_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
+#define THS_SUN8I_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+
+#define SUN8I_THS_MAX_TZDS 3
+
+struct sun8i_ths_sensor_desc {
+ u32 data_int_en;
+ u32 data_int_flag;
+ u32 data_offset;
+ u32 sense_en;
+};
+
+struct sun8i_ths_desc {
+ int num_sensors;
+ struct sun8i_ths_sensor_desc *sensors;
+ int (*calc_temp)(u32 reg_val);
+ bool has_cal1;
+};
+
+struct sun8i_ths_tzd {
+ struct sun8i_ths_data *data;
+ struct thermal_zone_device *tzd;
+ u32 temp;
+};
struct sun8i_ths_data {
+ struct device *dev;
struct reset_control *reset;
struct clk *clk;
struct clk *busclk;
void __iomem *regs;
- struct thermal_zone_device *tzd;
- u32 temp;
+ void __iomem *cal_regs;
+ struct sun8i_ths_desc *desc;
+ struct sun8i_ths_tzd tzds[SUN8I_THS_MAX_TZDS];
};
+static int sun8i_ths_calc_temp_h3(u32 reg_val)
+{
+ uint64_t temp = (uint64_t)reg_val * 1000000ll;
+
+ do_div(temp, 8253);
+
+ return 217000 - (int)temp;
+}
+
+static int sun8i_ths_calc_temp_a83t(u32 reg_val)
+{
+ uint64_t temp = (uint64_t)reg_val * 1000000ll;
+
+ do_div(temp, 14186);
+
+ return 192000 - (int)temp;
+}
+
static int sun8i_ths_get_temp(void *_data, int *out)
{
- struct sun8i_ths_data *data = _data;
+ struct sun8i_ths_tzd *tzd = _data;
+ struct sun8i_ths_data *data = tzd->data;
- if (data->temp == 0)
+ if (tzd->temp == 0)
return -EBUSY;
- /* Formula and parameters from the Allwinner 3.4 kernel */
- *out = 217000 - (int)((data->temp * 1000000) / 8253);
+ *out = data->desc->calc_temp(tzd->temp);
return 0;
}
static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data)
{
struct sun8i_ths_data *data = _data;
-
- writel(THS_H3_STAT_DATA_IRQ_STS, data->regs + THS_H3_STAT);
-
- data->temp = readl(data->regs + THS_H3_DATA);
- if (data->temp)
- thermal_zone_device_update(data->tzd, THERMAL_EVENT_TEMP_SAMPLE);
+ struct sun8i_ths_tzd *tzd;
+ struct sun8i_ths_sensor_desc *zdesc;
+ int i;
+ u32 status;
+
+ status = readl(data->regs + THS_SUN8I_STAT);
+ writel(THS_SUN8I_STAT_CLEAR, data->regs + THS_SUN8I_STAT);
+
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ tzd = &data->tzds[i];
+ zdesc = &data->desc->sensors[i];
+
+ if (status & zdesc->data_int_flag) {
+ tzd->temp = readl(data->regs + zdesc->data_offset);
+ if (tzd->temp)
+ thermal_zone_device_update(tzd->tzd,
+ THERMAL_EVENT_TEMP_SAMPLE);
+ }
+ }
return IRQ_HANDLED;
}
-static void sun8i_ths_h3_init(struct sun8i_ths_data *data)
+static void sun8i_ths_init(struct sun8i_ths_data *data)
{
- writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE),
- data->regs + THS_H3_CTRL0);
- writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE),
- data->regs + THS_H3_FILTER);
- writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) |
- THS_H3_CTRL2_SENSE_EN,
- data->regs + THS_H3_CTRL2);
- writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) |
- THS_H3_INT_CTRL_DATA_IRQ_EN,
- data->regs + THS_H3_INT_CTRL);
+ int i;
+ u32 int_ctrl = 0;
+ u32 ctrl2 = 0;
+
+ writel(THS_SUN8I_CTRL0_SENSOR_ACQ0(THS_SUN8I_CTRL0_SENSOR_ACQ0_VALUE),
+ data->regs + THS_SUN8I_CTRL0);
+ writel(THS_SUN8I_FILTER_EN | THS_SUN8I_FILTER_TYPE(THS_SUN8I_FILTER_TYPE_VALUE),
+ data->regs + THS_SUN8I_FILTER);
+
+ ctrl2 |= THS_SUN8I_CTRL2_SENSOR_ACQ1(THS_SUN8I_CTRL2_SENSOR_ACQ1_VALUE);
+ int_ctrl |= THS_SUN8I_INT_CTRL_THERMAL_PER(THS_SUN8I_INT_CTRL_THERMAL_PER_VALUE);
+
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ ctrl2 |= data->desc->sensors[i].sense_en;
+ int_ctrl |= data->desc->sensors[i].data_int_en;
+ }
+
+ if (data->cal_regs) {
+ u32 cal0, cal1;
+
+ cal0 = readl(data->cal_regs);
+ if (cal0)
+ writel(cal0, data->regs + THS_SUN8I_CDATA01);
+
+ if (data->desc->has_cal1) {
+ cal1 = readl(data->cal_regs + 4);
+ if (cal1)
+ writel(cal1, data->regs + THS_SUN8I_CDATA2);
+ }
+ }
+
+ writel(ctrl2, data->regs + THS_SUN8I_CTRL2);
+
+ /* enable interrupts */
+ writel(int_ctrl, data->regs + THS_SUN8I_INT_CTRL);
}
static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
@@ -108,100 +203,135 @@ static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
static int sun8i_ths_probe(struct platform_device *pdev)
{
struct sun8i_ths_data *data;
+ struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
- int irq;
+ int ret, irq, i;
- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->desc = (struct sun8i_ths_desc *)of_device_get_match_data(dev);
+ if (data->desc == NULL)
+ return -EINVAL;
+
+ data->dev = dev;
+ platform_set_drvdata(pdev, data);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ths");
if (!res) {
- dev_err(&pdev->dev, "no memory resources defined\n");
+ dev_err(dev, "no memory resources defined\n");
return -EINVAL;
}
- data->regs = devm_ioremap_resource(&pdev->dev, res);
+ data->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(data->regs)) {
ret = PTR_ERR(data->regs);
- dev_err(&pdev->dev, "failed to ioremap THS registers: %d\n", ret);
+ dev_err(dev, "failed to ioremap THS registers: %d\n", ret);
return ret;
}
+ /*XXX: use SRAM device in the future, instead of direct access to regs */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "calibration");
+ if (res) {
+ data->cal_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->cal_regs)) {
+ ret = PTR_ERR(data->cal_regs);
+ dev_err(dev, "failed to ioremap calibration SRAM: %d\n", ret);
+ return ret;
+ }
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
- dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
+ dev_err(dev, "failed to get IRQ: %d\n", irq);
return irq;
}
- ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ ret = devm_request_threaded_irq(dev, irq, NULL,
sun8i_ths_irq_thread, IRQF_ONESHOT,
- dev_name(&pdev->dev), data);
+ dev_name(dev), data);
if (ret)
return ret;
- data->busclk = devm_clk_get(&pdev->dev, "ahb");
+ data->busclk = devm_clk_get(dev, "ahb");
if (IS_ERR(data->busclk)) {
ret = PTR_ERR(data->busclk);
- dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret);
- return ret;
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get ahb clk: %d\n", ret);
+ return ret;
+ }
+
+ data->busclk = NULL;
}
- data->clk = devm_clk_get(&pdev->dev, "ths");
+ data->clk = devm_clk_get(dev, "ths");
if (IS_ERR(data->clk)) {
ret = PTR_ERR(data->clk);
- dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret);
- return ret;
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get ths clk: %d\n", ret);
+ return ret;
+ }
+
+ data->clk = NULL;
}
- data->reset = devm_reset_control_get(&pdev->dev, "ahb");
+ data->reset = devm_reset_control_get_optional(dev, "ahb");
if (IS_ERR(data->reset)) {
ret = PTR_ERR(data->reset);
- dev_err(&pdev->dev, "failed to get reset: %d\n", ret);
+ dev_err(dev, "failed to get reset: %d\n", ret);
return ret;
}
ret = reset_control_deassert(data->reset);
if (ret) {
- dev_err(&pdev->dev, "reset deassert failed: %d\n", ret);
+ dev_err(dev, "reset deassert failed: %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(data->busclk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret);
- goto err_assert_reset;
+ if (data->busclk) {
+ ret = clk_prepare_enable(data->busclk);
+ if (ret) {
+ dev_err(dev, "failed to enable bus clk: %d\n", ret);
+ goto err_assert_reset;
+ }
}
- ret = clk_prepare_enable(data->clk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret);
- goto err_disable_bus;
- }
+ if (data->clk) {
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable ths clk: %d\n", ret);
+ goto err_disable_bus;
+ }
- ret = clk_set_rate(data->clk, THS_H3_CLK_IN);
- if (ret)
- goto err_disable_ths;
-
- data->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, data,
- &sun8i_ths_thermal_ops);
- if (IS_ERR(data->tzd)) {
- ret = PTR_ERR(data->tzd);
- dev_err(&pdev->dev, "failed to register thermal zone: %d\n",
- ret);
- goto err_disable_ths;
+ ret = clk_set_rate(data->clk, THS_SUN8I_CLK_IN);
+ if (ret)
+ goto err_disable_ths;
}
- sun8i_ths_h3_init(data);
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ data->tzds[i].data = data;
+ data->tzds[i].tzd =
+ devm_thermal_zone_of_sensor_register(dev, i,
+ &data->tzds[i],
+ &sun8i_ths_thermal_ops);
+ if (IS_ERR(data->tzds[i].tzd)) {
+ ret = PTR_ERR(data->tzds[i].tzd);
+ dev_err(dev,
+ "failed to register thermal zone: %d\n", ret);
+ goto err_disable_ths;
+ }
+ }
- platform_set_drvdata(pdev, data);
+ sun8i_ths_init(data);
return 0;
err_disable_ths:
- clk_disable_unprepare(data->clk);
+ if (data->clk)
+ clk_disable_unprepare(data->clk);
err_disable_bus:
- clk_disable_unprepare(data->busclk);
+ if (data->busclk)
+ clk_disable_unprepare(data->busclk);
err_assert_reset:
reset_control_assert(data->reset);
return ret;
@@ -212,13 +342,60 @@ static int sun8i_ths_remove(struct platform_device *pdev)
struct sun8i_ths_data *data = platform_get_drvdata(pdev);
reset_control_assert(data->reset);
- clk_disable_unprepare(data->clk);
- clk_disable_unprepare(data->busclk);
+ if (data->clk)
+ clk_disable_unprepare(data->clk);
+ if (data->busclk)
+ clk_disable_unprepare(data->busclk);
return 0;
}
+struct sun8i_ths_sensor_desc sun8i_ths_h3_sensors[] = {
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA0_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA0_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA0,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN0,
+ },
+};
+
+struct sun8i_ths_sensor_desc sun8i_ths_a83t_sensors[] = {
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA0_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA0_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA0,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN0,
+ },
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA1_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA1_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA1,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN1,
+ },
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA2_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA2_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA2,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN2,
+ },
+};
+
+static const struct sun8i_ths_desc sun8i_ths_h3_desc = {
+ .num_sensors = ARRAY_SIZE(sun8i_ths_h3_sensors),
+ .sensors = sun8i_ths_h3_sensors,
+ .calc_temp = sun8i_ths_calc_temp_h3,
+ .has_cal1 = false,
+};
+
+static const struct sun8i_ths_desc sun8i_ths_a83t_desc = {
+ .num_sensors = ARRAY_SIZE(sun8i_ths_a83t_sensors),
+ .sensors = sun8i_ths_a83t_sensors,
+ .calc_temp = sun8i_ths_calc_temp_a83t,
+ .has_cal1 = true,
+};
+
static const struct of_device_id sun8i_ths_id_table[] = {
- { .compatible = "allwinner,sun8i-h3-ths", },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_ths_h3_desc },
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_ths_a83t_desc },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun8i_ths_id_table);
@@ -235,5 +412,5 @@ static struct platform_driver sun8i_ths_driver = {
module_platform_driver(sun8i_ths_driver);
MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
-MODULE_DESCRIPTION("Thermal sensor driver for Allwinner H3 SoC");
+MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SUN8I SoCs");
MODULE_LICENSE("GPL v2");
--
2.20.1

52
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0006-dt-bindings-document-sun8i_ths-H3-thermal-sensor-dri.patch Normal file
View file

@ -0,0 +1,52 @@
From 4e3d17aa91541ce9ad705432e6ef353efabeb06e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 25 Jun 2016 00:02:04 +0200
Subject: [PATCH 06/82] dt-bindings: document sun8i_ths - H3 thermal sensor
driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds the binding documentation for the
sun8i_ths driver. This is a driver for thermal sensor
found in Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman <megous@megous.com>
---
.../devicetree/bindings/thermal/sun8i-ths.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
new file mode 100644
index 000000000000..ba1288165e90
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
@@ -0,0 +1,24 @@
+* Thermal sensor driver for Allwinner H3 SoC
+
+Required properties:
+- compatible : "allwinner,sun8i-h3-ths"
+- reg : Address range of the thermal sensor registers
+- resets : Must contain phandles to reset controls matching the entries
+ of the names
+- reset-names : Must include the name "ahb"
+- clocks : Must contain phandles to clock controls matching the entries
+ of the names
+- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
+ clock
+
+Example:
+ths: ths@01c25000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bus_rst 136>;
+ reset-names = "ahb";
+ clocks = <&bus_gates 72>, <&ths_clk>;
+ clock-names = "ahb", "ths";
+};
--
2.20.1

50
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0007-ARM-dts-sunxi-h3-h5-Add-thermal-sensor-node-to-H3-H5.patch Normal file
View file

@ -0,0 +1,50 @@
From af866a2756362500a2e7a4d0cf600e266b5f5c4c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 26 Feb 2017 16:05:58 +0100
Subject: [PATCH 07/82] ARM: dts: sunxi-h3-h5: Add thermal sensor node to H3/H5
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc6131315c47..13fe5e316136 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -488,6 +488,19 @@
};
};
+ ths: ths@1c25000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>,
+ <0x01c14234 0x4>;
+ reg-names = "ths", "calibration";
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "ahb", "ths";
+ };
+
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
@@ -855,4 +868,12 @@
};
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <330>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 0>;
+ };
+ };
};
--
2.20.1

24
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0008-cpufreq-dt-platdev-Add-allwinner-sun50i-h5-compatibl.patch Normal file
View file

@ -0,0 +1,24 @@
From 1d78fb6bf60b011bd60ebc9d6ef9499f91c29267 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 12:58:43 +0200
Subject: [PATCH 08/82] cpufreq: dt-platdev: Add allwinner,sun50i-h5 compatible
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57de6ca..afb511aa5050 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -29,6 +29,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun8i-a23", },
{ .compatible = "allwinner,sun8i-a83t", },
{ .compatible = "allwinner,sun8i-h3", },
+ { .compatible = "allwinner,sun50i-h5", },
{ .compatible = "apm,xgene-shadowcat", },
--
2.20.1

32
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0009-ARM-dts-sun8i-Increase-max-CPUX-voltage-to-1.4V-on-O.patch Normal file
View file

@ -0,0 +1,32 @@
From 3ef8fd9d164316d26eb99afec111e0431c2f2c69 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 13 May 2018 21:00:43 +0200
Subject: [PATCH 09/82] ARM: dts: sun8i: Increase max CPUX voltage to 1.4V on
Orange Pi PC
When using thermal regulation we can afford to go higher. Also add
regulator-ramp-delay, because regulator takes some time to change
voltage.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 46240334128f..83f1866ed9e7 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -204,7 +204,8 @@
* Use 1.0V as the minimum voltage instead.
*/
regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1300000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <200>;
regulator-boot-on;
regulator-always-on;
};
--
2.20.1

51
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0010-ARM-dts-sun8i-h3-Add-clock-frequency.patch Normal file
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@ -0,0 +1,51 @@
From 0d1194aaf2b2ebc571cf01d2353d252c12146d2e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 27 Jun 2016 16:08:26 +0200
Subject: [PATCH 10/82] ARM: dts: sun8i-h3: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index f0096074a467..cb19ff797606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -78,6 +78,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@1 {
@@ -88,6 +89,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@2 {
@@ -98,6 +100,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@3 {
@@ -108,6 +111,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
};
--
2.20.1

51
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0011-arm64-dts-sun50i-h5-Add-clock-frequency.patch Normal file
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@ -0,0 +1,51 @@
From 6328da39df61f962190870089aaa171a7f8aab2c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 13:04:25 +0200
Subject: [PATCH 11/82] arm64: dts: sun50i-h5: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 62d646baac3c..4452ab873dec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,7 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@1 {
@@ -59,6 +60,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@2 {
@@ -66,6 +68,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@3 {
@@ -73,6 +76,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
};
--
2.20.1

85
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0012-ARM-dts-sunxi-h3-h5-Move-CPU-OPP-table-to-dtsi-share.patch Normal file
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@ -0,0 +1,85 @@
From d4028daf51824eb792fb3c9cc77553ff1edc5d68 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 00:56:50 +0200
Subject: [PATCH 12/82] ARM: dts: sunxi-h3-h5: Move CPU OPP table to dtsi
shared by H3/H5
It is identical for H3 and H5, so it better live there.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 23 -----------------------
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 23 +++++++++++++++++++++++
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index cb19ff797606..261ca0356358 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -43,29 +43,6 @@
#include "sunxi-h3-h5.dtsi"
/ {
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp@816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp@1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000 1200000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 13fe5e316136..539b69fecbe9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -105,6 +105,29 @@
};
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
de: display-engine {
compatible = "allwinner,sun8i-h3-display-engine";
allwinner,pipelines = <&mixer0>;
--
2.20.1

116
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0013-ARM-dts-sunxi-h3-h5-Add-more-CPU-OPP-for-H3-H5.patch Normal file
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@ -0,0 +1,116 @@
From 9e05f3d014b05df39a55dfd6a08d4bd18a301307 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:13:01 +0200
Subject: [PATCH 13/82] ARM: dts: sunxi-h3-h5: Add more CPU OPP for H3/H5
These OPPs can be used with better cooling and/or thermal regulation.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 78 ++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 539b69fecbe9..f47c22b622f9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,24 @@
compatible = "operating-points-v2";
opp-shared;
+ opp@120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1040000 1040000 1300000>;
@@ -121,11 +139,71 @@
clock-latency-ns = <244144>; /* 8 32k periods */
};
+ opp@960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000 1200000 1300000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp@1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1224000000 {
+ opp-hz = /bits/ 64 <1224000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-microvolt = <1400000 1400000 1400000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1368000000 {
+ opp-hz = /bits/ 64 <1368000000>;
+ opp-microvolt = <1400000 1400000 1400000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
};
de: display-engine {
--
2.20.1

86
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0014-ARM-dts-sunxi-h3-h5-Add-thermal-zone-trip-points.patch Normal file
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@ -0,0 +1,86 @@
From 6914945e888f1206df560ff36375e7257ce38970 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:16:06 +0200
Subject: [PATCH 14/82] ARM: dts: sunxi-h3-h5: Add thermal zone trip points
This enables passive cooling by downregulating CPU voltage/frequency.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 +++-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 21 ++++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 261ca0356358..af76a6d250b3 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -54,8 +54,10 @@
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
clock-frequency = <1200000000>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
};
cpu@1 {
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index f47c22b622f9..3b8b2234ab4d 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -975,6 +976,26 @@
polling-delay-passive = <330>;
polling-delay = <1000>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-warm {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-warm-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 4452ab873dec..60fc84a1fb44 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -53,6 +53,9 @@
reg = <0>;
enable-method = "psci";
clock-frequency = <1200000000>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
};
cpu@1 {
--
2.20.1

53
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0015-arm64-dts-sun50i-h5-Enable-cpufreq-dt-on-H5-CPU.patch Normal file
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@ -0,0 +1,53 @@
From 25be6ff78bebfd869a3be0017715f101bd75bb64 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:19:06 +0200
Subject: [PATCH 15/82] arm64: dts: sun50i-h5: Enable cpufreq-dt on H5 CPU
Uses OPPs shared with H3.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 60fc84a1fb44..acd90f390e88 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,9 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
#cooling-cells = <2>;
cooling-min-level = <0>;
@@ -63,6 +66,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
@@ -71,6 +75,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
@@ -79,6 +84,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
};
--
2.20.1

63
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0016-arm64-dts-sun50i-h5-orange-pi-pc2-Setup-CPUX-voltage.patch Normal file
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@ -0,0 +1,63 @@
From 2f3ebd02a475c51f0ee4ac20fd9462f7f8cad314 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 13:01:10 +0200
Subject: [PATCH 16/82] arm64: dts: sun50i-h5-orange-pi-pc2: Setup CPUX voltage
regulator
Orange Pi PC2 features sy8106a regulator just like Orange Pi PC.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 3e0d5a9c096d..af8e3fe26e20 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -124,6 +124,10 @@
};
};
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
&codec {
allwinner,audio-routing =
"Line Out", "LINEOUT",
@@ -219,6 +223,31 @@
};
};
+&r_i2c {
+ status = "okay";
+
+ reg_vdd_cpux: regulator@65 {
+ compatible = "silergy,sy8106a";
+ reg = <0x65>;
+ regulator-name = "vdd-cpux";
+ silergy,fixed-microvolt = <1200000>;
+ /*
+ * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
+ * however both the Armbian DVFS table and the official one
+ * have operating points with voltage under 1.1V, and both
+ * DVFS table are known to work properly at the lowest
+ * operating point.
+ *
+ * Use 1.0V as the minimum voltage instead.
+ */
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <200>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.20.1

127
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0017-Input-edt-ft5x06-Add-support-for-regulator.patch Normal file
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@ -0,0 +1,127 @@
From 997e53ee52efc4a0602bf298125a7c9758abf15c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:08 +0200
Subject: [PATCH 17/82] Input: edt-ft5x06 - Add support for regulator
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add the support of regulator to use it as VCC source.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/input/touchscreen/edt-ft5x06.txt | 1 +
drivers/input/touchscreen/edt-ft5x06.c | 43 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index da2dc5d6c98b..987faeb2fe4a 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -28,6 +28,7 @@ Required properties:
Optional properties:
- reset-gpios: GPIO specification for the RESET input
- wake-gpios: GPIO specification for the WAKE input
+ - vcc-supply: Regulator that supplies the touchscreen
- pinctrl-names: should be "default"
- pinctrl-0: a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..dcde719094f7 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
#include <linux/input/mt.h>
#include <linux/input/touchscreen.h>
#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
#define WORK_REGISTER_THRESHOLD 0x00
#define WORK_REGISTER_REPORT_RATE 0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+ struct regulator *vcc;
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data *tsdata)
}
}
+static void edt_ft5x06_disable_regulator(void *arg)
+{
+ struct edt_ft5x06_ts_data *data = arg;
+
+ regulator_disable(data->vcc);
+}
+
static int edt_ft5x06_ts_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
tsdata->max_support_points = chip_data->max_support_points;
+ tsdata->vcc = devm_regulator_get(&client->dev, "vcc");
+ if (IS_ERR(tsdata->vcc)) {
+ error = PTR_ERR(tsdata->vcc);
+ if (error != -EPROBE_DEFER)
+ dev_err(&client->dev, "failed to request regulator: %d\n",
+ error);
+ return error;
+ }
+
+ error = regulator_enable(tsdata->vcc);
+ if (error < 0) {
+ dev_err(&client->dev, "failed to enable vcc: %d\n",
+ error);
+ return error;
+ }
+
+ error = devm_add_action_or_reset(&client->dev,
+ edt_ft5x06_disable_regulator,
+ tsdata);
+ if (error)
+ return error;
+
tsdata->reset_gpio = devm_gpiod_get_optional(&client->dev,
"reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client *client)
static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+ else
+ regulator_disable(tsdata->vcc);
return 0;
}
@@ -1130,9 +1164,18 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+ int ret;
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+ else {
+ ret = regulator_enable(tsdata->vcc);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable vcc: %d\n", ret);
+ return ret;
+ }
+ }
return 0;
}
--
2.20.1

50
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0018-Input-edt-ft5x06-Set-wake-reset-values-on-resume-sus.patch Normal file
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@ -0,0 +1,50 @@
From 6ff7153330ff8a6c3427e6445e5015620d687c81 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:09 +0200
Subject: [PATCH 18/82] Input: edt-ft5x06 - Set wake/reset values on
resume/suspend
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
drivers/input/touchscreen/edt-ft5x06.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index dcde719094f7..dad2f1f8bf89 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1158,6 +1158,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
else
regulator_disable(tsdata->vcc);
+ if (tsdata->wake_gpio)
+ gpiod_set_value(tsdata->wake_gpio, 0);
+
+ if (tsdata->reset_gpio)
+ gpiod_set_value(tsdata->reset_gpio, 1);
+
return 0;
}
@@ -1177,6 +1183,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
}
}
+ if (tsdata->wake_gpio)
+ gpiod_set_value(tsdata->wake_gpio, 1);
+
+ if (tsdata->reset_gpio)
+ gpiod_set_value(tsdata->reset_gpio, 0);
+
return 0;
}
--
2.20.1

47
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0019-arm-dts-sun8i-a83t-a711-Add-touchscreen-node.patch Normal file
View file

@ -0,0 +1,47 @@
From 0e03253586345216dfb55cdd9b8f038023e0d9bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:10 +0200
Subject: [PATCH 19/82] arm: dts: sun8i: a83t: a711: Add touchscreen node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
};
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&reg_ldo_io0>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

86
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0020-power-supply-axp20x_usb_power-add-function-to-get-ma.patch Normal file
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@ -0,0 +1,86 @@
From 84a6ce439660f26a06219cdf1613f87a6395fdbd Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 14:15:59 +0200
Subject: [PATCH 20/82] power: supply: axp20x_usb_power: add function to get
max current
To prepare for a new PMIC, factor out the code responsible of returning
the maximum current to axp20x_get_current_max.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/power/supply/axp20x_usb_power.c | 51 ++++++++++++++-----------
1 file changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 42001df4bd13..464d4abd3798 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -63,6 +63,34 @@ static irqreturn_t axp20x_usb_power_irq(int irq, void *devid)
return IRQ_HANDLED;
}
+static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
+
+ if (ret)
+ return ret;
+
+ switch (v & AXP20X_VBUS_CLIMIT_MASK) {
+ case AXP20X_VBUC_CLIMIT_100mA:
+ if (power->axp20x_id == AXP221_ID)
+ *val = -1; /* No 100mA limit */
+ else
+ *val = 100000;
+ break;
+ case AXP20X_VBUC_CLIMIT_500mA:
+ *val = 500000;
+ break;
+ case AXP20X_VBUC_CLIMIT_900mA:
+ *val = 900000;
+ break;
+ case AXP20X_VBUC_CLIMIT_NONE:
+ *val = -1;
+ break;
+ }
+ return 0;
+}
+
static int axp20x_usb_power_get_property(struct power_supply *psy,
enum power_supply_property psp, union power_supply_propval *val)
{
@@ -101,28 +129,7 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
val->intval = ret * 1700; /* 1 step = 1.7 mV */
return 0;
case POWER_SUPPLY_PROP_CURRENT_MAX:
- ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
- if (ret)
- return ret;
-
- switch (v & AXP20X_VBUS_CLIMIT_MASK) {
- case AXP20X_VBUC_CLIMIT_100mA:
- if (power->axp20x_id == AXP221_ID)
- val->intval = -1; /* No 100mA limit */
- else
- val->intval = 100000;
- break;
- case AXP20X_VBUC_CLIMIT_500mA:
- val->intval = 500000;
- break;
- case AXP20X_VBUC_CLIMIT_900mA:
- val->intval = 900000;
- break;
- case AXP20X_VBUC_CLIMIT_NONE:
- val->intval = -1;
- break;
- }
- return 0;
+ return axp20x_get_current_max(power, &val->intval);
case POWER_SUPPLY_PROP_CURRENT_NOW:
if (IS_ENABLED(CONFIG_AXP20X_ADC)) {
ret = iio_read_channel_processed(power->vbus_i,
--
2.20.1

135
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0021-power-supply-axp20x_usb_power-add-support-for-AXP813.patch Normal file
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@ -0,0 +1,135 @@
From 5c2f08f5428ed5239b5e90a308e2f77cbc8238b0 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:03:42 +0200
Subject: [PATCH 21/82] power: supply: axp20x_usb_power: add support for AXP813
This adds support for AXP813 PMIC. It is almost the same as AXP22X but
has a different current limit.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/power/supply/axp20x_usb_power.c | 66 ++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 464d4abd3798..4b04fb8f496c 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -40,6 +40,11 @@
#define AXP20X_VBUC_CLIMIT_100mA 2
#define AXP20X_VBUC_CLIMIT_NONE 3
+#define AXP813_VBUC_CLIMIT_900mA 0
+#define AXP813_VBUC_CLIMIT_1500mA 1
+#define AXP813_VBUC_CLIMIT_2000mA 2
+#define AXP813_VBUC_CLIMIT_2500mA 3
+
#define AXP20X_ADC_EN1_VBUS_CURR BIT(2)
#define AXP20X_ADC_EN1_VBUS_VOLT BIT(3)
@@ -63,6 +68,31 @@ static irqreturn_t axp20x_usb_power_irq(int irq, void *devid)
return IRQ_HANDLED;
}
+static int axp813_get_current_max(struct axp20x_usb_power *power, int *val)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
+
+ if (ret)
+ return ret;
+
+ switch (v & AXP20X_VBUS_CLIMIT_MASK) {
+ case AXP813_VBUC_CLIMIT_900mA:
+ *val = 900000;
+ break;
+ case AXP813_VBUC_CLIMIT_1500mA:
+ *val = 1500000;
+ break;
+ case AXP813_VBUC_CLIMIT_2000mA:
+ *val = 2000000;
+ break;
+ case AXP813_VBUC_CLIMIT_2500mA:
+ *val = 2500000;
+ break;
+ }
+ return 0;
+}
+
static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
{
unsigned int v;
@@ -129,6 +159,8 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
val->intval = ret * 1700; /* 1 step = 1.7 mV */
return 0;
case POWER_SUPPLY_PROP_CURRENT_MAX:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_get_current_max(power, &val->intval);
return axp20x_get_current_max(power, &val->intval);
case POWER_SUPPLY_PROP_CURRENT_NOW:
if (IS_ENABLED(CONFIG_AXP20X_ADC)) {
@@ -220,6 +252,31 @@ static int axp20x_usb_power_set_voltage_min(struct axp20x_usb_power *power,
return -EINVAL;
}
+static int axp813_usb_power_set_current_max(struct axp20x_usb_power *power,
+ int intval)
+{
+ int val;
+
+ switch (intval) {
+ case 900000:
+ return regmap_update_bits(power->regmap,
+ AXP20X_VBUS_IPSOUT_MGMT,
+ AXP20X_VBUS_CLIMIT_MASK,
+ AXP813_VBUC_CLIMIT_900mA);
+ case 1500000:
+ case 2000000:
+ case 2500000:
+ val = (intval - 1000000) / 500000;
+ return regmap_update_bits(power->regmap,
+ AXP20X_VBUS_IPSOUT_MGMT,
+ AXP20X_VBUS_CLIMIT_MASK, val);
+ default:
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
static int axp20x_usb_power_set_current_max(struct axp20x_usb_power *power,
int intval)
{
@@ -254,6 +311,9 @@ static int axp20x_usb_power_set_property(struct power_supply *psy,
return axp20x_usb_power_set_voltage_min(power, val->intval);
case POWER_SUPPLY_PROP_CURRENT_MAX:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_set_current_max(power,
+ val->intval);
return axp20x_usb_power_set_current_max(power, val->intval);
default:
@@ -388,7 +448,8 @@ static int axp20x_usb_power_probe(struct platform_device *pdev)
usb_power_desc = &axp20x_usb_power_desc;
irq_names = axp20x_irq_names;
} else if (power->axp20x_id == AXP221_ID ||
- power->axp20x_id == AXP223_ID) {
+ power->axp20x_id == AXP223_ID ||
+ power->axp20x_id == AXP813_ID) {
usb_power_desc = &axp22x_usb_power_desc;
irq_names = axp22x_irq_names;
} else {
@@ -434,6 +495,9 @@ static const struct of_device_id axp20x_usb_power_match[] = {
}, {
.compatible = "x-powers,axp223-usb-power-supply",
.data = (void *)AXP223_ID,
+ }, {
+ .compatible = "x-powers,axp813-usb-power-supply",
+ .data = (void *)AXP813_ID,
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, axp20x_usb_power_match);
--
2.20.1

26
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0022-ARM-dtsi-axp813-add-USB-power-supply-node.patch Normal file
View file

@ -0,0 +1,26 @@
From 8d81c934be105c53309f66057cabaf5cb496aec7 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:06:28 +0200
Subject: [PATCH 22/82] ARM: dtsi: axp813: add USB power supply node
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
arch/arm/boot/dts/axp81x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index 043c717dcef1..f32a8ba53b85 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -166,4 +166,8 @@
status = "disabled";
};
};
+
+ usb_power_supply: usb-power-supply {
+ compatible = "x-powers,axp813-usb-power-supply";
+ };
};
--
2.20.1

27
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0023-mfd-axp20x-add-USB-power-supply-mfd-cell-to-AXP813.patch Normal file
View file

@ -0,0 +1,27 @@
From 95a44a737d3a50a67eabad266aeb7b8d763ef5d2 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:07:14 +0200
Subject: [PATCH 23/82] mfd: axp20x: add USB power supply mfd cell to AXP813
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/mfd/axp20x.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index f8e0fa97bb31..ac8da970bdfe 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -787,6 +787,9 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp813-battery-power-supply",
+ }, {
+ .name = "axp20x-usb-power-supply",
+ .of_compatible = "x-powers,axp813-usb-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
--
2.20.1

54
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0024-mfd-axp20x-add-regulator-userspace-consumer-to-mfd-c.patch Normal file
View file

@ -0,0 +1,54 @@
From b77e60c6a2797ada240b1d42b896b70853e2b1af Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Thu, 10 Aug 2017 09:40:21 +0200
Subject: [PATCH 24/82] mfd: axp20x: add regulator-userspace-consumer to mfd
cells of AXP813
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/mfd/axp20x.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index ac8da970bdfe..95f36a7e3cd4 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -24,6 +24,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include <linux/regulator/userspace-consumer.h>
#include <linux/mfd/axp20x.h>
#include <linux/mfd/core.h>
#include <linux/of_device.h>
@@ -771,6 +772,16 @@ static const struct mfd_cell axp809_cells[] = {
},
};
+static struct regulator_bulk_data vcc_vb = {
+ .supply = "vcc-vb",
+};
+
+static struct regulator_userspace_consumer_data vcc_vb_data = {
+ .name = "vcc-vb",
+ .num_supplies = 1,
+ .supplies = &vcc_vb,
+};
+
static const struct mfd_cell axp813_cells[] = {
{
.name = "axp221-pek",
@@ -790,6 +801,10 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp813-usb-power-supply",
+ }, {
+ .name = "reg-userspace-consumer",
+ .platform_data = &vcc_vb_data,
+ .pdata_size = sizeof(vcc_vb_data),
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
--
2.20.1

188
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0025-power-supply-axp20x-usb-power-Support-input-current-.patch Normal file
View file

@ -0,0 +1,188 @@
From 49675ccdafd63d0eee2fb0a57bd39fcb07a83bae Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 02:09:43 +0100
Subject: [PATCH 25/82] power: supply: axp20x-usb-power: Support input current
limit
Allow to set input current limit directly when autodetection fails
on incorrectly wired tablets, like TBS A711, that don't have
D+/D- pins connected, and can't detect the usb power supply type.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/power/supply/axp20x_usb_power.c | 104 +++++++++++++++++++++++-
include/linux/mfd/axp20x.h | 1 +
2 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 4b04fb8f496c..3bc2e1f7ab83 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -49,6 +49,8 @@
#define AXP20X_ADC_EN1_VBUS_VOLT BIT(3)
#define AXP20X_VBUS_MON_VBUS_VALID BIT(3)
+#define AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK GENMASK(7, 4)
+#define AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET 4
struct axp20x_usb_power {
struct device_node *np;
@@ -93,6 +95,50 @@ static int axp813_get_current_max(struct axp20x_usb_power *power, int *val)
return 0;
}
+static int
+axp813_usb_power_get_input_current_limit(struct axp20x_usb_power *power,
+ int *intval)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP813_CHRG_CTRL3, &v);
+
+ if (ret)
+ return ret;
+
+ v &= AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK;
+ v >>= AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET;
+
+ switch (v) {
+ case 0:
+ *intval = 100000;
+ return 0;
+ case 1:
+ *intval = 500000;
+ return 0;
+ case 2:
+ *intval = 900000;
+ return 0;
+ case 3:
+ *intval = 1500000;
+ return 0;
+ case 4:
+ *intval = 2000000;
+ return 0;
+ case 5:
+ *intval = 2500000;
+ return 0;
+ case 6:
+ *intval = 3000000;
+ return 0;
+ case 7:
+ *intval = 3500000;
+ return 0;
+ default:
+ *intval = 4000000;
+ return 0;
+ }
+}
+
static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
{
unsigned int v;
@@ -219,6 +265,11 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_ONLINE:
val->intval = !!(input & AXP20X_PWR_STATUS_VBUS_USED);
break;
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_get_input_current_limit(power,
+ &val->intval);
+ /* fallthrough */
default:
return -EINVAL;
}
@@ -252,6 +303,50 @@ static int axp20x_usb_power_set_voltage_min(struct axp20x_usb_power *power,
return -EINVAL;
}
+static int
+axp813_usb_power_set_input_current_limit(struct axp20x_usb_power *power,
+ int intval)
+{
+ unsigned int reg;
+
+ switch (intval) {
+ case 100000:
+ reg = 0;
+ break;
+ case 500000:
+ reg = 1;
+ break;
+ case 900000:
+ reg = 2;
+ break;
+ case 1500000:
+ reg = 3;
+ break;
+ case 2000000:
+ reg = 4;
+ break;
+ case 2500000:
+ reg = 5;
+ break;
+ case 3000000:
+ reg = 6;
+ break;
+ case 3500000:
+ reg = 7;
+ break;
+ case 4000000:
+ reg = 8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(power->regmap,
+ AXP813_CHRG_CTRL3,
+ AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK,
+ reg << AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET);
+}
+
static int axp813_usb_power_set_current_max(struct axp20x_usb_power *power,
int intval)
{
@@ -316,6 +411,11 @@ static int axp20x_usb_power_set_property(struct power_supply *psy,
val->intval);
return axp20x_usb_power_set_current_max(power, val->intval);
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_set_input_current_limit(power,
+ val->intval);
+ /* fallthrough */
default:
return -EINVAL;
}
@@ -327,7 +427,8 @@ static int axp20x_usb_power_prop_writeable(struct power_supply *psy,
enum power_supply_property psp)
{
return psp == POWER_SUPPLY_PROP_VOLTAGE_MIN ||
- psp == POWER_SUPPLY_PROP_CURRENT_MAX;
+ psp == POWER_SUPPLY_PROP_CURRENT_MAX ||
+ psp == POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT;
}
static enum power_supply_property axp20x_usb_power_properties[] = {
@@ -346,6 +447,7 @@ static enum power_supply_property axp22x_usb_power_properties[] = {
POWER_SUPPLY_PROP_ONLINE,
POWER_SUPPLY_PROP_VOLTAGE_MIN,
POWER_SUPPLY_PROP_CURRENT_MAX,
+ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
};
static const struct power_supply_desc axp20x_usb_power_desc = {
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 517e60eecbcb..1c968a2e31f7 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -133,6 +133,7 @@ enum axp20x_variants {
/* Other DCDC regulator control registers are the same as AXP803 */
#define AXP813_DCDC7_V_OUT 0x26
+#define AXP813_CHRG_CTRL3 0x35
/* Interrupt */
#define AXP152_IRQ1_EN 0x40
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0026-mfd-axp20x-Make-AXP22X_CHRG_CTRL3-because-it-is-upda.patch Normal file
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@ -0,0 +1,28 @@
From 22b15d77f99612906a02c96b9b926233d187605f Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 16 Nov 2017 00:30:19 +0100
Subject: [PATCH 26/82] mfd: axp20x: Make AXP22X_CHRG_CTRL3 because it is
updated by charger det.
Charger detection updates this to reflect allowed current.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/mfd/axp20x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 95f36a7e3cd4..81bf6ee4d8bb 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -131,6 +131,7 @@ static const struct regmap_range axp288_volatile_ranges[] = {
regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
+ regmap_reg_range(AXP22X_CHRG_CTRL3, AXP22X_CHRG_CTRL3),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
--
2.20.1

37
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0027-arm-dts-sun8i-a83t-a711-update-brightness-levels-to-.patch Normal file
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@ -0,0 +1,37 @@
From 5e76e10095d6370a3c7235543acda9b4f256d246 Mon Sep 17 00:00:00 2001
From: Tomas Novotny <tomas@novotny.cz>
Date: Tue, 24 Oct 2017 15:07:42 +0200
Subject: [PATCH 27/82] arm: dts: sun8i: a83t: a711: update brightness levels
to fit the device
The function is exponential with base of 1.32 and some offset and
tweaks. The lowest values produce no output, so we are starting at 8.
The default brigtness is a bit lower than maximum to boot with reduced
backlight.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index dc7b94a6c068..bd7e231e3aba 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -65,8 +65,11 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
- brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
- default-brightness-level = <9>;
+ brightness-levels = <0 8 9 10 11 13 15 17 19 21 23 25 28
+ 31 34 37 40 44 48 52 56 61 67 72 78
+ 84 91 98 106 115 124 133 143 154
+ 166 179 192 207 223 239 255>;
+ default-brightness-level = <39>;
};
panel {
--
2.20.1

2406
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0028-media-sun6i-csi-Add-support-for-Allwinner-CSI.patch Normal file
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30
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0029-MAINTAINERS-Add-entry-for-Himax-HM5065.patch Normal file
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@ -0,0 +1,30 @@
From 143f5c46be05234ca2618eb4515b9b1d2f329770 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 21:31:35 +0200
Subject: [PATCH 29/82] MAINTAINERS: Add entry for Himax HM5065
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 11a59e82d92e..93f4ff7d6eba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6611,6 +6611,12 @@ S: Supported
F: Documentation/scsi/hptiop.txt
F: drivers/scsi/hptiop.c
+HIMAX HM5065 SENSOR DRIVER
+M: Ondrej Jirman <kernel@xff.cz>
+L: linux-media@vger.kernel.org
+S: Supported
+F: drivers/media/i2c/hm5065.c
+
HIPPI
M: Jes Sorensen <jes@trained-monkey.org>
L: linux-hippi@sunsite.dk
--
2.20.1

71
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@ -0,0 +1,71 @@
From 086f56910cfcc26939c56dfd143c7ee3dc24cff1 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:30:39 +0200
Subject: [PATCH 30/82] media: dt-bindings: Add bindings for Himax HM5065
camera sensor
HM5065 is 5MP CMOS sensor...
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../devicetree/bindings/media/i2c/hm5065.txt | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.txt
diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.txt b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
new file mode 100644
index 000000000000..68ad7f529e18
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
@@ -0,0 +1,48 @@
+* Himax HM5065 CSI camera sensor
+
+Required Properties:
+- compatible: should be "himax,hm5065"
+- clocks: reference to the external input clock for the sensor.
+- clock-names: should be "xclk".
+- IOVDD-supply: Digital I/O voltage supply, 2.8 volts
+- AVDD-supply: Analog voltage supply, 2.8 volts
+- DVDD-supply: Digital core voltage supply, 1.8 volts
+- AFVDD-supply: Auto focus voltage supply, 2.8 volts
+
+Optional Properties (one or both must be configured):
+- reset-gpios: reference to the GPIO connected to the reset pin, if any.
+ This is an active low signal to the HM5065.
+- chipenable-gpios: reference to the GPIO connected to the CE pin,
+ if any. This is an active high signal to the HM5065.
+
+The device node must contain one 'port' child node for its digital output
+video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+&i2c1 {
+ hm5065: camera@1f {
+ compatible = "himax,hm5065";
+ reg = <0x1f>;
+ clocks = <&ccu CLK_CSI_MCLK>;
+ clock-names = "xclk";
+ IOVDD-supply = <&reg_dldo3>;
+ AVDD-supply = <&reg_dldo4>;
+ DVDD-supply = <&reg_eldo3>;
+ AFVDD-supply = <&reg_dldo3>;
+ reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
+ chipenable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
+
+ port {
+ hm5065_ep: endpoint {
+ remote-endpoint = <&csi0_hm5065_ep>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+};
--
2.20.1

53
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0031-ARM-dts-sun8i-a83t-Add-CSI0-node-for-cmos-sensor-int.patch Normal file
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@ -0,0 +1,53 @@
From 7fe79d7ef105939f10903d87c44b8ea4da3bc4ae Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:46:55 +0200
Subject: [PATCH 31/82] ARM: dts: sun8i-a83t: Add CSI0 node for cmos sensor
interface driver
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 00a02b037320..66f035ead79a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -636,6 +636,20 @@
#reset-cells = <1>;
};
+ csi0: csi@01cb0000 {
+ compatible = "allwinner,sun8i-a83t-csi";
+ reg = <0x01cb0000 0x1000>; /* manual says 0x40000 size */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
@@ -649,6 +663,13 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ csi0_pins: csi0-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE10", "PE11", "PE12", "PE13";
+ function = "csi";
+ };
+
emac_rgmii_pins: emac-rgmii-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD11", "PD12", "PD13", "PD14", "PD18",
--
2.20.1

38
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0032-ARM-dts-sun8i-a83t-tbs-a711-Force-dvdd-csi-r-f-regul.patch Normal file
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@ -0,0 +1,38 @@
From ac8826aeb1f157a76b1f1d31b13eb557d3f96108 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:53:26 +0200
Subject: [PATCH 32/82] ARM: dts: sun8i-a83t-tbs-a711: Force dvdd-csi-r/f
regulators to 1.8V
This is required by camera sensors that are connected to them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index bd7e231e3aba..7936405862c1 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -353,7 +353,7 @@
};
&reg_eldo1 {
- regulator-min-microvolt = <1200000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-r";
};
@@ -365,7 +365,7 @@
};
&reg_eldo3 {
- regulator-min-microvolt = <1200000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-f";
};
--
2.20.1

42
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0033-ARM-dts-sun8i-a83t-tbs-a711-Use-i2c-gpio-to-communic.patch Normal file
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@ -0,0 +1,42 @@
From 0ba507d286fc521e71ba048d81c7d1d751012bb8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:51:09 +0200
Subject: [PATCH 33/82] ARM: dts: sun8i-a83t-tbs-a711: Use i2c-gpio to
communicate with cameras
Camera sensors are connected via I2C to PE14/PE15 pins on A83T.
Unfortunately while the A83T datasheet suggests TWI2 I2C controller
can be configured to have SDA/SCL on these pins, this configuration
doesn't work in reality. We need to either use CCI I2C controller
that is part of the CSI module, or as is done in this patch, use GPIO
based bitbanging I2C driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 7936405862c1..8a0a8d39eb21 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -72,6 +72,16 @@
default-brightness-level = <39>;
};
+ i2c_gpio: i2c-gpio {
+ compatible = "i2c-gpio";
+ /* PE15 = sda, PE14 = scl */
+ sda-gpios = <&pio 4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pio 4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <1>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
panel {
compatible = "tbs,a711-panel", "panel-lvds";
backlight = <&backlight>;
--
2.20.1

79
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0034-ARM-dts-sun8i-a83t-tbs-a711-Add-rear-camera-sensor-H.patch Normal file
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@ -0,0 +1,79 @@
From 5436d28adbf6268496e20b4c43c43a59f597c340 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 10 Oct 2017 05:26:49 +0200
Subject: [PATCH 34/82] ARM: dts: sun8i-a83t-tbs-a711: Add rear camera sensor
(HM5065)
Sensor is connected via parallel bus to CSI0 and via I2C bus to
PE14/PE15 pins. Enable CSI0 module and add the node for HM5065
camera sensor.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 43 +++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 8a0a8d39eb21..9a87ce651224 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -149,6 +149,23 @@
cpu-supply = <&reg_dcdc3>;
};
+&csi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi0_pins>;
+
+ port {
+ csi0_hm5065_ep: endpoint {
+ remote-endpoint = <&hm5065_ep>;
+ bus-width = <8>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+};
+
&de {
status = "okay";
};
@@ -185,6 +202,32 @@
};
};
+&i2c_gpio {
+ hm5065: camera@1f {
+ compatible = "himax,hm5065";
+ reg = <0x1f>;
+ clocks = <&ccu CLK_CSI_MCLK>;
+ clock-names = "xclk";
+ IOVDD-supply = <&reg_dldo3>;
+ AVDD-supply = <&reg_dldo4>;
+ DVDD-supply = <&reg_eldo3>;
+ AFVDD-supply = <&reg_dldo3>;
+ reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
+ chipenable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
+
+ port {
+ hm5065_ep: endpoint {
+ remote-endpoint = <&csi0_hm5065_ep>;
+ bus-width = <8>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0035-ARM-dts-sun8i-a83t-tbs-a711-Reduce-camera-IOVDD-volt.patch Normal file
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@ -0,0 +1,28 @@
From 0f0c62c90fc072355b2118d118715492710b8735 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 8 Nov 2017 04:55:15 +0100
Subject: [PATCH 35/82] ARM: dts: sun8i-a83t-tbs-a711: Reduce camera IOVDD
voltage
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 9a87ce651224..1a711a28f682 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -389,8 +389,8 @@
};
&reg_dldo3 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
regulator-name = "vdd-csi";
};
--
2.20.1

32
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0036-ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch Normal file
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@ -0,0 +1,32 @@
From acfec807289ebf7c2af8aaf75aaa67159d549734 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 8 Nov 2017 21:57:45 +0100
Subject: [PATCH 36/82] ARM: dts: sun8i-a83t-tbs-a711: Add flash led support
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1a711a28f682..c8278e173f50 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -60,6 +60,15 @@
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ flash_led {
+ label = "flash";
+ gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
--
2.20.1

2380
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0037-media-hm5065-Add-subdev-driver-for-Himax-HM5065-came.patch Normal file
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34
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0038-arm-dts-sun8i-a83t-a711-Enable-I2C1.patch Normal file
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@ -0,0 +1,34 @@
From dd149592ded2be2ebbe64ee83bcb34054470cf07 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 9 Nov 2017 23:05:13 +0100
Subject: [PATCH 38/82] arm: dts: sun8i: a83t: a711: Enable I2C1
The A711 has some sensors connected to I2C1. Enable only the bus for the
moment.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index c8278e173f50..8e9f0de3d0c0 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -237,6 +237,13 @@
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

35
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0039-ARM-dts-sun8i-a83t-tbs-a711-Enable-BMA250-accelerome.patch Normal file
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@ -0,0 +1,35 @@
From 69c8e0651bb68ab80b0fc4033b8ca5e87b8bb164 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:20:43 +0100
Subject: [PATCH 39/82] ARM: dts: sun8i-a83t-tbs-a711: Enable BMA250
accelerometer IIO
It's already supported in mainline kernel.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 8e9f0de3d0c0..2427bf3461d7 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -242,6 +242,14 @@
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ };
};
&mmc0 {
--
2.20.1

36
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0040-ARM-dts-sun8i-a83t-tbs-a711-Enable-LTR-501-ALS-IIO.patch Normal file
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@ -0,0 +1,36 @@
From 113d3049c946e68e32fdec6f64672fe4cd181cc8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:21:55 +0100
Subject: [PATCH 40/82] ARM: dts: sun8i-a83t-tbs-a711: Enable LTR-501-ALS IIO
It's already supported in mainline kernel. Though, the driver didn't
have OF compativles table.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 2427bf3461d7..6acc678d1b5b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -250,6 +250,15 @@
interrupt-parent = <&pio>;
interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
};
+
+ /* Light Sensor */
+ ltr501: ltr501@23 {
+ status = "disabled"; /* no output */
+ compatible = "ltr,ltr501";
+ reg = <0x23>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 12 IRQ_TYPE_EDGE_FALLING>; /* PG12 */
+ };
};
&mmc0 {
--
2.20.1

68
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0041-iio-ltr501-Add-OF-compatibles.patch Normal file
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@ -0,0 +1,68 @@
From e4548a8a5ad34919a94b282369212b661e1d4382 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:23:01 +0100
Subject: [PATCH 41/82] iio: ltr501: Add OF compatibles
So that driver can be configured from DTS.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/iio/light/ltr501.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/light/ltr501.c b/drivers/iio/light/ltr501.c
index 830a2d45aa4d..bdb296dcb7c0 100644
--- a/drivers/iio/light/ltr501.c
+++ b/drivers/iio/light/ltr501.c
@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/acpi.h>
+#include <linux/of.h>
#include <linux/iio/iio.h>
#include <linux/iio/events.h>
@@ -1558,6 +1559,7 @@ static int ltr501_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(ltr501_pm_ops, ltr501_suspend, ltr501_resume);
+#ifdef CONFIG_ACPI
static const struct acpi_device_id ltr_acpi_match[] = {
{"LTER0501", ltr501},
{"LTER0559", ltr559},
@@ -1565,6 +1567,7 @@ static const struct acpi_device_id ltr_acpi_match[] = {
{ },
};
MODULE_DEVICE_TABLE(acpi, ltr_acpi_match);
+#endif
static const struct i2c_device_id ltr501_id[] = {
{ "ltr501", ltr501},
@@ -1574,11 +1577,22 @@ static const struct i2c_device_id ltr501_id[] = {
};
MODULE_DEVICE_TABLE(i2c, ltr501_id);
+#ifdef CONFIG_OF
+static const struct of_device_id ltr501_of_match[] = {
+ { .compatible = "ltr,ltr501", .data = (void*)ltr501 },
+ { .compatible = "ltr,ltr559", .data = (void*)ltr559 },
+ { .compatible = "ltr,ltr301", .data = (void*)ltr301 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ltr501_of_match);
+#endif
+
static struct i2c_driver ltr501_driver = {
.driver = {
- .name = LTR501_DRV_NAME,
- .pm = &ltr501_pm_ops,
+ .name = LTR501_DRV_NAME,
+ .pm = &ltr501_pm_ops,
.acpi_match_table = ACPI_PTR(ltr_acpi_match),
+ .of_match_table = of_match_ptr(ltr501_of_match)
},
.probe = ltr501_probe,
.remove = ltr501_remove,
--
2.20.1

46
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0042-ARM-dts-sun8i-a83t-tbs-a711-Enable-AK8963-magnetomet.patch Normal file
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@ -0,0 +1,46 @@
From 2a3460a07d4ef36bd754c83dce9b6b7ea9844aa3 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:24:58 +0100
Subject: [PATCH 42/82] ARM: dts: sun8i-a83t-tbs-a711: Enable AK8963
magnetometer
Though the chip is probably broken on my tablet. It doesn't respond
on I2C 0x0d address.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 6acc678d1b5b..ec986498114e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -251,6 +251,24 @@
interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
};
+ /* Magnetic Sensor */
+ ak8963: ak8963@0d {
+ status = "disabled"; /* broken */
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ interrupt-parent = <&pio>;
+ interrupts = <1 2 IRQ_TYPE_EDGE_RISING>; /* PB2 */
+ mount-matrix = /* x0 */ "-0.984807753012208",
+ /* y0 */ "0",
+ /* z0 */ "-0.173648177666930",
+ /* x1 */ "0",
+ /* y1 */ "-1",
+ /* z1 */ "0",
+ /* x2 */ "-0.173648177666930",
+ /* y2 */ "0",
+ /* z2 */ "0.984807753012208";
+ };
+
/* Light Sensor */
ltr501: ltr501@23 {
status = "disabled"; /* no output */
--
2.20.1

107
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0043-nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch Normal file
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@ -0,0 +1,107 @@
From 8df4a460c0459b0ba6a20634adc4ecb60b8e89d5 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 14:29:26 +0100
Subject: [PATCH 43/82] nfc: pn544: Add support for VBAT/PVDD regulators
Regulators are required, so this can't go into mainline as is.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/nfc/pn544/i2c.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/nfc/pn544/i2c.c b/drivers/nfc/pn544/i2c.c
index d0207f8e68b7..5d0a20d3f9c8 100644
--- a/drivers/nfc/pn544/i2c.c
+++ b/drivers/nfc/pn544/i2c.c
@@ -27,6 +27,7 @@
#include <linux/nfc.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>
@@ -70,6 +71,14 @@ MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
#define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
+/* regulator supplies */
+static const char * const pn544_supply_names[] = {
+ "PVDD", /* Digital Core (1.8V) supply */
+ "VBAT", /* Analog (2.9V-5.5V) supply */
+};
+
+#define PN544_NUM_SUPPLIES ARRAY_SIZE(pn544_supply_names)
+
/*
* Exposed through the 4 most significant bytes
* from the HCI SW_VERSION first byte, a.k.a.
@@ -161,6 +170,7 @@ struct pn544_i2c_phy {
struct i2c_client *i2c_dev;
struct nfc_hci_dev *hdev;
+ struct regulator_bulk_data supplies[PN544_NUM_SUPPLIES];
struct gpio_desc *gpiod_en;
struct gpio_desc *gpiod_fw;
@@ -250,9 +260,14 @@ static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
static int pn544_hci_i2c_enable(void *phy_id)
{
struct pn544_i2c_phy *phy = phy_id;
+ int ret;
pr_info("%s\n", __func__);
+ ret = regulator_bulk_enable(PN544_NUM_SUPPLIES, phy->supplies);
+ if (ret)
+ return ret;
+
pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
phy->powered = 1;
@@ -274,6 +289,8 @@ static void pn544_hci_i2c_disable(void *phy_id)
gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
usleep_range(10000, 15000);
+ regulator_bulk_disable(PN544_NUM_SUPPLIES, phy->supplies);
+
phy->powered = 0;
}
@@ -380,7 +397,7 @@ static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
(len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
- nfc_err(&client->dev, "invalid len byte\n");
+ nfc_err(&client->dev, "invalid len byte %hhx\n", len);
r = -EBADMSG;
goto flush;
}
@@ -883,7 +900,7 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
{
struct device *dev = &client->dev;
struct pn544_i2c_phy *phy;
- int r = 0;
+ int r = 0, i;
dev_dbg(&client->dev, "%s\n", __func__);
dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
@@ -908,6 +925,14 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
if (r)
dev_dbg(dev, "Unable to add GPIO mapping table\n");
+ for (i = 0; i < PN544_NUM_SUPPLIES; i++)
+ phy->supplies[i].supply = pn544_supply_names[i];
+
+ r = devm_regulator_bulk_get(&client->dev, PN544_NUM_SUPPLIES,
+ phy->supplies);
+ if (r)
+ return r;
+
/* Get EN GPIO */
phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(phy->gpiod_en)) {
--
2.20.1

66
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0044-ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch Normal file
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@ -0,0 +1,66 @@
From 69eafa62d60b993ba9500f56af568357b16b1504 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 14:33:28 +0100
Subject: [PATCH 44/82] ARM: dts: sun8i-a83t-tbs-a711: Add PN544 NFC support
Regulators on the schematic are named incorrectly. Both cameras are
is in fact connected to the dvdd-csi-f regulator and dvdd-csi-r is
in reality used for digital pad supply for NFC chip.
At the same time vcc-mipi regulator is not used for MIPI, but for NFC
VBAT power.
Interpreting schematics is an art form! :D
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index ec986498114e..787277f4d455 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -277,6 +277,16 @@
interrupt-parent = <&pio>;
interrupts = <6 12 IRQ_TYPE_EDGE_FALLING>; /* PG12 */
};
+
+ /* NFC (NPC 100) */
+ npc100: nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; /* PL6 */
+ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ firmware-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>; /* PD3 */
+ };
};
&mmc0 {
@@ -434,9 +444,10 @@
};
&reg_dldo2 {
- regulator-min-microvolt = <2800000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <4200000>;
- regulator-name = "vcc-mipi";
+ regulator-name = "vbat-nfc";
+ regulator-always-on;
};
&reg_dldo3 {
@@ -459,7 +470,8 @@
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "dvdd-csi-r";
+ regulator-name = "pvdd-nfc";
+ regulator-always-on;
};
&reg_eldo2 {
--
2.20.1

104
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0045-input-sun4i-a10-lradc-keys-Add-support-for-A83T.patch Normal file
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@ -0,0 +1,104 @@
From df802a8e12f7600dea15f67314bb1bfd7a981949 Mon Sep 17 00:00:00 2001
From: Ziping Chen <techping.chan@gmail.com>
Date: Mon, 13 Nov 2017 16:49:37 +0100
Subject: [PATCH 45/82] input: sun4i-a10-lradc-keys: Add support for A83T
Allwinner A83T SoC has a low res adc like the one
in Allwinner A10 SoC, however, the A10 SoC's vref
of lradc internally is divided by 2/3 and the A83T
SoC's vref of lradc internally is divided by 3/4,
thus add a hardware variant for it to be compatible
with various devices.
Signed-off-by: Ziping Chen <techping.chan@gmail.com>
---
drivers/input/keyboard/sun4i-lradc-keys.c | 38 ++++++++++++++++++++---
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/input/keyboard/sun4i-lradc-keys.c b/drivers/input/keyboard/sun4i-lradc-keys.c
index a37c172452e6..bfd2038a9047 100644
--- a/drivers/input/keyboard/sun4i-lradc-keys.c
+++ b/drivers/input/keyboard/sun4i-lradc-keys.c
@@ -46,6 +46,7 @@
#define CONTINUE_TIME_SEL(x) ((x) << 16) /* 4 bits */
#define KEY_MODE_SEL(x) ((x) << 12) /* 2 bits */
#define LEVELA_B_CNT(x) ((x) << 8) /* 4 bits */
+#define HOLD_KEY_EN(x) ((x) << 7)
#define HOLD_EN(x) ((x) << 6)
#define LEVELB_VOL(x) ((x) << 4) /* 2 bits */
#define SAMPLE_RATE(x) ((x) << 2) /* 2 bits */
@@ -63,6 +64,25 @@
#define CHAN0_KEYDOWN_IRQ BIT(1)
#define CHAN0_DATA_IRQ BIT(0)
+/* struct lradc_variant - Describe sun4i-a10-lradc-keys hardware variant
+ * @divisor_numerator: The numerator of lradc Vref internally divisor
+ * @divisor_denominator: The denominator of lradc Vref internally divisor
+ */
+struct lradc_variant {
+ u8 divisor_numerator;
+ u8 divisor_denominator;
+};
+
+static const struct lradc_variant lradc_variant_a10 = {
+ .divisor_numerator = 2,
+ .divisor_denominator = 3
+};
+
+static const struct lradc_variant r_lradc_variant_a83t = {
+ .divisor_numerator = 3,
+ .divisor_denominator = 4
+};
+
struct sun4i_lradc_keymap {
u32 voltage;
u32 keycode;
@@ -74,6 +94,7 @@ struct sun4i_lradc_data {
void __iomem *base;
struct regulator *vref_supply;
struct sun4i_lradc_keymap *chan0_map;
+ const struct lradc_variant *variant;
u32 chan0_map_count;
u32 chan0_keycode;
u32 vref;
@@ -128,9 +149,9 @@ static int sun4i_lradc_open(struct input_dev *dev)
if (error)
return error;
- /* lradc Vref internally is divided by 2/3 */
- lradc->vref = regulator_get_voltage(lradc->vref_supply) * 2 / 3;
-
+ lradc->vref = regulator_get_voltage(lradc->vref_supply) *
+ lradc->variant->divisor_numerator /
+ lradc->variant->divisor_denominator;
/*
* Set sample time to 4 ms / 250 Hz. Wait 2 * 4 ms for key to
* stabilize on press, wait (1 + 1) * 4 ms for key release
@@ -222,6 +243,12 @@ static int sun4i_lradc_probe(struct platform_device *pdev)
if (error)
return error;
+ lradc->variant = of_device_get_match_data(&pdev->dev);
+ if (!lradc->variant) {
+ dev_err(&pdev->dev, "Missing sun4i-a10-lradc-keys variant\n");
+ return -EINVAL;
+ }
+
lradc->vref_supply = devm_regulator_get(dev, "vref");
if (IS_ERR(lradc->vref_supply))
return PTR_ERR(lradc->vref_supply);
@@ -265,7 +292,10 @@ static int sun4i_lradc_probe(struct platform_device *pdev)
}
static const struct of_device_id sun4i_lradc_of_match[] = {
- { .compatible = "allwinner,sun4i-a10-lradc-keys", },
+ { .compatible = "allwinner,sun4i-a10-lradc-keys",
+ .data = &lradc_variant_a10 },
+ { .compatible = "allwinner,sun8i-a83t-r-lradc-keys",
+ .data = &r_lradc_variant_a83t },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match);
--
2.20.1

31
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0046-ARM-dts-sun8i-a83t-Add-lradc.patch Normal file
View file

@ -0,0 +1,31 @@
From b804df86f96f4bdc74abab55404a0bdcc7526f8b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 06:25:17 +0100
Subject: [PATCH 46/82] ARM: dts: sun8i-a83t: Add lradc
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 66f035ead79a..d9074f050a9c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -627,6 +627,13 @@
status = "disabled";
};
+ lradc: lradc@1f03c00 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01f03c00 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
--
2.20.1

52
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0047-ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-volume-k.patch Normal file
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@ -0,0 +1,52 @@
From 8c120e82a6cd86742dbdfd5c0a17d88737a74394 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 06:25:59 +0100
Subject: [PATCH 47/82] ARM: dts: sun8i-a83t-tbs-a711: Add support for volume
keys input
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 787277f4d455..ab4dce4b1e67 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -46,6 +46,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
/ {
model = "TBS A711 Tablet";
@@ -289,6 +290,25 @@
};
};
+&lradc {
+ vref-supply = <&reg_aldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <210000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <410000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

544
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0048-misc-tbs-a711-Power-manager-and-wakeup-monitoring-dr.patch Normal file
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@ -0,0 +1,544 @@
From 050ae3acc34834c56ee0a95ed2e96143e4f885b5 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 02:10:15 +0100
Subject: [PATCH 48/82] misc: tbs-a711: Power manager and wakeup monitoring
driver
This driver allows for powering/resetting devices that are otherwise
handled by other subsytems (USB). It also has mechanismsm for polling
from userspace on device->SoC wakeup events via GPIO.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/misc/Makefile | 1 +
drivers/misc/tbs-a711.c | 509 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 510 insertions(+)
create mode 100644 drivers/misc/tbs-a711.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index af22bbc3d00c..4b09a5b406e0 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
obj-$(CONFIG_OCXL) += ocxl/
obj-$(CONFIG_MISC_RTSX) += cardreader/
+obj-y += tbs-a711.o
diff --git a/drivers/misc/tbs-a711.c b/drivers/misc/tbs-a711.c
new file mode 100644
index 000000000000..05fe2ed76429
--- /dev/null
+++ b/drivers/misc/tbs-a711.c
@@ -0,0 +1,509 @@
+#include <linux/wait.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/cdev.h>
+#include <linux/module.h>
+#include <linux/poll.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#define DRIVER_NAME "tbs_a711"
+
+#define A711_IOCTL_RESET _IO('A', 0)
+#define A711_IOCTL_POWERUP _IO('A', 1)
+#define A711_IOCTL_POWERDN _IO('A', 2)
+#define A711_IOCTL_STATUS _IOR('A', 3, int)
+
+enum {
+ A711_REQ_NONE = 0,
+ A711_REQ_RESET,
+ A711_REQ_PWDN,
+ A711_REQ_PWUP,
+};
+
+struct a711_dev {
+ struct device *dev;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *wakeup_gpio;
+ struct regulator *regulator;
+ int wakeup_irq;
+ u32 reset_duration;
+ struct cdev cdev;
+ dev_t major;
+
+ // change
+ spinlock_t lock;
+ wait_queue_head_t waitqueue;
+ int got_wakeup;
+ int is_open;
+ struct work_struct work;
+ int last_request;
+ int is_enabled;
+};
+
+static void a711_reset(struct a711_dev* a711)
+{
+ struct device *dev = a711->dev;
+
+ if (!a711->is_enabled)
+ return;
+
+ if (!a711->reset_gpio) {
+ dev_err(dev, "reset is not configured for this device");
+ return;
+ }
+
+ dev_info(dev, "resetting");
+
+ gpiod_set_value(a711->reset_gpio, 1);
+ msleep(a711->reset_duration);
+ gpiod_set_value(a711->reset_gpio, 0);
+}
+
+static void a711_power_down(struct a711_dev* a711)
+{
+ struct device *dev = a711->dev;
+
+ if (!a711->is_enabled)
+ return;
+
+ dev_info(dev, "powering down");
+
+ gpiod_set_value(a711->enable_gpio, 0);
+ if (a711->regulator)
+ regulator_disable(a711->regulator);
+ else
+ gpiod_set_value(a711->reset_gpio, 1);
+ a711->is_enabled = 0;
+}
+
+static void a711_power_up(struct a711_dev* a711)
+{
+ struct device *dev = a711->dev;
+ int ret;
+
+ if (a711->is_enabled)
+ return;
+
+ dev_info(dev, "powering up");
+
+ // power up
+ if (a711->regulator) {
+ ret = regulator_enable(a711->regulator);
+ if (ret < 0) {
+ dev_err(dev, "can't enable power supply err=%d", ret);
+ return;
+ }
+ }
+
+ gpiod_set_value(a711->enable_gpio, 1);
+ gpiod_set_value(a711->reset_gpio, 1);
+ msleep(a711->reset_duration);
+ gpiod_set_value(a711->reset_gpio, 0);
+ a711->is_enabled = 1;
+}
+
+static struct class* a711_class;
+
+static void a711_work_handler(struct work_struct *work)
+{
+ struct a711_dev *a711 = container_of(work, struct a711_dev, work);
+ int last_request;
+
+ spin_lock(&a711->lock);
+ last_request = a711->last_request;
+ a711->last_request = 0;
+ spin_unlock(&a711->lock);
+
+ if (last_request == A711_REQ_RESET) {
+ a711_reset(a711);
+ } else if (last_request == A711_REQ_PWDN) {
+ a711_power_down(a711);
+ } else if (last_request == A711_REQ_PWUP) {
+ a711_power_up(a711);
+ }
+}
+
+static bool a711_has_wakeup(struct a711_dev* a711)
+{
+ bool got_wakeup;
+ spin_lock(&a711->lock);
+ got_wakeup = a711->got_wakeup;
+ spin_unlock(&a711->lock);
+ return got_wakeup;
+}
+
+static ssize_t a711_read(struct file *fp, char __user *buf, size_t len,
+ loff_t *off)
+{
+ struct a711_dev* a711 = fp->private_data;
+ int ret;
+ char tmp_buf[1] = {1};
+ int got_wakeup;
+ int non_blocking = fp->f_flags & O_NONBLOCK;
+
+ // first handle non-blocking path
+ if (non_blocking && !a711_has_wakeup(a711))
+ return -EWOULDBLOCK;
+
+ // wait for availability of wakeup
+ ret = wait_event_interruptible(a711->waitqueue,
+ a711_has_wakeup(a711));
+ if (ret)
+ return ret;
+
+ spin_lock(&a711->lock);
+
+ got_wakeup = a711->got_wakeup;
+ a711->got_wakeup = 0;
+
+ if (!got_wakeup) {
+ ret = -EIO;
+ } else {
+ if (copy_to_user(buf, tmp_buf, 1))
+ ret = -EFAULT;
+ else
+ ret = 1;
+ }
+
+ spin_unlock(&a711->lock);
+ return ret;
+}
+
+static ssize_t a711_write(struct file *fp, const char __user *buf,
+ size_t len, loff_t *off)
+{
+ struct a711_dev* a711 = fp->private_data;
+ int ret;
+ char tmp_buf[1];
+ int update = 0;
+
+ if (len == 0)
+ return 0;
+
+ ret = copy_from_user(tmp_buf, buf, 1);
+ if (ret)
+ return -EFAULT;
+
+ spin_lock(&a711->lock);
+
+ switch (tmp_buf[0]) {
+ case 'r':
+ a711->last_request = A711_REQ_RESET;
+ break;
+ case 'u':
+ a711->last_request = A711_REQ_PWUP;
+ break;
+ case 'd':
+ a711->last_request = A711_REQ_PWDN;
+ break;
+ default:
+ a711->last_request = A711_REQ_NONE;
+ break;
+ }
+
+ update = a711->last_request != 0;
+
+ spin_unlock(&a711->lock);
+
+ if (update)
+ schedule_work(&a711->work);
+
+ return 1;
+}
+
+static unsigned int a711_poll(struct file *fp, poll_table *wait)
+{
+ struct a711_dev* a711 = fp->private_data;
+ int ret = 0;
+
+ poll_wait(fp, &a711->waitqueue, wait);
+
+ spin_lock(&a711->lock);
+ if (a711->got_wakeup)
+ ret |= POLLIN | POLLRDNORM;
+ spin_unlock(&a711->lock);
+
+ return ret;
+}
+
+static long a711_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
+{
+ struct a711_dev* a711 = fp->private_data;
+ unsigned long flags;
+ int ret = -ENOSYS;
+ void __user *parg = (void __user *)arg;
+ int powered;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EACCES;
+
+ spin_lock_irqsave(&a711->lock, flags);
+
+ switch (cmd) {
+ case A711_IOCTL_RESET:
+ a711->last_request = A711_REQ_RESET;
+ ret = 0;
+ break;
+ case A711_IOCTL_POWERUP:
+ a711->last_request = A711_REQ_PWUP;
+ ret = 0;
+ break;
+ case A711_IOCTL_POWERDN:
+ a711->last_request = A711_REQ_PWDN;
+ ret = 0;
+ break;
+ case A711_IOCTL_STATUS:
+ powered = a711->is_enabled || a711->last_request == A711_REQ_PWUP;
+ spin_unlock_irqrestore(&a711->lock, flags);
+
+ if (copy_to_user(parg, &powered, sizeof powered))
+ return -EFAULT;
+
+ return 0;
+ }
+
+ spin_unlock_irqrestore(&a711->lock, flags);
+
+ if (ret == 0)
+ schedule_work(&a711->work);
+
+ return ret;
+}
+
+static int a711_release(struct inode *ip, struct file *fp)
+{
+ struct a711_dev* a711 = fp->private_data;
+
+ spin_lock(&a711->lock);
+ a711->is_open = 0;
+ spin_unlock(&a711->lock);
+
+ return 0;
+}
+
+static int a711_open(struct inode *ip, struct file *fp)
+{
+ struct a711_dev* a711 = container_of(ip->i_cdev, struct a711_dev, cdev);
+
+ fp->private_data = a711;
+
+ spin_lock(&a711->lock);
+ if (a711->is_open) {
+ spin_unlock(&a711->lock);
+ return -EBUSY;
+ }
+
+ a711->is_open = 1;
+ spin_unlock(&a711->lock);
+
+ nonseekable_open(ip, fp);
+ return 0;
+}
+
+static const struct file_operations a711_fops = {
+ .owner = THIS_MODULE,
+ .read = a711_read,
+ .write = a711_write,
+ .poll = a711_poll,
+ .unlocked_ioctl = a711_ioctl,
+ .open = a711_open,
+ .release = a711_release,
+ .llseek = noop_llseek,
+};
+
+static irqreturn_t a711_wakeup_isr(int irq, void *dev_id)
+{
+ struct a711_dev *a711 = dev_id;
+ unsigned long flags;
+
+ spin_lock_irqsave(&a711->lock, flags);
+ a711->got_wakeup = 1;
+ spin_unlock_irqrestore(&a711->lock, flags);
+
+ wake_up_interruptible(&a711->waitqueue);
+
+ return IRQ_HANDLED;
+}
+
+static int a711_probe(struct platform_device *pdev)
+{
+ struct a711_dev *a711;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device *sdev;
+ const char* cdev_name = NULL;
+ int ret;
+
+ a711 = devm_kzalloc(dev, sizeof(*a711), GFP_KERNEL);
+ if (!a711)
+ return -ENOMEM;
+
+ a711->dev = dev;
+ platform_set_drvdata(pdev, a711);
+ init_waitqueue_head(&a711->waitqueue);
+ spin_lock_init(&a711->lock);
+ INIT_WORK(&a711->work, &a711_work_handler);
+
+ // get device name and reset time from device tree
+ ret = of_property_read_u32_index(np, "reset-duration-ms", 0,
+ &a711->reset_duration);
+ if (ret) {
+ a711->reset_duration = 10;
+ }
+
+ ret = of_property_read_string(np, "char-device-name", &cdev_name);
+ if (ret) {
+ dev_err(dev, "char-device-name is not configured");
+ return -EINVAL;
+ }
+
+ a711->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH);
+ if (IS_ERR(a711->enable_gpio)) {
+ dev_err(dev, "can't get enable gpio err=%ld",
+ PTR_ERR(a711->enable_gpio));
+ return PTR_ERR(a711->enable_gpio);
+ }
+
+ a711->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(a711->reset_gpio)) {
+ dev_err(dev, "can't get reset gpio err=%ld",
+ PTR_ERR(a711->reset_gpio));
+ return PTR_ERR(a711->reset_gpio);
+ }
+
+ a711->wakeup_gpio = devm_gpiod_get_optional(dev, "wakeup", GPIOD_IN);
+ if (IS_ERR(a711->wakeup_gpio)) {
+ dev_err(dev, "can't get wakeup gpio err=%ld",
+ PTR_ERR(a711->wakeup_gpio));
+ return PTR_ERR(a711->wakeup_gpio);
+ }
+
+ a711->wakeup_irq = gpiod_to_irq(a711->wakeup_gpio);
+ if (a711->wakeup_irq > 0) {
+ ret = devm_request_irq(dev, a711->wakeup_irq,
+ a711_wakeup_isr,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING,
+ "a711-wakeup", a711);
+ if (ret) {
+ dev_err(dev, "error requesting wakeup-irq: %d", ret);
+ return ret;
+ }
+ }
+
+ a711->regulator = devm_regulator_get_optional(dev, "power");
+ if (IS_ERR(a711->regulator)) {
+ ret = PTR_ERR(a711->regulator);
+ if (ret != -ENODEV) {
+ dev_err(dev, "can't get power supply err=%d", ret);
+ return ret;
+ }
+
+ a711->regulator = NULL;
+ }
+
+ // create char device
+ ret = alloc_chrdev_region(&a711->major, 0, 1, "a711");
+ if (ret) {
+ dev_err(dev, "can't allocate chrdev region");
+ goto err_disable_regulator;
+ }
+
+ cdev_init(&a711->cdev, &a711_fops);
+ a711->cdev.owner = THIS_MODULE;
+ ret = cdev_add(&a711->cdev, a711->major, 1);
+ if (ret) {
+ dev_err(dev, "can't add cdev");
+ goto err_unreg_chrev_region;
+ }
+
+ sdev = device_create(a711_class, dev, a711->major, a711, cdev_name);
+ if (IS_ERR(sdev)) {
+ ret = PTR_ERR(sdev);
+ goto err_del_cdev;
+ }
+
+ gpiod_set_value(a711->enable_gpio, 0);
+ if (!a711->regulator)
+ gpiod_set_value(a711->reset_gpio, 1);
+
+ dev_info(dev, "initialized TBS A711 platform driver");
+
+ return 0;
+
+err_del_cdev:
+ cdev_del(&a711->cdev);
+err_unreg_chrev_region:
+ unregister_chrdev(a711->major, "a711");
+err_disable_regulator:
+ cancel_work_sync(&a711->work);
+ return ret;
+}
+
+static int a711_remove(struct platform_device *pdev)
+{
+ struct a711_dev *a711 = platform_get_drvdata(pdev);
+
+ a711_power_down(a711);
+
+ cancel_work_sync(&a711->work);
+
+ device_destroy(a711_class, a711->major);
+ cdev_del(&a711->cdev);
+ unregister_chrdev(a711->major, "a711");
+
+ if (a711->wakeup_irq > 0)
+ devm_free_irq(a711->dev, a711->wakeup_irq, a711);
+
+ return 0;
+}
+
+static const struct of_device_id a711_of_match[] = {
+ { .compatible = "custom,power-manager" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, a711_of_match);
+
+static struct platform_driver a711_platform_driver = {
+ .probe = a711_probe,
+ .remove = a711_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = a711_of_match,
+ },
+};
+
+static int __init a711_driver_init(void)
+{
+ int ret;
+
+ a711_class = class_create(THIS_MODULE, "a711");
+
+ ret = platform_driver_register(&a711_platform_driver);
+ if (ret)
+ class_destroy(a711_class);
+
+ return ret;
+}
+
+static void __exit a711_driver_exit(void)
+{
+ platform_driver_unregister(&a711_platform_driver);
+ class_destroy(a711_class);
+}
+
+module_init(a711_driver_init);
+module_exit(a711_driver_exit);
+
+MODULE_VERSION("1.0.0");
+MODULE_DESCRIPTION("TBS A711 Tablet Platform Driver");
+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
+MODULE_LICENSE("GPL v2");
--
2.20.1

57
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0049-ARM-dts-sun8i-a83t-Add-uart2-uart4.patch Normal file
View file

@ -0,0 +1,57 @@
From 1b732183172780283b7311bf0959b7ba7d4a4153 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 22:21:29 +0100
Subject: [PATCH 49/82] ARM: dts: sun8i-a83t: Add uart2-uart4
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 33 +++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index d9074f050a9c..788ecf540f55 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -880,6 +880,39 @@
status = "disabled";
};
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun8i-a83t-i2c",
"allwinner,sun6i-a31-i2c";
--
2.20.1

31
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0050-ARM-dts-sun8i-a83t-Add-uart2-PB-pins.patch Normal file
View file

@ -0,0 +1,31 @@
From 8921a3bf53f233c746f591c58b2840963cee88a2 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 22:22:44 +0100
Subject: [PATCH 50/82] ARM: dts: sun8i-a83t: Add uart2 PB pins
These are used on TBS A83T A711 tablet for GPS serial port.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 788ecf540f55..a8ff7a8efe71 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -775,6 +775,11 @@
pins = "PG8", "PG9";
function = "uart1";
};
+
+ uart2_pb_pins: uart2-pb-pins {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
};
timer@1c20c00 {
--
2.20.1

65
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0051-ARM-dts-sun8i-a83t-tbs-a711-Enable-uart2-and-add-gps.patch Normal file
View file

@ -0,0 +1,65 @@
From 9e45d6dd4dfcc8706081ee992b24acab372d845a Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 22:24:15 +0100
Subject: [PATCH 51/82] ARM: dts: sun8i-a83t-tbs-a711: Enable uart2 and add gps
regulator
Now we can use tbs-a711 driver for power/reset control for GPS module.
Enable this. This allows access to u-blox NEO-6M connected to uart2.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index ab4dce4b1e67..b0a94cf13740 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -121,6 +121,15 @@
};
};
+ reg_gps: reg-gps {
+ compatible = "regulator-fixed";
+ regulator-name = "gps";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ enable-active-high;
+ gpio = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4 */
+ };
+
reg_vbat: reg-vbat {
compatible = "regulator-fixed";
regulator-name = "vbat";
@@ -149,6 +158,13 @@
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
};
+
+ gps {
+ compatible = "custom,power-manager";
+ power-supply = <&reg_gps>;
+ reset-duration-ms = <5>;
+ char-device-name = "pwr-gps";
+ };
};
&cpu0 {
@@ -564,6 +580,13 @@
status = "okay";
};
+/* GPS NEO-6M */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pb_pins>;
+ status = "okay";
+};
+
&usb_otg {
dr_mode = "otg";
status = "okay";
--
2.20.1

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@ -0,0 +1,66 @@
From 747a078b6546e1bd51aa994a4b4da8d2a7b16882 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?=
<mylene.josserand@free-electrons.com>
Date: Thu, 6 Jul 2017 10:57:55 +0200
Subject: [PATCH 52/82] ARM: dts: sun8i-a83t-tbs-a711: Add powerup/down support
for the 3G modem
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The modem needs tree gpios to be powered-up:
- PL10 = reset
- PL8 = On/Off
- PL9 = vbat
Because of that, the PL9 corresponds to the regulator's gpio whereas
the PL8 (on/off) will be a power-gpio of the power sequence.
Thanks to that, the modem is powered up:
# lsusb
Bus 001 Device 004: ID 19d2:ffeb
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index b0a94cf13740..f22da26557f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -142,8 +142,10 @@
regulator-name = "vmain";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
enable-active-high;
+ //megi: See modem for comments
+ regulator-always-on;
vin-supply = <&reg_vbat>;
};
@@ -159,6 +161,19 @@
clock-names = "ext_clock";
};
+ modem {
+ compatible = "custom,power-manager";
+ //megi: switching Q5 MOSFET probably leads to brownouts on
+ //VBAT due to larger capacities on VMAIN. Only use PL8 to
+ //enable/disable the modem
+ //power-supply = <&reg_vmain>;
+ enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
+ reset-duration-ms = <5>;
+ char-device-name = "pwr-modem";
+ };
+
gps {
compatible = "custom,power-manager";
power-supply = <&reg_gps>;
--
2.20.1

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From 7e268d45be35f4355b8088980820da1858058d2b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 19:03:08 +0100
Subject: [PATCH 53/82] ARM: dts: suni-a83t: Add support for I2S controller
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a8ff7a8efe71..147f76a66a28 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -304,6 +304,19 @@
#size-cells = <1>;
ranges;
+ dai: dai@01c23000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-a83t-i2s";
+ reg = <0x01c23000 0x200>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TDM>, <&ccu CLK_TDM>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_TDM>;
+ dmas = <&dma 28>, <&dma 28>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-a83t-de2-clk";
reg = <0x01000000 0x100000>;
--
2.20.1

29
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@ -0,0 +1,29 @@
From 0cd8e96aad9dde4264e30208d50abde35e1a8afa Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 19:03:39 +0100
Subject: [PATCH 54/82] ARM: dts: suni-a83t: Add i2s0 pins
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 147f76a66a28..c79f5a678e62 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -769,6 +769,11 @@
function = "spdif";
};
+ i2s0_pins: i2s0-pins {
+ pins = "PB4", "PB5", "PB6", "PB7", "PB8";
+ function = "i2s0";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
--
2.20.1

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@ -0,0 +1,34 @@
From 35ac1469ce7641092c44fb3bc0c6d4b0248e0597 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 19:04:55 +0100
Subject: [PATCH 55/82] ARM: dts: suni-a83t-tbs-a711: Enable I2S0 for
communication with AC100
This will allow for sound playback after AC100 audio codec is
implemented.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index f22da26557f2..bc08c3c281c1 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -207,6 +207,12 @@
};
};
+&dai {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_pins>;
+};
+
&de {
status = "okay";
};
--
2.20.1

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@ -0,0 +1,349 @@
From f45ece9d10522312ec1bfe2e564b1638644b2c1b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 23:09:14 +0100
Subject: [PATCH 56/82] sound: soc: ac100-codec: Initial implementation
This driver provides AC100 codec controls.
Note: This does not yet provide anything, it's just a skeleton
for a future driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
sound/soc/sunxi/Kconfig | 11 ++
sound/soc/sunxi/Makefile | 1 +
sound/soc/sunxi/ac100-codec.c | 291 ++++++++++++++++++++++++++++++++++
3 files changed, 303 insertions(+)
create mode 100644 sound/soc/sunxi/ac100-codec.c
diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
index 22408bc2d6ec..e276cc94a8c5 100644
--- a/sound/soc/sunxi/Kconfig
+++ b/sound/soc/sunxi/Kconfig
@@ -20,6 +20,17 @@ config SND_SUN8I_CODEC
Say Y or M if you want to add sun8i digital audio codec support.
+config SND_AC100_CODEC
+ tristate "Allwinner (X-Powers) AC100 audio codec"
+ depends on OF
+ depends on MACH_SUN8I || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ This option enables the audio codec support for Allwinner (X-Powers)
+ AC100 chip.
+
+ Say Y or M if you want to add AC100 audio codec support.
+
config SND_SUN8I_CODEC_ANALOG
tristate "Allwinner sun8i Codec Analog Controls Support"
depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
index 4a9ef67386ca..83461fdbfaa2 100644
--- a/sound/soc/sunxi/Makefile
+++ b/sound/soc/sunxi/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
diff --git a/sound/soc/sunxi/ac100-codec.c b/sound/soc/sunxi/ac100-codec.c
new file mode 100644
index 000000000000..d5438815be75
--- /dev/null
+++ b/sound/soc/sunxi/ac100-codec.c
@@ -0,0 +1,291 @@
+/*
+ * This driver supports the controls for X-Powers (Allwinner)
+ * AC100 audio codec. This codec is co-packaged with AXP81x PMICs.
+ *
+ * (C) Copyright 2017 Ondrej Jirman <megous@megous.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/mfd/ac100.h>
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+/*
+ * Reasearch
+ * ---------
+ *
+ * Features:
+ * 2 A/D
+ * 2 D/A
+ * 2 I2S/PCM #1 and #2
+ * 1 PCM mono #3 muxable with I2S #2
+ * 3 mic inputs (mic #2 and #3 exclusively muxable at input)
+ * 1 line in (directly or through amp)
+ * 1 aux input
+ * all input signals mixable directly into output (bypass AD/DA)
+ *
+ * outputs:
+ * HPOUTL - headphone left
+ * HPOUTR - headphone right
+ * LINEOUT - line out differential
+ * EAROUT - earpeiece differential
+ * SPKOUT1 - SPOL left speaker differnetial
+ * SPKOUT2 - SPOR right speaker differnetial
+ *
+ * Power up:
+ * LDOIN - 1.5-3.3V external power
+ * AVCC - analog power 3V
+ * CPVDD - 1.8V
+ * VDD-IO1 - power for I2S #1 and #2 1.8/3V
+ * VDD-IO2 - power for I2S #3 1.8/3V
+ * VCC-RTC - power for RTC 1.8/3V
+ *
+ * Clocks: page 28
+ * SYSCLK must be 24576000 Hz (48kHz) or 22579200 Hz (44.1kHz)
+ * - Source I2S1CLK/MCLK1
+ * - If SRC# module is used SYSCLK must be generated by PLL
+ *
+ * A/D:
+ * ADC_APC_CTRL B15 B11 enable/disable A/D to save power
+ * ADC_APC_CTRL B14-12 B10-8 volume control for A/D
+ * ADC_DIG_CTRL B15 enable/disable digital A/D to save power
+ * ADDA_FS_I2S1 ADDA_FS_I2S2 - select sample rate
+ *
+ * D/A:
+ * OMIXER_DACA_CTRL B15-14 enable/disable D/A channels
+ * DAC_DIG_CTRL B15 enable/disable digital D/A
+ *
+ * Mixer:
+ * - 2 channels DAC Output mixers
+ * - inputs:
+ * - LINEINL/R
+ * - AXIL/R
+ * - MIC1P/N,MIC2P/N
+ * - Stereo DAC output
+ * - 2 channels ADC Record mixers
+ * - inputs:
+ * - LINEINL/R
+ * - AXIL/R
+ * - MIC1P/N,MIC2P/N
+ * - Stereo DAC output
+ * - Digital mixers
+ * - avaliable on:
+ * - before stereo DAC - DAC_MXR_SRC
+ * - I2S1 output - I2S1_MXR_SRC
+ * - I2S2 output - I2S2_MXR_SRC
+ * - Analogue inputs
+ * - LINEINL/R - 1 ch. mono
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - -9dB to 12dB in 1.5dB step by LINEIN_DIFF_PREG
+ * - AXIL/R - 2 ch. stereo
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - programmable volume level adj. and mute
+ * - -9dB to 12dB in 1.5dB steps by AXI_PREG
+ * - MIC1P/N - has preamp
+ * - MIC2P/N - has preamp
+ * - MIC3P/N - has preamp muxed with MIC2 (sel by ADC_SRCBST_CTRL B7)
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - preamps enable at ADC_SRCBST_CTRL B15 and B11
+ * - preamp gain at MIC1BOOST MIC2BOOST
+ * - Analogue outputs:
+ * - HPOUTL/R, HPOUTFB - 2ch. headphones
+ * - sources output mixer or directly from DAC
+ * - sel HPOUT_CTRL B15 B14
+ * - mute HPOUT_CTRL B13 B12
+ * - power amp
+ * - powerdown/up HPOUT_CTRL B11
+ * - volume HP_VOL[5:0] - 64dB range in 1dB step from 0dB to -62dB
+ * - mute by using 0 for HP_VOL[5:0]
+ * - DC offset cancellation (POP noise) HP_DCRM_EN
+ * - This bit must be set 0xf before headphone PA enabled, and this bit
+ * must be set 0x0 before headphone PA disabled.
+ * - zero cross to prevent noise/clicsk on volume change ZCROSS_EN
+ * - SPOLP/N, SPORP/N 2 ch. speakers (mono/stereo)
+ * - source for SPOLP
+ * - left output mixer or (left+right) output mixer
+ * - source for SPORP
+ * - right output mixer or (left+right) output mixer
+ * - volume 43.5dB rang in 1.5dB step from -43.5dB to 0dB
+ * - amp enable SPKOUT_CTRL B11 B7
+ * - EAROUTP/N - 1 ch earpeice
+ * - source left DAC, right DAC, left output mixer or right output mixer
+ * - volume ERPOUT_CTRL[4:0] 43.5dB range in 1.5dB step from -43.5dB to 0dB
+ * - power amp enable ERPOUT_CTRL B5
+ * - LINEOUTP/N - 1ch line out
+ * - source MIC1 preamp, MIC2 preamp, left output mix or right output mix
+ * - volume 10.5dB range in 1.5dB step from -4.5dB to 6dB
+ * - out buffer power up/down LOUT_CTRL B4
+ *
+ * Jack insert detection:
+ * - HBIAS current detection
+ * - 5bit ADC sample rate 16/32/64/128Hz
+ * - HMIC_STATUS[12:8] - ADC value
+ * - 2 thresholds TH1 for plug connection, TH2 for key press
+ * - can periodically trigger interrupts during key press (HBIAS above TH2)
+ *
+ * Interrupts:
+ * - FALLING_EDGE
+ * - for:
+ * - KEYDOWN
+ * - KEYUP
+ * - PLUG_IN
+ * - PLUG_OUT
+ * - HMIC_DATA
+ *
+ * High Pass Filter:
+ * - remove DC offset, can be disabled
+ *
+ * AGC:
+ * - automatic gain control before ADC input channels
+ * - params:
+ * - attack, decay time - 32/fs to 2^15*32/fs
+ * - target gain - –1dB to –30dB relative to a full-scale signal
+ * - noise threshold - –30dB to –90dB of full-scale (mute if input below this level)
+ * - max gain 0dB to 40dB in steps of 0.5dB
+ * - hysteresis - for noise detection in terms of signal level
+ * - debounce time - hysteresis for noise det in terms of time
+ * - also provides some output flags:
+ * - noise threshold reached
+ * - current gain
+ * - agc saturated (gain could get higher for the given input, but limited by
+ * params)
+ * - adc saturated - clipping at ADC input stage
+ *
+ * DRC:
+ * - dynamic range control for digital playback path
+ * - energy filter
+ * - compressor
+ * - smooth filter
+ * - can be disabled
+ */
+
+#define AC100_HMIC_DATA_MASK GENMASK(12, 8)
+#define AC100_HMIC_DATA_OFF 8
+#define AC100_HMIC_PULLOUT_PENDING BIT(4)
+#define AC100_HMIC_PLUGIN_PENDING BIT(3)
+#define AC100_HMIC_KEYUP_PENDING BIT(2)
+#define AC100_HMIC_KEYDOWN_PENDING BIT(1)
+#define AC100_HMIC_DATA_PENDING BIT(0)
+
+struct ac100_codec {
+ struct device *dev;
+ struct regmap *regmap;
+ int irq;
+};
+
+static irqreturn_t ac100_codec_irq(int irq, void *data)
+{
+ struct ac100_codec *codec = data;
+ unsigned int val = 0;
+ int ret;
+
+ /* read status */
+ ret = regmap_read(codec->regmap, AC100_HMIC_STATUS, &val);
+ if (ret)
+ return IRQ_HANDLED;
+
+ if (val & AC100_HMIC_PULLOUT_PENDING) {
+ dev_info(codec->dev, "IRQ: Pull out");
+ }
+
+ if (val & AC100_HMIC_PLUGIN_PENDING) {
+ dev_info(codec->dev, "IRQ: Plug in");
+ }
+
+ if (val & AC100_HMIC_KEYUP_PENDING) {
+ dev_info(codec->dev, "IRQ: Key up");
+ }
+
+ if (val & AC100_HMIC_KEYDOWN_PENDING) {
+ dev_info(codec->dev, "IRQ: Key down");
+ }
+
+ if (val & AC100_HMIC_DATA_PENDING) {
+ dev_info(codec->dev, "IRQ: Data");
+ }
+
+ /* clear status */
+ ret = regmap_write(codec->regmap, AC100_HMIC_STATUS, 0);
+ if (ret)
+ return IRQ_HANDLED;
+
+ return IRQ_HANDLED;
+}
+
+static int ac100_codec_probe(struct platform_device *pdev)
+{
+ struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
+ struct ac100_codec *codec;
+ int ret;
+
+ codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
+ if (!codec)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, codec);
+ codec->dev = &pdev->dev;
+ codec->regmap = ac100->regmap;
+
+ codec->irq = platform_get_irq(pdev, 0);
+ if (codec->irq < 0) {
+ dev_err(&pdev->dev, "No IRQ resource\n");
+ return codec->irq;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev, codec->irq, NULL,
+ ac100_codec_irq,
+ IRQF_SHARED | IRQF_ONESHOT,
+ dev_name(&pdev->dev), codec);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not request IRQ\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int ac100_codec_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct ac100_codec *codec = snd_soc_card_get_drvdata(card);
+
+ return 0;
+}
+
+static const struct of_device_id ac100_codec_of_match[] = {
+ { .compatible = "x-powers,ac100-codec" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ac100_codec_of_match);
+
+static struct platform_driver ac100_codec_driver = {
+ .driver = {
+ .name = "ac100-codec",
+ .of_match_table = ac100_codec_of_match,
+ },
+ .probe = ac100_codec_probe,
+ .remove = ac100_codec_remove,
+};
+module_platform_driver(ac100_codec_driver);
+
+MODULE_DESCRIPTION("X-Powers AC100 codec driver");
+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ac100-codec");
--
2.20.1

209
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0057-leds-axp20x-Support-leds-on-AXP20x-like-PMICs-AXP813.patch Normal file
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@ -0,0 +1,209 @@
From fc9173d7b8adaa12f8abd125bde351fe17add031 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 02:47:19 +0100
Subject: [PATCH 57/82] leds: axp20x: Support leds on AXP20x like PMICs, AXP813
at first
There is single led that can be turned on and off.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/leds/Kconfig | 8 +++
drivers/leds/Makefile | 1 +
drivers/leds/leds-axp20x.c | 138 +++++++++++++++++++++++++++++++++++++
drivers/mfd/axp20x.c | 3 +
4 files changed, 150 insertions(+)
create mode 100644 drivers/leds/leds-axp20x.c
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 44097a3e0fcc..a0cbdbb2c450 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -756,6 +756,14 @@ config LEDS_NIC78BX
To compile this driver as a module, choose M here: the module
will be called leds-nic78bx.
+config LEDS_AXP20X
+ tristate "LED support for AXP20X-like PMICs (AXP813, ...)"
+ depends on LEDS_CLASS && MFD_AXP20X
+ help
+ This option enables support for on-chip LED drivers on
+ AXP20X-like PMICs.
+
+
comment "LED Triggers"
source "drivers/leds/trigger/Kconfig"
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 420b5d2cfa62..a8149fb6e2d4 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
obj-$(CONFIG_LEDS_LM3601X) += leds-lm3601x.o
+obj-$(CONFIG_LEDS_AXP20X) += leds-axp20x.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o
diff --git a/drivers/leds/leds-axp20x.c b/drivers/leds/leds-axp20x.c
new file mode 100644
index 000000000000..de33c1d83054
--- /dev/null
+++ b/drivers/leds/leds-axp20x.c
@@ -0,0 +1,138 @@
+/*
+ * LED Driver for X-Powers AXP813 PMIC.
+ *
+ * Copyright(c) 2017 Ondrej Jirman <megous@megous.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/mfd/axp20x.h>
+
+#define AXP813_CHGLED_CTRL_MASK BIT(3)
+#define AXP813_CHGLED_CTRL_CHARGER BIT(3)
+#define AXP813_CHGLED_CTRL_USER 0
+
+#define AXP813_CHGLED_USER_STATE_MASK GENMASK(5, 4)
+#define AXP813_CHGLED_USER_STATE_OFFSET 4
+#define AXP813_CHGLED_USER_STATE_OFF 0
+#define AXP813_CHGLED_USER_STATE_BLINK_SLOW 1
+#define AXP813_CHGLED_USER_STATE_BLINK_FAST 2
+#define AXP813_CHGLED_USER_STATE_ON 3
+
+struct axp20x_led {
+ struct led_classdev cdev;
+ struct regmap *regmap;
+};
+
+static int axp20x_led_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ struct axp20x_led *led =
+ container_of(led_cdev, struct axp20x_led, cdev);
+ unsigned int val;
+
+ val = value == LED_OFF ? AXP813_CHGLED_USER_STATE_OFF :
+ AXP813_CHGLED_USER_STATE_ON;
+
+ return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_USER_STATE_MASK,
+ val << AXP813_CHGLED_USER_STATE_OFFSET);
+
+}
+
+static int axp20x_led_probe(struct platform_device *pdev)
+{
+ struct axp20x_dev *axp20x;
+ struct axp20x_led *led;
+ int ret;
+
+ if (!of_device_is_available(pdev->dev.of_node))
+ return -ENODEV;
+
+ axp20x = dev_get_drvdata(pdev->dev.parent);
+ if (!axp20x)
+ return -EINVAL;
+
+ led = devm_kzalloc(&pdev->dev,
+ sizeof(struct axp20x_led),
+ GFP_KERNEL);
+ if (!led)
+ return -ENOMEM;
+
+ led->regmap = axp20x->regmap;
+
+ led->cdev.name = "chgled";
+ led->cdev.brightness_set_blocking = axp20x_led_set;
+ led->cdev.brightness = LED_OFF;
+ led->cdev.max_brightness = 1;
+
+ ret = led_classdev_register(pdev->dev.parent, &led->cdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register led %s\n",
+ led->cdev.name);
+ return ret;
+ }
+
+ ret = regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_CTRL_MASK,
+ AXP813_CHGLED_CTRL_USER);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable user cnotrol\n");
+ }
+
+ ret = axp20x_led_set(&led->cdev, led->cdev.brightness);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to init led %s\n",
+ led->cdev.name);
+ }
+
+ platform_set_drvdata(pdev, led);
+ return 0;
+}
+
+static int axp20x_led_remove(struct platform_device *pdev)
+{
+ struct axp20x_led *led = platform_get_drvdata(pdev);
+
+ axp20x_led_set(&led->cdev, LED_OFF);
+
+ regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_CTRL_MASK,
+ AXP813_CHGLED_CTRL_CHARGER);
+
+ led_classdev_unregister(&led->cdev);
+
+ return 0;
+}
+
+static const struct of_device_id axp20x_leds_of_match[] = {
+ { .compatible = "x-powers,axp813-leds", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_leds_of_match);
+
+static struct platform_driver axp20x_led_driver = {
+ .driver = {
+ .name = "axp20x-leds",
+ .of_match_table = axp20x_leds_of_match,
+ },
+ .probe = axp20x_led_probe,
+ .remove = axp20x_led_remove,
+};
+
+module_platform_driver(axp20x_led_driver);
+
+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
+MODULE_DESCRIPTION("LED driver for AXP813 PMIC");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:leds-axp20x");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 81bf6ee4d8bb..ba616c1f28db 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -802,6 +802,9 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp813-usb-power-supply",
+ }, {
+ .name = "axp20x-leds",
+ .of_compatible = "x-powers,axp813-leds",
}, {
.name = "reg-userspace-consumer",
.platform_data = &vcc_vb_data,
--
2.20.1

26
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0058-ARM-dts-axp813-Enable-power-supply-led-control.patch Normal file
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@ -0,0 +1,26 @@
From 4bfe82217af51730d9d3dfe04509f7d415de7d53 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 02:47:51 +0100
Subject: [PATCH 58/82] ARM: dts: axp813: Enable power supply led control
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/axp81x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index f32a8ba53b85..6f4ea939b6ea 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -170,4 +170,8 @@
usb_power_supply: usb-power-supply {
compatible = "x-powers,axp813-usb-power-supply";
};
+
+ power_supply_leds: power-supply-leds {
+ compatible = "x-powers,axp813-leds";
+ };
};
--
2.20.1

82
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0059-ARM-dts-sun8i-a83t-Describe-A83T-thermal-zones.patch Normal file
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@ -0,0 +1,82 @@
From fcf4b68c77f7ce86a1976322cbb1f861962f8a66 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 17:16:45 +0100
Subject: [PATCH 59/82] ARM: dts: sun8i-a83t: Describe A83T thermal zones
There are three sensors, two for CPU, one for GPU.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c79f5a678e62..bffcee058627 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -69,6 +70,9 @@
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
};
cpu@1 {
@@ -107,6 +111,9 @@
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
};
cpu@101 {
@@ -1108,5 +1115,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ ths: ths@1f04000 {
+ #thermal-sensor-cells = <1>;
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100 0x01c14234 0x8>;
+ reg-names = "ths", "calibration";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <330>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 0>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <330>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 1>;
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <330>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 2>;
+ };
};
};
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0060-ARM-dts-sun8i-a83t-tbs-a711-Enable-thermal-sensor.patch Normal file
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@ -0,0 +1,28 @@
From a73c51c6adf95985d02f22670f45bc8d6a84739c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 17:17:14 +0100
Subject: [PATCH 60/82] ARM: dts: sun8i-a83t-tbs-a711: Enable thermal sensor
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index bc08c3c281c1..ed59185b9105 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -588,6 +588,10 @@
};
};
+&ths {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
2.20.1

71
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0061-ARM-dts-sun8i-a83t-tbs-a711-Enable-thermal-regulatio.patch Normal file
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@ -0,0 +1,71 @@
From 387b028e45a8c5a2fde464aba13138eb6b8df532 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 17:18:35 +0100
Subject: [PATCH 61/82] ARM: dts: sun8i-a83t-tbs-a711: Enable thermal
regulation of CPU frequency
Not very well tested for it's thermal properties, yet.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 44 +++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index ed59185b9105..99c5df15b036 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -190,6 +190,50 @@
cpu-supply = <&reg_dcdc3>;
};
+&cpu0_thermal {
+ trips {
+ cpu0_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_very_hot: cpu_very_hot {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_hot_limit {
+ trip = <&cpu0_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu1_thermal {
+ trips {
+ cpu1_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_very_hot: cpu_very_hot {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_hot_limit {
+ trip = <&cpu1_hot>;
+ cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&csi0 {
status = "okay";
pinctrl-names = "default";
--
2.20.1

31
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0062-ARM-dts-sun8i-a83t-tbs-Increase-voltage-on-the-vibra.patch Normal file
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@ -0,0 +1,31 @@
From 379fee744cb1fa4370ac692bc890e5e1182e337d Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 8 Dec 2017 12:44:22 +0100
Subject: [PATCH 62/82] ARM: dts: sun8i-a83t-tbs: Increase voltage on the
vibrator
To make it less sluggish.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 99c5df15b036..ea7b8bf4d327 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -608,8 +608,8 @@
};
&reg_ldo_io1 {
- regulator-min-microvolt = <3100000>;
- regulator-max-microvolt = <3100000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-name = "vcc-vb";
status = "okay";
};
--
2.20.1

74
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0063-phy-sun4i-usb-Add-DT-property-to-force-ID-VBUS-polli.patch Normal file
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@ -0,0 +1,74 @@
From 9a7e926353d5aea2d78ce507ae5bb3537cbccbed Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 12 Dec 2017 14:04:19 +0100
Subject: [PATCH 63/82] phy: sun4i-usb: Add DT property to force ID/VBUS
polling
In some cases interrupts on GPIO don't fire for whatever reason.
Allow to force polling of ID/VBUS detection pins from DT.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 44 ++++++++++++++-------------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 1f8809bab002..1cbb01c41d8d 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -816,29 +816,31 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
phy_set_drvdata(phy->phy, &data->phys[i]);
}
- data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
- if (data->id_det_irq > 0) {
- ret = devm_request_irq(dev, data->id_det_irq,
- sun4i_usb_phy0_id_vbus_det_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "usb0-id-det", data);
- if (ret) {
- dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
- return ret;
+ if (!of_find_property(np, "force-poll-vbus-id-det", NULL)) {
+ data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
+ if (data->id_det_irq > 0) {
+ ret = devm_request_irq(dev, data->id_det_irq,
+ sun4i_usb_phy0_id_vbus_det_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "usb0-id-det", data);
+ if (ret) {
+ dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
+ return ret;
+ }
}
- }
- data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
- if (data->vbus_det_irq > 0) {
- ret = devm_request_irq(dev, data->vbus_det_irq,
- sun4i_usb_phy0_id_vbus_det_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "usb0-vbus-det", data);
- if (ret) {
- dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
- data->vbus_det_irq = -1;
- sun4i_usb_phy_remove(pdev); /* Stop detect work */
- return ret;
+ data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
+ if (data->vbus_det_irq > 0) {
+ ret = devm_request_irq(dev, data->vbus_det_irq,
+ sun4i_usb_phy0_id_vbus_det_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "usb0-vbus-det", data);
+ if (ret) {
+ dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
+ data->vbus_det_irq = -1;
+ sun4i_usb_phy_remove(pdev); /* Stop detect work */
+ return ret;
+ }
}
}
--
2.20.1

27
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0064-ARM-dts-sun8i-a83t-tbs-a711-Enable-force-poll-vbus-i.patch Normal file
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@ -0,0 +1,27 @@
From a279c17434fbeaf040a553b6ce856ccbd00580f7 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 12 Dec 2017 14:06:13 +0100
Subject: [PATCH 64/82] ARM: dts: sun8i-a83t-tbs-a711: Enable
force-poll-vbus-id-det on usbphy
A83T doesn't fire interrupts on PH11. Force polling.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index ea7b8bf4d327..028dd29e13d7 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -666,5 +666,6 @@
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus_supply = <&reg_vmain>;
usb2_vbus_supply = <&reg_vmain>;
+ force-poll-vbus-id-det;
status = "okay";
};
--
2.20.1

29
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0065-arm-dts-sun8i-a83t-tbs-a711-GPS-regulator-is-apparen.patch Normal file
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@ -0,0 +1,29 @@
From f8b601516e29a67496d98414b2477928d79eb3eb Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 12 Dec 2017 16:15:26 +0100
Subject: [PATCH 65/82] arm: dts: sun8i-a83t-tbs-a711: GPS regulator is
apparently fixed
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 028dd29e13d7..027c6a76627f 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -127,7 +127,9 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
enable-active-high;
- gpio = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4 */
+ /*XXX: this doesn't control GPS regulator, shematics show FLAG
+ * pin */
+ //gpio = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4 */
};
reg_vbat: reg-vbat {
--
2.20.1

35
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@ -0,0 +1,35 @@
From 8a91463b53e778e876ca296882fd3285e02d129f Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 25 Dec 2017 22:05:19 +0100
Subject: [PATCH 66/82] WIP: Figure out how to use new bluetooth/OF driver
binding for BT chip
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 027c6a76627f..8bba9ccd2592 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -649,6 +649,16 @@
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
+
+/*
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ //max-speed = <921600>;
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>;
+ //host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+ };
+ */
};
/* GPS NEO-6M */
--
2.20.1

38
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0067-mmc-add-delay-after-power-class-selection.patch Normal file
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@ -0,0 +1,38 @@
From 2fecbde6fd1e7de568f19caaed3e0db75ac2d585 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 16 Mar 2018 20:31:55 +0100
Subject: [PATCH 67/82] mmc: add delay after power class selection
This seems to fix issue with sporadic ETIMEOUT in eMMC cache
initialization on second generation TBS A711 tablet.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/mmc/core/mmc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index f1fe446eee66..b29991135375 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1770,6 +1770,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
*/
mmc_select_powerclass(card);
+ msleep(20);
+
/*
* Enable HPI feature (if supported)
*/
@@ -1789,6 +1791,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
}
}
+ msleep(20);
+
/*
* If cache size is higher than 0, this indicates the existence of cache
* and it can be turned on. Note that some eMMCs from Micron has been
--
2.20.1

82
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@ -0,0 +1,82 @@
From 0ab580b2eac299d7f73c2ff3e7bf590a3fc7ea6d Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 20 Apr 2018 04:05:28 +0200
Subject: [PATCH 68/82] ARM: dts: sun8i-a83t: Add clock-frequency to avoid boot
warnings
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index bffcee058627..c09d8ee2f7c5 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -65,6 +65,7 @@
clocks = <&ccu CLK_C0CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
@@ -77,6 +78,7 @@
cpu@1 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
@@ -86,6 +88,7 @@
cpu@2 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
@@ -95,6 +98,7 @@
cpu@3 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
@@ -106,6 +110,7 @@
clocks = <&ccu CLK_C1CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
@@ -118,6 +123,7 @@
cpu@101 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
@@ -127,6 +133,7 @@
cpu@102 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
@@ -136,6 +143,7 @@
cpu@103 {
compatible = "arm,cortex-a7";
+ clock-frequency = <1200000000>;
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
--
2.20.1

73
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0069-media-hm5065-Port-to-4.17-drop-use-of-s_parm-g_parm-.patch Normal file
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@ -0,0 +1,73 @@
From 46beb097c9452520035e13c03c4ec0a66288c56b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 20 Apr 2018 04:02:26 +0200
Subject: [PATCH 69/82] media: hm5065: Port to 4.17 - drop use of s_parm/g_parm
callbacks
---
drivers/media/i2c/hm5065.c | 42 --------------------------------------
1 file changed, 42 deletions(-)
diff --git a/drivers/media/i2c/hm5065.c b/drivers/media/i2c/hm5065.c
index 1f0896bd8dff..07308e190494 100644
--- a/drivers/media/i2c/hm5065.c
+++ b/drivers/media/i2c/hm5065.c
@@ -1801,46 +1801,6 @@ static int hm5065_enum_frame_interval(
return 0;
}
-static int hm5065_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
-{
- struct v4l2_captureparm *cp = &parms->parm.capture;
- struct v4l2_subdev_frame_interval fi;
- int ret;
-
- if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
- cp->capability = V4L2_CAP_TIMEPERFRAME;
- fi.pad = 0;
- ret = hm5065_g_frame_interval(sd, &fi);
- if (ret)
- return ret;
-
- cp->timeperframe = fi.interval;
- return 0;
-}
-
-static int hm5065_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
-{
- struct v4l2_captureparm *cp = &parms->parm.capture;
- struct v4l2_subdev_frame_interval fi;
- int ret;
-
- if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
- fi.pad = 0;
- fi.interval = cp->timeperframe;
- cp->capability = V4L2_CAP_TIMEPERFRAME;
-
- ret = hm5065_s_frame_interval(sd, &fi);
- if (ret)
- return ret;
-
- cp->timeperframe = fi.interval;
- return 0;
-}
-
static int hm5065_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
@@ -2125,8 +2085,6 @@ static const struct v4l2_subdev_pad_ops hm5065_pad_ops = {
static const struct v4l2_subdev_video_ops hm5065_video_ops = {
.g_frame_interval = hm5065_g_frame_interval,
.s_frame_interval = hm5065_s_frame_interval,
- .g_parm = hm5065_g_parm,
- .s_parm = hm5065_s_parm,
.s_stream = hm5065_s_stream,
};
--
2.20.1

58
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0070-media-sun6i-csi-Port-to-4.17-use-v4l2_g_parm_cap-v4l.patch Normal file
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@ -0,0 +1,58 @@
From 0499b2f267962ce5e4c56d9be15f1366a524bb88 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 20 Apr 2018 04:03:28 +0200
Subject: [PATCH 70/82] media: sun6i-csi: Port to 4.17 - use
v4l2_g_parm_cap/v4l2_s_parm_cap helpers
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/media/platform/sun6i-csi/sun6i_csi.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sun6i-csi/sun6i_csi.c
index 2bd746c3efc4..3d13e26b2312 100644
--- a/drivers/media/platform/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sun6i-csi/sun6i_csi.c
@@ -454,21 +454,16 @@ static int sun6i_enum_frameintervals(struct file *file, void *priv,
return 0;
}
-
static int sun6i_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
{
struct sun6i_csi *csi = video_drvdata(file);
struct sun6i_csi_subdev *csi_sd;
- if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
csi_sd = sun6i_get_enabled_subdev(csi);
if (csi_sd == NULL)
return -ENXIO;
- a->parm.capture.readbuffers = 0;
- return v4l2_subdev_call(csi_sd->sd, video, g_parm, a);
+ return v4l2_g_parm_cap(video_devdata(file), csi_sd->sd, a);
}
static int sun6i_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
@@ -476,15 +471,11 @@ static int sun6i_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
struct sun6i_csi *csi = video_drvdata(file);
struct sun6i_csi_subdev *csi_sd;
- if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- return -EINVAL;
-
csi_sd = sun6i_get_enabled_subdev(csi);
if (csi_sd == NULL)
return -ENXIO;
- a->parm.capture.readbuffers = 0;
- return v4l2_subdev_call(csi_sd->sd, video, s_parm, a);
+ return v4l2_g_parm_cap(video_devdata(file), csi_sd->sd, a);
}
static int sun6i_enum_input(struct file *file, void *priv,
--
2.20.1

72
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@ -0,0 +1,72 @@
From 3bfe739a6da69c2a51dbd6d4288975bedaee04f8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Jun 2018 07:58:15 +0200
Subject: [PATCH 71/82] ARM: dts: sun8i-a83t: Add missing clock properties to
cpu nodes
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c09d8ee2f7c5..17371e0614e2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -77,6 +77,8 @@
};
cpu@1 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
@@ -87,6 +89,8 @@
};
cpu@2 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
@@ -97,6 +101,8 @@
};
cpu@3 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
@@ -122,6 +128,8 @@
};
cpu@101 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
@@ -132,6 +140,8 @@
};
cpu@102 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
@@ -142,6 +152,8 @@
};
cpu@103 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <1200000000>;
device_type = "cpu";
--
2.20.1

84
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@ -0,0 +1,84 @@
From 6352f285dc5071be981ac30d72b4fbd11bed7fcd Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Jun 2018 07:58:54 +0200
Subject: [PATCH 72/82] ARM: dts: sun8i-a83t: Add missing cooling-cells
properties to cpu nodes
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 17371e0614e2..cb0607580d04 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -72,8 +72,6 @@
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
};
cpu@1 {
@@ -86,6 +84,7 @@
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
+ #cooling-cells = <2>;
};
cpu@2 {
@@ -98,6 +97,7 @@
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
+ #cooling-cells = <2>;
};
cpu@3 {
@@ -110,6 +110,7 @@
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
+ #cooling-cells = <2>;
};
cpu100: cpu@100 {
@@ -123,8 +124,6 @@
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
#cooling-cells = <2>;
- cooling-min-level = <0>;
- cooling-max-level = <7>;
};
cpu@101 {
@@ -137,6 +136,7 @@
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
+ #cooling-cells = <2>;
};
cpu@102 {
@@ -149,6 +149,7 @@
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
+ #cooling-cells = <2>;
};
cpu@103 {
@@ -161,6 +162,7 @@
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
+ #cooling-cells = <2>;
};
};
--
2.20.1

71
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@ -0,0 +1,71 @@
From 99c501a975040dd3a233d5ec6193c5a9f32d7b2e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Jun 2018 07:59:21 +0200
Subject: [PATCH 73/82] ARM: dts: sun8i-a83t: Add labels to all cpu nodes
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index cb0607580d04..7b87029904bc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -74,7 +74,7 @@
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
clocks = <&ccu CLK_C0CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
@@ -87,7 +87,7 @@
#cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
clocks = <&ccu CLK_C0CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
@@ -100,7 +100,7 @@
#cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
clocks = <&ccu CLK_C0CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
@@ -126,7 +126,7 @@
#cooling-cells = <2>;
};
- cpu@101 {
+ cpu101: cpu@101 {
clocks = <&ccu CLK_C1CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
@@ -139,7 +139,7 @@
#cooling-cells = <2>;
};
- cpu@102 {
+ cpu102: cpu@102 {
clocks = <&ccu CLK_C1CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
@@ -152,7 +152,7 @@
#cooling-cells = <2>;
};
- cpu@103 {
+ cpu103: cpu@103 {
clocks = <&ccu CLK_C1CPUX>;
clock-names = "cpu";
compatible = "arm,cortex-a7";
--
2.20.1

103
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0074-Allow-to-disable-cluster2-on-A83T-permanently.patch Normal file
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@ -0,0 +1,103 @@
From 177d470754881e3cff95d90e6b6d79d96ae92ccd Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 28 Jul 2018 00:42:25 +0200
Subject: [PATCH 74/82] Allow to disable cluster2 on A83T permanently
Hotplug is broken for now. Therfore this.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-a83t.dtsi | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 8bba9ccd2592..7a1b6154cda9 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -41,6 +41,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#define A83T_C1_DISABLE
+
/dts-v1/;
#include "sun8i-a83t.dtsi"
@@ -188,9 +190,11 @@
cpu-supply = <&reg_dcdc2>;
};
+#ifndef A83T_C1_DISABLE
&cpu100 {
cpu-supply = <&reg_dcdc3>;
};
+#endif
&cpu0_thermal {
trips {
@@ -214,6 +218,7 @@
};
};
+#ifndef A83T_C1_DISABLE
&cpu1_thermal {
trips {
cpu1_hot: cpu_hot {
@@ -235,6 +240,7 @@
};
};
};
+#endif
&csi0 {
status = "okay";
@@ -516,7 +522,9 @@
&reg_dcdc3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
+#ifndef A83T_C1_DISABLE
regulator-always-on;
+#endif
regulator-name = "vdd-cpu-B";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7b87029904bc..0bc7482744d7 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -113,6 +113,7 @@
#cooling-cells = <2>;
};
+#ifndef A83T_C1_DISABLE
cpu100: cpu@100 {
clocks = <&ccu CLK_C1CPUX>;
clock-names = "cpu";
@@ -164,6 +165,7 @@
reg = <0x103>;
#cooling-cells = <2>;
};
+#endif
};
timer {
@@ -274,6 +276,7 @@
};
};
+#ifndef A83T_C1_DISABLE
cpu1_opp_table: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
@@ -326,6 +329,7 @@
clock-latency-ns = <244144>; /* 8 32k periods */
};
};
+#endif
soc {
compatible = "simple-bus";
--
2.20.1

54
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0075-Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-p.patch Normal file
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@ -0,0 +1,54 @@
From dc476b21de3ab98df3b94514d995bf4fc0fa0db4 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 18 Aug 2017 13:55:48 +0200
Subject: [PATCH 75/82] Make microbuttons on Orange Pi PC and PC 2 work as
power off buttons
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 2 +-
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 2 +-
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 245fd658defb..a30c4fae5466 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -95,7 +95,7 @@
sw4 {
label = "sw4";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 83f1866ed9e7..056cb587f3c0 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -95,7 +95,7 @@
sw4 {
label = "sw4";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index af8e3fe26e20..4846d76dd908 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -98,7 +98,7 @@
sw4 {
label = "sw4";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
--
2.20.1

62
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0076-arm64-dts-sun50i-h5-Add-mali-GPU-node.patch Normal file
View file

@ -0,0 +1,62 @@
From 30bbeb66d0f9cc6f49cc95e60443eeca952b119c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Jun 2018 07:55:34 +0200
Subject: [PATCH 76/82] arm64: dts: sun50i-h5: Add mali GPU node
https://github.com/jernejsk/LibreELEC.tv/blob/aw_h5_init/projects/Allwinner/devices/H5/patches/linux/20-add-mali-node.patch
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 38 ++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index acd90f390e88..67e2246a6374 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -94,6 +94,44 @@
method = "smc";
};
+ soc {
+ mali: gpu@1280000 {
+ compatible = "allwinner,sun50i-h5-mali",
+ "arm,mali-450";
+ reg = <0x01e80000 0x30000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
--
2.20.1

68
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0077-drm-bridge-synopsys-dw_hdmi-Add-a-quirk-to-automatic.patch Normal file
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@ -0,0 +1,68 @@
From 796acec22305cbd6c1bf6dcc4e103482ca525025 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Thu, 8 Mar 2018 17:16:22 +0100
Subject: [PATCH 77/82] drm/bridge/synopsys: dw_hdmi: Add a quirk to
automatically set CTS
On some SoCs with DW HDMI, like Allwinner H3, HDMI audio doesn't work
well if CTS is not set automatically. Add a quirk for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 26 ++++++++++++++---------
include/drm/bridge/dw_hdmi.h | 2 ++
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 5971976284bf..822d0093a990 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -424,16 +424,22 @@ static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
unsigned int n)
{
- /* Must be set/cleared first */
- hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
-
- /* nshift factor = 0 */
- hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
-
- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
- hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
- hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+ if (!hdmi->plat_data->auto_cts) {
+ /* Must be set/cleared first */
+ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+
+ /* nshift factor = 0 */
+ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
+
+ hdmi_writeb(hdmi,
+ ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
+ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+ hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
+ hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+ } else {
+ /* set automatic CTS calculation */
+ hdmi_writeb(hdmi, 0x00, HDMI_AUD_CTS3);
+ }
hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index ccb5aa8468e0..b6a878455364 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -129,6 +129,8 @@ struct dw_hdmi_plat_data {
unsigned long input_bus_format;
unsigned long input_bus_encoding;
+ bool auto_cts;
+
/* Vendor PHY support */
const struct dw_hdmi_phy_ops *phy_ops;
const char *phy_name;
--
2.20.1

30
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0078-drm-sun4i-Enable-auto_cts-quirk-for-DW-HDMI.patch Normal file
View file

@ -0,0 +1,30 @@
From aab02e1c386fa2ab761aea583b59ce72824f70c4 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Thu, 8 Mar 2018 17:21:29 +0100
Subject: [PATCH 78/82] drm/sun4i: Enable auto_cts quirk for DW HDMI
Allwinner SoCs with DW HDMI don't output any sound if auto CTS option is
not enabled.
Enable it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 31875b636434..9aaec57f7441 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -156,6 +156,7 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
sun8i_hdmi_phy_init(hdmi->phy);
+ plat_data->auto_cts = true;
plat_data->mode_valid = &sun8i_dw_hdmi_mode_valid;
plat_data->phy_ops = sun8i_hdmi_phy_get_ops();
plat_data->phy_name = "sun8i_dw_hdmi_phy";
--
2.20.1

64
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0079-HACK-Enable-HDMI-audio-on-H3-H5.patch Normal file
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@ -0,0 +1,64 @@
From 0bc585fb429d295cd9ff0f35326e52e212053af2 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Thu, 8 Mar 2018 17:23:01 +0100
Subject: [PATCH 79/82] HACK: Enable HDMI audio on H3/H5
This is quick way to enable HDMI audio, but it is not a proper way to do
it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3b8b2234ab4d..586ce53fc058 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -743,6 +743,35 @@
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ //status = "disabled";
+ };
+
+ sound_hdmi: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "allwinner,hdmi";
+ simple-audio-card,mclk-fs = <256>;
+ //status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s2>;
+ };
+ };
+
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-codec";
@@ -860,6 +889,7 @@
};
hdmi: hdmi@1ee0000 {
+ #sound-dai-cells = <0>;
compatible = "allwinner,sun8i-h3-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
--
2.20.1

66
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0080-Add-support-for-my-private-Sapomat-device.patch Normal file
View file

@ -0,0 +1,66 @@
From 75347dd025a7da146944c69c724dbd6d24e10100 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 18 Aug 2017 13:56:06 +0200
Subject: [PATCH 80/82] Add support for my private Sapomat device
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-h3-orangepi-pc-sapomat.dts | 34 +++++++++++++++++++
2 files changed, 35 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-pc-sapomat.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b5bd3de87c33..c3720b0ffbe1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1043,6 +1043,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-pc.dtb \
+ sun8i-h3-orangepi-pc-sapomat.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-sapomat.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-sapomat.dts
new file mode 100644
index 000000000000..55c82d5fb63f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-sapomat.dts
@@ -0,0 +1,34 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "sun8i-h3-orangepi-pc.dts"
+
+/ {
+ model = "Xunlong Orange Pi PC Sapomat";
+
+ sapomat_gpio_keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sapomat_btn_pins>;
+
+ red_btn {
+ label = "Red Button";
+ linux,code = <BTN_4>;
+ gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; /* PC4 */
+ };
+
+ green_btn {
+ label = "Green Button";
+ linux,code = <BTN_5>;
+ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
+ };
+ };
+};
+
+&pio {
+ sapomat_btn_pins: btn_pins@0 {
+ pins = "PC4", "PC7";
+ function = "gpio_in";
+ bias-pull-up;
+ };
+};
--
2.20.1

27
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0081-Support-Castles-Vega5000-PoS-terminal-USB.patch Normal file
View file

@ -0,0 +1,27 @@
From 499a575b5a0eb15899fdf3d79292b44e030d542a Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 24 Mar 2018 19:30:22 +0100
Subject: [PATCH 81/82] Support Castles Vega5000 PoS terminal USB
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/usb/class/cdc-acm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 5b442bc68a76..7352548a7e6f 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -1769,6 +1769,9 @@ static const struct usb_device_id acm_ids[] = {
{ USB_DEVICE(0x22b8, 0x2d9a), /* modem + AT port + diagnostics + NMEA */
.driver_info = NO_UNION_NORMAL, /* handle only modem interface */
},
+ { USB_DEVICE(0x0ca6, 0xa050), /* Castles Technology VEGA 5000 */
+ .driver_info = NO_UNION_NORMAL, /* reports zero length descriptor */
+ },
{ USB_DEVICE(0x0572, 0x1329), /* Hummingbird huc56s (Conexant) */
.driver_info = NO_UNION_NORMAL, /* union descriptor misplaced on
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-0082-ARM-dts-sun8i-a83t-tbs-a711-Change-MMC0-bus-width-to.patch Normal file
View file

@ -0,0 +1,28 @@
From 81f714ab3bd523c7d8644e8d7b85544252c12dc4 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 15 Oct 2018 04:28:07 +0200
Subject: [PATCH 82/82] ARM: dts: sun8i-a83t-tbs-a711: Change MMC0 bus-width to
4
The actual hardware has 4 data lines. Use them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 7a1b6154cda9..f320f915b413 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -402,6 +402,7 @@
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
+ bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
--
2.20.1

229
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-axp-adjustements.patch.disabled Normal file
View file

@ -0,0 +1,229 @@
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 44097a3e0..a0cbdbb2c 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -756,6 +756,14 @@ config LEDS_NIC78BX
To compile this driver as a module, choose M here: the module
will be called leds-nic78bx.
+config LEDS_AXP20X
+ tristate "LED support for AXP20X-like PMICs (AXP813, ...)"
+ depends on LEDS_CLASS && MFD_AXP20X
+ help
+ This option enables support for on-chip LED drivers on
+ AXP20X-like PMICs.
+
+
comment "LED Triggers"
source "drivers/leds/trigger/Kconfig"
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 420b5d2cf..a8149fb6e 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_MT6323) += leds-mt6323.o
obj-$(CONFIG_LEDS_LM3692X) += leds-lm3692x.o
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
obj-$(CONFIG_LEDS_LM3601X) += leds-lm3601x.o
+obj-$(CONFIG_LEDS_AXP20X) += leds-axp20x.o
# LED SPI Drivers
obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o
diff --git a/drivers/leds/leds-axp20x.c b/drivers/leds/leds-axp20x.c
new file mode 100644
index 000000000..de33c1d83
--- /dev/null
+++ b/drivers/leds/leds-axp20x.c
@@ -0,0 +1,138 @@
+/*
+ * LED Driver for X-Powers AXP813 PMIC.
+ *
+ * Copyright(c) 2017 Ondrej Jirman <megous@megous.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/mfd/axp20x.h>
+
+#define AXP813_CHGLED_CTRL_MASK BIT(3)
+#define AXP813_CHGLED_CTRL_CHARGER BIT(3)
+#define AXP813_CHGLED_CTRL_USER 0
+
+#define AXP813_CHGLED_USER_STATE_MASK GENMASK(5, 4)
+#define AXP813_CHGLED_USER_STATE_OFFSET 4
+#define AXP813_CHGLED_USER_STATE_OFF 0
+#define AXP813_CHGLED_USER_STATE_BLINK_SLOW 1
+#define AXP813_CHGLED_USER_STATE_BLINK_FAST 2
+#define AXP813_CHGLED_USER_STATE_ON 3
+
+struct axp20x_led {
+ struct led_classdev cdev;
+ struct regmap *regmap;
+};
+
+static int axp20x_led_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ struct axp20x_led *led =
+ container_of(led_cdev, struct axp20x_led, cdev);
+ unsigned int val;
+
+ val = value == LED_OFF ? AXP813_CHGLED_USER_STATE_OFF :
+ AXP813_CHGLED_USER_STATE_ON;
+
+ return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_USER_STATE_MASK,
+ val << AXP813_CHGLED_USER_STATE_OFFSET);
+
+}
+
+static int axp20x_led_probe(struct platform_device *pdev)
+{
+ struct axp20x_dev *axp20x;
+ struct axp20x_led *led;
+ int ret;
+
+ if (!of_device_is_available(pdev->dev.of_node))
+ return -ENODEV;
+
+ axp20x = dev_get_drvdata(pdev->dev.parent);
+ if (!axp20x)
+ return -EINVAL;
+
+ led = devm_kzalloc(&pdev->dev,
+ sizeof(struct axp20x_led),
+ GFP_KERNEL);
+ if (!led)
+ return -ENOMEM;
+
+ led->regmap = axp20x->regmap;
+
+ led->cdev.name = "chgled";
+ led->cdev.brightness_set_blocking = axp20x_led_set;
+ led->cdev.brightness = LED_OFF;
+ led->cdev.max_brightness = 1;
+
+ ret = led_classdev_register(pdev->dev.parent, &led->cdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register led %s\n",
+ led->cdev.name);
+ return ret;
+ }
+
+ ret = regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_CTRL_MASK,
+ AXP813_CHGLED_CTRL_USER);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable user cnotrol\n");
+ }
+
+ ret = axp20x_led_set(&led->cdev, led->cdev.brightness);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to init led %s\n",
+ led->cdev.name);
+ }
+
+ platform_set_drvdata(pdev, led);
+ return 0;
+}
+
+static int axp20x_led_remove(struct platform_device *pdev)
+{
+ struct axp20x_led *led = platform_get_drvdata(pdev);
+
+ axp20x_led_set(&led->cdev, LED_OFF);
+
+ regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
+ AXP813_CHGLED_CTRL_MASK,
+ AXP813_CHGLED_CTRL_CHARGER);
+
+ led_classdev_unregister(&led->cdev);
+
+ return 0;
+}
+
+static const struct of_device_id axp20x_leds_of_match[] = {
+ { .compatible = "x-powers,axp813-leds", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_leds_of_match);
+
+static struct platform_driver axp20x_led_driver = {
+ .driver = {
+ .name = "axp20x-leds",
+ .of_match_table = axp20x_leds_of_match,
+ },
+ .probe = axp20x_led_probe,
+ .remove = axp20x_led_remove,
+};
+
+module_platform_driver(axp20x_led_driver);
+
+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
+MODULE_DESCRIPTION("LED driver for AXP813 PMIC");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:leds-axp20x");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 0be511dd9..a9bdf3cdd 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -24,6 +24,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include <linux/regulator/userspace-consumer.h>
#include <linux/mfd/axp20x.h>
#include <linux/mfd/core.h>
#include <linux/of_device.h>
@@ -130,6 +131,7 @@ static const struct regmap_range axp288_volatile_ranges[] = {
regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
+ regmap_reg_range(AXP22X_CHRG_CTRL3, AXP22X_CHRG_CTRL3),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
@@ -762,6 +764,16 @@ static const struct mfd_cell axp809_cells[] = {
},
};
+static struct regulator_bulk_data vcc_vb = {
+ .supply = "vcc-vb",
+};
+
+static struct regulator_userspace_consumer_data vcc_vb_data = {
+ .name = "vcc-vb",
+ .num_supplies = 1,
+ .supplies = &vcc_vb,
+};
+
static const struct mfd_cell axp813_cells[] = {
{
.name = "axp221-pek",
@@ -778,6 +790,16 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp813-battery-power-supply",
+ }, {
+ .name = "axp20x-usb-power-supply",
+ .of_compatible = "x-powers,axp813-usb-power-supply",
+ }, {
+ .name = "axp20x-leds",
+ .of_compatible = "x-powers,axp813-leds",
+ }, {
+ .name = "reg-userspace-consumer",
+ .platform_data = &vcc_vb_data,
+ .pdata_size = sizeof(vcc_vb_data),
},
};

24
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-remove-old-ths-node.patch Normal file
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@ -0,0 +1,24 @@
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 586ce53fc..e72c24470 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -590,19 +590,6 @@
};
};
- ths: ths@1c25000 {
- #thermal-sensor-cells = <0>;
- compatible = "allwinner,sun8i-h3-ths";
- reg = <0x01c25000 0x400>,
- <0x01c14234 0x4>;
- reg-names = "ths", "calibration";
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_BUS_THS>;
- reset-names = "ahb";
- clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
- clock-names = "ahb", "ths";
- };
-
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;

346
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@ -0,0 +1,346 @@
From 6eb4890e1b83490864f18d3926182069e54a4dfb Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 12 Nov 2017 23:09:14 +0100
Subject: [PATCH] sound: soc: ac100-codec: Initial implementation
This driver provides AC100 codec controls.
Note: This does not yet provide anything, it's just a skeleton
for a future driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
sound/soc/sunxi/Kconfig | 11 ++
sound/soc/sunxi/Makefile | 1 +
sound/soc/sunxi/ac100-codec.c | 291 ++++++++++++++++++++++++++++++++++
3 files changed, 303 insertions(+)
create mode 100644 sound/soc/sunxi/ac100-codec.c
diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
index 22408bc2d6ec6..e276cc94a8c5e 100644
--- a/sound/soc/sunxi/Kconfig
+++ b/sound/soc/sunxi/Kconfig
@@ -20,6 +20,17 @@ config SND_SUN8I_CODEC
Say Y or M if you want to add sun8i digital audio codec support.
+config SND_AC100_CODEC
+ tristate "Allwinner (X-Powers) AC100 audio codec"
+ depends on OF
+ depends on MACH_SUN8I || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ This option enables the audio codec support for Allwinner (X-Powers)
+ AC100 chip.
+
+ Say Y or M if you want to add AC100 audio codec support.
+
config SND_SUN8I_CODEC_ANALOG
tristate "Allwinner sun8i Codec Analog Controls Support"
depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
index 4a9ef67386caf..83461fdbfaa2a 100644
--- a/sound/soc/sunxi/Makefile
+++ b/sound/soc/sunxi/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
diff --git a/sound/soc/sunxi/ac100-codec.c b/sound/soc/sunxi/ac100-codec.c
new file mode 100644
index 0000000000000..d5438815be754
--- /dev/null
+++ b/sound/soc/sunxi/ac100-codec.c
@@ -0,0 +1,291 @@
+/*
+ * This driver supports the controls for X-Powers (Allwinner)
+ * AC100 audio codec. This codec is co-packaged with AXP81x PMICs.
+ *
+ * (C) Copyright 2017 Ondrej Jirman <megous@megous.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/mfd/ac100.h>
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+/*
+ * Reasearch
+ * ---------
+ *
+ * Features:
+ * 2 A/D
+ * 2 D/A
+ * 2 I2S/PCM #1 and #2
+ * 1 PCM mono #3 muxable with I2S #2
+ * 3 mic inputs (mic #2 and #3 exclusively muxable at input)
+ * 1 line in (directly or through amp)
+ * 1 aux input
+ * all input signals mixable directly into output (bypass AD/DA)
+ *
+ * outputs:
+ * HPOUTL - headphone left
+ * HPOUTR - headphone right
+ * LINEOUT - line out differential
+ * EAROUT - earpeiece differential
+ * SPKOUT1 - SPOL left speaker differnetial
+ * SPKOUT2 - SPOR right speaker differnetial
+ *
+ * Power up:
+ * LDOIN - 1.5-3.3V external power
+ * AVCC - analog power 3V
+ * CPVDD - 1.8V
+ * VDD-IO1 - power for I2S #1 and #2 1.8/3V
+ * VDD-IO2 - power for I2S #3 1.8/3V
+ * VCC-RTC - power for RTC 1.8/3V
+ *
+ * Clocks: page 28
+ * SYSCLK must be 24576000 Hz (48kHz) or 22579200 Hz (44.1kHz)
+ * - Source I2S1CLK/MCLK1
+ * - If SRC# module is used SYSCLK must be generated by PLL
+ *
+ * A/D:
+ * ADC_APC_CTRL B15 B11 enable/disable A/D to save power
+ * ADC_APC_CTRL B14-12 B10-8 volume control for A/D
+ * ADC_DIG_CTRL B15 enable/disable digital A/D to save power
+ * ADDA_FS_I2S1 ADDA_FS_I2S2 - select sample rate
+ *
+ * D/A:
+ * OMIXER_DACA_CTRL B15-14 enable/disable D/A channels
+ * DAC_DIG_CTRL B15 enable/disable digital D/A
+ *
+ * Mixer:
+ * - 2 channels DAC Output mixers
+ * - inputs:
+ * - LINEINL/R
+ * - AXIL/R
+ * - MIC1P/N,MIC2P/N
+ * - Stereo DAC output
+ * - 2 channels ADC Record mixers
+ * - inputs:
+ * - LINEINL/R
+ * - AXIL/R
+ * - MIC1P/N,MIC2P/N
+ * - Stereo DAC output
+ * - Digital mixers
+ * - avaliable on:
+ * - before stereo DAC - DAC_MXR_SRC
+ * - I2S1 output - I2S1_MXR_SRC
+ * - I2S2 output - I2S2_MXR_SRC
+ * - Analogue inputs
+ * - LINEINL/R - 1 ch. mono
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - -9dB to 12dB in 1.5dB step by LINEIN_DIFF_PREG
+ * - AXIL/R - 2 ch. stereo
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - programmable volume level adj. and mute
+ * - -9dB to 12dB in 1.5dB steps by AXI_PREG
+ * - MIC1P/N - has preamp
+ * - MIC2P/N - has preamp
+ * - MIC3P/N - has preamp muxed with MIC2 (sel by ADC_SRCBST_CTRL B7)
+ * - can be mixed into ADC record mixer or DAC output mixer
+ * - preamps enable at ADC_SRCBST_CTRL B15 and B11
+ * - preamp gain at MIC1BOOST MIC2BOOST
+ * - Analogue outputs:
+ * - HPOUTL/R, HPOUTFB - 2ch. headphones
+ * - sources output mixer or directly from DAC
+ * - sel HPOUT_CTRL B15 B14
+ * - mute HPOUT_CTRL B13 B12
+ * - power amp
+ * - powerdown/up HPOUT_CTRL B11
+ * - volume HP_VOL[5:0] - 64dB range in 1dB step from 0dB to -62dB
+ * - mute by using 0 for HP_VOL[5:0]
+ * - DC offset cancellation (POP noise) HP_DCRM_EN
+ * - This bit must be set 0xf before headphone PA enabled, and this bit
+ * must be set 0x0 before headphone PA disabled.
+ * - zero cross to prevent noise/clicsk on volume change ZCROSS_EN
+ * - SPOLP/N, SPORP/N 2 ch. speakers (mono/stereo)
+ * - source for SPOLP
+ * - left output mixer or (left+right) output mixer
+ * - source for SPORP
+ * - right output mixer or (left+right) output mixer
+ * - volume 43.5dB rang in 1.5dB step from -43.5dB to 0dB
+ * - amp enable SPKOUT_CTRL B11 B7
+ * - EAROUTP/N - 1 ch earpeice
+ * - source left DAC, right DAC, left output mixer or right output mixer
+ * - volume ERPOUT_CTRL[4:0] 43.5dB range in 1.5dB step from -43.5dB to 0dB
+ * - power amp enable ERPOUT_CTRL B5
+ * - LINEOUTP/N - 1ch line out
+ * - source MIC1 preamp, MIC2 preamp, left output mix or right output mix
+ * - volume 10.5dB range in 1.5dB step from -4.5dB to 6dB
+ * - out buffer power up/down LOUT_CTRL B4
+ *
+ * Jack insert detection:
+ * - HBIAS current detection
+ * - 5bit ADC sample rate 16/32/64/128Hz
+ * - HMIC_STATUS[12:8] - ADC value
+ * - 2 thresholds TH1 for plug connection, TH2 for key press
+ * - can periodically trigger interrupts during key press (HBIAS above TH2)
+ *
+ * Interrupts:
+ * - FALLING_EDGE
+ * - for:
+ * - KEYDOWN
+ * - KEYUP
+ * - PLUG_IN
+ * - PLUG_OUT
+ * - HMIC_DATA
+ *
+ * High Pass Filter:
+ * - remove DC offset, can be disabled
+ *
+ * AGC:
+ * - automatic gain control before ADC input channels
+ * - params:
+ * - attack, decay time - 32/fs to 2^15*32/fs
+ * - target gain - –1dB to –30dB relative to a full-scale signal
+ * - noise threshold - –30dB to –90dB of full-scale (mute if input below this level)
+ * - max gain 0dB to 40dB in steps of 0.5dB
+ * - hysteresis - for noise detection in terms of signal level
+ * - debounce time - hysteresis for noise det in terms of time
+ * - also provides some output flags:
+ * - noise threshold reached
+ * - current gain
+ * - agc saturated (gain could get higher for the given input, but limited by
+ * params)
+ * - adc saturated - clipping at ADC input stage
+ *
+ * DRC:
+ * - dynamic range control for digital playback path
+ * - energy filter
+ * - compressor
+ * - smooth filter
+ * - can be disabled
+ */
+
+#define AC100_HMIC_DATA_MASK GENMASK(12, 8)
+#define AC100_HMIC_DATA_OFF 8
+#define AC100_HMIC_PULLOUT_PENDING BIT(4)
+#define AC100_HMIC_PLUGIN_PENDING BIT(3)
+#define AC100_HMIC_KEYUP_PENDING BIT(2)
+#define AC100_HMIC_KEYDOWN_PENDING BIT(1)
+#define AC100_HMIC_DATA_PENDING BIT(0)
+
+struct ac100_codec {
+ struct device *dev;
+ struct regmap *regmap;
+ int irq;
+};
+
+static irqreturn_t ac100_codec_irq(int irq, void *data)
+{
+ struct ac100_codec *codec = data;
+ unsigned int val = 0;
+ int ret;
+
+ /* read status */
+ ret = regmap_read(codec->regmap, AC100_HMIC_STATUS, &val);
+ if (ret)
+ return IRQ_HANDLED;
+
+ if (val & AC100_HMIC_PULLOUT_PENDING) {
+ dev_info(codec->dev, "IRQ: Pull out");
+ }
+
+ if (val & AC100_HMIC_PLUGIN_PENDING) {
+ dev_info(codec->dev, "IRQ: Plug in");
+ }
+
+ if (val & AC100_HMIC_KEYUP_PENDING) {
+ dev_info(codec->dev, "IRQ: Key up");
+ }
+
+ if (val & AC100_HMIC_KEYDOWN_PENDING) {
+ dev_info(codec->dev, "IRQ: Key down");
+ }
+
+ if (val & AC100_HMIC_DATA_PENDING) {
+ dev_info(codec->dev, "IRQ: Data");
+ }
+
+ /* clear status */
+ ret = regmap_write(codec->regmap, AC100_HMIC_STATUS, 0);
+ if (ret)
+ return IRQ_HANDLED;
+
+ return IRQ_HANDLED;
+}
+
+static int ac100_codec_probe(struct platform_device *pdev)
+{
+ struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
+ struct ac100_codec *codec;
+ int ret;
+
+ codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
+ if (!codec)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, codec);
+ codec->dev = &pdev->dev;
+ codec->regmap = ac100->regmap;
+
+ codec->irq = platform_get_irq(pdev, 0);
+ if (codec->irq < 0) {
+ dev_err(&pdev->dev, "No IRQ resource\n");
+ return codec->irq;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev, codec->irq, NULL,
+ ac100_codec_irq,
+ IRQF_SHARED | IRQF_ONESHOT,
+ dev_name(&pdev->dev), codec);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not request IRQ\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int ac100_codec_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct ac100_codec *codec = snd_soc_card_get_drvdata(card);
+
+ return 0;
+}
+
+static const struct of_device_id ac100_codec_of_match[] = {
+ { .compatible = "x-powers,ac100-codec" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ac100_codec_of_match);
+
+static struct platform_driver ac100_codec_driver = {
+ .driver = {
+ .name = "ac100-codec",
+ .of_match_table = ac100_codec_of_match,
+ },
+ .probe = ac100_codec_probe,
+ .remove = ac100_codec_remove,
+};
+module_platform_driver(ac100_codec_driver);
+
+MODULE_DESCRIPTION("X-Powers AC100 codec driver");
+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ac100-codec");

46
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0000-unlock-h5-dvfs.patch Normal file
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@ -0,0 +1,46 @@
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 67e2246a6..e37d779f8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -55,7 +55,6 @@
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
- clock-frequency = <1200000000>;
#cooling-cells = <2>;
cooling-min-level = <0>;
cooling-max-level = <15>;
@@ -67,7 +66,6 @@
reg = <1>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
- clock-frequency = <1200000000>;
};
cpu@2 {
@@ -76,7 +74,6 @@
reg = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
- clock-frequency = <1200000000>;
};
cpu@3 {
@@ -85,10 +82,16 @@
reg = <3>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
- clock-frequency = <1200000000>;
};
};
+ reg_cpu_fallback: reg_cpu_fallback {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpux-dummy";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";

52
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0001-arm64-allwinner-a64-enable-Wi-Fi-for-Pine64.patch Normal file
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@ -0,0 +1,52 @@
From a5b709a81ad9a5e2e6e4be6a696711ad7f35ad57 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Thu, 9 Feb 2017 00:18:56 +0800
Subject: [PATCH 001/146] arm64: allwinner: a64: enable Wi-Fi for Pine64
The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter
one provides I/O voltage).
Add device node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 1b9b92e541d2..d06b5b88f60e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -62,6 +62,11 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
};
&ehci0 {
@@ -109,6 +114,17 @@
status = "okay";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_dldo4>;
+ vqmmc-supply = <&reg_eldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
--
2.17.1

31
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0001-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch Normal file
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@ -0,0 +1,31 @@
From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 12 Jan 2019 20:17:19 -0600
Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround
As instability in the architectural timer has been observed on multiple
devices using this SoC, inluding the Pine64 and the Orange Pi Win,
enable the workaround in the SoC's device tree.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index bf9b719481c4..8171c0a7f265 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -200,6 +200,7 @@
timer {
compatible = "arm,armv8-timer";
+ allwinner,erratum-unknown1;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
--
2.19.2

30
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0001-pinctrl-sunxi-Disable-strict-mode-for-A64-pinctrl-dr.patch Normal file
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@ -0,0 +1,30 @@
From 4aa7894de903660f5c8d5155f2590d00022ca95e Mon Sep 17 00:00:00 2001
From: WaterByWind <WaterByWind@users.noreply.github.com>
Date: Sun, 14 Apr 2019 16:16:09 -0400
Subject: [PATCH] pinctrl: sunxi: Disable strict mode for A64 pinctrl driver
With kernel 4.15.y (and later):
* Strict mode was enabled by default via commit 1396007286b1e2fd5dd10ae6a5ccaaaed51ab762 which can/will cause breakage with existing implementations.
* The ability to configure strict mode was added via commit aae842a3ff3385f27f1df8a9ee1494a416ec032d to allow older drivers to maintain existing behavior and avoid breakage.
* Commit cd70387f892205bcd7b8093b0837269b0739cbe0 had then explicitly disabled strict mode for most other existing SoCs but did not include A64.
This change is to update the A64 pinctrl driver similar to the other pre-existing SoC pinctrl drivers.
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
index 7b83d3755a0e..bea52c5a9afa 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
@@ -578,6 +578,7 @@ static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
.pins = a64_pins,
.npins = ARRAY_SIZE(a64_pins),
.irq_banks = 3,
+ .disable_strict_mode = true,
};
static int a64_pinctrl_probe(struct platform_device *pdev)
--
2.20.1 (Apple Git-117)

72
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@ -0,0 +1,72 @@
From fa666ec858630bad5d3bf2952c96460302065102 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 6 May 2017 19:29:44 +0800
Subject: [PATCH 002/146] arm64: allwinner: a64: add Mali device node
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d3daf90a8715..0f69f3593975 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -157,6 +157,20 @@
compatible = "linux,spdif-dit";
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x4000000>;
+ alignment = <0x2000>;
+ linux,cma-default;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@@ -664,6 +678,33 @@
};
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun50i-a64-mali",
+ "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+ memory-region = <&cma>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
--
2.17.1

35
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0003-net-stmmac-dwmac-sun8i-support-RGMII-modes-with-PHY-.patch Normal file
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@ -0,0 +1,35 @@
From 98800eeb2244387e821f4af8d21ccf2deaf18da0 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Mon, 21 Aug 2017 23:02:32 +0800
Subject: [PATCH 003/146] net: stmmac: dwmac-sun8i: support RGMII modes with
PHY internal delay
Some boards uses a PHY with internal delay with an Allwinner SoC.
Support these PHY modes in the driver.
As the driver has no configuration registers for these modes, just treat
them as ordinary RGMII.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index f9a61f90cfbc..3c18f4a9dd6c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -933,6 +933,9 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
/* default */
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
break;
case PHY_INTERFACE_MODE_RMII:
--
2.17.1

35
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0004-arm64-allwinner-a64-disable-the-RTL8211E-internal-RX.patch Normal file
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@ -0,0 +1,35 @@
From e89cb84d23d2537cd1b256afdd0fe880648ee1a9 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Mon, 21 Aug 2017 23:08:08 +0800
Subject: [PATCH 004/146] arm64: allwinner: a64: disable the RTL8211E internal
RX delay on Pine64+
Some Pine64+ boards have a broken RTL8211E PHY, which cannot work
reliably in 1000Base-T mode with default configuration.
A solution is passed to Pine64, which is said to be disabling the
internal RX delay of the PHY.
Enable the hack by set the PHY mode to RGMII-TXID.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index 24f1aac366d6..ed715426fffc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -52,7 +52,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
--
2.17.1

50
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0005-drm-gem-cma-Export-with-handle-allocator.patch Normal file
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@ -0,0 +1,50 @@
From ea69ff188dd5d9ac7162f05a22bf299b83a7536e Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Mon, 7 Dec 2015 09:33:28 +0100
Subject: [PATCH 005/146] drm: gem: cma: Export with handle allocator
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/drm_gem_cma_helper.c | 3 ++-
include/drm/drm_gem_cma_helper.h | 4 ++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c
index 80a5115c3846..077c61f065d9 100644
--- a/drivers/gpu/drm/drm_gem_cma_helper.c
+++ b/drivers/gpu/drm/drm_gem_cma_helper.c
@@ -142,7 +142,7 @@ EXPORT_SYMBOL_GPL(drm_gem_cma_create);
* A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
* error code on failure.
*/
-static struct drm_gem_cma_object *
+struct drm_gem_cma_object *
drm_gem_cma_create_with_handle(struct drm_file *file_priv,
struct drm_device *drm, size_t size,
uint32_t *handle)
@@ -169,6 +169,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv,
return cma_obj;
}
+EXPORT_SYMBOL_GPL(drm_gem_cma_create_with_handle);
/**
* drm_gem_cma_free_object - free resources associated with a CMA GEM object
diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
index 19777145cf8e..79f397c91517 100644
--- a/include/drm/drm_gem_cma_helper.h
+++ b/include/drm/drm_gem_cma_helper.h
@@ -79,6 +79,10 @@ int drm_gem_cma_mmap(struct file *filp, struct vm_area_struct *vma);
/* allocate physical memory */
struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
size_t size);
+struct drm_gem_cma_object *
+drm_gem_cma_create_with_handle(struct drm_file *file_priv,
+ struct drm_device *drm, size_t size,
+ uint32_t *handle);
extern const struct vm_operations_struct drm_gem_cma_vm_ops;
--
2.17.1

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layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0006-drm-sun4i-Add-GEM-allocator.patch Normal file
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@ -0,0 +1,102 @@
From b143de6aef8be007256082e0f89606b7f5e3c757 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Mon, 7 Dec 2015 09:47:34 +0100
Subject: [PATCH 006/146] drm/sun4i: Add GEM allocator
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++
include/uapi/drm/sun4i_drm.h | 29 +++++++++++++++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 include/uapi/drm/sun4i_drm.h
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 8b0cd08034e0..9f5de14fb2fe 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -22,6 +22,8 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_of.h>
+#include <uapi/drm/sun4i_drm.h>
+
#include "sun4i_drv.h"
#include "sun4i_frontend.h"
#include "sun4i_framebuffer.h"
@@ -30,6 +32,27 @@
DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops);
+static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_sun4i_gem_create *args = data;
+ struct drm_gem_cma_object *cma_obj;
+ size_t size;
+
+ /* The Mali requires a 64 bytes alignment */
+ size = ALIGN(args->size, 64);
+
+ cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, size,
+ &args->handle);
+
+ return PTR_ERR_OR_ZERO(cma_obj);
+}
+
+static const struct drm_ioctl_desc sun4i_drv_ioctls[] = {
+ DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl,
+ DRM_UNLOCKED | DRM_AUTH),
+};
+
static struct drm_driver sun4i_drv_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC,
@@ -42,6 +65,10 @@ static struct drm_driver sun4i_drv_driver = {
.major = 1,
.minor = 0,
+ /* Custom ioctls */
+ .ioctls = sun4i_drv_ioctls,
+ .num_ioctls = ARRAY_SIZE(sun4i_drv_ioctls),
+
/* GEM Operations */
.dumb_create = drm_gem_cma_dumb_create,
.gem_free_object_unlocked = drm_gem_cma_free_object,
diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h
new file mode 100644
index 000000000000..67b9dd4ee594
--- /dev/null
+++ b/include/uapi/drm/sun4i_drm.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _UAPI_SUN4I_DRM_H_
+#define _UAPI_SUN4I_DRM_H_
+
+#include <drm/drm.h>
+
+struct drm_sun4i_gem_create {
+ __u64 size;
+ __u32 flags;
+ __u32 handle;
+};
+
+#define DRM_SUN4I_GEM_CREATE 0x00
+
+#define DRM_IOCTL_SUN4I_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \
+ struct drm_sun4i_gem_create)
+
+#endif
--
2.17.1

96
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0007-Add-sopine-HDMI-sound-and-WiFi-support.patch Normal file
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@ -0,0 +1,96 @@
From 87020e638ad511e0ebe9c72208d2f0192c905812 Mon Sep 17 00:00:00 2001
From: Vasily Khoruzhick <anarsoul@gmail.com>
Date: Sun, 3 Dec 2017 11:43:08 -0800
Subject: [PATCH 007/146] Add sopine HDMI sound and WiFi support
---
.../allwinner/sun50i-a64-sopine-baseboard.dts | 18 ++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 29 +++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index c21f2331add6..8161895dde52 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -86,6 +86,10 @@
status = "okay";
};
+&i2s2 {
+ status = "okay";
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -93,6 +97,16 @@
};
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_dldo4>;
+ vqmmc-supply = <&reg_eldo1>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+};
+
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
@@ -138,6 +152,10 @@
vcc-hdmi-supply = <&reg_dldo1>;
};
+&sound_hdmi {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 0f69f3593975..0b44018361cb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -727,6 +727,35 @@
status = "disabled";
};
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 27>;
+ resets = <&ccu RST_BUS_I2S2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ sound_hdmi: sound_hdmi {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "allwinner,hdmi";
+ simple-audio-card,mclk-fs = <256>;
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s2>;
+ };
+ };
+
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
--
2.17.1

39
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0008-arm64-dts-sun50i-a64-pine64-add-HDMI-audio-nodes.patch Normal file
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@ -0,0 +1,39 @@
From 887b96d878bb0e261bc19062dc73d193c75bc56a Mon Sep 17 00:00:00 2001
From: Vasily Khoruzhick <anarsoul@gmail.com>
Date: Tue, 26 Dec 2017 15:53:53 -0800
Subject: [PATCH 008/146] arm64: dts: sun50i-a64-pine64: add HDMI audio nodes
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06b5b88f60e..8c5dd99cc9ac 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -97,6 +97,10 @@
bias-pull-up;
};
+&i2s2 {
+ status = "okay";
+};
+
&mdio {
ext_rmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -254,6 +258,10 @@
status = "disabled";
};
+&sound_hdmi {
+ status = "okay";
+};
+
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
--
2.17.1

95
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0009-dt-bindings-update-the-Allwinner-GPADC-device-tree-b.patch Normal file
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@ -0,0 +1,95 @@
From 92e5c7876cef2b53ed3d1701169fcd93b73e0e33 Mon Sep 17 00:00:00 2001
From: Philipp Rossak <embed3d@gmail.com>
Date: Sat, 20 Jan 2018 13:25:21 +0100
Subject: [PATCH 009/146] dt-bindings: update the Allwinner GPADC device tree
binding for H3 & A83T
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
the bus clock and the reset was removed from the CCU. The THS in A83T
has a clock that is directly connected and runs with 24 MHz.
Update the binding document to cover H3 and A83T.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
---
.../devicetree/bindings/mfd/sun4i-gpadc.txt | 50 +++++++++++++++++--
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index 86dd8191b04c..f6b939617a6d 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
and sometimes as a touchscreen controller.
Required properties:
- - compatible: "allwinner,sun8i-a33-ths",
+ - compatible: must contain one of the following compatibles:
+ - "allwinner,sun8i-a33-ths"
+ - "allwinner,sun8i-h3-ths"
+ - "allwinner,sun8i-a83t-ths"
- reg: mmio address range of the chip,
- - #thermal-sensor-cells: shall be 0,
+ - #thermal-sensor-cells: shall be 0 or 1,
- #io-channel-cells: shall be 0,
-Example:
+Required properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - "allwinner,sun8i-a83t-ths"
+ - interrupts: the sampling interrupt of the ADC,
+
+Required properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - clocks: the bus clock and the input clock of the ADC,
+ - clock-names: should be "bus" and "mod",
+ - resets: the bus reset of the ADC,
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-ths"
+ - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
+ If unspecified default values shall be used. The size should
+ be 0x4 or 0x8, depending on the amount of CDATA registers.
+ - nvmem-cell-names: Should be "calibration".
+
+Details see: bindings/nvmem/nvmem.txt
+
+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,27 @@ Example:
#io-channel-cells = <0>;
};
+Example for H3:
+ ths: thermal-sensor@1c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_THS>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
+ #io-channel-cells = <0>;
+ };
+
+Example for A83T:
+ ths: thermal-sensor@1f04000 {
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ #io-channel-cells = <0>;
+ };
+
sun4i, sun5i and sun6i SoCs are also supported via the older binding:
sun4i resistive touchscreen controller
--
2.17.1

56
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@ -0,0 +1,56 @@
From ef6a8862ab9440c5d6a73da32be83edc46e2fe94 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Thu, 14 Sep 2017 22:52:47 +0800
Subject: [PATCH 011/146] iio: adc: sun4i-gpadc-iio: rename A33-specified
registers to contain A33
As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A33, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A33".
Add "_A33" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux/mfd/sun4i-gpadc.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 04d7147e0110..03804ff9c006 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -88,7 +88,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
- .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+ .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
};
struct sun4i_gpadc_iio {
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..78d31984a222 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -38,9 +38,9 @@
#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
#define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
+/* TP_CTRL1 bits for A33 */
+#define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
#define SUN4I_GPADC_CTRL2 0x08
--
2.17.1

237
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@ -0,0 +1,237 @@
From 3de3b1512ed5905e9522a4966d238f571825ee70 Mon Sep 17 00:00:00 2001
From: Philipp Rossak <embed3d@gmail.com>
Date: Sat, 20 Jan 2018 14:03:10 +0100
Subject: [PATCH 012/146] iio: adc: sun4i-gpadc-iio: rework: sampling start/end
code readout reg
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and allows the sampling start/end code and
the position of value readout register to be altered. Later the start/end
functions will be used to configure the ths and start/stop the
sampling.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 87 ++++++++++++++++++++++++++++---
include/linux/mfd/sun4i-gpadc.h | 19 +++++--
2 files changed, 94 insertions(+), 12 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 03804ff9c006..363936b37c5a 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -49,6 +49,18 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
}
+struct sun4i_gpadc_iio;
+
+/*
+ * Prototypes for these functions, which enable these functions to be
+ * referenced in gpadc_data structures.
+ */
+static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info);
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info);
+
+static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info);
+static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info);
+
struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,6 +68,13 @@ struct gpadc_data {
unsigned int tp_adc_select;
unsigned int (*adc_chan_select)(unsigned int chan);
unsigned int adc_chan_mask;
+ unsigned int temp_data;
+ int (*sample_start)(struct sun4i_gpadc_iio *info);
+ int (*sample_end)(struct sun4i_gpadc_iio *info);
+ u32 ctrl0_map;
+ u32 ctrl2_map;
+ u32 sensor_en_map;
+ u32 filter_map;
};
static const struct gpadc_data sun4i_gpadc_data = {
@@ -65,6 +84,9 @@ static const struct gpadc_data sun4i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = &sun4i_gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .temp_data = SUN4I_GPADC_TEMP_DATA,
+ .sample_start = sun4i_gpadc_sample_start,
+ .sample_end = sun4i_gpadc_sample_end,
};
static const struct gpadc_data sun5i_gpadc_data = {
@@ -74,6 +96,9 @@ static const struct gpadc_data sun5i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = &sun4i_gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .temp_data = SUN4I_GPADC_TEMP_DATA,
+ .sample_start = sun4i_gpadc_sample_start,
+ .sample_end = sun4i_gpadc_sample_end,
};
static const struct gpadc_data sun6i_gpadc_data = {
@@ -83,12 +108,18 @@ static const struct gpadc_data sun6i_gpadc_data = {
.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = &sun6i_gpadc_chan_select,
.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
+ .temp_data = SUN4I_GPADC_TEMP_DATA,
+ .sample_start = sun4i_gpadc_sample_start,
+ .sample_end = sun4i_gpadc_sample_end,
};
static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
+ .temp_data = SUN4I_GPADC_TEMP_DATA,
+ .sample_start = sun4i_gpadc_sample_start,
+ .sample_end = sun4i_gpadc_sample_end,
};
struct sun4i_gpadc_iio {
@@ -277,7 +308,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
if (info->no_irq) {
pm_runtime_get_sync(indio_dev->dev.parent);
- regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+ regmap_read(info->regmap, info->data->temp_data, val);
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -382,10 +413,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static int sun4i_gpadc_runtime_suspend(struct device *dev)
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info)
{
- struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
-
/* Disable the ADC on IP */
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
/* Disable temperature sensor on IP */
@@ -394,19 +423,32 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
return 0;
}
-static int sun4i_gpadc_runtime_resume(struct device *dev)
+static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info)
+{
+ /* Disable temperature sensor */
+ regmap_write(info->regmap, SUNXI_THS_CTRL2, 0x0);
+
+ return 0;
+}
+
+static int sun4i_gpadc_runtime_suspend(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+ return info->data->sample_end(info);
+}
+
+static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info)
+{
/* clkin = 6MHz */
regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
SUN4I_GPADC_CTRL0_FS_DIV(7) |
- SUN4I_GPADC_CTRL0_T_ACQ(63));
+ SUNXI_THS_ACQ0(63));
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en);
regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
- SUN4I_GPADC_CTRL3_FILTER_EN |
- SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
+ SUNXI_THS_FILTER_EN |
+ SUNXI_THS_FILTER_TYPE(1));
/* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */
regmap_write(info->regmap, SUN4I_GPADC_TPR,
SUN4I_GPADC_TPR_TEMP_ENABLE |
@@ -415,6 +457,35 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
return 0;
}
+static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info)
+{
+ u32 value;
+
+ if (info->data->ctrl0_map)
+ regmap_write(info->regmap, SUNXI_THS_CTRL0,
+ info->data->ctrl0_map);
+
+ regmap_write(info->regmap, SUNXI_THS_CTRL2,
+ info->data->ctrl2_map);
+
+ regmap_write(info->regmap, SUNXI_THS_FILTER,
+ info->data->filter_map);
+
+ regmap_read(info->regmap, SUNXI_THS_CTRL2, &value);
+
+ regmap_write(info->regmap, SUNXI_THS_CTRL2,
+ info->data->sensor_en_map | value);
+
+ return 0;
+}
+
+static int sun4i_gpadc_runtime_resume(struct device *dev)
+{
+ struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+
+ return info->data->sample_start(info);
+}
+
static int sun4i_gpadc_get_temp(void *data, int *temp)
{
struct sun4i_gpadc_iio *info = data;
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 78d31984a222..39e096c3ddac 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -17,7 +17,6 @@
#define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22)
#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
#define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
-#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
#define SUN4I_GPADC_CTRL1 0x04
@@ -51,9 +50,6 @@
#define SUN4I_GPADC_CTRL3 0x0c
-#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
-#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
-
#define SUN4I_GPADC_TPR 0x18
#define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16)
@@ -90,6 +86,21 @@
/* 10s delay before suspending the IP */
#define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000
+/* SUNXI_THS COMMON REGISTERS + DEFINES */
+#define SUNXI_THS_CTRL0 0x00
+#define SUNXI_THS_CTRL2 0x40
+#define SUNXI_THS_FILTER 0x70
+
+#define SUNXI_THS_FILTER_EN BIT(2)
+#define SUNXI_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
+#define SUNXI_THS_ACQ0(x) (GENMASK(15, 0) & (x))
+#define SUNXI_THS_ACQ1(x) (GENMASK(31, 16) & ((x) << 16))
+
+#define SUNXI_THS_TEMP_SENSE_EN0 BIT(0)
+#define SUNXI_THS_TEMP_SENSE_EN1 BIT(1)
+#define SUNXI_THS_TEMP_SENSE_EN2 BIT(2)
+#define SUNXI_THS_TEMP_SENSE_EN3 BIT(3)
+
struct sun4i_gpadc_dev {
struct device *dev;
struct regmap *regmap;
--
2.17.1

168
layers/meta-balena-allwinner/recipes-kernel/linux/linux-4.19/0013-iio-adc-sun4i-gpadc-iio-rework-support-clocks-and-re.patch Normal file
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@ -0,0 +1,168 @@
From c2d19fecbff6a21b3ab351c7843ae27de0d10b5b Mon Sep 17 00:00:00 2001
From: Philipp Rossak <embed3d@gmail.com>
Date: Sun, 21 Jan 2018 22:23:00 +0100
Subject: [PATCH 013/146] iio: adc: sun4i-gpadc-iio: rework: support clocks and
reset
For adding newer sensor some basic rework of the code is necessary.
The SoCs after H3 has newer thermal sensor ADCs, which have two clock
inputs (bus clock and sampling clock) and a reset. The registers are
also re-arranged.
This commit reworks the code, adds the process of the clocks and
resets.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 80 +++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 363936b37c5a..1a80744bd472 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
* shutdown for not being used.
*/
+#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -31,6 +32,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
#include <linux/thermal.h>
#include <linux/delay.h>
@@ -75,6 +77,9 @@ struct gpadc_data {
u32 ctrl2_map;
u32 sensor_en_map;
u32 filter_map;
+ bool has_bus_clk;
+ bool has_bus_rst;
+ bool has_mod_clk;
};
static const struct gpadc_data sun4i_gpadc_data = {
@@ -134,6 +139,9 @@ struct sun4i_gpadc_iio {
atomic_t ignore_temp_data_irq;
const struct gpadc_data *data;
bool no_irq;
+ struct clk *bus_clk;
+ struct clk *mod_clk;
+ struct reset_control *reset;
/* prevents concurrent reads of temperature and ADC */
struct mutex mutex;
struct thermal_zone_device *tzd;
@@ -435,6 +443,12 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+ if (info->data->has_mod_clk)
+ clk_disable(info->mod_clk);
+
+ if (info->data->has_bus_clk)
+ clk_disable(info->bus_clk);
+
return info->data->sample_end(info);
}
@@ -483,6 +497,12 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
{
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+ if (info->data->has_mod_clk)
+ clk_enable(info->mod_clk);
+
+ if (info->data->has_bus_clk)
+ clk_enable(info->bus_clk);
+
return info->data->sample_start(info);
}
@@ -597,10 +617,61 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
return ret;
}
+ if (info->data->has_bus_rst) {
+ info->reset = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ return ret;
+ }
+
+ ret = reset_control_deassert(info->reset);
+ if (ret)
+ return ret;
+ }
+
+ if (info->data->has_bus_clk) {
+ info->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(info->bus_clk)) {
+ ret = PTR_ERR(info->bus_clk);
+ goto assert_reset;
+ }
+
+ ret = clk_prepare_enable(info->bus_clk);
+ if (ret)
+ goto assert_reset;
+ }
+
+ if (info->data->has_mod_clk) {
+ info->mod_clk = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(info->mod_clk)) {
+ ret = PTR_ERR(info->mod_clk);
+ goto disable_bus_clk;
+ }
+
+ /* Running at 6MHz */
+ ret = clk_set_rate(info->mod_clk, 4000000);
+ if (ret)
+ goto disable_bus_clk;
+
+ ret = clk_prepare_enable(info->mod_clk);
+ if (ret)
+ goto disable_bus_clk;
+ }
+
if (IS_ENABLED(CONFIG_THERMAL_OF))
info->sensor_device = &pdev->dev;
return 0;
+
+disable_bus_clk:
+ if (info->data->has_bus_clk)
+ clk_disable_unprepare(info->bus_clk);
+
+assert_reset:
+ if (info->data->has_bus_rst)
+ reset_control_assert(info->reset);
+
+ return ret;
}
static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
@@ -766,6 +837,15 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
if (!info->no_irq)
iio_map_array_unregister(indio_dev);
+ if (info->data->has_mod_clk)
+ clk_disable_unprepare(info->mod_clk);
+
+ if (info->data->has_bus_clk)
+ clk_disable_unprepare(info->bus_clk);
+
+ if (info->data->has_bus_rst)
+ reset_control_assert(info->reset);
+
return 0;
}
--
2.17.1

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