b167421e55
Add the latest linux available from https://github.com/armbian/build commit de58ac1faac92724c6449db12c22affaeb003875, tag: sunxi-5.3, alongside all the patches that it comes with. Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
29 lines
965 B
Diff
29 lines
965 B
Diff
From d46f1f53618ceffa33a5920802a9247337fd3ff3 Mon Sep 17 00:00:00 2001
|
|
From: Ondrej Jirman <megous@megous.com>
|
|
Date: Wed, 5 Apr 2017 15:43:48 +0200
|
|
Subject: [PATCH 03/82] clk: sunxi-ng: Limit pll_cpux P factor for rates >
|
|
288MHz on H3
|
|
|
|
Datasheet for H3 mandates that CPUX PLL must not use postdivider
|
|
(P factor must be 1) for clock rates above 288MHz.
|
|
|
|
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
|
---
|
|
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
|
|
index 8d47742def49..7cc9467f373f 100644
|
|
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
|
|
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
|
|
@@ -37,6 +37,7 @@ static struct ccu_nkmp pll_cpux_clk = {
|
|
.k = _SUNXI_CCU_MULT(4, 2),
|
|
.m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
|
|
.p = _SUNXI_CCU_DIV(16, 2),
|
|
+ .max_rate_for_p = 288000000,
|
|
.common = {
|
|
.reg = 0x000,
|
|
.hw.init = CLK_HW_INIT("pll-cpux",
|
|
--
|
|
2.20.1
|
|
|