b167421e55
Add the latest linux available from https://github.com/armbian/build commit de58ac1faac92724c6449db12c22affaeb003875, tag: sunxi-5.3, alongside all the patches that it comes with. Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
From 734e26b5a4b061d5f0667d59ce27a4a50f6d5c25 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Thu, 18 Oct 2018 15:07:29 +0800
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Subject: [PATCH 135/146] clk: sunxi-ng: enable so-said LDOs for A64 SoC's
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pll-mipi clock
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In the user manual of A64 SoC, the bit 22 and 23 of pll-mipi control
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register is called "LDO{1,2}_EN", and according to the BSP source code
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from Allwinner , the LDOs are enabled during the clock's enabling
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process.
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The clock failed to generate output if the two LDOs are not enabled.
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Add the two bits to the clock's gate bits, so that the LDOs are enabled
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when the PLL is enabled.
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Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 7 ++++++-
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1 file changed, 6 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index 90ffee824c33..a637e62ae1c4 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -162,7 +162,12 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
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#define SUN50I_A64_PLL_MIPI_REG 0x040
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static struct ccu_nkm pll_mipi_clk = {
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- .enable = BIT(31),
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+ /*
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+ * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
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+ * user manual, and by experiments the PLL doesn't work without
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+ * these bits toggled.
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+ */
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+ .enable = BIT(31) | BIT(23) | BIT(22),
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.lock = BIT(28),
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.n = _SUNXI_CCU_MULT(8, 4),
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.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
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--
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2.17.1
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