b167421e55
Add the latest linux available from https://github.com/armbian/build commit de58ac1faac92724c6449db12c22affaeb003875, tag: sunxi-5.3, alongside all the patches that it comes with. Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
58 lines
2.2 KiB
Diff
58 lines
2.2 KiB
Diff
From 0957f917d9a53bd9264bde6c2bd9d4f93cdd1d0c Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Thu, 18 Oct 2018 15:33:27 +0800
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Subject: [PATCH 134/146] drm/sun4i: rgb: Add 5% tolerance to dot clock
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frequency check
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The panels shipped with Allwinner devices are very "generic", i.e.
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they do not have model numbers or reliable sources of information
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for the timings (that we know of) other than the fex files shipped
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on them. The dot clock frequency provided in the fex files have all
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been rounded to the nearest MHz, as that is the unit used in them.
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We were using the simple panel "urt,umsh-8596md-t" as a substitute
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for the A13 Q8 tablets in the absence of a specific model for what
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may be many different but otherwise timing compatible panels. This
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was usable without any visual artifacts or side effects, until the
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dot clock rate check was added in commit bb43d40d7c83 ("drm/sun4i:
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rgb: Validate the clock rate").
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The reason this check fails is because the dotclock frequency for
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this model is 33.26 MHz, which is not achievable with our dot clock
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hardware, and the rate returned by clk_round_rate deviates slightly,
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causing the driver to reject the display mode.
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The LCD panels have some tolerance on the dot clock frequency, even
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if it's not specified in their datasheets.
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This patch adds a 5% tolerence to the dot clock check.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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drivers/gpu/drm/sun4i/sun4i_rgb.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
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index bf068da6b12e..23bdc449eacc 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
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@@ -92,13 +92,14 @@ static enum drm_mode_status sun4i_rgb_mode_valid(struct drm_encoder *crtc,
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DRM_DEBUG_DRIVER("Vertical parameters OK\n");
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+ /* Check against a 5% tolerance for the dot clock */
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tcon->dclk_min_div = 6;
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tcon->dclk_max_div = 127;
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rounded_rate = clk_round_rate(tcon->dclk, rate);
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- if (rounded_rate < rate)
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+ if (rounded_rate < rate * 19 / 20 )
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return MODE_CLOCK_LOW;
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- if (rounded_rate > rate)
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+ if (rounded_rate > rate * 21 / 20)
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return MODE_CLOCK_HIGH;
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DRM_DEBUG_DRIVER("Clock rate OK\n");
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--
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2.17.1
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