b167421e55
Add the latest linux available from https://github.com/armbian/build commit de58ac1faac92724c6449db12c22affaeb003875, tag: sunxi-5.3, alongside all the patches that it comes with. Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
107 lines
3.1 KiB
Text
107 lines
3.1 KiB
Text
From b0019c82e8ffbce13b5a98eb4fa16b966809c04a Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 7 Oct 2018 11:38:38 +0200
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Subject: [PATCH 085/146] clk: sunxi-ng: Adjust MP clock parent rate when
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allowed
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Currently MP clocks don't consider adjusting parent rate even if they
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are allowed to do so. Such behaviour considerably lowers amount of
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possible rates, which is very inconvenient when such clock is used for
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pixel clock, for example.
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In order to improve the situation, adjusting parent rate is considered
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when allowed.
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This code is inspired by clk_divider_bestdiv() function, which does
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basically the same thing for different clock type.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu_mp.c | 64 +++++++++++++++++++++++++++++++++--
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1 file changed, 62 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
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index 5d0af4051737..0357349eb767 100644
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--- a/drivers/clk/sunxi-ng/ccu_mp.c
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+++ b/drivers/clk/sunxi-ng/ccu_mp.c
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@@ -40,6 +40,61 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
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*p = best_p;
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}
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+static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
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+ unsigned long *parent,
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+ unsigned long rate,
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+ unsigned int max_m,
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+ unsigned int max_p)
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+{
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+ unsigned long parent_rate_saved;
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+ unsigned long parent_rate, now;
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+ unsigned long best_rate = 0;
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+ unsigned int _m, _p, div;
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+ unsigned long maxdiv;
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+
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+ parent_rate_saved = *parent;
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+
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+ /*
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+ * The maximum divider we can use without overflowing
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+ * unsigned long in rate * m * p below
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+ */
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+ maxdiv = max_m * max_p;
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+ maxdiv = min(ULONG_MAX / rate, maxdiv);
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+
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+ for (_p = 1; _p <= max_p; _p <<= 1) {
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+ for (_m = 1; _m <= max_m; _m++) {
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+ div = _m * _p;
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+
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+ if (div > maxdiv)
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+ break;
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+
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+ if (rate * div == parent_rate_saved) {
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+ /*
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+ * It's the most ideal case if the requested
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+ * rate can be divided from parent clock without
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+ * needing to change parent rate, so return the
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+ * divider immediately.
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+ */
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+ *parent = parent_rate_saved;
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+ return rate;
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+ }
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+
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+ parent_rate = clk_hw_round_rate(hw, rate * div);
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+ now = parent_rate / div;
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+
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+ if (now <= rate && now > best_rate) {
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+ best_rate = now;
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+ *parent = parent_rate;
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+
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+ if (now == rate)
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+ return rate;
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+ }
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+ }
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+ }
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+
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+ return best_rate;
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+}
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+
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static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
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struct clk_hw *hw,
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unsigned long *parent_rate,
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@@ -56,8 +111,13 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
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- rate = *parent_rate / p / m;
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+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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+ ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
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+ rate = *parent_rate / p / m;
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+ } else {
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+ rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
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+ max_m, max_p);
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+ }
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if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= cmp->fixed_post_div;
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--
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2.17.1
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