191 lines
14 KiB
C++
191 lines
14 KiB
C++
#ifndef _RADIOLIB_NRF24_H
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#define _RADIOLIB_NRF24_H
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#include "Module.h"
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// nRF24 SPI commands
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#define NRF24_CMD_READ 0b00000000
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#define NRF24_CMD_WRITE 0b00100000
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#define NRF24_CMD_READ_RX_PAYLOAD 0b01100001
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#define NRF24_CMD_WRITE_TX_PAYLOAD 0b10100000
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#define NRF24_CMD_FLUSH_TX 0b11100001
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#define NRF24_CMD_FLUSH_RX 0b11100010
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#define NRF24_CMD_REUSE_TX_PAXLOAD 0b11100011
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#define NRF24_CMD_READ_RX_PAYLOAD_WIDTH 0b01100000
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#define NRF24_CMD_WRITE_ACK_PAYLOAD 0b10101000
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#define NRF24_CMD_WRITE_TX_PAYLOAD_NOACK 0b10110000
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#define NRF24_CMD_NOP 0b11111111
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// nRF24 register map
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#define NRF24_REG_CONFIG 0x00
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#define NRF24_REG_EN_AA 0x01
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#define NRF24_REG_EN_RXADDR 0x02
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#define NRF24_REG_SETUP_AW 0x03
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#define NRF24_REG_SETUP_RETR 0x04
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#define NRF24_REG_RF_CH 0x05
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#define NRF24_REG_RF_SETUP 0x06
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#define NRF24_REG_STATUS 0x07
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#define NRF24_REG_OBSERVE_TX 0x08
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#define NRF24_REG_RPD 0x09
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#define NRF24_REG_RX_ADDR_P0 0x0A
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#define NRF24_REG_RX_ADDR_P1 0x0B
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#define NRF24_REG_RX_ADDR_P2 0x0C
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#define NRF24_REG_RX_ADDR_P3 0x0D
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#define NRF24_REG_RX_ADDR_P4 0x0E
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#define NRF24_REG_RX_ADDR_P5 0x0F
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#define NRF24_REG_TX_ADDR 0x10
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#define NRF24_REG_RX_PW_P0 0x11
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#define NRF24_REG_RX_PW_P1 0x12
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#define NRF24_REG_RX_PW_P2 0x13
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#define NRF24_REG_RX_PW_P3 0x14
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#define NRF24_REG_RX_PW_P4 0x15
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#define NRF24_REG_RX_PW_P5 0x16
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#define NRF24_REG_FIFO_STATUS 0x17
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#define NRF24_REG_DYNPD 0x1C
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#define NRF24_REG_FEATURE 0x1D
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// NRF24_REG_CONFIG MSB LSB DESCRIPTION
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#define NRF24_MASK_RX_DR_IRQ_OFF 0b01000000 // 6 6 RX_DR will not be reflected on IRQ pin
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#define NRF24_MASK_RX_DR_IRQ_ON 0b00000000 // 6 6 RX_DR will be reflected on IRQ pin as active low (default)
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#define NRF24_MASK_TX_DS_IRQ_OFF 0b00100000 // 5 5 TX_DS will not be reflected on IRQ pin
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#define NRF24_MASK_TX_DS_IRQ_ON 0b00000000 // 5 5 TX_DS will be reflected on IRQ pin as active low (default)
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#define NRF24_MASK_MAX_RT_IRQ_OFF 0b00010000 // 4 4 MAX_RT will not be reflected on IRQ pin
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#define NRF24_MASK_MAX_RT_IRQ_ON 0b00000000 // 4 4 MAX_RT will be reflected on IRQ pin as active low (default)
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#define NRF24_CRC_OFF 0b00000000 // 3 3 CRC calculation: disabled
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#define NRF24_CRC_ON 0b00001000 // 3 3 enabled (default)
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#define NRF24_CRC_8 0b00000000 // 2 2 CRC scheme: CRC8 (default)
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#define NRF24_CRC_16 0b00000100 // 2 2 CRC16
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#define NRF24_POWER_UP 0b00000010 // 1 1 power up
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#define NRF24_POWER_DOWN 0b00000000 // 1 1 power down
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#define NRF24_PTX 0b00000000 // 0 0 enable primary Tx
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#define NRF24_PRX 0b00000001 // 0 0 enable primary Rx
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// NRF24_REG_EN_AA
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#define NRF24_AA_P5_OFF 0b00000000 // 5 5 auto-ACK on pipe 5: disabled
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#define NRF24_AA_P5_ON 0b00100000 // 5 5 enabled (default)
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#define NRF24_AA_P4_OFF 0b00000000 // 4 4 auto-ACK on pipe 4: disabled
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#define NRF24_AA_P4_ON 0b00010000 // 4 4 enabled (default)
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#define NRF24_AA_P3_OFF 0b00000000 // 3 3 auto-ACK on pipe 3: disabled
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#define NRF24_AA_P3_ON 0b00001000 // 3 3 enabled (default)
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#define NRF24_AA_P2_OFF 0b00000000 // 2 2 auto-ACK on pipe 2: disabled
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#define NRF24_AA_P2_ON 0b00000100 // 2 2 enabled (default)
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#define NRF24_AA_P1_OFF 0b00000000 // 1 1 auto-ACK on pipe 1: disabled
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#define NRF24_AA_P1_ON 0b00000010 // 1 1 enabled (default)
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#define NRF24_AA_P0_OFF 0b00000000 // 0 0 auto-ACK on pipe 0: disabled
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#define NRF24_AA_P0_ON 0b00000001 // 0 0 enabled (default)
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// NRF24_REG_EN_RXADDR
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#define NRF24_P5_OFF 0b00000000 // 5 5 receive pipe 5: disabled (default)
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#define NRF24_P5_ON 0b00100000 // 5 5 enabled
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#define NRF24_P4_OFF 0b00000000 // 4 4 receive pipe 4: disabled (default)
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#define NRF24_P4_ON 0b00010000 // 4 4 enabled
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#define NRF24_P3_OFF 0b00000000 // 3 3 receive pipe 3: disabled (default)
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#define NRF24_P3_ON 0b00001000 // 3 3 enabled
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#define NRF24_P2_OFF 0b00000000 // 2 2 receive pipe 2: disabled (default)
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#define NRF24_P2_ON 0b00000100 // 2 2 enabled
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#define NRF24_P1_OFF 0b00000000 // 1 1 receive pipe 1: disabled
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#define NRF24_P1_ON 0b00000010 // 1 1 enabled (default)
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#define NRF24_P0_OFF 0b00000000 // 0 0 receive pipe 0: disabled
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#define NRF24_P0_ON 0b00000001 // 0 0 enabled (default)
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// NRF24_REG_SETUP_AW
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#define NRF24_ADDRESS_3_BYTES 0b00000001 // 1 0 address width: 3 bytes
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#define NRF24_ADDRESS_4_BYTES 0b00000010 // 1 0 4 bytes
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#define NRF24_ADDRESS_5_BYTES 0b00000011 // 1 0 5 bytes (default)
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// NRF24_REG_SETUP_RETR
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#define NRF24_ARD 0b00000000 // 7 4 auto retransmit delay: t[us] = (NRF24_ARD + 1) * 250 us
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#define NRF24_ARC_OFF 0b00000000 // 3 0 auto retransmit count: auto retransmit disabled
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#define NRF24_ARC 0b00000011 // 3 0 up to 3 retransmits on AA fail (default)
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// NRF24_REG_RF_CH
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#define NRF24_RF_CH 0b00000010 // 6 0 RF channel: f_CH[MHz] = 2400 MHz + NRF24_RF_CH
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// NRF24_REG_RF_SETUP
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#define NRF24_CONT_WAVE_OFF 0b00000000 // 7 7 continuous carrier transmit: disabled (default)
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#define NRF24_CONT_WAVE_ON 0b10000000 // 7 7 enabled
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#define NRF24_DR_250_KBPS 0b00100000 // 5 5 data rate: 250 kbps
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#define NRF24_DR_1_MBPS 0b00000000 // 3 3 1 Mbps (default)
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#define NRF24_DR_2_MBPS 0b00001000 // 3 3 2 Mbps
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#define NRF24_RF_PWR_18_DBM 0b00000000 // 2 1 output power: -18 dBm
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#define NRF24_RF_PWR_12_DBM 0b00000010 // 2 1 -12 dBm
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#define NRF24_RF_PWR_6_DBM 0b00000100 // 2 1 -6 dBm
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#define NRF24_RF_PWR_0_DBM 0b00000110 // 2 1 0 dBm (default)
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// NRF24_REG_STATUS
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#define NRF24_RX_DR 0b01000000 // 6 6 Rx data ready
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#define NRF24_TX_DS 0b00100000 // 5 5 Tx data sent
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#define NRF24_MAX_RT 0b00010000 // 4 4 maximum number of rentransmits reached (must be cleared to continue)
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#define NRF24_RX_FIFO_EMPTY 0b00001110 // 3 1 Rx FIFO is empty
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#define NRF24_RX_P_NO 0b00000000 // 3 1 number of data pipe that received data
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#define NRF24_TX_FIFO_FULL 0b00000001 // 0 0 Tx FIFO is full
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// NRF24_REG_OBSERVE_TX
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#define NRF24_PLOS_CNT 0b00000000 // 7 4 number of lost packets
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#define NRF24_ARC_CNT 0b00000000 // 3 0 number of retransmitted packets
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// NRF24_REG_RPD
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#define NRF24_RP_BELOW_64_DBM 0b00000000 // 0 0 received power in the current channel: less than -64 dBm
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#define NRF24_RP_ABOVE_64_DBM 0b00000001 // 0 0 more than -64 dBm
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// NRF24_REG_FIFO_STATUS
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#define NRF24_TX_REUSE 0b01000000 // 6 6 reusing last transmitted payload
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#define NRF24_TX_FIFO_FULL_FLAG 0b00100000 // 5 5 Tx FIFO is full
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#define NRF24_TX_FIFO_EMPTY_FLAG 0b00010000 // 4 4 Tx FIFO is empty
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#define NRF24_RX_FIFO_FULL_FLAG 0b00000010 // 5 5 Rx FIFO is full
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#define NRF24_RX_FIFO_EMPTY_FLAG 0b00000001 // 4 4 Rx FIFO is empty
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// NRF24_REG_DYNPD
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#define NRF24_DPL_P5_OFF 0b00000000 // 5 5 dynamic payload length on pipe 5: disabled (default)
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#define NRF24_DPL_P5_ON 0b00100000 // 5 5 enabled
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#define NRF24_DPL_P4_OFF 0b00000000 // 4 4 dynamic payload length on pipe 4: disabled (default)
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#define NRF24_DPL_P4_ON 0b00010000 // 4 4 enabled
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#define NRF24_DPL_P3_OFF 0b00000000 // 3 3 dynamic payload length on pipe 3: disabled (default)
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#define NRF24_DPL_P3_ON 0b00001000 // 3 3 enabled
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#define NRF24_DPL_P2_OFF 0b00000000 // 2 2 dynamic payload length on pipe 2: disabled (default)
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#define NRF24_DPL_P2_ON 0b00000100 // 2 2 enabled
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#define NRF24_DPL_P1_OFF 0b00000000 // 1 1 dynamic payload length on pipe 1: disabled (default)
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#define NRF24_DPL_P1_ON 0b00000010 // 1 1 enabled
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#define NRF24_DPL_P0_OFF 0b00000000 // 0 0 dynamic payload length on pipe 0: disabled (default)
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#define NRF24_DPL_P0_ON 0b00000001 // 0 0 enabled
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// NRF24_REG_FEATURE
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#define NRF24_DPL_OFF 0b00000000 // 2 2 dynamic payload length: disabled (default)
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#define NRF24_DPL_ON 0b00000100 // 2 2 enabled
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#define NRF24_ACK_PAY_OFF 0b00000000 // 1 1 payload with ACK packets: disabled (default)
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#define NRF24_ACK_PAY_ON 0b00000010 // 1 1 enabled
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#define NRF24_DYN_ACK_OFF 0b00000000 // 0 0 payloads without ACK packets: disabled (default)
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#define NRF24_DYN_ACK_ON 0b00000001 // 0 0 enabled
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class nRF24 {
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public:
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// constructor
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nRF24(Module* module);
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// basic methods
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int16_t begin(int16_t freq = 2400, int16_t dataRate = 1000, uint8_t addrWidth = 5);
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int16_t sleep();
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int16_t standby();
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int16_t transmit(String& str, uint8_t* addr);
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int16_t transmit(const char* str, uint8_t* addr);
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int16_t transmit(uint8_t* data, size_t len, uint8_t* addr);
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// configuration methods
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int16_t setFrequency(int16_t freq);
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int16_t setDataRate(int16_t dataRate);
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int16_t setAddressWidth(uint8_t addrWidth);
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int16_t setReceivePipe(uint8_t pipeNum, uint8_t* addr);
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int16_t setReceivePipe(uint8_t pipeNum, uint8_t addrByte);
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int16_t disablePipe(uint8_t pipeNum);
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private:
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Module* _mod;
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uint8_t _addrWidth;
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void SPIreadRxPayload(uint8_t numBytes, uint8_t* inBytes);
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void SPIwriteTxPayload(uint8_t* data, uint8_t numBytes);
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void clearIRQ();
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};
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#endif
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