[nRF24][WIP] Added nRF24 files
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4 changed files with 576 additions and 0 deletions
102
examples/nRF24/nRF24_Transmit/nRF24_Transmit.ino
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102
examples/nRF24/nRF24_Transmit/nRF24_Transmit.ino
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/*
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RadioLib nRF24 Transmit Example
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*/
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// include the library
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#include <RadioLib.h>
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// nRF24 is in slot A on the shield
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nRF24 nrf = RadioShield.ModuleA;
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void setup() {
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Serial.begin(9600);
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// initialize nRF24
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Serial.print(F("[nRF24] Initializing ... "));
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// carrier frequency: 2400 MHz
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// data rate: 1000 kbps
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// address width: 5 bytes
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int state = nrf.begin();
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if(state == ERR_NONE) {
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Serial.println(F("success!"));
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} else {
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Serial.print(F("failed, code "));
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Serial.println(state);
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while(true);
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}
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// set receive pipe 0 address
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// NOTE: address width in bytes MUST be equal to the
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// width set in begin() or setAddressWidth()
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// methods (5 by default)
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Serial.print(F("[nRF24] Setting address for receive pipe 0 ... "));
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byte receiveAddr0[] = {0x05, 0x06, 0x07, 0x08, 0x09};
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state = nrf.setReceivePipe(0, receiveAddr0);
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if(state == ERR_NONE) {
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Serial.println(F("success!"));
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} else {
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Serial.print(F("failed, code "));
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Serial.println(state);
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while(true);
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}
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// set receive pipe 1 - 5 address
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// NOTE: unlike receive pipe 0, pipes 1 - 5 are only
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// distinguished by their least significant byte,
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// the upper bytes will be the same!
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Serial.print(F("[nRF24] Setting addresses for receive pipes 1 - 5 ... "));
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byte receiveAddr1[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xE1};
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// set pipe 1 address
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state = nrf.setReceivePipe(1, receiveAddr1);
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// set the addresses for rest of pipes
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state |= nrf.setReceivePipe(2, 0xE2);
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state |= nrf.setReceivePipe(3, 0xE3);
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state |= nrf.setReceivePipe(4, 0xE4);
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state |= nrf.setReceivePipe(5, 0xE5);
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if(state == ERR_NONE) {
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Serial.println(F("success!"));
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} else {
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Serial.print(F("failed, code "));
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Serial.println(state);
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while(true);
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}
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// pipes 1 - 5 are automatically enabled upon address
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// change, but can be disabled manually
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Serial.print(F("[nRF24] Disabling pipes 2 - 5 ... "));
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state = nrf.disablePipe(2);
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if(state == ERR_NONE) {
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Serial.println(F("success!"));
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} else {
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Serial.print(F("failed, code "));
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Serial.println(state);
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while(true);
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}
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}
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void loop() {
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Serial.print(F("[nRF24] Transmitting packet ... "));
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// set transmit address
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// NOTE: address width in bytes MUST be equal to the
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// width set in begin() or setAddressWidth()
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// methods (5 by default)
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byte addr[] = {0x00, 0x01, 0x02, 0x03, 0x04};
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// you can transmit C-string or Arduino string up to
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// 32 characters long
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int state = nrf.transmit("Hello World!", addr);
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if (state == ERR_NONE) {
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// the packet was successfully transmitted
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Serial.println(" success!");
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} else if (state == ERR_PACKET_TOO_LONG) {
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// the supplied packet was longer than 256 bytes
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Serial.println(" too long!");
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}
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// wait for a second before transmitting again
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delay(1000);
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}
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@ -42,6 +42,7 @@
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#include "modules/ESP8266.h"
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#include "modules/HC05.h"
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#include "modules/JDY08.h"
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#include "modules/nRF24.h"
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#include "modules/RF69.h"
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#include "modules/RFM95.h"
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#include "modules/RFM96.h"
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282
src/modules/nRF24.cpp
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282
src/modules/nRF24.cpp
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#include "nRF24.h"
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nRF24::nRF24(Module* mod) {
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_mod = mod;
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}
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int16_t nRF24::begin(int16_t freq, int16_t dataRate, uint8_t addrWidth) {
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// set module properties
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_mod->SPIreadCommand = NRF24_CMD_READ;
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_mod->SPIwriteCommand = NRF24_CMD_WRITE;
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_mod->init(USE_SPI, INT_BOTH);
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// override pin mode on INT0 (connected to nRF24 CE pin)
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pinMode(_mod->getInt0(), OUTPUT);
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// set frequency
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int16_t state = setFrequency(freq);
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if(state != ERR_NONE) {
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return(state);
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}
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// set data rate
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state = setDataRate(dataRate);
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if(state != ERR_NONE) {
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return(state);
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}
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// set address width
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state = setAddressWidth(addrWidth);
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if(state != ERR_NONE) {
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return(state);
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}
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return(state);
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}
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int16_t nRF24::sleep() {
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return(_mod->SPIsetRegValue(NRF24_REG_CONFIG, NRF24_POWER_DOWN, 1, 1));
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}
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int16_t nRF24::standby() {
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return(_mod->SPIsetRegValue(NRF24_REG_CONFIG, NRF24_POWER_UP, 1, 1));
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}
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int16_t nRF24::transmit(String& str, uint8_t* addr) {
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return(nRF24::transmit(str.c_str(), addr));
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}
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int16_t nRF24::transmit(const char* str, uint8_t* addr) {
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return(nRF24::transmit((uint8_t*)str, strlen(str), addr));
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}
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int16_t nRF24::transmit(uint8_t* data, size_t len, uint8_t* addr) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// reverse address byte order (LSB must be written first)
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uint8_t* addrReversed = new uint8_t[_addrWidth];
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for(uint8_t i = 0; i < _addrWidth; i++) {
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addrReversed[i] = addr[_addrWidth - 1 - i];
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}
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// set transmit address
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_mod->SPIwriteRegisterBurst(NRF24_REG_TX_ADDR, addrReversed, _addrWidth);
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// check packet length
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if(len > 32) {
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return(ERR_PACKET_TOO_LONG);
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}
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// enable Tx_DataSent interrupt
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state = _mod->SPIsetRegValue(NRF24_REG_CONFIG, NRF24_MASK_RX_DR_IRQ_OFF | NRF24_MASK_TX_DS_IRQ_ON | NRF24_MASK_MAX_RT_IRQ_OFF, 6, 4);
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// fill Tx FIFO
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SPIwriteTxPayload(data, len);
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// enable primary Tx mode
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state |= _mod->SPIsetRegValue(NRF24_REG_CONFIG, NRF24_PTX, 0, 0);
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// CE high to start transmitting
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digitalWrite(_mod->getInt0(), HIGH);
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// wait until transmission is finished
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while(digitalRead(_mod->getInt1()));
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// CE low
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digitalWrite(_mod->getInt0(), LOW);
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// clear interrupt
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clearIRQ();
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return(state);
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}
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int16_t nRF24::setFrequency(int16_t freq) {
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// check allowed range
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if(!((freq >= 2400) && (freq <= 2525))) {
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return(ERR_INVALID_FREQUENCY);
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}
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// set frequency
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uint8_t freqRaw = freq - 2400;
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state = _mod->SPIsetRegValue(NRF24_REG_RF_CH, freqRaw, 6, 0);
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return(state);
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}
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int16_t nRF24::setDataRate(int16_t dataRate) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// set data rate
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if(dataRate == 250) {
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state = _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_250_KBPS, 5, 5);
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state |= _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_250_KBPS, 3, 3);
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} else if(dataRate == 1000) {
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state = _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_1_MBPS, 5, 5);
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state |= _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_1_MBPS, 3, 3);
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} else if(dataRate == 2000) {
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state = _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_2_MBPS, 5, 5);
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state |= _mod->SPIsetRegValue(NRF24_REG_RF_SETUP, NRF24_DR_2_MBPS, 3, 3);
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} else {
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return(ERR_INVALID_DATA_RATE);
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}
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return(state);
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}
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int16_t nRF24::setAddressWidth(uint8_t addrWidth) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// set address width
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switch(addrWidth) {
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case 3:
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state = _mod->SPIsetRegValue(NRF24_REG_SETUP_AW, NRF24_ADDRESS_3_BYTES, 1, 0);
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break;
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case 4:
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state = _mod->SPIsetRegValue(NRF24_REG_SETUP_AW, NRF24_ADDRESS_4_BYTES, 1, 0);
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break;
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case 5:
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state = _mod->SPIsetRegValue(NRF24_REG_SETUP_AW, NRF24_ADDRESS_5_BYTES, 1, 0);
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break;
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default:
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return(ERR_INVALID_ADDRESS_WIDTH);
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}
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// save address width
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_addrWidth = addrWidth;
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return(state);
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}
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int16_t nRF24::setReceivePipe(uint8_t pipeNum, uint8_t* addr) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// reverse byte order (LSB must be written first)
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uint8_t* addrReversed = new uint8_t[_addrWidth];
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for(uint8_t i = 0; i < _addrWidth; i++) {
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addrReversed[i] = addr[_addrWidth - 1 - i];
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}
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// write full pipe 0 - 1 address and enable the pipe
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switch(pipeNum) {
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case 0:
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_mod->SPIwriteRegisterBurst(NRF24_REG_RX_ADDR_P0, addrReversed, _addrWidth);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P0_ON, 0, 0);
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case 1:
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_mod->SPIwriteRegisterBurst(NRF24_REG_RX_ADDR_P1, addrReversed, _addrWidth);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P1_ON, 1, 1);
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break;
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default:
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return(ERR_INVALID_PIPE_NUMBER);
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}
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return(state);
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}
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int16_t nRF24::setReceivePipe(uint8_t pipeNum, uint8_t addrByte) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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// write unique pipe 2 - 5 address and enable the pipe
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switch(pipeNum) {
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case 2:
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state = _mod->SPIsetRegValue(NRF24_REG_RX_ADDR_P2, addrByte);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P2_ON, 2, 2);
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break;
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case 3:
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state = _mod->SPIsetRegValue(NRF24_REG_RX_ADDR_P3, addrByte);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P3_ON, 3, 3);
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break;
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case 4:
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state = _mod->SPIsetRegValue(NRF24_REG_RX_ADDR_P4, addrByte);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P4_ON, 4, 4);
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break;
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case 5:
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state = _mod->SPIsetRegValue(NRF24_REG_RX_ADDR_P5, addrByte);
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state |= _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P5_ON, 5, 5);
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break;
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default:
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return(ERR_INVALID_PIPE_NUMBER);
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}
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return(state);
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}
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int16_t nRF24::disablePipe(uint8_t pipeNum) {
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// set mode to standby
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int16_t state = standby();
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if(state != ERR_NONE) {
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return(state);
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}
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switch(pipeNum) {
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case 0:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P0_OFF, 0, 0);
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break;
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case 1:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P1_OFF, 1, 1);
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break;
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case 2:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P2_OFF, 2, 2);
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break;
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case 3:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P3_OFF, 3, 3);
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break;
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case 4:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P4_OFF, 4, 4);
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break;
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case 5:
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state = _mod->SPIsetRegValue(NRF24_REG_EN_RXADDR, NRF24_P5_OFF, 5, 5);
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break;
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default:
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return(ERR_INVALID_PIPE_NUMBER);
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}
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return(state);
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}
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void nRF24::SPIreadRxPayload(uint8_t numBytes, uint8_t* inBytes) {
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digitalWrite(_mod->getCs(), LOW);
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SPI.transfer(NRF24_CMD_READ_RX_PAYLOAD);
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for(uint8_t i = 0; i < numBytes; i++) {
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inBytes[i] = SPI.transfer(0x00);
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}
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digitalWrite(_mod->getCs(), HIGH);
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}
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void nRF24::SPIwriteTxPayload(uint8_t* data, uint8_t numBytes) {
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digitalWrite(_mod->getCs(), LOW);
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SPI.transfer(NRF24_CMD_WRITE_TX_PAYLOAD);
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for(uint8_t i = 0; i < numBytes; i++) {
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SPI.transfer(data[i]);
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}
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digitalWrite(_mod->getCs(), HIGH);
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}
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void nRF24::clearIRQ() {
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_mod->SPIsetRegValue(NRF24_REG_CONFIG, NRF24_MASK_RX_DR_IRQ_OFF | NRF24_MASK_TX_DS_IRQ_OFF | NRF24_MASK_MAX_RT_IRQ_OFF, 6, 4);
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}
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191
src/modules/nRF24.h
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191
src/modules/nRF24.h
Normal file
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#ifndef _RADIOLIB_NRF24_H
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#define _RADIOLIB_NRF24_H
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#include "Module.h"
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// nRF24 SPI commands
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#define NRF24_CMD_READ 0b00000000
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#define NRF24_CMD_WRITE 0b00100000
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#define NRF24_CMD_READ_RX_PAYLOAD 0b01100001
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#define NRF24_CMD_WRITE_TX_PAYLOAD 0b10100000
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#define NRF24_CMD_FLUSH_TX 0b11100001
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#define NRF24_CMD_FLUSH_RX 0b11100010
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#define NRF24_CMD_REUSE_TX_PAXLOAD 0b11100011
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#define NRF24_CMD_READ_RX_PAYLOAD_WIDTH 0b01100000
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#define NRF24_CMD_WRITE_ACK_PAYLOAD 0b10101000
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#define NRF24_CMD_WRITE_TX_PAYLOAD_NOACK 0b10110000
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#define NRF24_CMD_NOP 0b11111111
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// nRF24 register map
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#define NRF24_REG_CONFIG 0x00
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#define NRF24_REG_EN_AA 0x01
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#define NRF24_REG_EN_RXADDR 0x02
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#define NRF24_REG_SETUP_AW 0x03
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#define NRF24_REG_SETUP_RETR 0x04
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#define NRF24_REG_RF_CH 0x05
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#define NRF24_REG_RF_SETUP 0x06
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#define NRF24_REG_STATUS 0x07
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#define NRF24_REG_OBSERVE_TX 0x08
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#define NRF24_REG_RPD 0x09
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#define NRF24_REG_RX_ADDR_P0 0x0A
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#define NRF24_REG_RX_ADDR_P1 0x0B
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#define NRF24_REG_RX_ADDR_P2 0x0C
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#define NRF24_REG_RX_ADDR_P3 0x0D
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#define NRF24_REG_RX_ADDR_P4 0x0E
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#define NRF24_REG_RX_ADDR_P5 0x0F
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#define NRF24_REG_TX_ADDR 0x10
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#define NRF24_REG_RX_PW_P0 0x11
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#define NRF24_REG_RX_PW_P1 0x12
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#define NRF24_REG_RX_PW_P2 0x13
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#define NRF24_REG_RX_PW_P3 0x14
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#define NRF24_REG_RX_PW_P4 0x15
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#define NRF24_REG_RX_PW_P5 0x16
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#define NRF24_REG_FIFO_STATUS 0x17
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#define NRF24_REG_DYNPD 0x1C
|
||||
#define NRF24_REG_FEATURE 0x1D
|
||||
|
||||
// NRF24_REG_CONFIG MSB LSB DESCRIPTION
|
||||
#define NRF24_MASK_RX_DR_IRQ_OFF 0b01000000 // 6 6 RX_DR will not be reflected on IRQ pin
|
||||
#define NRF24_MASK_RX_DR_IRQ_ON 0b00000000 // 6 6 RX_DR will be reflected on IRQ pin as active low (default)
|
||||
#define NRF24_MASK_TX_DS_IRQ_OFF 0b00100000 // 5 5 TX_DS will not be reflected on IRQ pin
|
||||
#define NRF24_MASK_TX_DS_IRQ_ON 0b00000000 // 5 5 TX_DS will be reflected on IRQ pin as active low (default)
|
||||
#define NRF24_MASK_MAX_RT_IRQ_OFF 0b00010000 // 4 4 MAX_RT will not be reflected on IRQ pin
|
||||
#define NRF24_MASK_MAX_RT_IRQ_ON 0b00000000 // 4 4 MAX_RT will be reflected on IRQ pin as active low (default)
|
||||
#define NRF24_CRC_OFF 0b00000000 // 3 3 CRC calculation: disabled
|
||||
#define NRF24_CRC_ON 0b00001000 // 3 3 enabled (default)
|
||||
#define NRF24_CRC_8 0b00000000 // 2 2 CRC scheme: CRC8 (default)
|
||||
#define NRF24_CRC_16 0b00000100 // 2 2 CRC16
|
||||
#define NRF24_POWER_UP 0b00000010 // 1 1 power up
|
||||
#define NRF24_POWER_DOWN 0b00000000 // 1 1 power down
|
||||
#define NRF24_PTX 0b00000000 // 0 0 enable primary Tx
|
||||
#define NRF24_PRX 0b00000001 // 0 0 enable primary Rx
|
||||
|
||||
// NRF24_REG_EN_AA
|
||||
#define NRF24_AA_P5_OFF 0b00000000 // 5 5 auto-ACK on pipe 5: disabled
|
||||
#define NRF24_AA_P5_ON 0b00100000 // 5 5 enabled (default)
|
||||
#define NRF24_AA_P4_OFF 0b00000000 // 4 4 auto-ACK on pipe 4: disabled
|
||||
#define NRF24_AA_P4_ON 0b00010000 // 4 4 enabled (default)
|
||||
#define NRF24_AA_P3_OFF 0b00000000 // 3 3 auto-ACK on pipe 3: disabled
|
||||
#define NRF24_AA_P3_ON 0b00001000 // 3 3 enabled (default)
|
||||
#define NRF24_AA_P2_OFF 0b00000000 // 2 2 auto-ACK on pipe 2: disabled
|
||||
#define NRF24_AA_P2_ON 0b00000100 // 2 2 enabled (default)
|
||||
#define NRF24_AA_P1_OFF 0b00000000 // 1 1 auto-ACK on pipe 1: disabled
|
||||
#define NRF24_AA_P1_ON 0b00000010 // 1 1 enabled (default)
|
||||
#define NRF24_AA_P0_OFF 0b00000000 // 0 0 auto-ACK on pipe 0: disabled
|
||||
#define NRF24_AA_P0_ON 0b00000001 // 0 0 enabled (default)
|
||||
|
||||
// NRF24_REG_EN_RXADDR
|
||||
#define NRF24_P5_OFF 0b00000000 // 5 5 receive pipe 5: disabled (default)
|
||||
#define NRF24_P5_ON 0b00100000 // 5 5 enabled
|
||||
#define NRF24_P4_OFF 0b00000000 // 4 4 receive pipe 4: disabled (default)
|
||||
#define NRF24_P4_ON 0b00010000 // 4 4 enabled
|
||||
#define NRF24_P3_OFF 0b00000000 // 3 3 receive pipe 3: disabled (default)
|
||||
#define NRF24_P3_ON 0b00001000 // 3 3 enabled
|
||||
#define NRF24_P2_OFF 0b00000000 // 2 2 receive pipe 2: disabled (default)
|
||||
#define NRF24_P2_ON 0b00000100 // 2 2 enabled
|
||||
#define NRF24_P1_OFF 0b00000000 // 1 1 receive pipe 1: disabled
|
||||
#define NRF24_P1_ON 0b00000010 // 1 1 enabled (default)
|
||||
#define NRF24_P0_OFF 0b00000000 // 0 0 receive pipe 0: disabled
|
||||
#define NRF24_P0_ON 0b00000001 // 0 0 enabled (default)
|
||||
|
||||
// NRF24_REG_SETUP_AW
|
||||
#define NRF24_ADDRESS_3_BYTES 0b00000001 // 1 0 address width: 3 bytes
|
||||
#define NRF24_ADDRESS_4_BYTES 0b00000010 // 1 0 4 bytes
|
||||
#define NRF24_ADDRESS_5_BYTES 0b00000011 // 1 0 5 bytes (default)
|
||||
|
||||
// NRF24_REG_SETUP_RETR
|
||||
#define NRF24_ARD 0b00000000 // 7 4 auto retransmit delay: t[us] = (NRF24_ARD + 1) * 250 us
|
||||
#define NRF24_ARC_OFF 0b00000000 // 3 0 auto retransmit count: auto retransmit disabled
|
||||
#define NRF24_ARC 0b00000011 // 3 0 up to 3 retransmits on AA fail (default)
|
||||
|
||||
// NRF24_REG_RF_CH
|
||||
#define NRF24_RF_CH 0b00000010 // 6 0 RF channel: f_CH[MHz] = 2400 MHz + NRF24_RF_CH
|
||||
|
||||
// NRF24_REG_RF_SETUP
|
||||
#define NRF24_CONT_WAVE_OFF 0b00000000 // 7 7 continuous carrier transmit: disabled (default)
|
||||
#define NRF24_CONT_WAVE_ON 0b10000000 // 7 7 enabled
|
||||
#define NRF24_DR_250_KBPS 0b00100000 // 5 5 data rate: 250 kbps
|
||||
#define NRF24_DR_1_MBPS 0b00000000 // 3 3 1 Mbps (default)
|
||||
#define NRF24_DR_2_MBPS 0b00001000 // 3 3 2 Mbps
|
||||
#define NRF24_RF_PWR_18_DBM 0b00000000 // 2 1 output power: -18 dBm
|
||||
#define NRF24_RF_PWR_12_DBM 0b00000010 // 2 1 -12 dBm
|
||||
#define NRF24_RF_PWR_6_DBM 0b00000100 // 2 1 -6 dBm
|
||||
#define NRF24_RF_PWR_0_DBM 0b00000110 // 2 1 0 dBm (default)
|
||||
|
||||
// NRF24_REG_STATUS
|
||||
#define NRF24_RX_DR 0b01000000 // 6 6 Rx data ready
|
||||
#define NRF24_TX_DS 0b00100000 // 5 5 Tx data sent
|
||||
#define NRF24_MAX_RT 0b00010000 // 4 4 maximum number of rentransmits reached (must be cleared to continue)
|
||||
#define NRF24_RX_FIFO_EMPTY 0b00001110 // 3 1 Rx FIFO is empty
|
||||
#define NRF24_RX_P_NO 0b00000000 // 3 1 number of data pipe that received data
|
||||
#define NRF24_TX_FIFO_FULL 0b00000001 // 0 0 Tx FIFO is full
|
||||
|
||||
// NRF24_REG_OBSERVE_TX
|
||||
#define NRF24_PLOS_CNT 0b00000000 // 7 4 number of lost packets
|
||||
#define NRF24_ARC_CNT 0b00000000 // 3 0 number of retransmitted packets
|
||||
|
||||
// NRF24_REG_RPD
|
||||
#define NRF24_RP_BELOW_64_DBM 0b00000000 // 0 0 received power in the current channel: less than -64 dBm
|
||||
#define NRF24_RP_ABOVE_64_DBM 0b00000001 // 0 0 more than -64 dBm
|
||||
|
||||
// NRF24_REG_FIFO_STATUS
|
||||
#define NRF24_TX_REUSE 0b01000000 // 6 6 reusing last transmitted payload
|
||||
#define NRF24_TX_FIFO_FULL_FLAG 0b00100000 // 5 5 Tx FIFO is full
|
||||
#define NRF24_TX_FIFO_EMPTY_FLAG 0b00010000 // 4 4 Tx FIFO is empty
|
||||
#define NRF24_RX_FIFO_FULL_FLAG 0b00000010 // 5 5 Rx FIFO is full
|
||||
#define NRF24_RX_FIFO_EMPTY_FLAG 0b00000001 // 4 4 Rx FIFO is empty
|
||||
|
||||
// NRF24_REG_DYNPD
|
||||
#define NRF24_DPL_P5_OFF 0b00000000 // 5 5 dynamic payload length on pipe 5: disabled (default)
|
||||
#define NRF24_DPL_P5_ON 0b00100000 // 5 5 enabled
|
||||
#define NRF24_DPL_P4_OFF 0b00000000 // 4 4 dynamic payload length on pipe 4: disabled (default)
|
||||
#define NRF24_DPL_P4_ON 0b00010000 // 4 4 enabled
|
||||
#define NRF24_DPL_P3_OFF 0b00000000 // 3 3 dynamic payload length on pipe 3: disabled (default)
|
||||
#define NRF24_DPL_P3_ON 0b00001000 // 3 3 enabled
|
||||
#define NRF24_DPL_P2_OFF 0b00000000 // 2 2 dynamic payload length on pipe 2: disabled (default)
|
||||
#define NRF24_DPL_P2_ON 0b00000100 // 2 2 enabled
|
||||
#define NRF24_DPL_P1_OFF 0b00000000 // 1 1 dynamic payload length on pipe 1: disabled (default)
|
||||
#define NRF24_DPL_P1_ON 0b00000010 // 1 1 enabled
|
||||
#define NRF24_DPL_P0_OFF 0b00000000 // 0 0 dynamic payload length on pipe 0: disabled (default)
|
||||
#define NRF24_DPL_P0_ON 0b00000001 // 0 0 enabled
|
||||
|
||||
// NRF24_REG_FEATURE
|
||||
#define NRF24_DPL_OFF 0b00000000 // 2 2 dynamic payload length: disabled (default)
|
||||
#define NRF24_DPL_ON 0b00000100 // 2 2 enabled
|
||||
#define NRF24_ACK_PAY_OFF 0b00000000 // 1 1 payload with ACK packets: disabled (default)
|
||||
#define NRF24_ACK_PAY_ON 0b00000010 // 1 1 enabled
|
||||
#define NRF24_DYN_ACK_OFF 0b00000000 // 0 0 payloads without ACK packets: disabled (default)
|
||||
#define NRF24_DYN_ACK_ON 0b00000001 // 0 0 enabled
|
||||
|
||||
class nRF24 {
|
||||
public:
|
||||
// constructor
|
||||
nRF24(Module* module);
|
||||
|
||||
// basic methods
|
||||
int16_t begin(int16_t freq = 2400, int16_t dataRate = 1000, uint8_t addrWidth = 5);
|
||||
int16_t sleep();
|
||||
int16_t standby();
|
||||
int16_t transmit(String& str, uint8_t* addr);
|
||||
int16_t transmit(const char* str, uint8_t* addr);
|
||||
int16_t transmit(uint8_t* data, size_t len, uint8_t* addr);
|
||||
|
||||
// configuration methods
|
||||
int16_t setFrequency(int16_t freq);
|
||||
int16_t setDataRate(int16_t dataRate);
|
||||
int16_t setAddressWidth(uint8_t addrWidth);
|
||||
int16_t setReceivePipe(uint8_t pipeNum, uint8_t* addr);
|
||||
int16_t setReceivePipe(uint8_t pipeNum, uint8_t addrByte);
|
||||
int16_t disablePipe(uint8_t pipeNum);
|
||||
|
||||
private:
|
||||
Module* _mod;
|
||||
|
||||
uint8_t _addrWidth;
|
||||
|
||||
void SPIreadRxPayload(uint8_t numBytes, uint8_t* inBytes);
|
||||
void SPIwriteTxPayload(uint8_t* data, uint8_t numBytes);
|
||||
void clearIRQ();
|
||||
};
|
||||
|
||||
#endif
|
Loading…
Add table
Reference in a new issue