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55 commits

Author SHA1 Message Date
jgromes
6a96d44b2b [SX127x] Fix automated RFO selection (#1412) 2025-02-17 21:19:18 +01:00
Matej Frančeškin
f3276c2e66 fix implicit conversion from float to double warnings 2025-01-15 16:06:47 +01:00
jgromes
0cc72c8310 [SX127x] Use length from startReceive in implicit header mode (#1345) 2024-12-15 15:48:05 +01:00
jgromes
4564d87721 [PHY] Use less generic modem names (#1294) 2024-10-29 17:14:04 +00:00
Jan Gromeš
e44e9b4bce
[PHY] Get/Set modem (#1294) 
* [PHY] Added set modem method

* Added new keyword

* [SX126x] Added setModem implementation

* [LoRaWAN] Use setModem

* [PHY] Added getModem

* [LoRaWAN] Use getModem instead of caching modulation

* [SX126x] Implement getModem

* Added new keywords

* [LR11x0] Added get/set modem

* [LLCC68] Added get/set modem

* [SX126x] Added missing default branch

* [SX127x] Added get/set modem

* [SX128x] Added get/set modem

* [CI] Drop Hellschreiber from AVR builds

* [CI] Drop Arduino Uno from CI
 2024-10-26 17:49:35 +02:00
Pavlo Manovi
6847fcda5c Reconcile implicit double / float promotion with math functions and passed function value types. Also suppress incorrect unused variable warnings when variables are used in logging macros. 2024-08-29 09:30:31 -04:00
StevenCellist
1b2b8bd67b
[LoRaWAN] Improve PHY behaviour, update beginABP, bugfixes (#1080) 
* [LoRaWAN] Add getter for ToA, prevent MAC queue overflow

* [LoRaWAN] Permute arguments to beginABP

* Implement & split off checkOutputPower

* [LoRaWAN] Configure physical layer on each up/downlink

* [LoRaWAN] Remove unnecessary dynamic array

* [LoRaWAN] Improve downlink handling

* Resolve return-warnings in checkOutputPower()

* [LoRaWAN] Improve buffer definition

* [LoRaWAN] Prevent requesting repeated MAC commands

* Update keywords.txt

* [CC1101] Resolve unused variable warning

* [CC1101] Update checkOutputPower

* [SX1278] Fix variable assignment

* Update keywords.txt

* [CC1101] Added checkOutputPower override for PHY compatibility

* [LR11x0] Added checkOutputPower override for PHY compatibility

* [SX127x] Added checkOutputPower override for PHY compatibility

---------

Co-authored-by: jgromes <jan.gromes@gmail.com>
 2024-05-01 13:35:22 +02:00
jgromes
c11ac4703b [SX127x] Fixed getRSSI overload for PhysicalLayer (#1064) 2024-04-13 21:21:33 +02:00
jgromes
a168f9ba41 [SX127x] Fixed data rate checking 2024-01-28 13:29:14 +01:00
jgromes
a4b148d609 [SX127x] Implemented data rate check 2024-01-27 18:45:37 +01:00
jgromes
bbe407b50f [SX127x] Cleanup private/protected members 2024-01-12 18:51:55 +01:00
jgromes
34c861cfbe [SX127x] Reworked macro configuration system 2023-11-27 21:14:33 +01:00
jgromes
10d225fadb [SX127x] Allow alternate chip versions 2023-09-24 18:19:19 +02:00
jgromes
7dec9477ae [PHY] Added coding rate to data rate struct 2023-09-12 19:06:30 +02:00
jgromes
44ffce1725 [SX127x] Skip printing symbol length 2023-09-12 19:05:06 +02:00
jgromes
d5ce384bda [SX127x] Implemented new common PHY methods 2023-07-06 11:17:29 +02:00
Olocool17
acc16c25bd [SX1272] Correct LoRa mode CRC register values 2023-05-11 20:47:19 +02:00
jgromes
cc8c8f2eed [SX127x] General reformatting 2023-04-23 22:42:13 +02:00
Mestery
ec3d4eaf20 Improve hardware abstraction layer 2023-04-12 23:16:18 +02:00
Mestery
220b4dad7f
use printf in both build 2023-04-10 09:13:58 +00:00
jgromes
8587f73bd9 [SX127x] Implemented fractional bit rate (#505) 2023-04-09 17:08:45 +02:00
jgromes
f62f912c87 [SX127x] Unified getRSSI interface 2023-03-27 23:22:03 +02:00
jgromes
c3de8b9099 [SX127x] Explicitly enabled CRC (#706) 2023-03-23 19:06:43 +01:00
jgromes
1698409e84 [SX127x] Set default FSK bitrate to 4k8 2021-11-27 18:13:06 +01:00
jgromes
8c7b8a1b63 [SX127x] Update to 5.0.0 2021-11-14 11:42:12 +01:00
jgromes
8579b2cb1b [SX127x] Removed redundant default argument 2021-10-18 21:30:54 +02:00
jgromes
9d3807168f [SX127x] Fixed low-power output on RFO pin (#385) 2021-10-17 11:10:52 +02:00
jgromes
498b638234 [SX127x] Reworked errata fix (#372) 2021-09-22 22:17:12 +02:00
jgromes
8ffca81521 [SX127x] Replace abs() with fabs() 2021-05-04 09:21:23 +02:00
jgromes
86ca714d00 [SX127x] OOK functions style cleanup 2021-03-26 05:55:22 +01:00
Christophe Painchaud
3e1088f34a styles and syntax changes 2021-03-25 13:39:44 +01:00
jgromes
be1471c32a [SX127x] Fixed shaping in OOK (#268) 2021-03-14 21:50:42 +01:00
jgromes
519b34d309 [SX127x] Added FSK CRC mode configuration (#266) 2021-03-14 16:07:44 +01:00
jgromes
0cdd49ca11 [SX127x] Implemented implicit LoRa header (#181) 2021-02-21 16:54:38 +01:00
jgromes
1e47f8bca3 [SX127x] Swap frequency and bandwidth config in LoRa begin (#251) 2021-02-13 18:14:07 +01:00
jgromes
09a73591ba [SX127x] Fixed top-level configFSK not being called 2021-02-13 16:21:00 +01:00
jgromes
bc613daf23 [SX127x] Moved non-configurable parameters config into base class 2021-02-07 17:51:55 +01:00
jgromes
c63c8f376f [SX127x] Clarify ternary operator priority (#217) 2020-12-29 08:41:48 +01:00
jgromes
8438aa93ef [SX127x] Fixed incorrect CRC configuration (#217) 2020-12-25 09:37:06 +01:00
jgromes
c127712c5e [SX127x] Added check for LoRa header CRC mismatch (#200) 2020-11-19 17:07:32 +01:00
jgromes
d7a620c8ea [SX1272] Fixed incorrect FSK/OOK modulation check 2020-08-07 17:45:39 +02:00
jgromes
6ff84d7b23 [SX127x] Added Module overrides for all Arduino core functions 2020-08-01 16:34:37 +02:00
jgromes
58194483b1 [SX127x] Added methods to manually set LoRa LDRO (#162) 2020-07-08 18:52:34 +02:00
jgromes
e1141ca64c [SX127x] Synced parameters of all LoRa modules 2020-07-06 11:48:14 +02:00
jgromes
82e4cb7f97 [SX127x] Synced parameters of all FSK modules 2020-07-06 11:13:53 +02:00
jgromes
7dc7f4d76c [SX127x] Changed shaping datatype to uint8_t 2020-07-06 08:53:05 +02:00
jgromes
a367a3fe69 [SX127x] Fixes from cppcheck scan 2020-07-04 14:49:05 +02:00
jgromes
3dd3a471e5 [SX127x] Reworked driver exclusion 2020-06-30 10:43:56 +02:00
jgromes
274b38d556 [SX127x] Using range check macro 2020-03-30 19:29:29 +02:00
Callan Bryant
6c99486343
Swap delayMicroseconds() to delay where appropriate 
See https://github.com/jgromes/RadioLib/issues/126 for context.
 2020-03-16 12:12:06 +00:00