7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
86 lines
2.6 KiB
Diff
86 lines
2.6 KiB
Diff
From a977683c5364eb855601b152e20bd7b45f157874 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Thu, 9 Aug 2018 18:52:13 +0200
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Subject: [PATCH 083/146] clk: sunxi-ng: Add maximum rate constraint to NM PLLs
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On some NM PLLs, frequency can be set above PLL working range.
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Add a constraint for maximum supported rate. This way, drivers can
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specify which is maximum allowed rate for PLL.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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drivers/clk/sunxi-ng/ccu_nm.c | 7 +++++++
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drivers/clk/sunxi-ng/ccu_nm.h | 30 ++++++++++++++++++++++++++++++
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2 files changed, 37 insertions(+)
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diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
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index 4e2073307f34..6fe3c14f7b2d 100644
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--- a/drivers/clk/sunxi-ng/ccu_nm.c
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+++ b/drivers/clk/sunxi-ng/ccu_nm.c
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@@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
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return rate;
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}
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+ if (nm->max_rate && rate > nm->max_rate) {
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+ rate = nm->max_rate;
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+ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
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+ rate /= nm->fixed_post_div;
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+ return rate;
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+ }
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+
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if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
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if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= nm->fixed_post_div;
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diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
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index 1d8b459c50b7..de232f2199a6 100644
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--- a/drivers/clk/sunxi-ng/ccu_nm.h
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+++ b/drivers/clk/sunxi-ng/ccu_nm.h
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@@ -38,6 +38,7 @@ struct ccu_nm {
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unsigned int fixed_post_div;
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unsigned int min_rate;
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+ unsigned int max_rate;
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struct ccu_common common;
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};
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@@ -115,6 +116,35 @@ struct ccu_nm {
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}, \
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}
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+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
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+ _parent, _reg, \
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+ _min_rate, _max_rate, \
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+ _nshift, _nwidth, \
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+ _mshift, _mwidth, \
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+ _frac_en, _frac_sel, \
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+ _frac_rate_0, \
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+ _frac_rate_1, \
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+ _gate, _lock, _flags) \
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+ struct ccu_nm _struct = { \
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+ .enable = _gate, \
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+ .lock = _lock, \
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+ .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
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+ .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
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+ .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
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+ _frac_rate_0, \
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+ _frac_rate_1), \
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+ .min_rate = _min_rate, \
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+ .max_rate = _max_rate, \
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+ .common = { \
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+ .reg = _reg, \
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+ .features = CCU_FEATURE_FRACTIONAL, \
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+ .hw.init = CLK_HW_INIT(_name, \
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+ _parent, \
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+ &ccu_nm_ops, \
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+ _flags), \
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+ }, \
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+ }
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+
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#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
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_nshift, _nwidth, \
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_mshift, _mwidth, \
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--
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2.17.1
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