7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From 30bbeb66d0f9cc6f49cc95e60443eeca952b119c Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Sat, 30 Jun 2018 07:55:34 +0200
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Subject: [PATCH 76/82] arm64: dts: sun50i-h5: Add mali GPU node
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https://github.com/jernejsk/LibreELEC.tv/blob/aw_h5_init/projects/Allwinner/devices/H5/patches/linux/20-add-mali-node.patch
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---
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arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 38 ++++++++++++++++++++
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1 file changed, 38 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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index acd90f390e88..67e2246a6374 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@@ -94,6 +94,44 @@
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method = "smc";
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};
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+ soc {
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+ mali: gpu@1280000 {
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+ compatible = "allwinner,sun50i-h5-mali",
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+ "arm,mali-450";
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+ reg = <0x01e80000 0x30000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "gp",
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+ "gpmmu",
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+ "pmu",
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+ "pp",
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+ "pp0",
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+ "ppmmu0",
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+ "pp1",
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+ "ppmmu1",
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+ "pp2",
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+ "ppmmu2",
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+ "pp3",
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+ "ppmmu3";
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+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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+ clock-names = "bus", "core";
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+ resets = <&ccu RST_BUS_GPU>;
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+
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+ assigned-clocks = <&ccu CLK_GPU>;
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+ assigned-clock-rates = <384000000>;
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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--
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2.20.1
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