7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
116 lines
3.2 KiB
Diff
116 lines
3.2 KiB
Diff
From 9e05f3d014b05df39a55dfd6a08d4bd18a301307 Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Mon, 14 May 2018 01:13:01 +0200
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Subject: [PATCH 13/82] ARM: dts: sunxi-h3-h5: Add more CPU OPP for H3/H5
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These OPPs can be used with better cooling and/or thermal regulation.
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 78 ++++++++++++++++++++++++++++++
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1 file changed, 78 insertions(+)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index 539b69fecbe9..f47c22b622f9 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -109,6 +109,24 @@
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compatible = "operating-points-v2";
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opp-shared;
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+ opp@120000000 {
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+ opp-hz = /bits/ 64 <120000000>;
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+ opp-microvolt = <1040000 1040000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@240000000 {
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+ opp-hz = /bits/ 64 <240000000>;
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+ opp-microvolt = <1040000 1040000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@480000000 {
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+ opp-hz = /bits/ 64 <480000000>;
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+ opp-microvolt = <1040000 1040000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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opp@648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000 1040000 1300000>;
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@@ -121,11 +139,71 @@
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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+ opp@960000000 {
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+ opp-hz = /bits/ 64 <960000000>;
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+ opp-microvolt = <1200000 1200000 1300000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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opp@1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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+
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+ opp@1056000000 {
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+ opp-hz = /bits/ 64 <1056000000>;
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+ opp-microvolt = <1320000 1320000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <1320000 1320000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1152000000 {
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+ opp-hz = /bits/ 64 <1152000000>;
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+ opp-microvolt = <1320000 1320000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1320000 1320000 1320000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1224000000 {
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+ opp-hz = /bits/ 64 <1224000000>;
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+ opp-microvolt = <1340000 1340000 1340000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1248000000 {
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+ opp-hz = /bits/ 64 <1248000000>;
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+ opp-microvolt = <1340000 1340000 1340000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1296000000 {
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+ opp-hz = /bits/ 64 <1296000000>;
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+ opp-microvolt = <1340000 1340000 1340000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1344000000 {
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+ opp-hz = /bits/ 64 <1344000000>;
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+ opp-microvolt = <1400000 1400000 1400000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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+ opp@1368000000 {
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+ opp-hz = /bits/ 64 <1368000000>;
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+ opp-microvolt = <1400000 1400000 1400000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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};
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de: display-engine {
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--
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2.20.1
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