7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
90 lines
3.1 KiB
Diff
90 lines
3.1 KiB
Diff
From 99ce6e04231a5a185c1cc7d8d2bd9484c8eabc56 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Tue, 4 Sep 2018 12:40:44 +0800
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Subject: [PATCH 092/146] clk: sunxi-ng: a64: Add max. rate constraint to video
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PLLs
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Video PLLs on A64 can be set to higher rate that it is actually
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supported by HW.
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Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
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clock driver. Interestengly, user manual specifies maximum frequency to
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be 600 MHz. Historically, this data was wrong in some user manuals for
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other SoCs, so more faith is put in BSP clock driver.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++++++++++++++-------------
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1 file changed, 26 insertions(+), 24 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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index 40a7b5fd091c..90ffee824c33 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@@ -64,18 +64,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
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- "osc24M", 0x010,
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- 192000000, /* Minimum rate */
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- 8, 7, /* N */
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- 0, 4, /* M */
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- BIT(24), /* frac enable */
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- BIT(25), /* frac select */
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- 270000000, /* frac rate 0 */
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- 297000000, /* frac rate 1 */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
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+ "osc24M", 0x010,
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+ 192000000, /* Minimum rate */
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+ 1008000000, /* Maximum rate */
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+ 8, 7, /* N */
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+ 0, 4, /* M */
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+ BIT(24), /* frac enable */
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+ BIT(25), /* frac select */
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+ 270000000, /* frac rate 0 */
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+ 297000000, /* frac rate 1 */
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+ BIT(31), /* gate */
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+ BIT(28), /* lock */
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x018,
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@@ -126,18 +127,19 @@ static struct ccu_nk pll_periph1_clk = {
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},
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};
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
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- "osc24M", 0x030,
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- 192000000, /* Minimum rate */
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- 8, 7, /* N */
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- 0, 4, /* M */
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- BIT(24), /* frac enable */
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- BIT(25), /* frac select */
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- 270000000, /* frac rate 0 */
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- 297000000, /* frac rate 1 */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
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+ "osc24M", 0x030,
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+ 192000000, /* Minimum rate */
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+ 1008000000, /* Maximum rate */
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+ 8, 7, /* N */
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+ 0, 4, /* M */
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+ BIT(24), /* frac enable */
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+ BIT(25), /* frac select */
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+ 270000000, /* frac rate 0 */
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+ 297000000, /* frac rate 1 */
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+ BIT(31), /* gate */
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+ BIT(28), /* lock */
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
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"osc24M", 0x038,
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--
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2.17.1
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