7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
132 lines
4.6 KiB
Diff
132 lines
4.6 KiB
Diff
From 559d035001097a7ce6018117866e8f573fb15211 Mon Sep 17 00:00:00 2001
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From: Jonathan Liu <net147@gmail.com>
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Date: Fri, 7 Sep 2018 12:19:45 +0800
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Subject: [PATCH 089/146] drm/sun4i: tcon: Add dithering support for
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RGB565/RGB666 LCD panels
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The hardware supports dithering on TCON channel 0 which is used for LCD
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panels.
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Dithering is a method of approximating a color from a mixture of other
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colors when the required color isn't available. It reduces color
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banding artifacts that can be observed when displaying gradients
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(e.g. grayscale gradients). This may occur when the image that needs
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to be displayed is 24-bit but the LCD panel is a lower bit depth and
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does not perform dithering on its own.
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Signed-off-by: Jonathan Liu <net147@gmail.com>
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[wens@csie.org: check display_info.bpc first; handle LVDS and MIPI DSI]
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 62 ++++++++++++++++++++++++++++++
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1 file changed, 62 insertions(+)
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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index 52e1150612ba..0d438f633b5d 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -12,11 +12,13 @@
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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+#include <drm/drm_connector.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_of.h>
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+#include <drm/drm_panel.h>
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#include <uapi/drm/drm_mode.h>
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@@ -275,6 +277,57 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
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SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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}
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+static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
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+ const struct drm_connector *connector)
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+{
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+ u32 bus_format = 0;
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+ u32 val = 0;
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+
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+ /* XXX Would this ever happen? */
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+ if (!connector)
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+ return;
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+
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+ /*
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+ * FIXME: Undocumented bits
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+ *
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+ * The whole dithering process and these parameters are not
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+ * explained in the vendor documents or BSP kernel code.
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+ */
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
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+ regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
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+
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+ /* Do dithering if panel only supports 6 bits per color */
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+ if (connector->display_info.bpc == 6)
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+ val |= SUN4I_TCON0_FRM_CTL_EN;
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+
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+ if (connector->display_info.num_bus_formats == 1)
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+ bus_format = connector->display_info.bus_formats[0];
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+
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+ /* Check the connection format */
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+ switch (bus_format) {
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+ case MEDIA_BUS_FMT_RGB565_1X16:
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+ /* R and B components are only 5 bits deep */
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+ val |= SUN4I_TCON0_FRM_CTL_MODE_R;
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+ val |= SUN4I_TCON0_FRM_CTL_MODE_B;
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+ case MEDIA_BUS_FMT_RGB666_1X18:
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+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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+ /* Fall through: enable dithering */
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+ val |= SUN4I_TCON0_FRM_CTL_EN;
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+ break;
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+ }
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+
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+ /* Write dithering settings */
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+ regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
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+}
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+
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static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
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const struct drm_encoder *encoder,
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const struct drm_display_mode *mode)
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@@ -292,6 +345,9 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
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sun4i_tcon0_mode_set_common(tcon, mode);
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+ /* Set dithering if needed */
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+ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
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+
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_IF_MASK,
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SUN4I_TCON0_CTL_IF_8080);
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@@ -357,6 +413,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
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tcon->dclk_max_div = 7;
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sun4i_tcon0_mode_set_common(tcon, mode);
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+ /* Set dithering if needed */
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+ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
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+
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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@@ -430,6 +489,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
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tcon->dclk_max_div = 127;
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sun4i_tcon0_mode_set_common(tcon, mode);
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+ /* Set dithering if needed */
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+ sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector);
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+
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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--
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2.17.1
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