7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
63 lines
2.3 KiB
Diff
63 lines
2.3 KiB
Diff
From 461aa98f7ee6d5347625728949d51122ee92999b Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Thu, 9 Aug 2018 18:52:14 +0200
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Subject: [PATCH 084/146] clk: sunxi-ng: h3/h5: Add max. rate constraint to
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pll-video
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As it turns out, pll-video can be set to higher rate that it is really
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supported by HW.
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For example, one monitor requested 185.58 MHz pixel clock. Clock
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framework calculated that minimum rate error would be when pll-video
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is set to 2040 MHz. This is clearly out of specs.
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Both H3 and H5 user manuals specify 600 MHz as maximum supported rate.
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However, BSP clock drivers allow up to 912 MHz and 1008 MHz
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respectively. Here 912 MHz is chosen because user manuals were already
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proven wrong once for lower limits.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 25 +++++++++++++------------
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1 file changed, 13 insertions(+), 12 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 77ed0b0ba681..eb5c608428fa 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -69,18 +69,19 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
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- "osc24M", 0x0010,
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- 192000000, /* Minimum rate */
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- 8, 7, /* N */
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- 0, 4, /* M */
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- BIT(24), /* frac enable */
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- BIT(25), /* frac select */
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- 270000000, /* frac rate 0 */
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- 297000000, /* frac rate 1 */
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- BIT(31), /* gate */
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- BIT(28), /* lock */
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- CLK_SET_RATE_UNGATE);
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+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
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+ "osc24M", 0x0010,
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+ 192000000, /* Minimum rate */
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+ 912000000, /* Maximum rate */
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+ 8, 7, /* N */
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+ 0, 4, /* M */
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+ BIT(24), /* frac enable */
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+ BIT(25), /* frac select */
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+ 270000000, /* frac rate 0 */
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+ 297000000, /* frac rate 1 */
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+ BIT(31), /* gate */
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+ BIT(28), /* lock */
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+ CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x0018,
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--
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2.17.1
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