96 lines
3.6 KiB
Diff
96 lines
3.6 KiB
Diff
From 7cc4ab225ae30bd9ec9239e7dba5b2937f526ccc Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Mon, 31 Jul 2017 15:29:46 +0100
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Subject: drm/bridge: dw-hdmi: add better clock disable control
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The video setup path aways sets the clock disable register to a specific
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value, which has the effect of disabling the CEC engine. When we add the
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CEC driver, this becomes a problem.
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Fix this by only setting/clearing the bits that the video path needs to.
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Reviewed-by: Jose Abreu <joabreu@synopsys.com>
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Link: https://patchwork.freedesktop.org/patch/msgid/E1dcBha-00088l-DE@rmk-PC.armlinux.org.uk
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---
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drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 29 ++++++++++++++++++-----------
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1 file changed, 18 insertions(+), 11 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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index 67b4af0..f8171cd 100644
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--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
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@@ -166,6 +166,7 @@ struct dw_hdmi {
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bool bridge_is_on; /* indicates the bridge is on */
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bool rxsense; /* rxsense state */
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u8 phy_mask; /* desired phy int mask settings */
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+ u8 mc_clkdis; /* clock disable register */
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spinlock_t audio_lock;
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struct mutex audio_mutex;
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@@ -551,8 +552,11 @@ EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
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static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
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{
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- hdmi_modb(hdmi, enable ? 0 : HDMI_MC_CLKDIS_AUDCLK_DISABLE,
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- HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
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+ if (enable)
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+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
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+ else
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+ hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
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+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
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}
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static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
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@@ -1574,8 +1578,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
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/* HDMI Initialization Step B.4 */
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static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
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{
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- u8 clkdis;
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-
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/* control period minimum duration */
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hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
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hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
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@@ -1587,17 +1589,21 @@ static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
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hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
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/* Enable pixel clock and tmds data path */
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- clkdis = 0x7F;
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- clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
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- hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
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+ hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
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+ HDMI_MC_CLKDIS_CSCCLK_DISABLE |
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+ HDMI_MC_CLKDIS_AUDCLK_DISABLE |
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+ HDMI_MC_CLKDIS_PREPCLK_DISABLE |
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+ HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
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+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
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+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
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- clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
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- hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
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+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
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+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
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/* Enable csc path */
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if (is_color_space_conversion(hdmi)) {
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- clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
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- hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
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+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
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+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
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}
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/* Enable color space conversion if needed */
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@@ -2272,6 +2278,7 @@ __dw_hdmi_probe(struct platform_device *pdev,
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hdmi->disabled = true;
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hdmi->rxsense = true;
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hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
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+ hdmi->mc_clkdis = 0x7f;
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mutex_init(&hdmi->mutex);
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mutex_init(&hdmi->audio_mutex);
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--
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cgit v1.1
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