7d5f1dbda1
Some patches were part of other linux-mainline kernel versions but are not anymore part of the current 4.19.76. Move 0001-Enable-uart3-for-NanoPi-Neo-Air-used-by-BT.patch in linux-mainline_4.19.76.bbappend to avoid error patching file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Hunk #2 FAILED at 162. 1 out of 2 hunks FAILED -- rejects in file arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts Place all patches from Armbian in a separate directory and do all the Balena specific operations in linux-mainline_%.bbappend only. Changelog-entry: Remove unused patches and cleanup Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
82 lines
2.3 KiB
Diff
82 lines
2.3 KiB
Diff
From 0ab580b2eac299d7f73c2ff3e7bf590a3fc7ea6d Mon Sep 17 00:00:00 2001
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From: Ondrej Jirman <megous@megous.com>
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Date: Fri, 20 Apr 2018 04:05:28 +0200
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Subject: [PATCH 68/82] ARM: dts: sun8i-a83t: Add clock-frequency to avoid boot
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warnings
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Signed-off-by: Ondrej Jirman <megous@megous.com>
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---
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arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
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index bffcee058627..c09d8ee2f7c5 100644
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--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
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+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
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@@ -65,6 +65,7 @@
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clocks = <&ccu CLK_C0CPUX>;
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clock-names = "cpu";
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -77,6 +78,7 @@
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cpu@1 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -86,6 +88,7 @@
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cpu@2 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -95,6 +98,7 @@
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cpu@3 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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cci-control-port = <&cci_control0>;
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@@ -106,6 +110,7 @@
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clocks = <&ccu CLK_C1CPUX>;
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clock-names = "cpu";
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -118,6 +123,7 @@
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cpu@101 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -127,6 +133,7 @@
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cpu@102 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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@@ -136,6 +143,7 @@
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cpu@103 {
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compatible = "arm,cortex-a7";
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+ clock-frequency = <1200000000>;
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device_type = "cpu";
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operating-points-v2 = <&cpu1_opp_table>;
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cci-control-port = <&cci_control1>;
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--
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2.20.1
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