52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
From 33a54161aeee56fbf78b0222fd24ad9846dca269 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Thu, 13 Apr 2017 10:13:54 +0800
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Subject: [PATCH 42/87] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after
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rate change
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This patch utilizes the new PLL clk notifier to gate then ungate the
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PLL CPU clock after rate changes. This should prevent any system hangs
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resulting from cpufreq changes to the clk.
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Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
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Reported-by: Ondrej Jirman <megous@megous.com>
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Tested-by: Icenowy Zheng <icenowy@aosc.io>
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Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 552a1ff3f4fc..b886ebc55eaa 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
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.num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
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};
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+static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
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+ .common = &pll_cpux_clk.common,
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+ /* copy from pll_cpux_clk */
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+ .enable = BIT(31),
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+ .lock = BIT(28),
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+};
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+
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static struct ccu_mux_nb sun8i_h3_cpu_nb = {
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.common = &cpux_clk.common,
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.cm = &cpux_clk.mux,
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@@ -1130,6 +1137,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
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sunxi_ccu_probe(node, reg, desc);
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+ /* Gate then ungate PLL CPU after any rate changes */
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+ ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
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+
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+ /* Reparent CPU during PLL CPU rate changes */
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ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
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&sun8i_h3_cpu_nb);
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}
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--
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2.13.5
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