36 lines
1.4 KiB
Diff
36 lines
1.4 KiB
Diff
From 14663856bae0502be3efa0bff5506507b1e8af26 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Sun, 9 Apr 2017 02:10:34 +0800
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Subject: [PATCH 43/87] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for
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CPUX clock on H3
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The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
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can be adjusted by changing the frequency of the PLL_CPUX clock.
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Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
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clock can be adjusted when adjusting the CPUX clock.
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Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Reviewed-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index b886ebc55eaa..8321d2167cc3 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
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static const char * const cpux_parents[] = { "osc32k", "osc24M",
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"pll-cpux" , "pll-cpux" };
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static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
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- 0x050, 16, 2, CLK_IS_CRITICAL);
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+ 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
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--
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2.13.5
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