28 lines
1.1 KiB
Diff
28 lines
1.1 KiB
Diff
From 7bdf732ba13e452e4ae2a717ea50d7e0f2d64ddd Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Tue, 11 Apr 2017 21:45:23 +0200
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Subject: [PATCH] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
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When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
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Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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---
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 7a222ff1ad0a9..36224ba93f9da 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
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static const char * const hdmi_parents[] = { "pll-video" };
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static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
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- 0x150, 0, 4, 24, 2, BIT(31), 0);
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+ 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
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0x154, BIT(31), 0);
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