49 lines
1.9 KiB
Diff
49 lines
1.9 KiB
Diff
From b64dfec01050a010fa764dae3746353bdbdecfe1 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jernej=20=C5=A0krabec?= <jernej.skrabec@siol.net>
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Date: Sun, 30 Jul 2017 18:41:47 +0200
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Subject: [PATCH] clk: sunxi-ng: Fix fractional mode for N-M clocks
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N-M factor clock driver is missing a call to ccu_frac_helper_enable()
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when fractional mode is used. Additionally, most SoCs require that M
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factor must be set to 0 when fractional mode is used.
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Without this patch, clock keeps the old value and clk_set_rate() returns
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without error.
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Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
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CC: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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drivers/clk/sunxi-ng/ccu_nm.c | 16 ++++++++++++++--
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1 file changed, 14 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
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index 5e5e90a4a50c8..c6ba866b99d3c 100644
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--- a/drivers/clk/sunxi-ng/ccu_nm.c
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+++ b/drivers/clk/sunxi-ng/ccu_nm.c
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@@ -117,10 +117,22 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long flags;
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u32 reg;
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- if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
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+ if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
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+ spin_lock_irqsave(nm->common.lock, flags);
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+
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+ /* most SoCs require M to be 0 if fractional mode is used */
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+ reg = readl(nm->common.base + nm->common.reg);
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+ reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
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+ writel(reg, nm->common.base + nm->common.reg);
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+
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+ spin_unlock_irqrestore(nm->common.lock, flags);
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+
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+ ccu_frac_helper_enable(&nm->common, &nm->frac);
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+
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return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate);
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- else
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+ } else {
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ccu_frac_helper_disable(&nm->common, &nm->frac);
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+ }
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_nm.min_n = nm->n.min ?: 1;
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_nm.max_n = nm->n.max ?: 1 << nm->n.width;
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