From 7bdf732ba13e452e4ae2a717ea50d7e0f2d64ddd Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 11 Apr 2017 21:45:23 +0200 Subject: [PATCH] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set. Add CLK_SET_RATE_PARENT flag for H3 HDMI clock. Signed-off-by: Jernej Skrabec Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 7a222ff1ad0a9..36224ba93f9da 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", static const char * const hdmi_parents[] = { "pll-video" }; static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, - 0x150, 0, 4, 24, 2, BIT(31), 0); + 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x154, BIT(31), 0);