From a3e8bf0e49687679382fd76aaad5be49bd65793c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 25 Dec 2017 12:10:06 +0800 Subject: [PATCH 23/35] arm64: allwinner: h6: add USB3 device nodes Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and a custom PHY. Add device tree nodes for them. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index f3ca411..b3d8da4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -233,6 +233,44 @@ status = "disabled"; }; + usb3: usb@5200000 { + compatible = "allwinner,sun50i-h6-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&ccu CLK_BUS_XHCI>; + clock-names = "bus"; + resets = <&ccu RST_BUS_XHCI>; + reset-names = "bus"; + status = "disabled"; + + dwc3: dwc3 { + compatible = "snps,dwc3"; + reg = <0x5200000 0x10000>; + interrupts = ; + /* + * According to Wink from Allwinner, the + * USB3 port on H6 is not capable of OTG; + * the datasheet doesn't mention OTG at all + * either, so the dr_mode is default to + * "host" here. + */ + dr_mode = "host"; + phys = <&usb3phy>; + phy-names = "usb3-phy"; + status = "disabled"; + }; + }; + + usb3phy: phy@5210000 { + compatible = "allwinner,sun50i-h6-usb3-phy"; + reg = <0x5210000 0x10000>; + clocks = <&ccu CLK_USB_PHY1>; + resets = <&ccu RST_USB_PHY1>; + #phy-cells = <0>; + status = "disabled"; + }; + r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; -- 2.7.4