From 9e05f3d014b05df39a55dfd6a08d4bd18a301307 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 14 May 2018 01:13:01 +0200 Subject: [PATCH 13/82] ARM: dts: sunxi-h3-h5: Add more CPU OPP for H3/H5 These OPPs can be used with better cooling and/or thermal regulation. Signed-off-by: Ondrej Jirman --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 78 ++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 539b69fecbe9..f47c22b622f9 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -109,6 +109,24 @@ compatible = "operating-points-v2"; opp-shared; + opp@120000000 { + opp-hz = /bits/ 64 <120000000>; + opp-microvolt = <1040000 1040000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1040000 1040000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1040000 1040000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000 1040000 1300000>; @@ -121,11 +139,71 @@ clock-latency-ns = <244144>; /* 8 32k periods */ }; + opp@960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1200000 1200000 1300000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + opp@1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1300000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; + + opp@1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1320000 1320000 1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1320000 1320000 1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1320000 1320000 1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1320000 1320000 1320000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1224000000 { + opp-hz = /bits/ 64 <1224000000>; + opp-microvolt = <1340000 1340000 1340000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1340000 1340000 1340000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1340000 1340000 1340000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-microvolt = <1400000 1400000 1400000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1368000000 { + opp-hz = /bits/ 64 <1368000000>; + opp-microvolt = <1400000 1400000 1400000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; }; de: display-engine { -- 2.20.1