diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bb b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bb new file mode 100644 index 0000000..692dbd3 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bb @@ -0,0 +1,80 @@ +DESCRIPTION="Upstream's U-boot configured for sunxi devices" + +FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot_2019.04:" +require recipes-bsp/u-boot/u-boot.inc + +DEPENDS += " bc-native dtc-native swig-native python3-native flex-native bison-native " +DEPENDS_append_sun50i = " atf-sunxi " + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" + +COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i|sun8i|sun50i)" + +DEFAULT_PREFERENCE_sun4i="1" +DEFAULT_PREFERENCE_sun5i="1" +DEFAULT_PREFERENCE_sun7i="1" +DEFAULT_PREFERENCE_sun8i="1" +DEFAULT_PREFERENCE_sun50i="1" + +SRC_URI = "git://git.denx.de/u-boot.git;branch=master \ + file://0000-sunxi-allwinner-a10-spi-driver.patch \ + file://0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch \ + file://Merrii_Hummingbird_A20.patch \ + file://add-a20-optional-eMMC.patch \ + file://add-a64-olinuxino-emmc-support.patch \ + file://add-a64-olinuxino-spl-spi.patch \ + file://add-a64-orangepiwinplus-emmc-support.patch \ + file://add-awsom-defconfig.patch \ + file://add-beelink-x2.patch \ + file://add-emmc_support_to_neo1_and_2.patch \ + file://add-nanopi-air-emmc.patch \ + file://add-nanopi-duo.patch \ + file://add-nanopi-m1-plus2-emmc.patch \ + file://add-nanopi-neo-core.patch \ + file://add-nanopi-r1-and-duo2.patch \ + file://add-orangepi-plus2-emmc.patch \ + file://add-orangepi-zero-usb-boot-support.patch \ + file://add-orangepi-zeroplus2_h3.patch \ + file://add-sunvell-r69.patch \ + file://add-teres.patch \ + file://add-xx-boot-auto-dt-select-neo2.patch \ + file://add-xx-nanopi-k1-plus-emmc.patch \ + file://add-xx-nanopineocore2.patch \ + file://add-zeropi.patch \ + file://adjust-default-dram-clockspeeds.patch \ + file://adjust-small-boards-cpufreq.patch \ + file://enable-autoboot-keyed.patch \ + file://enable-ethernet-orangepiprime.patch \ + file://enable-r_pio-gpio-access-h3-h5.patch \ + file://fdt-setprop-fix-unaligned-access.patch \ + file://fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch \ + file://fix-orangepizero-plus-h3.patch \ + file://h3-Fix-PLL1-setup-to-never-use-dividers.patch \ + file://h3-enable-power-led.patch \ + file://h3-set-safe-axi_apb-clock-dividers.patch \ + file://lower-default-DRAM-freq-A64-H5.patch \ + file://sun8i-set-machid.patch \ + file://sunxi-boot-splash.patch \ + file://armbianEnv.txt \ + file://boot.cmd \ + " + +SRCREV = "3c99166441bf3ea325af2da83cfe65430b49c066" + +PV = "v2019.04+git${SRCPV}" +PE = "2" + +S = "${WORKDIR}/git" + +UBOOT_ENV_SUFFIX = "scr" +UBOOT_ENV = "boot" + +EXTRA_OEMAKE += ' HOSTLDSHARED="${BUILD_CC} -shared ${BUILD_LDFLAGS} ${BUILD_CFLAGS}" ' +EXTRA_OEMAKE_append_sun50i = " BL31=${DEPLOY_DIR_IMAGE}/bl31.bin " + +do_compile_sun50i[depends] += "atf-sunxi:do_deploy" + +do_compile_append() { + ${B}/tools/mkimage -C none -A arm -T script -d ${WORKDIR}/boot.cmd ${WORKDIR}/${UBOOT_ENV_BINARY} +} diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bbappend b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bbappend new file mode 100644 index 0000000..9dc67d8 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bbappend @@ -0,0 +1,20 @@ +UBOOT_KCONFIG_SUPPORT = "1" +inherit resin-u-boot + +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +#remove the resin-specific-env-integration-kconfig.patch patch from meta-resin +#and the 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch patch from +#meta-sunxi because these fail to apply +SRC_URI_remove = "file://0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch \ + file://resin-specific-env-integration-kconfig.patch" + +#Add updated patches for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch +#and for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch +SRC_URI += "file://0001-Add-Resin-specific-boot-command.patch \ + file://resin-specific-env-integration-kconfig.patch \ + " + +do_deploy_append() { + install -m 0644 ${WORKDIR}/armbianEnv.txt ${DEPLOYDIR}/armbianEnv.txt +} diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0000-sunxi-allwinner-a10-spi-driver.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0000-sunxi-allwinner-a10-spi-driver.patch new file mode 100644 index 0000000..08e086d --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0000-sunxi-allwinner-a10-spi-driver.patch @@ -0,0 +1,507 @@ +From 7f25d8179776226a8ecfbaad3d3a88e9acd89f28 Mon Sep 17 00:00:00 2001 +From: Stefan Mavrodiev +Date: Tue, 6 Feb 2018 15:14:33 +0200 +Subject: [PATCH] arm: sunxi: Allwinner A10 SPI driver + +Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is +adapted from mailine kernel. + +Signed-off-by: Stefan Mavrodiev +Reviewed-by: Jagan Teki +--- + drivers/spi/Kconfig | 5 + + drivers/spi/Makefile | 1 + + drivers/spi/sun4i_spi.c | 456 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 462 insertions(+) + create mode 100644 drivers/spi/sun4i_spi.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index b85fca56289..dcd719ff0ac 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -174,6 +174,11 @@ config STM32_QSPI + used to access the SPI NOR flash chips on platforms embedding + this ST IP core. + ++config SUN4I_SPI ++ bool "Allwinner A10 SoCs SPI controller" ++ help ++ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs ++ + config TEGRA114_SPI + bool "nVidia Tegra114 SPI driver" + help +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 95b03a29dc0..728e30c5383 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -44,6 +44,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o + obj-$(CONFIG_SH_SPI) += sh_spi.o + obj-$(CONFIG_SH_QSPI) += sh_qspi.o + obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o ++obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o + obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o + obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o + obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c +new file mode 100644 +index 00000000000..b86b5a00adb +--- /dev/null ++++ b/drivers/spi/sun4i_spi.c +@@ -0,0 +1,456 @@ ++/* ++ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V. ++ * S.J.R. van Schaik ++ * M.B.W. Wajer ++ * ++ * (C) Copyright 2017 Olimex Ltd.. ++ * Stefan Mavrodiev ++ * ++ * Based on linux spi driver. Original copyright follows: ++ * linux/drivers/spi/spi-sun4i.c ++ * ++ * Copyright (C) 2012 - 2014 Allwinner Tech ++ * Pan Nan ++ * ++ * Copyright (C) 2014 Maxime Ripard ++ * Maxime Ripard ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#define SUN4I_FIFO_DEPTH 64 ++ ++#define SUN4I_RXDATA_REG 0x00 ++ ++#define SUN4I_TXDATA_REG 0x04 ++ ++#define SUN4I_CTL_REG 0x08 ++#define SUN4I_CTL_ENABLE BIT(0) ++#define SUN4I_CTL_MASTER BIT(1) ++#define SUN4I_CTL_CPHA BIT(2) ++#define SUN4I_CTL_CPOL BIT(3) ++#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) ++#define SUN4I_CTL_LMTF BIT(6) ++#define SUN4I_CTL_TF_RST BIT(8) ++#define SUN4I_CTL_RF_RST BIT(9) ++#define SUN4I_CTL_XCH_MASK 0x0400 ++#define SUN4I_CTL_XCH BIT(10) ++#define SUN4I_CTL_CS_MASK 0x3000 ++#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) ++#define SUN4I_CTL_DHB BIT(15) ++#define SUN4I_CTL_CS_MANUAL BIT(16) ++#define SUN4I_CTL_CS_LEVEL BIT(17) ++#define SUN4I_CTL_TP BIT(18) ++ ++#define SUN4I_INT_CTL_REG 0x0c ++#define SUN4I_INT_CTL_RF_F34 BIT(4) ++#define SUN4I_INT_CTL_TF_E34 BIT(12) ++#define SUN4I_INT_CTL_TC BIT(16) ++ ++#define SUN4I_INT_STA_REG 0x10 ++ ++#define SUN4I_DMA_CTL_REG 0x14 ++ ++#define SUN4I_WAIT_REG 0x18 ++ ++#define SUN4I_CLK_CTL_REG 0x1c ++#define SUN4I_CLK_CTL_CDR2_MASK 0xff ++#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) ++#define SUN4I_CLK_CTL_CDR1_MASK 0xf ++#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) ++#define SUN4I_CLK_CTL_DRS BIT(12) ++ ++#define SUN4I_MAX_XFER_SIZE 0xffffff ++ ++#define SUN4I_BURST_CNT_REG 0x20 ++#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) ++ ++#define SUN4I_XMIT_CNT_REG 0x24 ++#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) ++ ++#define SUN4I_FIFO_STA_REG 0x28 ++#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f ++#define SUN4I_FIFO_STA_RF_CNT_BITS 0 ++#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f ++#define SUN4I_FIFO_STA_TF_CNT_BITS 16 ++ ++#define SUN4I_SPI_MAX_RATE 24000000 ++#define SUN4I_SPI_MIN_RATE 3000 ++#define SUN4I_SPI_DEFAULT_RATE 1000000 ++#define SUN4I_SPI_TIMEOUT_US 1000000 ++ ++/* sun4i spi register set */ ++struct sun4i_spi_regs { ++ u32 rxdata; ++ u32 txdata; ++ u32 ctl; ++ u32 intctl; ++ u32 st; ++ u32 dmactl; ++ u32 wait; ++ u32 cctl; ++ u32 bc; ++ u32 tc; ++ u32 fifo_sta; ++}; ++ ++struct sun4i_spi_platdata { ++ u32 base_addr; ++ u32 max_hz; ++}; ++ ++struct sun4i_spi_priv { ++ struct sun4i_spi_regs *regs; ++ u32 freq; ++ u32 mode; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++}; ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) ++{ ++ u8 byte; ++ ++ while (len--) { ++ byte = readb(&priv->regs->rxdata); ++ *priv->rx_buf++ = byte; ++ } ++} ++ ++static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) ++{ ++ u8 byte; ++ ++ while (len--) { ++ byte = priv->tx_buf ? *priv->tx_buf++ : 0; ++ writeb(byte, &priv->regs->txdata); ++ } ++} ++ ++static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) ++{ ++ struct sun4i_spi_priv *priv = dev_get_priv(bus); ++ u32 reg; ++ ++ reg = readl(&priv->regs->ctl); ++ ++ reg &= ~SUN4I_CTL_CS_MASK; ++ reg |= SUN4I_CTL_CS(cs); ++ ++ if (enable) ++ reg &= ~SUN4I_CTL_CS_LEVEL; ++ else ++ reg |= SUN4I_CTL_CS_LEVEL; ++ ++ writel(reg, &priv->regs->ctl); ++} ++ ++static int sun4i_spi_parse_pins(struct udevice *dev) ++{ ++ const void *fdt = gd->fdt_blob; ++ const char *pin_name; ++ const fdt32_t *list; ++ u32 phandle; ++ int drive, pull = 0, pin, i; ++ int offset; ++ int size; ++ ++ list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); ++ if (!list) { ++ printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n"); ++ return -EINVAL; ++ } ++ ++ while (size) { ++ phandle = fdt32_to_cpu(*list++); ++ size -= sizeof(*list); ++ ++ offset = fdt_node_offset_by_phandle(fdt, phandle); ++ if (offset < 0) ++ return offset; ++ ++ drive = fdt_getprop_u32_default_node(fdt, offset, 0, ++ "drive-strength", 0); ++ if (drive) { ++ if (drive <= 10) ++ drive = 0; ++ else if (drive <= 20) ++ drive = 1; ++ else if (drive <= 30) ++ drive = 2; ++ else ++ drive = 3; ++ } else { ++ drive = fdt_getprop_u32_default_node(fdt, offset, 0, ++ "allwinner,drive", ++ 0); ++ drive = min(drive, 3); ++ } ++ ++ if (fdt_get_property(fdt, offset, "bias-disable", NULL)) ++ pull = 0; ++ else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) ++ pull = 1; ++ else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) ++ pull = 2; ++ else ++ pull = fdt_getprop_u32_default_node(fdt, offset, 0, ++ "allwinner,pull", ++ 0); ++ pull = min(pull, 2); ++ ++ for (i = 0; ; i++) { ++ pin_name = fdt_stringlist_get(fdt, offset, ++ "pins", i, NULL); ++ if (!pin_name) { ++ pin_name = fdt_stringlist_get(fdt, offset, ++ "allwinner,pins", ++ i, NULL); ++ if (!pin_name) ++ break; ++ } ++ ++ pin = name_to_gpio(pin_name); ++ if (pin < 0) ++ break; ++ ++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); ++ sunxi_gpio_set_drv(pin, drive); ++ sunxi_gpio_set_pull(pin, pull); ++ } ++ } ++ return 0; ++} ++ ++static inline void sun4i_spi_enable_clock(void) ++{ ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE; ++ ++ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); ++ writel((1 << 31), &ccm->spi0_clk_cfg); ++} ++ ++static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) ++{ ++ struct sun4i_spi_platdata *plat = dev_get_platdata(bus); ++ int node = dev_of_offset(bus); ++ ++ plat->base_addr = devfdt_get_addr(bus); ++ plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, ++ "spi-max-frequency", ++ SUN4I_SPI_DEFAULT_RATE); ++ ++ if (plat->max_hz > SUN4I_SPI_MAX_RATE) ++ plat->max_hz = SUN4I_SPI_MAX_RATE; ++ ++ return 0; ++} ++ ++static int sun4i_spi_probe(struct udevice *bus) ++{ ++ struct sun4i_spi_platdata *plat = dev_get_platdata(bus); ++ struct sun4i_spi_priv *priv = dev_get_priv(bus); ++ ++ sun4i_spi_enable_clock(); ++ sun4i_spi_parse_pins(bus); ++ ++ priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr; ++ priv->freq = plat->max_hz; ++ ++ return 0; ++} ++ ++static int sun4i_spi_claim_bus(struct udevice *dev) ++{ ++ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); ++ ++ writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP | ++ SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW, ++ &priv->regs->ctl); ++ return 0; ++} ++ ++static int sun4i_spi_release_bus(struct udevice *dev) ++{ ++ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); ++ u32 reg; ++ ++ reg = readl(&priv->regs->ctl); ++ reg &= ~SUN4I_CTL_ENABLE; ++ writel(reg, &priv->regs->ctl); ++ ++ return 0; ++} ++ ++static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, ++ const void *dout, void *din, unsigned long flags) ++{ ++ struct udevice *bus = dev->parent; ++ struct sun4i_spi_priv *priv = dev_get_priv(bus); ++ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); ++ ++ u32 len = bitlen / 8; ++ u32 reg; ++ u8 nbytes; ++ int ret; ++ ++ priv->tx_buf = dout; ++ priv->rx_buf = din; ++ ++ if (bitlen % 8) { ++ debug("%s: non byte-aligned SPI transfer.\n", __func__); ++ return -ENAVAIL; ++ } ++ ++ if (flags & SPI_XFER_BEGIN) ++ sun4i_spi_set_cs(bus, slave_plat->cs, true); ++ ++ reg = readl(&priv->regs->ctl); ++ ++ /* Reset FIFOs */ ++ writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl); ++ ++ while (len) { ++ /* Setup the transfer now... */ ++ nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1)); ++ ++ /* Setup the counters */ ++ writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc); ++ writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc); ++ ++ /* Fill the TX FIFO */ ++ sun4i_spi_fill_fifo(priv, nbytes); ++ ++ /* Start the transfer */ ++ reg = readl(&priv->regs->ctl); ++ writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl); ++ ++ /* Wait transfer to complete */ ++ ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK, ++ false, SUN4I_SPI_TIMEOUT_US, false); ++ if (ret) { ++ printf("ERROR: sun4i_spi: Timeout transferring data\n"); ++ sun4i_spi_set_cs(bus, slave_plat->cs, false); ++ return ret; ++ } ++ ++ /* Drain the RX FIFO */ ++ sun4i_spi_drain_fifo(priv, nbytes); ++ ++ len -= nbytes; ++ } ++ ++ if (flags & SPI_XFER_END) ++ sun4i_spi_set_cs(bus, slave_plat->cs, false); ++ ++ return 0; ++} ++ ++static int sun4i_spi_set_speed(struct udevice *dev, uint speed) ++{ ++ struct sun4i_spi_platdata *plat = dev_get_platdata(dev); ++ struct sun4i_spi_priv *priv = dev_get_priv(dev); ++ unsigned int div; ++ u32 reg; ++ ++ if (speed > plat->max_hz) ++ speed = plat->max_hz; ++ ++ if (speed < SUN4I_SPI_MIN_RATE) ++ speed = SUN4I_SPI_MIN_RATE; ++ /* ++ * Setup clock divider. ++ * ++ * We have two choices there. Either we can use the clock ++ * divide rate 1, which is calculated thanks to this formula: ++ * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) ++ * Or we can use CDR2, which is calculated with the formula: ++ * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) ++ * Whether we use the former or the latter is set through the ++ * DRS bit. ++ * ++ * First try CDR2, and if we can't reach the expected ++ * frequency, fall back to CDR1. ++ */ ++ ++ div = SUN4I_SPI_MAX_RATE / (2 * speed); ++ reg = readl(&priv->regs->cctl); ++ ++ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { ++ if (div > 0) ++ div--; ++ ++ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); ++ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; ++ } else { ++ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); ++ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); ++ reg |= SUN4I_CLK_CTL_CDR1(div); ++ } ++ ++ priv->freq = speed; ++ writel(reg, &priv->regs->cctl); ++ ++ return 0; ++} ++ ++static int sun4i_spi_set_mode(struct udevice *dev, uint mode) ++{ ++ struct sun4i_spi_priv *priv = dev_get_priv(dev); ++ u32 reg; ++ ++ reg = readl(&priv->regs->ctl); ++ reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA); ++ ++ if (mode & SPI_CPOL) ++ reg |= SUN4I_CTL_CPOL; ++ ++ if (mode & SPI_CPHA) ++ reg |= SUN4I_CTL_CPHA; ++ ++ priv->mode = mode; ++ writel(reg, &priv->regs->ctl); ++ ++ return 0; ++} ++ ++static const struct dm_spi_ops sun4i_spi_ops = { ++ .claim_bus = sun4i_spi_claim_bus, ++ .release_bus = sun4i_spi_release_bus, ++ .xfer = sun4i_spi_xfer, ++ .set_speed = sun4i_spi_set_speed, ++ .set_mode = sun4i_spi_set_mode, ++}; ++ ++static const struct udevice_id sun4i_spi_ids[] = { ++ { .compatible = "allwinner,sun4i-a10-spi" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sun4i_spi) = { ++ .name = "sun4i_spi", ++ .id = UCLASS_SPI, ++ .of_match = sun4i_spi_ids, ++ .ops = &sun4i_spi_ops, ++ .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata, ++ .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata), ++ .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv), ++ .probe = sun4i_spi_probe, ++}; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch new file mode 100644 index 0000000..bdd63ef --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch @@ -0,0 +1,42 @@ +From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Fri, 27 Oct 2017 17:25:00 +0800 +Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for + more aliases + +Sometimes some ethernet aliases do not exist in U-Boot FDT but they +exist in the FDT used to boot the system. In this situation +setup_environment is called again in ft_board_setup to generate macaddr +environment variable for them. However now the call to +fdt_fixup_ethernet is moved before the call of ft_board_setup. + +Call fdt_fixup_ethernet again to add MAC addresses for the extra +ethernet aliases. + +Signed-off-by: Icenowy Zheng +--- + board/sunxi/board.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 192cf8ca45..0fe70f47cb 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd) + int __maybe_unused r; + + /* +- * Call setup_environment again in case the boot fdt has +- * ethernet aliases the u-boot copy does not have. ++ * Call setup_environment and fdt_fixup_ethernet again ++ * in case the boot fdt has ethernet aliases the u-boot ++ * copy does not have. + */ + setup_environment(blob); ++ fdt_fixup_ethernet(blob); + + #ifdef CONFIG_VIDEO_DT_SIMPLEFB + r = sunxi_simplefb_setup(blob); +-- +2.13.6 + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/4kfix-limit-screen-to-full-hd.patch.disabled b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/4kfix-limit-screen-to-full-hd.patch.disabled new file mode 100644 index 0000000..4bbb37a --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/4kfix-limit-screen-to-full-hd.patch.disabled @@ -0,0 +1,19 @@ +diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c +index 92c9d06054..cd16d69e30 100644 +--- a/drivers/video/sunxi/sunxi_display.c ++++ b/drivers/video/sunxi/sunxi_display.c +@@ -1274,8 +1274,12 @@ void *video_hw_init(void) + ret = sunxi_hdmi_hpd_detect(hpd_delay); + if (ret) { + printf("HDMI connected: "); +- if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) +- mode = &custom; ++ if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) { ++ if ((custom.xres <= 1920) && (custom.yres <= 1080)) ++ mode = &custom; ++ else ++ mode = &res_mode_init[RES_MODE_1920x1080]; ++ } + } else if (hpd) { + sunxi_hdmi_shutdown(); + sunxi_display.monitor = sunxi_get_default_mon(false); diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/Merrii_Hummingbird_A20.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/Merrii_Hummingbird_A20.patch new file mode 100644 index 0000000..652a58d --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/Merrii_Hummingbird_A20.patch @@ -0,0 +1,29 @@ +diff --git a/configs/Merrii_Hummingbird_A20_defconfig b/configs/Merrii_Hummingbird_A20_defconfig +new file mode 100644 +index 0000000..20a98bb +--- /dev/null ++++ b/configs/Merrii_Hummingbird_A20_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_MACH_SUN7I=y ++CONFIG_DRAM_CLK=432 ++CONFIG_MMC0_CD_PIN="PH1" ++CONFIG_SATAPWR="PB8" ++CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-hummingbird" ++CONFIG_AHCI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_SUN7I_GMAC=y ++CONFIG_SCSI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a20-optional-eMMC.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a20-optional-eMMC.patch new file mode 100644 index 0000000..a1719b6 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a20-optional-eMMC.patch @@ -0,0 +1,18 @@ +diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig +index ef95ac6a5e..7565786648 100644 +--- a/configs/Cubieboard2_defconfig ++++ b/configs/Cubieboard2_defconfig +@@ -19,3 +19,4 @@ CONFIG_SUN7I_GMAC=y + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig +index f9f73fdb23..ecb4f2f24e 100644 +--- a/configs/Cubietruck_defconfig ++++ b/configs/Cubietruck_defconfig +@@ -30,3 +30,4 @@ CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_MUSB_GADGET=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-emmc-support.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-emmc-support.patch new file mode 100644 index 0000000..d2589b5 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-emmc-support.patch @@ -0,0 +1,21 @@ +diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts +index f7a4bcc..9d77afb 100644 +--- a/arch/arm/dts/sun50i-a64-olinuxino.dts ++++ b/arch/arm/dts/sun50i-a64-olinuxino.dts +@@ -155,6 +155,16 @@ + }; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ + &ohci0 { + status = "okay"; + }; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-spl-spi.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-spl-spi.patch new file mode 100644 index 0000000..c6b949c --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-spl-spi.patch @@ -0,0 +1,13 @@ +diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig +index 01fcb86..528fe16 100644 +--- a/configs/a64-olinuxino_defconfig ++++ b/configs/a64-olinuxino_defconfig +@@ -1,6 +1,8 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUNXI=y + CONFIG_MACH_SUN50I=y + CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-orangepiwinplus-emmc-support.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-orangepiwinplus-emmc-support.patch new file mode 100644 index 0000000..d5f6542 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-orangepiwinplus-emmc-support.patch @@ -0,0 +1,51 @@ +diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts +index 2c39d10..819fd97 +--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts ++++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts +@@ -151,6 +151,16 @@ + }; + }; + ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++&i2c1_pins { ++ bias-pull-up; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +@@ -172,6 +182,16 @@ + status = "okay"; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ + &ohci0 { + status = "okay"; + }; +diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig +index ab889ea..6f16cc0 100644 +--- a/configs/orangepi_win_defconfig ++++ b/configs/orangepi_win_defconfig +@@ -5,6 +5,8 @@ CONFIG_MACH_SUN50I=y + CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y + CONFIG_SPL_SPI_SUNXI=y + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_MMC0_CD_PIN="PH13" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-awsom-defconfig.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-awsom-defconfig.patch new file mode 100644 index 0000000..ee708eb --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-awsom-defconfig.patch @@ -0,0 +1,35 @@ +=================================================================== +--- /dev/null ++++ u-boot-2015.01/configs/Awsom_defconfig +@@ -0,0 +1,31 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN7I=y ++CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_ZQ=127 ++CONFIG_DRAM_EMR1=4 ++CONFIG_MMC0_CD_PIN="PB9" ++CONFIG_SATAPWR="PB8" ++CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" ++CONFIG_AHCI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_I2C=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_SUN7I_GMAC=y ++CONFIG_DM_SERIAL=y ++CONFIG_USB=y ++CONFIG_DM_USB=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-beelink-x2.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-beelink-x2.patch new file mode 100644 index 0000000..452a512 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-beelink-x2.patch @@ -0,0 +1,136 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +old mode 100644 +new mode 100644 +index d1bd78c..f268593 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -317,6 +317,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ ++ sun8i-h3-beelink-x2.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts +new file mode 100644 +index 0000000..515a3da +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (C) 2016 Hans de Goede ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* The Orange Pi PC Plus is an extended version of the regular PC */ ++#include "sun8i-h3-orangepi-pc.dts" ++ ++/ { ++ model = "Beelink X2"; ++ compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; ++ ++ aliases { ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &rtl8189ftv; ++ }; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ /* ++ * Explicitly define the sdio device, so that we can add an ethernet ++ * alias for it (which e.g. makes u-boot set a mac-address). ++ */ ++ rtl8189ftv: sdio_wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ allwinner,drive = ; ++ /* eMMC is missing pull-ups */ ++ allwinner,pull = ; ++}; +diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig +new file mode 100644 +index 0000000..098fc05 +--- /dev/null ++++ b/configs/beelink_x2_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++CONFIG_SPL_I2C_SUPPORT=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_SY8106A_POWER=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-emmc_support_to_neo1_and_2.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-emmc_support_to_neo1_and_2.patch new file mode 100644 index 0000000..b907c03 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-emmc_support_to_neo1_and_2.patch @@ -0,0 +1,24 @@ +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +old mode 100644 +new mode 100644 +index fc3465a..a885a85 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -14,3 +14,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file +diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig +old mode 100644 +new mode 100644 +index f87148c..9c8689b +--- a/configs/nanopi_neo_defconfig ++++ b/configs/nanopi_neo_defconfig +@@ -18,3 +18,4 @@ CONFIG_SYS_CLK_FREQ=480000000 + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-air-emmc.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-air-emmc.patch new file mode 100644 index 0000000..9043eeb --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-air-emmc.patch @@ -0,0 +1,37 @@ +diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +index 6246d3e..4f213e1 100644 +--- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts ++++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +@@ -103,6 +103,23 @@ + }; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ drive-strength = <40>; ++ /* eMMC is missing pull-ups */ ++ bias-pull-up; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig +index 11eb3ab13b..9f83068dd7 100644 +--- a/configs/nanopi_neo_air_defconfig ++++ b/configs/nanopi_neo_air_defconfig +@@ -16,3 +16,4 @@ CONFIG_SPL=y + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-duo.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-duo.patch new file mode 100644 index 0000000..2fce488 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-duo.patch @@ -0,0 +1,143 @@ +diff --git a/configs/nanopi_duo_defconfig b/configs/nanopi_duo_defconfig +new file mode 100644 +index 0000000..1e51018 +--- /dev/null ++++ b/configs/nanopi_duo_defconfig +@@ -0,0 +1,21 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-nanopi-duo" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SPL=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 4f8ca34..019ac0b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -312,6 +312,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-sinovoip-bpi-m3.dtb + dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-zero.dtb \ ++ sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ +diff --git a/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts +new file mode 100644 +index 0000000..b6afe20 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts +@@ -0,0 +1,98 @@ ++/* ++ * adapted by , based on ++ * Copyright (C) 2017 Jelle van der Waa ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi DUO Air"; ++ compatible = "friendlyarm,nanopi-duo-air", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "nanopi:blue:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-m1-plus2-emmc.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-m1-plus2-emmc.patch new file mode 100644 index 0000000..d8fd4c8 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-m1-plus2-emmc.patch @@ -0,0 +1,172 @@ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts +new file mode 100644 +index 0000000..fdf2c87 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM Nanopi M1 Plus 2"; ++ compatible = "friendlyarm,nanopi-m1-plus2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &emac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy = <&phy1>; ++ status = "okay"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/configs/nanopi_m1_plus2_defconfig b/configs/nanopi_m1_plus2_defconfig +new file mode 100644 +index 0000000..f710366 +--- /dev/null ++++ b/configs/nanopi_m1_plus2_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=576 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-m1-plus2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index d36447d..49a94d7 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -388,6 +389,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-libretech-all-h3-cc.dtb \ ++ sun50i-h5-nanopi-m1-plus2.dtb \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-neo-core.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-neo-core.patch new file mode 100644 index 0000000..2fba0c3 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-neo-core.patch @@ -0,0 +1,21 @@ +diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts +index 9f33f6f..4a56e6a 100644 +--- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts ++++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts +@@ -58,6 +58,16 @@ + status = "okay"; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ + &ohci0 { + status = "okay"; + }; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-r1-and-duo2.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-r1-and-duo2.patch new file mode 100644 index 0000000..8e58372 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-r1-and-duo2.patch @@ -0,0 +1,279 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index d17045a..9e1be8b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -446,5 +446,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ ++ sun8i-h3-nanopi-r1.dtb \ ++ sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts +new file mode 100644 +index 0000000..9f33f6f +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (C) 2019 Igor Pecovnik ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyARM NanoPi R1"; ++ compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&pio { ++ gmac_power_pin_nanopi: gmac_power_pin@0 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ status = "okay"; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; +diff --git a/configs/nanopi_r1_defconfig b/configs/nanopi_r1_defconfig +new file mode 100644 +index 0000000..dee7d9d +--- /dev/null ++++ b/configs/nanopi_r1_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MACPWR="PD6" ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1" ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig +new file mode 100644 +index 0000000..1e51018 +--- /dev/null ++++ b/configs/nanopi_duo2_defconfig +@@ -0,0 +1,21 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SPL=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +new file mode 100644 +index 0000000..b6afe20 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +@@ -0,0 +1,98 @@ ++/* ++ * adapted by Igor Pecovnik igor@armbian.com ++ * Copyright (C) 2017 Jelle van der Waa ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi DUO 2"; ++ compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "nanopi:blue:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-plus2-emmc.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-plus2-emmc.patch new file mode 100644 index 0000000..9dea5cc --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-plus2-emmc.patch @@ -0,0 +1,9 @@ +diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig +index 7c9cc454c3..2642239c6a 100644 +--- a/configs/orangepi_2_defconfig ++++ b/configs/orangepi_2_defconfig +@@ -20,3 +20,4 @@ CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zero-usb-boot-support.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zero-usb-boot-support.patch new file mode 100644 index 0000000..f995858 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zero-usb-boot-support.patch @@ -0,0 +1,26 @@ +diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +index e0efcb3..0fb2099 100644 +--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -99,6 +99,10 @@ + status = "okay"; + }; + ++&ehci2 { ++ status = "okay"; ++}; ++ + &emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; +@@ -138,6 +142,10 @@ + status = "okay"; + }; + ++&ohci2 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zeroplus2_h3.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zeroplus2_h3.patch new file mode 100644 index 0000000..f5d2985 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zeroplus2_h3.patch @@ -0,0 +1,207 @@ +diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +new file mode 100644 +index 0000000000..b03e3a51a2 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (C) 2016 Icenowy Zheng ++ * ++ * Based on sun8i-h3-orangepi-one.dts, which is: ++ * Copyright (C) 2016 Hans de Goede ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Xunlong Orange Pi Zero Plus 2"; ++ compatible = "xunlong,orangepi-zeroplus", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &brcmf; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "orangepi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ status_led { ++ label = "orangepi:red:status"; ++ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <50>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy = <&phy1>; ++ phy-mode = "mii"; ++ allwinner,use-internal-phy; ++ allwinner,leds-active-low; ++ status = "okay"; ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; ++ +diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig +new file mode 100644 +index 0000000000..9257b7c1ed +--- /dev/null ++++ b/configs/orangepi_zero_plus2_h3_defconfig +@@ -0,0 +1,20 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_USB_EHCI_HCD=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-sunvell-r69.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-sunvell-r69.patch new file mode 100644 index 0000000..5ec6502 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-sunvell-r69.patch @@ -0,0 +1,212 @@ +diff --git a/configs/sunvell_r69_defconfig b/configs/sunvell_r69_defconfig +new file mode 100644 +index 0000000..f4947ab +--- /dev/null ++++ b/configs/sunvell_r69_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO_DE2 is not set ++# CONFIG_VIDEO_COMPOSITE is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-sunvell-r69" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++# CONFIG_CONSOLE_MUX is not set ++CONFIG_SPL=y ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_SPI_SUNXI is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_CLK_FREQ=480000000 ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 7202541..1af2005 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -320,6 +320,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ ++ sun8i-h2-plus-sunvell-r69.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ +diff --git a/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts +new file mode 100644 +index 0000000..4b41116 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts +@@ -0,0 +1,166 @@ ++/* ++ * Based original Sunvell R69 FEX file (2017 ) ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Sunvell R69"; ++ compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus"; ++ ++ aliases { ++ serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &xr819; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "sunvell-r69:blue:pwr"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ status_led { ++ label = "sunvell-r69:red:status"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ reg_vcc_wifi: reg_vcc_wifi { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++ enable-active-high; ++ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy = <&phy1>; ++ phy-mode = "mii"; ++ allwinner,use-internal-phy; ++ allwinner,leds-active-low; ++ status = "okay"; ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc_wifi>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ /* ++ * Explicitly define the sdio device, so that we can add an ethernet ++ * alias for it (which e.g. makes u-boot set a mac-address). ++ */ ++ xr819: sdio_wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase current from 30mA to 40mA for DDR eMMC */ ++ allwinner,drive = ; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-teres.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-teres.patch new file mode 100644 index 0000000..b15de06 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-teres.patch @@ -0,0 +1,186 @@ +From 960ae79950a2b0a8d2e62bb3dfb5727764512a8b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 22 Jan 2018 00:49:10 +0800 +Subject: [PATCH] test + +Signed-off-by: Icenowy Zheng +--- + arch/arm/dts/sun50i-a64-teres-i.dts | 114 ++++++++++++++++++++++++++++++++++++ + configs/teres_i_defconfig | 35 +++++++++++ + 2 files changed, 149 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts + create mode 100644 configs/teres_i_defconfig + +diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts +new file mode 100644 +index 0000000000..1b836c1f49 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-teres-i.dts +@@ -0,0 +1,114 @@ ++/* ++ * Copyright (c) 2018 Icenowy Zheng ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include ++#include "sun50i-a64-pine64.dts" ++ ++/ { ++ model = "TERES I"; ++ compatible = "olimex,teres-i", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ i2c0 = "/i2c_gpio@0"; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 10 20 30 40 50 60 70 100>; ++ default-brightness-level = <3>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ soc { ++ i2c_gpio@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>, /* sda - PL9 */ ++ <&pio 7 0 GPIO_ACTIVE_HIGH>; /* scl - PL8 */ ++ i2c-gpio,sda-open-drain; ++ i2c-gpio,scl-open-drain; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ anx6345: edp-bridge@38 { ++ compatible = "analogix,anx6345"; ++ reg = <0x38>; ++ sleep-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 dummy */ ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ ++ status = "okay"; ++ ++ /* ++ ports { ++ port@0 { ++ bridge_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ ++ port@1 { ++ bridge_in: endpoint { ++ remote-endpoint = <&rgb_out>; ++ }; ++ }; ++ }; ++ */ ++ }; ++ }; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; +diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig +new file mode 100644 +index 0000000000..da33b4131d +--- /dev/null ++++ b/configs/teres_i_defconfig +@@ -0,0 +1,35 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I=y ++CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF_SUPPORT=y ++CONFIG_SPL_ATF_TEXT_BASE=0x44000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_CMD_I2C=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_DM_I2C_GPIO=y ++# CONFIG_SPL_SPI_SUNXI is not set ++CONFIG_DM_REGULATOR=y ++CONFIG_AXP_DLDO2_VOLT=2500 ++CONFIG_AXP_DLDO3_VOLT=1200 ++CONFIG_AXP_SW_ON=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_VIDEO_BRIDGE=y ++CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -406,7 +406,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ +- sun50i-a64-sopine-baseboard.dtb ++ sun50i-a64-sopine-baseboard.dtb \ ++ sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb \ diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-boot-auto-dt-select-neo2.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-boot-auto-dt-select-neo2.patch new file mode 100644 index 0000000..85a98b4 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-boot-auto-dt-select-neo2.patch @@ -0,0 +1,119 @@ +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 818d2a0..a3ee6ed 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -725,6 +725,74 @@ static void setup_environment(const void *fdt) + } + } + ++#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) ++ ++#define NP_NEO2_DT_SS "nanopi-neo2." ++ ++#define NP_NEO2_DT_EXT_V1_1 "-v1.1.dtb" ++ ++#define NP_NEO2_BOARD_ID_GPIO "PL3" ++#define NP_NEO2_BOARD_ID_1_0 1 ++#define NP_NEO2_BOARD_ID_1_1 0 ++ ++void boot_process_multi_dtb(void) ++{ ++ const char *fdtfile = env_get("fdtfile"); ++ if (fdtfile == NULL) { ++ return; ++ } ++ ++ /* check for a NanoPi NEO2 */ ++ if (strstr(fdtfile, NP_NEO2_DT_SS) != NULL) { ++ int board_id_pin, prev_cfg, ret, rev_1_1; ++ ++ /* NEO2 DT found; process board revision and select corresponding DT */ ++ ++ board_id_pin = sunxi_name_to_gpio(NP_NEO2_BOARD_ID_GPIO); ++ if (board_id_pin < 0) { ++ return; ++ } ++ ++ ret = gpio_request(board_id_pin, "board_id_pin"); ++ if (ret) { ++ return; ++ } ++ ++ prev_cfg = sunxi_gpio_get_cfgpin(board_id_pin); ++ ++ gpio_direction_input(board_id_pin); ++ sunxi_gpio_set_pull(board_id_pin, SUNXI_GPIO_PULL_DISABLE); ++ ++ mdelay(2); ++ ++ rev_1_1 = gpio_get_value(board_id_pin) == NP_NEO2_BOARD_ID_1_1; ++ ++ sunxi_gpio_set_cfgpin(board_id_pin, prev_cfg); ++ gpio_free(board_id_pin); ++ ++ printf("NanoPi NEO2 v1.%d detected\n", rev_1_1); ++ ++ if (rev_1_1) { ++ int ddt_len = sizeof(CONFIG_DEFAULT_DEVICE_TREE); ++ int fdt_len = strlen(fdtfile); ++ ++ char *n_fdtfile = (char *)malloc(max(fdt_len, ddt_len) + sizeof(NP_NEO2_DT_EXT_V1_1) + 1); ++ if (n_fdtfile != NULL) { ++ char *cp = strstr(strcpy(n_fdtfile, fdtfile), CONFIG_DEFAULT_DEVICE_TREE); ++ if (cp != NULL) { ++ cp[ddt_len - 1] = '\0'; ++ strcat(cp, NP_NEO2_DT_EXT_V1_1); ++ ++ env_set("fdtfile", n_fdtfile); ++ } ++ ++ free(n_fdtfile); ++ } ++ } ++ } ++} ++#endif ++ + int misc_init_r(void) + { + __maybe_unused int ret; +@@ -758,6 +826,10 @@ int misc_init_r(void) + usb_ether_init(); + #endif + ++#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) ++ boot_process_multi_dtb(); ++#endif ++ + return 0; + } + +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +index 78d587f..ca8a842 100755 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_BOOT_PROCESS_MULTI_DTB=y +diff --git a/dts/Kconfig b/dts/Kconfig +index 0cef225..cd4d101 100644 +--- a/dts/Kconfig ++++ b/dts/Kconfig +@@ -166,6 +166,12 @@ config SPL_OF_LIST + device tree files (without the directory or .dtb suffix) + separated by . + ++if ARCH_SUNXI ++config BOOT_PROCESS_MULTI_DTB ++ bool "Adjust default board DT as necessary at boot" ++ default n ++endif ++ + choice + prompt "SPL OF LIST compression" + depends on SPL_MULTI_DTB_FIT diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopi-k1-plus-emmc.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopi-k1-plus-emmc.patch new file mode 100644 index 0000000..51bae6b --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopi-k1-plus-emmc.patch @@ -0,0 +1,172 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index b6eebe8..a6eb75b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -371,6 +371,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-orangepi-zero-plus.dtb \ + sun50i-h5-nanopi-m1-plus2.dts \ + sun50i-h5-orangepi-pc2.dtb \ ++ sun50i-h5-nanopi-k1-plus.dtb \ + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb + dtb-$(CONFIG_MACH_SUN50I) += \ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts +new file mode 100644 +index 0000000..c08af78 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts +@@ -0,0 +1,125 @@ ++/* ++ * Copyright (C) 2017 Icenowy Zheng ++ * Copyright (C) 2017 Jagan Teki ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi K1 plus"; ++ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ +diff --git a/configs/nanopi_k1_plus_defconfig b/configs/nanopi_k1_plus_defconfig +new file mode 100644 +index 0000000..670c3c7 +--- /dev/null ++++ b/configs/nanopi_k1_plus_defconfig +@@ -0,0 +1,23 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=504 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-k1-plus" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopineocore2.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopineocore2.patch new file mode 100644 index 0000000..f41564a --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopineocore2.patch @@ -0,0 +1,161 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +old mode 100644 +new mode 100755 +index d36447d..7311063 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -388,8 +393,9 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-libretech-all-h3-cc.dtb \ + sun50i-h5-nanopi-m1-plus2.dtb \ + sun50i-h5-nanopi-neo2.dtb \ ++ sun50i-h5-nanopi-neo-core2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ + sun50i-h5-orangepi-pc2.dtb \ + sun50i-h5-nanopi-k1-plus.dtb \ + dtb-$(CONFIG_MACH_SUN50I_H6) += \ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts +new file mode 100644 +index 0000000..dd25549 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts +@@ -0,0 +1,113 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi NEO Core 2"; ++ compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/configs/nanopi_neo_core2_defconfig b/configs/nanopi_neo_core2_defconfig +new file mode 100644 +index 0000000..4624ec3 +--- /dev/null ++++ b/configs/nanopi_neo_core2_defconfig +@@ -0,0 +1,19 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-core2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_SD_BOOT=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-zeropi.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-zeropi.patch new file mode 100644 index 0000000..ed5f8b5 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-zeropi.patch @@ -0,0 +1,147 @@ +diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig +new file mode 100644 +index 0000000..1e51018 +--- /dev/null ++++ b/configs/zeropi_defconfig +@@ -0,0 +1,21 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MACPWR="PD6" ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SPL=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 4f8ca34..019ac0b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -312,6 +312,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-sunvell-r69.dtb \ ++ sun8i-h3-zeropi.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-nanopi-m1.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-zeropi.dts b/arch/arm/dts/sun8i-h3-zeropi.dts +new file mode 100644 +index 0000000000000..4edee84316249 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-zeropi.dts +@@ -0,0 +1,100 @@ ++/* ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyElec ZeroPi"; ++ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac_power_pin_nanopi>; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&pio { ++ gmac_power_pin_nanopi: gmac_power_pin@0 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ status = "okay"; ++ dr_mode = "peripheral"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++}; ++ +\ No newline at end of file diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-default-dram-clockspeeds.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-default-dram-clockspeeds.patch new file mode 100644 index 0000000..2ba790e --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-default-dram-clockspeeds.patch @@ -0,0 +1,272 @@ +diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig +index fe75eef513..74bcfc64af 100644 +--- a/configs/Bananapi_defconfig ++++ b/configs/Bananapi_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_VIDEO_COMPOSITE=y + CONFIG_GMAC_TX_DELAY=3 +diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig +index df65922e83..80a45fde6f 100644 +--- a/configs/Bananapro_defconfig ++++ b/configs/Bananapro_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_USB1_VBUS_PIN="PH0" + CONFIG_USB2_VBUS_PIN="PH1" +diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig +index 02c503f672..cf9c16351d 100644 +--- a/configs/Cubieboard2_defconfig ++++ b/configs/Cubieboard2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_SATAPWR="PB8" + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" +diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig +index a8e9c988d5..9d892d6343 100644 +--- a/configs/Cubieboard_defconfig ++++ b/configs/Cubieboard_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN4I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_SATAPWR="PB8" + CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" +diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig +index f9d56c8f9d..5d42b59e57 100644 +--- a/configs/Cubietruck_defconfig ++++ b/configs/Cubietruck_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_USB0_VBUS_PIN="PH17" + CONFIG_USB0_VBUS_DET="PH22" +diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig +index cc29d606a9..dbbdfcc529 100644 +--- a/configs/Lamobo_R1_defconfig ++++ b/configs/Lamobo_R1_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_MMC0_CD_PIN="PH10" + CONFIG_SATAPWR="PB3" +diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig +index b9f89a013e..6a42c4b500 100644 +--- a/configs/Linksprite_pcDuino3_defconfig ++++ b/configs/Linksprite_pcDuino3_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=122 + CONFIG_SATAPWR="PH2" + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" +diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig +index abe93f6..1fc2e53 100644 +--- a/configs/nanopi_m1_plus_defconfig ++++ b/configs/nanopi_m1_plus_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_CLK=576 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="PH13" +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +index c7db07a..38b6646 100644 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig +index f6b4ca7..34437fc 100644 +--- a/configs/nanopi_neo_plus2_defconfig ++++ b/configs/nanopi_neo_plus2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MACPWR="PD6" + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" +diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig +index b8c1ea4d7c..b4b20372aa 100644 +--- a/configs/Orangepi_defconfig ++++ b/configs/Orangepi_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_USB1_VBUS_PIN="PH26" + CONFIG_USB2_VBUS_PIN="PH22" +diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig +index a72d506..2c49525 100644 +--- a/configs/orangepi_lite_defconfig ++++ b/configs/orangepi_lite_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" +diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig +index 19c35ef103..80404ab377 100644 +--- a/configs/Orangepi_mini_defconfig ++++ b/configs/Orangepi_mini_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_MMC0_CD_PIN="PH10" + CONFIG_MMC3_CD_PIN="PH11" +diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig +index 5a7aba1..3ba4009 100644 +--- a/configs/orangepi_one_defconfig ++++ b/configs/orangepi_one_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" +diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig +index 61b2d98705..e4771dce7d 100644 +--- a/configs/orangepi_pc2_defconfig ++++ b/configs/orangepi_pc2_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MACPWR="PD6" + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" +diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig +index 2374f1d..579bc70 100644 +--- a/configs/orangepi_plus2e_defconfig ++++ b/configs/orangepi_plus2e_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig +index f2ed941..e8219bb 100644 +--- a/configs/orangepi_plus_defconfig ++++ b/configs/orangepi_plus_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig +index 103936d772..990cf2a8c0 100644 +--- a/configs/orangepi_prime_defconfig ++++ b/configs/orangepi_prime_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig +index ac44937..0e761b6 100644 +--- a/configs/orangepi_zero_defconfig ++++ b/configs/orangepi_zero_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + # CONFIG_VIDEO_DE2 is not set +diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig +index 57c63b962a..ec9e5c73b1 100644 +--- a/configs/orangepi_zero_plus2_defconfig ++++ b/configs/orangepi_zero_plus2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MMC0_CD_PIN="PH13" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig +index 48e174a..7d74791 100644 +--- a/configs/a64-olinuxino_defconfig ++++ b/configs/a64-olinuxino_defconfig +@@ -7,5 +7,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881949 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-small-boards-cpufreq.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-small-boards-cpufreq.patch new file mode 100644 index 0000000..dffd0ba --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/adjust-small-boards-cpufreq.patch @@ -0,0 +1,33 @@ +diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig +index ed30708f90..f87148c7e6 100644 +--- a/configs/nanopi_neo_defconfig ++++ b/configs/nanopi_neo_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig +index 11eb3ab13b..d8f3f75192 100644 +--- a/configs/nanopi_neo_air_defconfig ++++ b/configs/nanopi_neo_air_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig +index 5792e7a4a3..46805991d2 100644 +--- a/configs/orangepi_zero_defconfig ++++ b/configs/orangepi_zero_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-autoboot-keyed.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-autoboot-keyed.patch new file mode 100644 index 0000000..70aab22 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-autoboot-keyed.patch @@ -0,0 +1,34 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 53eae8953e..1e931a0eb0 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -843,6 +843,8 @@ config ARCH_SUNXI + select USB_KEYBOARD if DISTRO_DEFAULTS + select USB_STORAGE if DISTRO_DEFAULTS + select USE_TINY_PRINTF ++ imply AUTOBOOT_KEYED ++ imply AUTOBOOT_KEYED_CTRLC + imply CMD_DM + imply CMD_GPT + imply CMD_UBI if NAND +diff --git a/cmd/Kconfig b/cmd/Kconfig +index d6d130edfa..46ed3a9d76 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -51,7 +51,7 @@ config AUTOBOOT_KEYED + config AUTOBOOT_PROMPT + string "Autoboot stop prompt" + depends on AUTOBOOT_KEYED +- default "Autoboot in %d seconds\\n" ++ default "Autoboot in %d seconds, press to stop\\n" + help + This string is displayed before the boot delay selected by + CONFIG_BOOTDELAY starts. If it is not defined there is no +@@ -84,6 +84,7 @@ config AUTOBOOT_DELAY_STR + config AUTOBOOT_STOP_STR + string "Stop autobooting via specific input key / string" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION ++ default " " + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-ethernet-orangepiprime.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-ethernet-orangepiprime.patch new file mode 100644 index 0000000..9bd762c --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-ethernet-orangepiprime.patch @@ -0,0 +1,13 @@ +diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig +index 7e10ebe..8d13489 100644 +--- a/configs/orangepi_prime_defconfig ++++ b/configs/orangepi_prime_defconfig +@@ -10,6 +10,8 @@ CONFIG_NR_DRAM_BANKS=1 + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" ++CONFIG_MACPWR="PD6" ++CONFIG_SPL_SPI_SUNXI=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_MUSB_GADGET=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-r_pio-gpio-access-h3-h5.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-r_pio-gpio-access-h3-h5.patch new file mode 100644 index 0000000..9d492d8 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-r_pio-gpio-access-h3-h5.patch @@ -0,0 +1,24 @@ +diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c +index 7ac8360..0484e7a 100644 +--- a/arch/arm/mach-sunxi/board.c ++++ b/arch/arm/mach-sunxi/board.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + + #include + +@@ -65,6 +66,11 @@ struct mm_region *mem_map = sunxi_mem_map; + + static int gpio_init(void) + { ++#if defined(CONFIG_MACH_SUNXI_H3_H5) ++ /* enable R_PIO GPIO access */ ++ prcm_apb0_enable(PRCM_APB0_GATE_PIO); ++#endif ++ + #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) + #if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fdt-setprop-fix-unaligned-access.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fdt-setprop-fix-unaligned-access.patch new file mode 100644 index 0000000..f164f18 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fdt-setprop-fix-unaligned-access.patch @@ -0,0 +1,24 @@ +diff --git a/cmd/fdt.c b/cmd/fdt.c +index d7654b2c4f..a71b7713a8 100644 +--- a/cmd/fdt.c ++++ b/cmd/fdt.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #define MAX_LEVEL 32 /* how deeply nested we will go */ + #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ +@@ -781,7 +782,10 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) + cp = newp; + tmp = simple_strtoul(cp, &newp, 0); + if (*cp != '?') +- *(fdt32_t *)data = cpu_to_fdt32(tmp); ++ { ++ tmp = cpu_to_fdt32(tmp); ++ put_unaligned(tmp, (fdt32_t *)data); ++ } + else + newp++; + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch new file mode 100644 index 0000000..abf7cae --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch @@ -0,0 +1,12 @@ +diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi +index fc61313..8340dd9 100644 +--- a/arch/arm/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/dts/sunxi-h3-h5.dtsi +@@ -793,6 +793,7 @@ + reg = <0x01f00000 0x54>; + interrupts = , + ; ++ #clock-cells = <1>; + }; + + r_ccu: clock@1f01400 { diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-orangepizero-plus-h3.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-orangepizero-plus-h3.patch new file mode 100644 index 0000000..05020df --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-orangepizero-plus-h3.patch @@ -0,0 +1,29 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 7311063..f8a0784 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -382,6 +382,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-beelink-x2.dtb \ ++ sun8i-h3-orangepi-zeroplus2.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts +similarity index 100% +rename from arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +rename to arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts +diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig +index 98c7e0a..cad0390 100644 +--- a/configs/orangepi_zero_plus2_h3_defconfig ++++ b/configs/orangepi_zero_plus2_h3_defconfig +@@ -5,7 +5,7 @@ CONFIG_MACH_SUN8I_H3=y + CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y +-CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zeroplus2" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL=y diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb-phy-probe.patch.disabled b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb-phy-probe.patch.disabled new file mode 100644 index 0000000..85dda51 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb-phy-probe.patch.disabled @@ -0,0 +1,102 @@ +diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h +index cef6c98..5670d9b 100644 +--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h ++++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h +@@ -10,8 +10,8 @@ + * SPDX-License-Identifier: GPL-2.0+ + */ + +-int sunxi_usb_phy_probe(void); +-int sunxi_usb_phy_remove(void); ++int sunxi_usb_phy_probe(int index); ++int sunxi_usb_phy_remove(int index); + void sunxi_usb_phy_init(int index); + void sunxi_usb_phy_exit(int index); + void sunxi_usb_phy_power_on(int index); +diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c +index 9bf0b56..405cf99 100644 +--- a/arch/arm/mach-sunxi/usb_phy.c ++++ b/arch/arm/mach-sunxi/usb_phy.c +@@ -329,13 +329,13 @@ int sunxi_usb_phy_id_detect(int index) + return gpio_get_value(phy->gpio_id_det); + } + +-int sunxi_usb_phy_probe(void) ++int sunxi_usb_phy_probe(int i) + { + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; +- int i, ret = 0; ++ int ret = 0; + +- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { ++ { + phy = &sunxi_usb_phy[i]; + + phy->gpio_vbus = get_vbus_gpio(i); +@@ -376,15 +376,14 @@ int sunxi_usb_phy_probe(void) + return 0; + } + +-int sunxi_usb_phy_remove(void) ++int sunxi_usb_phy_remove(int i) + { + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; +- int i; + + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + +- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { ++ { + phy = &sunxi_usb_phy[i]; + + if (phy->gpio_vbus >= 0) +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 70e0143..77f282b 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -514,6 +514,11 @@ void sunxi_board_init(void) + { + int power_failed = 0; + ++#ifdef CONFIG_MACH_SUN8I_H3 ++ /* turn on power LED (PL10) on H3 boards */ ++ gpio_direction_output(SUNXI_GPL(10), 1); ++#endif ++ + #ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); + #endif +@@ -731,11 +736,6 @@ int misc_init_r(void) + + setup_environment(gd->fdt_blob); + +-#ifndef CONFIG_MACH_SUN9I +- ret = sunxi_usb_phy_probe(); +- if (ret) +- return ret; +-#endif + sunxi_musb_board_init(); + + return 0; +diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c +index 6ecb7c4..6f1463e 100644 +--- a/drivers/usb/host/ehci-sunxi.c ++++ b/drivers/usb/host/ehci-sunxi.c +@@ -60,6 +60,7 @@ static int ehci_usb_probe(struct udevice *dev) + priv->ahb_gate_mask | extra_ahb_gate_mask); + #endif + ++ sunxi_usb_phy_probe(priv->phy_index); + sunxi_usb_phy_init(priv->phy_index); + sunxi_usb_phy_power_on(priv->phy_index); + +@@ -80,6 +81,7 @@ static int ehci_usb_remove(struct udevice *dev) + return ret; + + sunxi_usb_phy_exit(priv->phy_index); ++ sunxi_usb_phy_remove(priv->phy_index); + + #ifdef CONFIG_SUNXI_GEN_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb1-vbus-opiwin.patch.disabled b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb1-vbus-opiwin.patch.disabled new file mode 100644 index 0000000..18436a5 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb1-vbus-opiwin.patch.disabled @@ -0,0 +1,62 @@ +diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig +old mode 100644 +new mode 100644 +index ab889ea..61c24ba +--- a/configs/orangepi_win_defconfig ++++ b/configs/orangepi_win_defconfig +@@ -10,6 +10,9 @@ CONFIG_NR_DRAM_BANKS=1 + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_USB1_VBUS_PIN="PD7" ++CONFIG_USB_HOST=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts +index cf76c35..a7d36a5 100644 +--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts ++++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts +@@ -64,6 +64,19 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb1_vbus_pin_opiwin>; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; + }; + + &ehci1 { +@@ -83,6 +96,13 @@ + status = "okay"; + }; + ++&pio { ++ usb1_vbus_pin_opiwin: usb1_vbus_pin@0 { ++ allwinner,pins = "PD7"; ++ allwinner,function = "gpio_out"; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +@@ -198,6 +198,7 @@ + }; + + &usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-Fix-PLL1-setup-to-never-use-dividers.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-Fix-PLL1-setup-to-never-use-dividers.patch new file mode 100644 index 0000000..60badbd --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-Fix-PLL1-setup-to-never-use-dividers.patch @@ -0,0 +1,33 @@ +From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 20 Dec 2016 11:25:12 +0100 +Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers + +Kernel would lower the divider on first CLK change and cause the +lock up. +--- + arch/arm/mach-sunxi/clock_sun6i.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index 50fb302a19..91aa2a0478 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk) + int k = 1; + int m = 1; + +- if (clk > 1152000000) { +- k = 2; +- } else if (clk > 768000000) { ++ if (clk >= 1368000000) { + k = 3; +- m = 2; ++ } else if (clk >= 768000000) { ++ k = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ +-- +2.11.0 + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-enable-power-led.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-enable-power-led.patch new file mode 100644 index 0000000..aec4ccc --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-enable-power-led.patch @@ -0,0 +1,17 @@ +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 3cf3614..89cf7f5 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -478,6 +478,11 @@ void sunxi_board_init(void) + int power_failed = 0; + unsigned long ramsize; + ++#ifdef CONFIG_MACH_SUN8I_H3 ++ /* turn on power LED (PL10) on H3 boards */ ++ gpio_direction_output(SUNXI_GPL(10), 1); ++#endif ++ + #ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); + #endif + diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-set-safe-axi_apb-clock-dividers.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-set-safe-axi_apb-clock-dividers.patch new file mode 100644 index 0000000..128bf50 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-set-safe-axi_apb-clock-dividers.patch @@ -0,0 +1,42 @@ +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index 15272c9..cedddc2 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk) + sdelay(200); + + /* Switch CPU to PLL1 */ +- writel(AXI_DIV_3 << AXI_DIV_SHIFT | +- ATB_DIV_2 << ATB_DIV_SHIFT | ++ writel(AXI_DIV_4 << AXI_DIV_SHIFT | ++ ATB_DIV_4 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + } +diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +index f2990db..b3a8575 100644 +--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h ++++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +@@ -180,6 +180,7 @@ struct sunxi_ccm_reg { + #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) + #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) + #define CCM_PLL1_CTRL_EN (0x1 << 31) ++#define CCM_PLL1_CTRL_LOCK (0x1 << 28) + + #define CCM_PLL3_CTRL_M_SHIFT 0 + #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index cedddc2..3fe9305 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk) + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); +- sdelay(200); ++ ++ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK)) ++ ; + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_4 << AXI_DIV_SHIFT | diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/lower-default-DRAM-freq-A64-H5.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/lower-default-DRAM-freq-A64-H5.patch new file mode 100644 index 0000000..932fca6 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/lower-default-DRAM-freq-A64-H5.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig +index 6277abc..84c087e 100644 +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -394,7 +394,7 @@ config DRAM_CLK + default 312 if MACH_SUN6I || MACH_SUN8I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ + MACH_SUN8I_V3S +- default 672 if MACH_SUN50I ++ default 648 if MACH_SUN50I || MACH_SUN50I_H5 + default 744 if MACH_SUN50I_H6 + ---help--- + Set the dram clock speed, valid range 240 - 480 (prior to sun9i), diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/remove-boot-messages-from-hdmi.patch.disabled b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/remove-boot-messages-from-hdmi.patch.disabled new file mode 100644 index 0000000..395654b --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/remove-boot-messages-from-hdmi.patch.disabled @@ -0,0 +1,21 @@ +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -461,13 +461,13 @@ extern int soft_i2c_gpio_scl; + + #ifdef CONFIG_VIDEO + #define CONSOLE_STDOUT_SETTINGS \ +- "stdout=serial,vga\0" \ +- "stderr=serial,vga\0" ++ "stdout=serial\0" \ ++ "stderr=serial\0" + #elif CONFIG_DM_VIDEO + #define CONFIG_SYS_WHITE_ON_BLACK + #define CONSOLE_STDOUT_SETTINGS \ +- "stdout=serial,vidconsole\0" \ +- "stderr=serial,vidconsole\0" ++ "stdout=serial\0" \ ++ "stderr=serial\0" + #else + #define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sun8i-set-machid.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sun8i-set-machid.patch new file mode 100644 index 0000000..24a33af --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sun8i-set-machid.patch @@ -0,0 +1,11 @@ +diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h +index a4c3fb69e..47ce2e9e6 100644 +--- a/include/configs/sun8i.h ++++ b/include/configs/sun8i.h +@@ -30,4 +30,6 @@ + */ + #include + ++#define CONFIG_MACH_TYPE (0x1029) ++ + #endif /* __CONFIG_H */ diff --git a/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sunxi-boot-splash.patch b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sunxi-boot-splash.patch new file mode 100644 index 0000000..85f4144 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sunxi-boot-splash.patch @@ -0,0 +1,65 @@ +diff --git a/cmd/Kconfig b/cmd/Kconfig +index d6d130edfa..92795119ea 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1029,6 +1029,7 @@ menu "Misc commands" + config CMD_BMP + bool "Enable 'bmp' command" + depends on LCD || DM_VIDEO || VIDEO ++ default y + help + This provides a way to obtain information about a BMP-format iamge + and to display it. BMP (which presumably stands for BitMaP) is a +diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h +index 9ed6b9892c..75d5176edf 100644 +--- a/include/config_distro_bootcmd.h ++++ b/include/config_distro_bootcmd.h +@@ -323,6 +323,15 @@ + BOOTENV_SHARED_UBIFS \ + BOOTENV_SHARED_EFI \ + "boot_prefixes=/ /boot/\0" \ ++ "splashpos=m,m\0" \ ++ "splashimage=66000000\0" \ ++ "loadsplash= " \ ++ "for prefix in ${boot_prefixes}; do " \ ++ "if test -e mmc 0 ${prefix}boot.bmp; then " \ ++ "load mmc 0 ${splashimage} ${prefix}boot.bmp; " \ ++ "bmp d ${splashimage}; " \ ++ "fi; " \ ++ "done\0" \ + "boot_scripts=boot.scr.uimg boot.scr\0" \ + "boot_script_dhcp=boot.scr.uimg\0" \ + BOOTENV_BOOT_TARGETS \ +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +index 02d7be0849..cbdea20d08 100644 +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -284,6 +284,16 @@ extern int soft_i2c_gpio_scl; + + #endif /* CONFIG_VIDEO */ + ++#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CONFIG_SPLASH_SCREEN_ALIGN ++#define CONFIG_BMP_16BPP ++#define CONFIG_BMP_24BPP ++#define CONFIG_BMP_32BPP ++#define CONFIG_VIDEO_BMP_RLE8 ++#endif ++ + /* Ethernet support */ + #ifdef CONFIG_SUNXI_EMAC + #define CONFIG_PHY_ADDR 1 +@@ -442,6 +442,11 @@ extern int soft_i2c_gpio_scl; + #define CONSOLE_STDIN_SETTINGS \ + "preboot=usb start\0" \ + "stdin=serial,usbkbd\0" ++#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO ++#define CONSOLE_STDIN_SETTINGS \ ++ "preboot=run loadsplash; usb start\0" \ ++ "stdin=serial,usbkbd\0" ++#endif + #else + #define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0"