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Merge pull request #84 from balena-os/warrior_update

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Warrior update
This commit is contained in:
Florin Sarbu 2019-10-11 10:53:05 +03:00 • committed by GitHub
commit 843bf65ed5
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GPG key ID: 4AEE18F83AFDEB23
432 changed files with 1229514 additions and 50 deletions
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2
bananapi-m1-plus.coffee
View file

@ -22,7 +22,7 @@ module.exports =
machine: 'bananapi-m1-plus'
image: 'resin-image'
fstype: 'resinos-img'
version: 'yocto-sumo'
version: 'yocto-warrior'
deployArtifact: 'resin-image-bananapi-m1-plus.resinos-img'
compressed: true

2
layers/meta-balena-allwinner/conf/layer.conf
View file

@ -7,6 +7,6 @@ BBFILE_COLLECTIONS += "balena-allwinner"
BBFILE_PATTERN_balena-allwinner := "^${LAYERDIR}/"
BBFILE_PRIORITY_balena-allwinner = "1337"
LAYERSERIES_COMPAT_balena-allwinner = "sumo"
LAYERSERIES_COMPAT_balena-allwinner = "warrior"
PREFERRED_VERSION_linux-mainline_nanopi-neo-air = "4.16.13"

1
layers/meta-balena-allwinner/conf/machine/bananapi-m1-plus.conf
View file

@ -8,4 +8,3 @@ include conf/machine/bananapi.conf
KERNEL_DEVICETREE = "sun7i-a20-bananapi-m1-plus.dtb"
UBOOT_MACHINE = "bananapi_m1_plus_config"
PREFERRED_VERSION_linux-mainline = "4.17.3"

3
layers/meta-balena-allwinner/conf/machine/orange-pi-lite.conf
View file

@ -4,9 +4,6 @@
require conf/machine/include/sun8i.inc
PREFERRED_VERSION_linux = "4.14%"
PREFERRED_VERSION_u-boot = "v2017.11%"
KERNEL_DEVICETREE = "sun8i-h3-orangepi-lite.dtb \
overlay/sun8i-h3-analog-codec.dtbo \
overlay/sun8i-h3-cir.dtbo \

1
layers/meta-balena-allwinner/conf/machine/orangepi-plus2.conf
View file

@ -6,4 +6,3 @@ require conf/machine/include/sun8i.inc
KERNEL_DEVICETREE = "sun8i-h3-orangepi-plus.dtb"
UBOOT_MACHINE = "orangepi_plus_defconfig"
PREFERRED_VERSION_linux-mainline = "4.17.3"

4
layers/meta-balena-allwinner/conf/samples/bblayers.conf.sample
View file

@ -13,8 +13,8 @@ BBLAYERS ?= " \
${TOPDIR}/../layers/meta-openembedded/meta-networking \
${TOPDIR}/../layers/meta-openembedded/meta-python \
${TOPDIR}/../layers/meta-sunxi \
${TOPDIR}/../layers/meta-balena/meta-resin-common \
${TOPDIR}/../layers/meta-balena/meta-resin-sumo \
${TOPDIR}/../layers/meta-balena/meta-balena-common \
${TOPDIR}/../layers/meta-balena/meta-balena-warrior \
${TOPDIR}/../layers/meta-balena-allwinner \
${TOPDIR}/../layers/meta-rust \
"

26
layers/meta-balena-allwinner/recipes-bsp/u-boot/files/0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch Normal file
View file

@ -0,0 +1,26 @@
From f4a77da23b3890b53efab6a927cbe99b76ef3b26 Mon Sep 17 00:00:00 2001
From: Florin Sarbu <florin@resin.io>
Date: Wed, 12 Sep 2018 14:22:49 +0200
Subject: [PATCH] nanopi_neo_air_defconfig: Enable eMMC support
Upstream-status: Pending
Signed-off-by: Florin Sarbu <florin@resin.io>
---
configs/nanopi_neo_air_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index ca9c2dd..74ce044 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
--
2.7.4

41
layers/meta-balena-allwinner/recipes-bsp/u-boot/files/resin-specific-env-integration-kconfig.patch Normal file
View file

@ -0,0 +1,41 @@
From be9bb7163c2a29cd8e5ddea24226ea059a6ed224 Mon Sep 17 00:00:00 2001
From: Vicentiu Galanopulo <vicentiu@balena.io>
Date: Fri, 27 Sep 2019 16:20:49 +0200
Subject: [PATCH] From 40731af98d8a1ad6a2c8dfb4ee9641ecb90dfe4c Mon Sep 17
00:00:00 2001 From: Andrei Gherzan <andrei@resin.io> Date: Wed, 1 Mar 2017
23:53:02 +0100 Subject: Integrate machine independent resin environment
configuration
This patch integrates resin default environment configuration in an u-boot which
has a version with Kconfig support.
Signed-off-by: Andrei Gherzan <andrei@resin.io>
Upstream-Status: Inappropriate [configuration]
---
include/env_default.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/env_default.h b/include/env_default.h
index 86b639d3e2..6cb5153406 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -8,6 +8,7 @@
*/
#include <env_callback.h>
+#include <env_resin.h>
#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
env_t environment __UBOOT_ENV_SECTION__(environment) = {
@@ -21,6 +22,7 @@ static char default_environment[] = {
#else
const uchar default_environment[] = {
#endif
+ RESIN_ENV
#ifndef CONFIG_USE_DEFAULT_ENV_FILE
#ifdef CONFIG_ENV_CALLBACK_LIST_DEFAULT
ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
--
2.17.1

1
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2017.11.bb
View file

@ -63,6 +63,7 @@ SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
file://boot.cmd \
file://0001-Increase-size-of-memory-available-to-bootm.patch \
file://0002-Add-Resin-specific-boot-command.patch \
file://0003-libftd_fix.patch \
"
SRCREV = "v2017.11"

35
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2017.11/0003-libftd_fix.patch Normal file
View file

@ -0,0 +1,35 @@
From 6eecc74a9178ddd29375a6c3ee354f2e8b989c45 Mon Sep 17 00:00:00 2001
From: Vicentiu Galanopulo <vicentiu@balena.io>
Date: Thu, 26 Sep 2019 16:19:02 +0200
Subject: [PATCH] Include U-Boot libfdt headers from their actual path
There are no headers for libfdt in lib/libfdt, as they are instead
located in scripts/dtc/libfdt. Specifying lib/libfdt for headers
inclusion in host tools results in using the system libfdt headers,
which is not what we want. Change this to the proper path.
Signed-off-by:Paul Kocialkowski <contact@paulk.fr>
Upstream-Status: Inappropriate [Backport]
Signed-off-by: Vicentiu Galanopulo <vicentiu@balena.io>
---
tools/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/Makefile b/tools/Makefile
index 54bd22406a..39ccbaa881 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -266,7 +266,7 @@ endif # !LOGO_BMP
#
HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
$(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
- -I$(srctree)/lib/libfdt \
+ -I$(srctree)/scripts/dtc/libfdt \
-I$(srctree)/tools \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
--
2.17.1

6
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2018.03.bbappend
View file

@ -1,6 +0,0 @@
UBOOT_KCONFIG_SUPPORT = "1"
inherit resin-u-boot
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://0001-Add-Resin-specific-boot-command.patch"

17
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2018.09.bbappend Normal file
View file

@ -0,0 +1,17 @@
UBOOT_KCONFIG_SUPPORT = "1"
inherit resin-u-boot
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
#remove the resin-specific-env-integration-kconfig.patch patch from meta-resin
#and the 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch patch from
#meta-sunxi because these fail to apply
SRC_URI_remove = "file://0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch \
file://resin-specific-env-integration-kconfig.patch"
#Add updated patches for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch
#and for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch
SRC_URI += "file://0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch \
file://0001-Add-Resin-specific-boot-command.patch \
file://resin-specific-env-integration-kconfig.patch \
"

80
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bb Normal file
View file

@ -0,0 +1,80 @@
DESCRIPTION="Upstream's U-boot configured for sunxi devices"
FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot_2019.04:"
require recipes-bsp/u-boot/u-boot.inc
DEPENDS += " bc-native dtc-native swig-native python3-native flex-native bison-native "
DEPENDS_append_sun50i = " atf-sunxi "
LICENSE = "GPLv2+"
LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e"
COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i|sun8i|sun50i)"
DEFAULT_PREFERENCE_sun4i="1"
DEFAULT_PREFERENCE_sun5i="1"
DEFAULT_PREFERENCE_sun7i="1"
DEFAULT_PREFERENCE_sun8i="1"
DEFAULT_PREFERENCE_sun50i="1"
SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
file://0000-sunxi-allwinner-a10-spi-driver.patch \
file://0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch \
file://Merrii_Hummingbird_A20.patch \
file://add-a20-optional-eMMC.patch \
file://add-a64-olinuxino-emmc-support.patch \
file://add-a64-olinuxino-spl-spi.patch \
file://add-a64-orangepiwinplus-emmc-support.patch \
file://add-awsom-defconfig.patch \
file://add-beelink-x2.patch \
file://add-emmc_support_to_neo1_and_2.patch \
file://add-nanopi-air-emmc.patch \
file://add-nanopi-duo.patch \
file://add-nanopi-m1-plus2-emmc.patch \
file://add-nanopi-neo-core.patch \
file://add-nanopi-r1-and-duo2.patch \
file://add-orangepi-plus2-emmc.patch \
file://add-orangepi-zero-usb-boot-support.patch \
file://add-orangepi-zeroplus2_h3.patch \
file://add-sunvell-r69.patch \
file://add-teres.patch \
file://add-xx-boot-auto-dt-select-neo2.patch \
file://add-xx-nanopi-k1-plus-emmc.patch \
file://add-xx-nanopineocore2.patch \
file://add-zeropi.patch \
file://adjust-default-dram-clockspeeds.patch \
file://adjust-small-boards-cpufreq.patch \
file://enable-autoboot-keyed.patch \
file://enable-ethernet-orangepiprime.patch \
file://enable-r_pio-gpio-access-h3-h5.patch \
file://fdt-setprop-fix-unaligned-access.patch \
file://fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch \
file://fix-orangepizero-plus-h3.patch \
file://h3-Fix-PLL1-setup-to-never-use-dividers.patch \
file://h3-enable-power-led.patch \
file://h3-set-safe-axi_apb-clock-dividers.patch \
file://lower-default-DRAM-freq-A64-H5.patch \
file://sun8i-set-machid.patch \
file://sunxi-boot-splash.patch \
file://armbianEnv.txt \
file://boot.cmd \
"
SRCREV = "3c99166441bf3ea325af2da83cfe65430b49c066"
PV = "v2019.04+git${SRCPV}"
PE = "2"
S = "${WORKDIR}/git"
UBOOT_ENV_SUFFIX = "scr"
UBOOT_ENV = "boot"
EXTRA_OEMAKE += ' HOSTLDSHARED="${BUILD_CC} -shared ${BUILD_LDFLAGS} ${BUILD_CFLAGS}" '
EXTRA_OEMAKE_append_sun50i = " BL31=${DEPLOY_DIR_IMAGE}/bl31.bin "
do_compile_sun50i[depends] += "atf-sunxi:do_deploy"
do_compile_append() {
${B}/tools/mkimage -C none -A arm -T script -d ${WORKDIR}/boot.cmd ${WORKDIR}/${UBOOT_ENV_BINARY}
}

20
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04.bbappend Normal file
View file

@ -0,0 +1,20 @@
UBOOT_KCONFIG_SUPPORT = "1"
inherit resin-u-boot pythonnative
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
#remove the resin-specific-env-integration-kconfig.patch patch from meta-resin
#and the 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch patch from
#meta-sunxi because these fail to apply
SRC_URI_remove = "file://0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch \
file://resin-specific-env-integration-kconfig.patch"
#Add updated patches for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch
#and for 0001-nanopi_neo_air_defconfig-Enable-eMMC-support.patch
SRC_URI += "file://0001-Add-Resin-specific-boot-command.patch \
file://resin-specific-env-integration-kconfig.patch \
"
do_deploy_append() {
install -m 0644 ${WORKDIR}/armbianEnv.txt ${DEPLOYDIR}/armbianEnv.txt
}

507
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0000-sunxi-allwinner-a10-spi-driver.patch Normal file
View file

@ -0,0 +1,507 @@
From 7f25d8179776226a8ecfbaad3d3a88e9acd89f28 Mon Sep 17 00:00:00 2001
From: Stefan Mavrodiev <stefan@olimex.com>
Date: Tue, 6 Feb 2018 15:14:33 +0200
Subject: [PATCH] arm: sunxi: Allwinner A10 SPI driver
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
---
drivers/spi/Kconfig | 5 +
drivers/spi/Makefile | 1 +
drivers/spi/sun4i_spi.c | 456 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 462 insertions(+)
create mode 100644 drivers/spi/sun4i_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b85fca56289..dcd719ff0ac 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -174,6 +174,11 @@ config STM32_QSPI
used to access the SPI NOR flash chips on platforms embedding
this ST IP core.
+config SUN4I_SPI
+ bool "Allwinner A10 SoCs SPI controller"
+ help
+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
+
config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 95b03a29dc0..728e30c5383 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
new file mode 100644
index 00000000000..b86b5a00adb
--- /dev/null
+++ b/drivers/spi/sun4i_spi.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
+ * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
+ *
+ * (C) Copyright 2017 Olimex Ltd..
+ * Stefan Mavrodiev <stefan@olimex.com>
+ *
+ * Based on linux spi driver. Original copyright follows:
+ * linux/drivers/spi/spi-sun4i.c
+ *
+ * Copyright (C) 2012 - 2014 Allwinner Tech
+ * Pan Nan <pannan@allwinnertech.com>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <wait_bit.h>
+
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#include <asm/arch/clock.h>
+
+#define SUN4I_FIFO_DEPTH 64
+
+#define SUN4I_RXDATA_REG 0x00
+
+#define SUN4I_TXDATA_REG 0x04
+
+#define SUN4I_CTL_REG 0x08
+#define SUN4I_CTL_ENABLE BIT(0)
+#define SUN4I_CTL_MASTER BIT(1)
+#define SUN4I_CTL_CPHA BIT(2)
+#define SUN4I_CTL_CPOL BIT(3)
+#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
+#define SUN4I_CTL_LMTF BIT(6)
+#define SUN4I_CTL_TF_RST BIT(8)
+#define SUN4I_CTL_RF_RST BIT(9)
+#define SUN4I_CTL_XCH_MASK 0x0400
+#define SUN4I_CTL_XCH BIT(10)
+#define SUN4I_CTL_CS_MASK 0x3000
+#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
+#define SUN4I_CTL_DHB BIT(15)
+#define SUN4I_CTL_CS_MANUAL BIT(16)
+#define SUN4I_CTL_CS_LEVEL BIT(17)
+#define SUN4I_CTL_TP BIT(18)
+
+#define SUN4I_INT_CTL_REG 0x0c
+#define SUN4I_INT_CTL_RF_F34 BIT(4)
+#define SUN4I_INT_CTL_TF_E34 BIT(12)
+#define SUN4I_INT_CTL_TC BIT(16)
+
+#define SUN4I_INT_STA_REG 0x10
+
+#define SUN4I_DMA_CTL_REG 0x14
+
+#define SUN4I_WAIT_REG 0x18
+
+#define SUN4I_CLK_CTL_REG 0x1c
+#define SUN4I_CLK_CTL_CDR2_MASK 0xff
+#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
+#define SUN4I_CLK_CTL_CDR1_MASK 0xf
+#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
+#define SUN4I_CLK_CTL_DRS BIT(12)
+
+#define SUN4I_MAX_XFER_SIZE 0xffffff
+
+#define SUN4I_BURST_CNT_REG 0x20
+#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_XMIT_CNT_REG 0x24
+#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
+
+#define SUN4I_FIFO_STA_REG 0x28
+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
+
+#define SUN4I_SPI_MAX_RATE 24000000
+#define SUN4I_SPI_MIN_RATE 3000
+#define SUN4I_SPI_DEFAULT_RATE 1000000
+#define SUN4I_SPI_TIMEOUT_US 1000000
+
+/* sun4i spi register set */
+struct sun4i_spi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctl;
+ u32 intctl;
+ u32 st;
+ u32 dmactl;
+ u32 wait;
+ u32 cctl;
+ u32 bc;
+ u32 tc;
+ u32 fifo_sta;
+};
+
+struct sun4i_spi_platdata {
+ u32 base_addr;
+ u32 max_hz;
+};
+
+struct sun4i_spi_priv {
+ struct sun4i_spi_regs *regs;
+ u32 freq;
+ u32 mode;
+
+ const u8 *tx_buf;
+ u8 *rx_buf;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
+{
+ u8 byte;
+
+ while (len--) {
+ byte = readb(&priv->regs->rxdata);
+ *priv->rx_buf++ = byte;
+ }
+}
+
+static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
+{
+ u8 byte;
+
+ while (len--) {
+ byte = priv->tx_buf ? *priv->tx_buf++ : 0;
+ writeb(byte, &priv->regs->txdata);
+ }
+}
+
+static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+
+ reg &= ~SUN4I_CTL_CS_MASK;
+ reg |= SUN4I_CTL_CS(cs);
+
+ if (enable)
+ reg &= ~SUN4I_CTL_CS_LEVEL;
+ else
+ reg |= SUN4I_CTL_CS_LEVEL;
+
+ writel(reg, &priv->regs->ctl);
+}
+
+static int sun4i_spi_parse_pins(struct udevice *dev)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *pin_name;
+ const fdt32_t *list;
+ u32 phandle;
+ int drive, pull = 0, pin, i;
+ int offset;
+ int size;
+
+ list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
+ if (!list) {
+ printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
+ return -EINVAL;
+ }
+
+ while (size) {
+ phandle = fdt32_to_cpu(*list++);
+ size -= sizeof(*list);
+
+ offset = fdt_node_offset_by_phandle(fdt, phandle);
+ if (offset < 0)
+ return offset;
+
+ drive = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "drive-strength", 0);
+ if (drive) {
+ if (drive <= 10)
+ drive = 0;
+ else if (drive <= 20)
+ drive = 1;
+ else if (drive <= 30)
+ drive = 2;
+ else
+ drive = 3;
+ } else {
+ drive = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "allwinner,drive",
+ 0);
+ drive = min(drive, 3);
+ }
+
+ if (fdt_get_property(fdt, offset, "bias-disable", NULL))
+ pull = 0;
+ else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
+ pull = 1;
+ else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
+ pull = 2;
+ else
+ pull = fdt_getprop_u32_default_node(fdt, offset, 0,
+ "allwinner,pull",
+ 0);
+ pull = min(pull, 2);
+
+ for (i = 0; ; i++) {
+ pin_name = fdt_stringlist_get(fdt, offset,
+ "pins", i, NULL);
+ if (!pin_name) {
+ pin_name = fdt_stringlist_get(fdt, offset,
+ "allwinner,pins",
+ i, NULL);
+ if (!pin_name)
+ break;
+ }
+
+ pin = name_to_gpio(pin_name);
+ if (pin < 0)
+ break;
+
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
+ sunxi_gpio_set_drv(pin, drive);
+ sunxi_gpio_set_pull(pin, pull);
+ }
+ }
+ return 0;
+}
+
+static inline void sun4i_spi_enable_clock(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
+ writel((1 << 31), &ccm->spi0_clk_cfg);
+}
+
+static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ int node = dev_of_offset(bus);
+
+ plat->base_addr = devfdt_get_addr(bus);
+ plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
+ "spi-max-frequency",
+ SUN4I_SPI_DEFAULT_RATE);
+
+ if (plat->max_hz > SUN4I_SPI_MAX_RATE)
+ plat->max_hz = SUN4I_SPI_MAX_RATE;
+
+ return 0;
+}
+
+static int sun4i_spi_probe(struct udevice *bus)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+
+ sun4i_spi_enable_clock();
+ sun4i_spi_parse_pins(bus);
+
+ priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
+ priv->freq = plat->max_hz;
+
+ return 0;
+}
+
+static int sun4i_spi_claim_bus(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
+
+ writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
+ SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
+ &priv->regs->ctl);
+ return 0;
+}
+
+static int sun4i_spi_release_bus(struct udevice *dev)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+ reg &= ~SUN4I_CTL_ENABLE;
+ writel(reg, &priv->regs->ctl);
+
+ return 0;
+}
+
+static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+ u32 len = bitlen / 8;
+ u32 reg;
+ u8 nbytes;
+ int ret;
+
+ priv->tx_buf = dout;
+ priv->rx_buf = din;
+
+ if (bitlen % 8) {
+ debug("%s: non byte-aligned SPI transfer.\n", __func__);
+ return -ENAVAIL;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ sun4i_spi_set_cs(bus, slave_plat->cs, true);
+
+ reg = readl(&priv->regs->ctl);
+
+ /* Reset FIFOs */
+ writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
+
+ while (len) {
+ /* Setup the transfer now... */
+ nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
+
+ /* Setup the counters */
+ writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
+ writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
+
+ /* Fill the TX FIFO */
+ sun4i_spi_fill_fifo(priv, nbytes);
+
+ /* Start the transfer */
+ reg = readl(&priv->regs->ctl);
+ writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
+
+ /* Wait transfer to complete */
+ ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
+ false, SUN4I_SPI_TIMEOUT_US, false);
+ if (ret) {
+ printf("ERROR: sun4i_spi: Timeout transferring data\n");
+ sun4i_spi_set_cs(bus, slave_plat->cs, false);
+ return ret;
+ }
+
+ /* Drain the RX FIFO */
+ sun4i_spi_drain_fifo(priv, nbytes);
+
+ len -= nbytes;
+ }
+
+ if (flags & SPI_XFER_END)
+ sun4i_spi_set_cs(bus, slave_plat->cs, false);
+
+ return 0;
+}
+
+static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ unsigned int div;
+ u32 reg;
+
+ if (speed > plat->max_hz)
+ speed = plat->max_hz;
+
+ if (speed < SUN4I_SPI_MIN_RATE)
+ speed = SUN4I_SPI_MIN_RATE;
+ /*
+ * Setup clock divider.
+ *
+ * We have two choices there. Either we can use the clock
+ * divide rate 1, which is calculated thanks to this formula:
+ * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+ * Or we can use CDR2, which is calculated with the formula:
+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+ * Whether we use the former or the latter is set through the
+ * DRS bit.
+ *
+ * First try CDR2, and if we can't reach the expected
+ * frequency, fall back to CDR1.
+ */
+
+ div = SUN4I_SPI_MAX_RATE / (2 * speed);
+ reg = readl(&priv->regs->cctl);
+
+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+ if (div > 0)
+ div--;
+
+ reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+ } else {
+ div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
+ reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+ reg |= SUN4I_CLK_CTL_CDR1(div);
+ }
+
+ priv->freq = speed;
+ writel(reg, &priv->regs->cctl);
+
+ return 0;
+}
+
+static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
+{
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ u32 reg;
+
+ reg = readl(&priv->regs->ctl);
+ reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
+
+ if (mode & SPI_CPOL)
+ reg |= SUN4I_CTL_CPOL;
+
+ if (mode & SPI_CPHA)
+ reg |= SUN4I_CTL_CPHA;
+
+ priv->mode = mode;
+ writel(reg, &priv->regs->ctl);
+
+ return 0;
+}
+
+static const struct dm_spi_ops sun4i_spi_ops = {
+ .claim_bus = sun4i_spi_claim_bus,
+ .release_bus = sun4i_spi_release_bus,
+ .xfer = sun4i_spi_xfer,
+ .set_speed = sun4i_spi_set_speed,
+ .set_mode = sun4i_spi_set_mode,
+};
+
+static const struct udevice_id sun4i_spi_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(sun4i_spi) = {
+ .name = "sun4i_spi",
+ .id = UCLASS_SPI,
+ .of_match = sun4i_spi_ids,
+ .ops = &sun4i_spi_ops,
+ .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
+ .probe = sun4i_spi_probe,
+};

42
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch Normal file
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@ -0,0 +1,42 @@
From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 27 Oct 2017 17:25:00 +0800
Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for
more aliases
Sometimes some ethernet aliases do not exist in U-Boot FDT but they
exist in the FDT used to boot the system. In this situation
setup_environment is called again in ft_board_setup to generate macaddr
environment variable for them. However now the call to
fdt_fixup_ethernet is moved before the call of ft_board_setup.
Call fdt_fixup_ethernet again to add MAC addresses for the extra
ethernet aliases.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
board/sunxi/board.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 192cf8ca45..0fe70f47cb 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd)
int __maybe_unused r;
/*
- * Call setup_environment again in case the boot fdt has
- * ethernet aliases the u-boot copy does not have.
+ * Call setup_environment and fdt_fixup_ethernet again
+ * in case the boot fdt has ethernet aliases the u-boot
+ * copy does not have.
*/
setup_environment(blob);
+ fdt_fixup_ethernet(blob);
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
r = sunxi_simplefb_setup(blob);
--
2.13.6

19
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/4kfix-limit-screen-to-full-hd.patch.disabled Normal file
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@ -0,0 +1,19 @@
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 92c9d06054..cd16d69e30 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -1274,8 +1274,12 @@ void *video_hw_init(void)
ret = sunxi_hdmi_hpd_detect(hpd_delay);
if (ret) {
printf("HDMI connected: ");
- if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
- mode = &custom;
+ if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) {
+ if ((custom.xres <= 1920) && (custom.yres <= 1080))
+ mode = &custom;
+ else
+ mode = &res_mode_init[RES_MODE_1920x1080];
+ }
} else if (hpd) {
sunxi_hdmi_shutdown();
sunxi_display.monitor = sunxi_get_default_mon(false);

29
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/Merrii_Hummingbird_A20.patch Normal file
View file

@ -0,0 +1,29 @@
diff --git a/configs/Merrii_Hummingbird_A20_defconfig b/configs/Merrii_Hummingbird_A20_defconfig
new file mode 100644
index 0000000..20a98bb
--- /dev/null
+++ b/configs/Merrii_Hummingbird_A20_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_SATAPWR="PB8"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-hummingbird"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

18
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a20-optional-eMMC.patch Normal file
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@ -0,0 +1,18 @@
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index ef95ac6a5e..7565786648 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -19,3 +19,4 @@ CONFIG_SUN7I_GMAC=y
CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index f9f73fdb23..ecb4f2f24e 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -30,3 +30,4 @@ CONFIG_SCSI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

21
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-emmc-support.patch Normal file
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@ -0,0 +1,21 @@
diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts
index f7a4bcc..9d77afb 100644
--- a/arch/arm/dts/sun50i-a64-olinuxino.dts
+++ b/arch/arm/dts/sun50i-a64-olinuxino.dts
@@ -155,6 +155,16 @@
};
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};

13
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-olinuxino-spl-spi.patch Normal file
View file

@ -0,0 +1,13 @@
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index 01fcb86..528fe16 100644
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -1,6 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2

51
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-a64-orangepiwinplus-emmc-support.patch Normal file
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@ -0,0 +1,51 @@
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index 2c39d10..819fd97
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -151,6 +151,16 @@
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c1_pins {
+ bias-pull-up;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -172,6 +182,16 @@
status = "okay";
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index ab889ea..6f16cc0 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -5,6 +5,8 @@ CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SPL_SPI_SUNXI=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_MMC0_CD_PIN="PH13"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

35
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-awsom-defconfig.patch Normal file
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@ -0,0 +1,35 @@
===================================================================
--- /dev/null
+++ u-boot-2015.01/configs/Awsom_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PB9"
+CONFIG_SATAPWR="PB8"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_DM_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

136
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-beelink-x2.patch Normal file
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@ -0,0 +1,136 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
old mode 100644
new mode 100644
index d1bd78c..f268593
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -317,6 +317,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
+ sun8i-h3-beelink-x2.dtb \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts
new file mode 100644
index 0000000..515a3da
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* The Orange Pi PC Plus is an extended version of the regular PC */
+#include "sun8i-h3-orangepi-pc.dts"
+
+/ {
+ model = "Beelink X2";
+ compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet1 = &rtl8189ftv;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ rtl8189ftv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ /* eMMC is missing pull-ups */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig
new file mode 100644
index 0000000..098fc05
--- /dev/null
+++ b/configs/beelink_x2_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

24
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-emmc_support_to_neo1_and_2.patch Normal file
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@ -0,0 +1,24 @@
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
old mode 100644
new mode 100644
index fc3465a..a885a85
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
\ No newline at end of file
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
old mode 100644
new mode 100644
index f87148c..9c8689b
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -18,3 +18,4 @@ CONFIG_SYS_CLK_FREQ=480000000
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
\ No newline at end of file

37
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-air-emmc.patch Normal file
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@ -0,0 +1,37 @@
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
index 6246d3e..4f213e1 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
@@ -103,6 +103,23 @@
};
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ drive-strength = <40>;
+ /* eMMC is missing pull-ups */
+ bias-pull-up;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index 11eb3ab13b..9f83068dd7 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -16,3 +16,4 @@ CONFIG_SPL=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

143
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-duo.patch Normal file
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@ -0,0 +1,143 @@
diff --git a/configs/nanopi_duo_defconfig b/configs/nanopi_duo_defconfig
new file mode 100644
index 0000000..1e51018
--- /dev/null
+++ b/configs/nanopi_duo_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-nanopi-duo"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4f8ca34..019ac0b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-sinovoip-bpi-m3.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
+ sun8i-h2-plus-nanopi-duo.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
diff --git a/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts
new file mode 100644
index 0000000..b6afe20
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts
@@ -0,0 +1,98 @@
+/*
+ * adapted by <github.com/karabek>, based on
+ * Copyright (C) 2017 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "FriendlyARM NanoPi DUO Air";
+ compatible = "friendlyarm,nanopi-duo-air", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};

172
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-m1-plus2-emmc.patch Normal file
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@ -0,0 +1,172 @@
diff --git a/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts
new file mode 100644
index 0000000..fdf2c87
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM Nanopi M1 Plus 2";
+ compatible = "friendlyarm,nanopi-m1-plus2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/configs/nanopi_m1_plus2_defconfig b/configs/nanopi_m1_plus2_defconfig
new file mode 100644
index 0000000..f710366
--- /dev/null
+++ b/configs/nanopi_m1_plus2_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=576
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-m1-plus2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d..49a94d7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -388,6 +389,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-libretech-all-h3-cc.dtb \
+ sun50i-h5-nanopi-m1-plus2.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
sun50i-h5-orangepi-zero-plus.dtb \

21
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-neo-core.patch Normal file
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@ -0,0 +1,21 @@
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
index 9f33f6f..4a56e6a 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts
@@ -58,6 +58,16 @@
status = "okay";
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};

279
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-nanopi-r1-and-duo2.patch Normal file
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@ -0,0 +1,279 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d17045a..9e1be8b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -446,5 +446,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-r1.dtb \
+ sun8i-h3-nanopi-duo2.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
new file mode 100644
index 0000000..9f33f6f
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R1";
+ compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&pio {
+ gmac_power_pin_nanopi: gmac_power_pin@0 {
+ pins = "PD6";
+ function = "gpio_out";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
diff --git a/configs/nanopi_r1_defconfig b/configs/nanopi_r1_defconfig
new file mode 100644
index 0000000..dee7d9d
--- /dev/null
+++ b/configs/nanopi_r1_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig
new file mode 100644
index 0000000..1e51018
--- /dev/null
+++ b/configs/nanopi_duo2_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
new file mode 100644
index 0000000..b6afe20
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts
@@ -0,0 +1,98 @@
+/*
+ * adapted by Igor Pecovnik igor@armbian.com
+ * Copyright (C) 2017 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "FriendlyARM NanoPi DUO 2";
+ compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};

9
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-plus2-emmc.patch Normal file
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@ -0,0 +1,9 @@
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 7c9cc454c3..2642239c6a 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -20,3 +20,4 @@ CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

26
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zero-usb-boot-support.patch Normal file
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@ -0,0 +1,26 @@
diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
index e0efcb3..0fb2099 100644
--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -99,6 +99,10 @@
status = "okay";
};
+&ehci2 {
+ status = "okay";
+};
+
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
@@ -138,6 +142,10 @@
status = "okay";
};
+&ohci2 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;

207
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-orangepi-zeroplus2_h3.patch Normal file
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@ -0,0 +1,207 @@
diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
new file mode 100644
index 0000000000..b03e3a51a2
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-orangepi-one.dts, which is:
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero Plus 2";
+ compatible = "xunlong,orangepi-zeroplus", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet1 = &brcmf;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <50>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
+
diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig
new file mode 100644
index 0000000000..9257b7c1ed
--- /dev/null
+++ b/configs/orangepi_zero_plus2_h3_defconfig
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUNXI=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_EHCI_HCD=y

212
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-sunvell-r69.patch Normal file
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@ -0,0 +1,212 @@
diff --git a/configs/sunvell_r69_defconfig b/configs/sunvell_r69_defconfig
new file mode 100644
index 0000000..f4947ab
--- /dev/null
+++ b/configs/sunvell_r69_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO_DE2 is not set
+# CONFIG_VIDEO_COMPOSITE is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-sunvell-r69"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_SPI_SUNXI is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_CLK_FREQ=480000000
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7202541..1af2005 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -320,6 +320,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h2-plus-nanopi-duo.dtb \
+ sun8i-h2-plus-sunvell-r69.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
diff --git a/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts
new file mode 100644
index 0000000..4b41116
--- /dev/null
+++ b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts
@@ -0,0 +1,166 @@
+/*
+ * Based original Sunvell R69 FEX file (2017 <github.com/karabek>)
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Sunvell R69";
+ compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus";
+
+ aliases {
+ serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet1 = &xr819;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "sunvell-r69:blue:pwr";
+ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "sunvell-r69:red:status";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vcc_wifi: reg_vcc_wifi {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ enable-active-high;
+ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ xr819: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase current from 30mA to 40mA for DDR eMMC */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};

186
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-teres.patch Normal file
View file

@ -0,0 +1,186 @@
From 960ae79950a2b0a8d2e62bb3dfb5727764512a8b Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Mon, 22 Jan 2018 00:49:10 +0800
Subject: [PATCH] test
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/dts/sun50i-a64-teres-i.dts | 114 ++++++++++++++++++++++++++++++++++++
configs/teres_i_defconfig | 35 +++++++++++
2 files changed, 149 insertions(+)
create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts
create mode 100644 configs/teres_i_defconfig
diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts
new file mode 100644
index 0000000000..1b836c1f49
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-teres-i.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include "sun50i-a64-pine64.dts"
+
+/ {
+ model = "TERES I";
+ compatible = "olimex,teres-i", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = "/i2c_gpio@0";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 100>;
+ default-brightness-level = <3>;
+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ soc {
+ i2c_gpio@0 {
+ compatible = "i2c-gpio";
+ gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>, /* sda - PL9 */
+ <&pio 7 0 GPIO_ACTIVE_HIGH>; /* scl - PL8 */
+ i2c-gpio,sda-open-drain;
+ i2c-gpio,scl-open-drain;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ anx6345: edp-bridge@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ sleep-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 dummy */
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ status = "okay";
+
+ /*
+ ports {
+ port@0 {
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+
+ port@1 {
+ bridge_in: endpoint {
+ remote-endpoint = <&rgb_out>;
+ };
+ };
+ };
+ */
+ };
+ };
+ };
+};
+
+&pwm {
+ status = "okay";
+};
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
new file mode 100644
index 0000000000..da33b4131d
--- /dev/null
+++ b/configs/teres_i_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF_SUPPORT=y
+CONFIG_SPL_ATF_TEXT_BASE=0x44000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_DM_I2C_GPIO=y
+# CONFIG_SPL_SPI_SUNXI is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_AXP_DLDO2_VOLT=2500
+CONFIG_AXP_DLDO3_VOLT=1200
+CONFIG_AXP_SW_ON=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -406,7 +406,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
- sun50i-a64-sopine-baseboard.dtb
+ sun50i-a64-sopine-baseboard.dtb \
+ sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \

119
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-boot-auto-dt-select-neo2.patch Normal file
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@ -0,0 +1,119 @@
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 818d2a0..a3ee6ed 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -725,6 +725,74 @@ static void setup_environment(const void *fdt)
}
}
+#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD)
+
+#define NP_NEO2_DT_SS "nanopi-neo2."
+
+#define NP_NEO2_DT_EXT_V1_1 "-v1.1.dtb"
+
+#define NP_NEO2_BOARD_ID_GPIO "PL3"
+#define NP_NEO2_BOARD_ID_1_0 1
+#define NP_NEO2_BOARD_ID_1_1 0
+
+void boot_process_multi_dtb(void)
+{
+ const char *fdtfile = env_get("fdtfile");
+ if (fdtfile == NULL) {
+ return;
+ }
+
+ /* check for a NanoPi NEO2 */
+ if (strstr(fdtfile, NP_NEO2_DT_SS) != NULL) {
+ int board_id_pin, prev_cfg, ret, rev_1_1;
+
+ /* NEO2 DT found; process board revision and select corresponding DT */
+
+ board_id_pin = sunxi_name_to_gpio(NP_NEO2_BOARD_ID_GPIO);
+ if (board_id_pin < 0) {
+ return;
+ }
+
+ ret = gpio_request(board_id_pin, "board_id_pin");
+ if (ret) {
+ return;
+ }
+
+ prev_cfg = sunxi_gpio_get_cfgpin(board_id_pin);
+
+ gpio_direction_input(board_id_pin);
+ sunxi_gpio_set_pull(board_id_pin, SUNXI_GPIO_PULL_DISABLE);
+
+ mdelay(2);
+
+ rev_1_1 = gpio_get_value(board_id_pin) == NP_NEO2_BOARD_ID_1_1;
+
+ sunxi_gpio_set_cfgpin(board_id_pin, prev_cfg);
+ gpio_free(board_id_pin);
+
+ printf("NanoPi NEO2 v1.%d detected\n", rev_1_1);
+
+ if (rev_1_1) {
+ int ddt_len = sizeof(CONFIG_DEFAULT_DEVICE_TREE);
+ int fdt_len = strlen(fdtfile);
+
+ char *n_fdtfile = (char *)malloc(max(fdt_len, ddt_len) + sizeof(NP_NEO2_DT_EXT_V1_1) + 1);
+ if (n_fdtfile != NULL) {
+ char *cp = strstr(strcpy(n_fdtfile, fdtfile), CONFIG_DEFAULT_DEVICE_TREE);
+ if (cp != NULL) {
+ cp[ddt_len - 1] = '\0';
+ strcat(cp, NP_NEO2_DT_EXT_V1_1);
+
+ env_set("fdtfile", n_fdtfile);
+ }
+
+ free(n_fdtfile);
+ }
+ }
+ }
+}
+#endif
+
int misc_init_r(void)
{
__maybe_unused int ret;
@@ -758,6 +826,10 @@ int misc_init_r(void)
usb_ether_init();
#endif
+#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD)
+ boot_process_multi_dtb();
+#endif
+
return 0;
}
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
index 78d587f..ca8a842 100755
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-CONFIG_MMC_SUNXI_SLOT_EXTRA=2
\ No newline at end of file
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_BOOT_PROCESS_MULTI_DTB=y
diff --git a/dts/Kconfig b/dts/Kconfig
index 0cef225..cd4d101 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -166,6 +166,12 @@ config SPL_OF_LIST
device tree files (without the directory or .dtb suffix)
separated by <space>.
+if ARCH_SUNXI
+config BOOT_PROCESS_MULTI_DTB
+ bool "Adjust default board DT as necessary at boot"
+ default n
+endif
+
choice
prompt "SPL OF LIST compression"
depends on SPL_MULTI_DTB_FIT

172
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopi-k1-plus-emmc.patch Normal file
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@ -0,0 +1,172 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b6eebe8..a6eb75b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -371,6 +371,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-nanopi-m1-plus2.dts \
sun50i-h5-orangepi-pc2.dtb \
+ sun50i-h5-nanopi-k1-plus.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
diff --git a/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts
new file mode 100644
index 0000000..c08af78
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi K1 plus";
+ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
diff --git a/configs/nanopi_k1_plus_defconfig b/configs/nanopi_k1_plus_defconfig
new file mode 100644
index 0000000..670c3c7
--- /dev/null
+++ b/configs/nanopi_k1_plus_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SYS_TEXT_BASE=0x4a000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=504
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-k1-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

161
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-xx-nanopineocore2.patch Normal file
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@ -0,0 +1,161 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
old mode 100644
new mode 100755
index d36447d..7311063
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -388,8 +393,9 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-libretech-all-h3-cc.dtb \
sun50i-h5-nanopi-m1-plus2.dtb \
sun50i-h5-nanopi-neo2.dtb \
+ sun50i-h5-nanopi-neo-core2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-nanopi-k1-plus.dtb \
dtb-$(CONFIG_MACH_SUN50I_H6) += \
diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts
new file mode 100644
index 0000000..dd25549
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "FriendlyARM NanoPi NEO Core 2";
+ compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc",
+ "allwinner,sun5i-a13-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/configs/nanopi_neo_core2_defconfig b/configs/nanopi_neo_core2_defconfig
new file mode 100644
index 0000000..4624ec3
--- /dev/null
+++ b/configs/nanopi_neo_core2_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-core2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_SD_BOOT=y

147
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/add-zeropi.patch Normal file
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@ -0,0 +1,147 @@
diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
new file mode 100644
index 0000000..1e51018
--- /dev/null
+++ b/configs/zeropi_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4f8ca34..019ac0b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h2-plus-nanopi-duo.dtb \
sun8i-h2-plus-sunvell-r69.dtb \
+ sun8i-h3-zeropi.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-nanopi-m1.dtb \
diff --git a/arch/arm/dts/sun8i-h3-zeropi.dts b/arch/arm/dts/sun8i-h3-zeropi.dts
new file mode 100644
index 0000000000000..4edee84316249
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-zeropi.dts
@@ -0,0 +1,100 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyElec ZeroPi";
+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_nanopi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ gmac_power_pin_nanopi: gmac_power_pin@0 {
+ pins = "PD6";
+ function = "gpio_out";
+ };
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+};
+
\ No newline at end of file

272
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@ -0,0 +1,272 @@
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index fe75eef513..74bcfc64af 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index df65922e83..80a45fde6f 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 02c503f672..cf9c16351d 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index a8e9c988d5..9d892d6343 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index f9d56c8f9d..5d42b59e57 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PH17"
CONFIG_USB0_VBUS_DET="PH22"
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index cc29d606a9..dbbdfcc529 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH23"
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_SATAPWR="PB3"
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index b9f89a013e..6a42c4b500 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=480
+CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_SATAPWR="PH2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index abe93f6..1fc2e53 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=408
+CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PH13"
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
index c7db07a..38b6646 100644
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index f6b4ca7..34437fc 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=408
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index b8c1ea4d7c..b4b20372aa 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index a72d506..2c49525 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 19c35ef103..80404ab377 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
-CONFIG_DRAM_CLK=432
+CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH23"
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_MMC3_CD_PIN="PH11"
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 5a7aba1..3ba4009 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 61b2d98705..e4771dce7d 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 2374f1d..579bc70 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index f2ed941..e8219bb 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index 103936d772..990cf2a8c0 100644
--- a/configs/orangepi_prime_defconfig
+++ b/configs/orangepi_prime_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index ac44937..0e761b6 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
# CONFIG_VIDEO_DE2 is not set
diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig
index 57c63b962a..ec9e5c73b1 100644
--- a/configs/orangepi_zero_plus2_defconfig
+++ b/configs/orangepi_zero_plus2_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index 48e174a..7d74791 100644
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -7,5 +7,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881949
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

33
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@ -0,0 +1,33 @@
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index ed30708f90..f87148c7e6 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CLK_FREQ=480000000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index 11eb3ab13b..d8f3f75192 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CLK_FREQ=480000000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index 5792e7a4a3..46805991d2 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CLK_FREQ=480000000
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

34
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@ -0,0 +1,34 @@
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 53eae8953e..1e931a0eb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -843,6 +843,8 @@ config ARCH_SUNXI
select USB_KEYBOARD if DISTRO_DEFAULTS
select USB_STORAGE if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+ imply AUTOBOOT_KEYED
+ imply AUTOBOOT_KEYED_CTRLC
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if NAND
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d6d130edfa..46ed3a9d76 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -51,7 +51,7 @@ config AUTOBOOT_KEYED
config AUTOBOOT_PROMPT
string "Autoboot stop prompt"
depends on AUTOBOOT_KEYED
- default "Autoboot in %d seconds\\n"
+ default "Autoboot in %d seconds, press <Space> to stop\\n"
help
This string is displayed before the boot delay selected by
CONFIG_BOOTDELAY starts. If it is not defined there is no
@@ -84,6 +84,7 @@ config AUTOBOOT_DELAY_STR
config AUTOBOOT_STOP_STR
string "Stop autobooting via specific input key / string"
depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ default " "
help
This option enables stopping (aborting) of the automatic
boot feature only by issuing a specific input key or

13
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-ethernet-orangepiprime.patch Normal file
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@ -0,0 +1,13 @@
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index 7e10ebe..8d13489 100644
--- a/configs/orangepi_prime_defconfig
+++ b/configs/orangepi_prime_defconfig
@@ -10,6 +10,8 @@ CONFIG_NR_DRAM_BANKS=1
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
+CONFIG_MACPWR="PD6"
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y

24
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/enable-r_pio-gpio-access-h3-h5.patch Normal file
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@ -0,0 +1,24 @@
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 7ac8360..0484e7a 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -23,6 +23,7 @@
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/prcm.h>
#include <linux/compiler.h>
@@ -65,6 +66,11 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
+#if defined(CONFIG_MACH_SUNXI_H3_H5)
+ /* enable R_PIO GPIO access */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO);
+#endif
+
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \

24
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fdt-setprop-fix-unaligned-access.patch Normal file
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@ -0,0 +1,24 @@
diff --git a/cmd/fdt.c b/cmd/fdt.c
index d7654b2c4f..a71b7713a8 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -17,6 +17,7 @@
#include <fdt_support.h>
#include <mapmem.h>
#include <asm/io.h>
+#include <asm/unaligned.h>
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
@@ -781,7 +782,10 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len)
cp = newp;
tmp = simple_strtoul(cp, &newp, 0);
if (*cp != '?')
- *(fdt32_t *)data = cpu_to_fdt32(tmp);
+ {
+ tmp = cpu_to_fdt32(tmp);
+ put_unaligned(tmp, (fdt32_t *)data);
+ }
else
newp++;

12
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-missing-clock-cells-in-rtc-sunxi-h3-h5.patch Normal file
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@ -0,0 +1,12 @@
diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
index fc61313..8340dd9 100644
--- a/arch/arm/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/dts/sunxi-h3-h5.dtsi
@@ -793,6 +793,7 @@
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
};
r_ccu: clock@1f01400 {

29
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-orangepizero-plus-h3.patch Normal file
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@ -0,0 +1,29 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7311063..f8a0784 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -382,6 +382,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
sun8i-h3-beelink-x2.dtb \
+ sun8i-h3-orangepi-zeroplus2.dtb \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts
similarity index 100%
rename from arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts
rename to arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts
diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig
index 98c7e0a..cad0390 100644
--- a/configs/orangepi_zero_plus2_h3_defconfig
+++ b/configs/orangepi_zero_plus2_h3_defconfig
@@ -5,7 +5,7 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zeroplus2"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y

102
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb-phy-probe.patch.disabled Normal file
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@ -0,0 +1,102 @@
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h
index cef6c98..5670d9b 100644
--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h
+++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h
@@ -10,8 +10,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-int sunxi_usb_phy_probe(void);
-int sunxi_usb_phy_remove(void);
+int sunxi_usb_phy_probe(int index);
+int sunxi_usb_phy_remove(int index);
void sunxi_usb_phy_init(int index);
void sunxi_usb_phy_exit(int index);
void sunxi_usb_phy_power_on(int index);
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 9bf0b56..405cf99 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -329,13 +329,13 @@ int sunxi_usb_phy_id_detect(int index)
return gpio_get_value(phy->gpio_id_det);
}
-int sunxi_usb_phy_probe(void)
+int sunxi_usb_phy_probe(int i)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_usb_phy *phy;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ {
phy = &sunxi_usb_phy[i];
phy->gpio_vbus = get_vbus_gpio(i);
@@ -376,15 +376,14 @@ int sunxi_usb_phy_probe(void)
return 0;
}
-int sunxi_usb_phy_remove(void)
+int sunxi_usb_phy_remove(int i)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_usb_phy *phy;
- int i;
clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ {
phy = &sunxi_usb_phy[i];
if (phy->gpio_vbus >= 0)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 70e0143..77f282b 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -514,6 +514,11 @@ void sunxi_board_init(void)
{
int power_failed = 0;
+#ifdef CONFIG_MACH_SUN8I_H3
+ /* turn on power LED (PL10) on H3 boards */
+ gpio_direction_output(SUNXI_GPL(10), 1);
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
@@ -731,11 +736,6 @@ int misc_init_r(void)
setup_environment(gd->fdt_blob);
-#ifndef CONFIG_MACH_SUN9I
- ret = sunxi_usb_phy_probe();
- if (ret)
- return ret;
-#endif
sunxi_musb_board_init();
return 0;
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 6ecb7c4..6f1463e 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -60,6 +60,7 @@ static int ehci_usb_probe(struct udevice *dev)
priv->ahb_gate_mask | extra_ahb_gate_mask);
#endif
+ sunxi_usb_phy_probe(priv->phy_index);
sunxi_usb_phy_init(priv->phy_index);
sunxi_usb_phy_power_on(priv->phy_index);
@@ -80,6 +81,7 @@ static int ehci_usb_remove(struct udevice *dev)
return ret;
sunxi_usb_phy_exit(priv->phy_index);
+ sunxi_usb_phy_remove(priv->phy_index);
#ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask);

62
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/fix-usb1-vbus-opiwin.patch.disabled Normal file
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@ -0,0 +1,62 @@
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
old mode 100644
new mode 100644
index ab889ea..61c24ba
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -10,6 +10,9 @@ CONFIG_NR_DRAM_BANKS=1
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_USB1_VBUS_PIN="PD7"
+CONFIG_USB_HOST=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index cf76c35..a7d36a5 100644
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -64,6 +64,19 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_opiwin>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
};
&ehci1 {
@@ -83,6 +96,13 @@
status = "okay";
};
+&pio {
+ usb1_vbus_pin_opiwin: usb1_vbus_pin@0 {
+ allwinner,pins = "PD7";
+ allwinner,function = "gpio_out";
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -198,6 +198,7 @@
};
&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

33
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-Fix-PLL1-setup-to-never-use-dividers.patch Normal file
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@ -0,0 +1,33 @@
From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 20 Dec 2016 11:25:12 +0100
Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
Kernel would lower the divider on first CLK change and cause the
lock up.
---
arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 50fb302a19..91aa2a0478 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
int k = 1;
int m = 1;
- if (clk > 1152000000) {
- k = 2;
- } else if (clk > 768000000) {
+ if (clk >= 1368000000) {
k = 3;
- m = 2;
+ } else if (clk >= 768000000) {
+ k = 2;
}
/* Switch to 24MHz clock while changing PLL1 */
--
2.11.0

17
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-enable-power-led.patch Normal file
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@ -0,0 +1,17 @@
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3cf3614..89cf7f5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -478,6 +478,11 @@ void sunxi_board_init(void)
int power_failed = 0;
unsigned long ramsize;
+#ifdef CONFIG_MACH_SUN8I_H3
+ /* turn on power LED (PL10) on H3 boards */
+ gpio_direction_output(SUNXI_GPL(10), 1);
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif

42
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/h3-set-safe-axi_apb-clock-dividers.patch Normal file
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@ -0,0 +1,42 @@
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 15272c9..cedddc2 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
+ writel(AXI_DIV_4 << AXI_DIV_SHIFT |
+ ATB_DIV_4 << ATB_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2990db..b3a8575 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -180,6 +180,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL1_CTRL_LOCK (0x1 << 28)
#define CCM_PLL3_CTRL_M_SHIFT 0
#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index cedddc2..3fe9305 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk)
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
- sdelay(200);
+
+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
+ ;
/* Switch CPU to PLL1 */
writel(AXI_DIV_4 << AXI_DIV_SHIFT |

13
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/lower-default-DRAM-freq-A64-H5.patch Normal file
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@ -0,0 +1,13 @@
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6277abc..84c087e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -394,7 +394,7 @@ config DRAM_CLK
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
MACH_SUN8I_V3S
- default 672 if MACH_SUN50I
+ default 648 if MACH_SUN50I || MACH_SUN50I_H5
default 744 if MACH_SUN50I_H6
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),

21
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/remove-boot-messages-from-hdmi.patch.disabled Normal file
View file

@ -0,0 +1,21 @@
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -461,13 +461,13 @@ extern int soft_i2c_gpio_scl;
#ifdef CONFIG_VIDEO
#define CONSOLE_STDOUT_SETTINGS \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0"
+ "stdout=serial\0" \
+ "stderr=serial\0"
#elif CONFIG_DM_VIDEO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONSOLE_STDOUT_SETTINGS \
- "stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0"
+ "stdout=serial\0" \
+ "stderr=serial\0"
#else
#define CONSOLE_STDOUT_SETTINGS \
"stdout=serial\0" \

11
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sun8i-set-machid.patch Normal file
View file

@ -0,0 +1,11 @@
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index a4c3fb69e..47ce2e9e6 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -30,4 +30,6 @@
*/
#include <configs/sunxi-common.h>
+#define CONFIG_MACH_TYPE (0x1029)
+
#endif /* __CONFIG_H */

65
layers/meta-balena-allwinner/recipes-bsp/u-boot/u-boot_2019.04/sunxi-boot-splash.patch Normal file
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@ -0,0 +1,65 @@
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d6d130edfa..92795119ea 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1029,6 +1029,7 @@ menu "Misc commands"
config CMD_BMP
bool "Enable 'bmp' command"
depends on LCD || DM_VIDEO || VIDEO
+ default y
help
This provides a way to obtain information about a BMP-format iamge
and to display it. BMP (which presumably stands for BitMaP) is a
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 9ed6b9892c..75d5176edf 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -323,6 +323,15 @@
BOOTENV_SHARED_UBIFS \
BOOTENV_SHARED_EFI \
"boot_prefixes=/ /boot/\0" \
+ "splashpos=m,m\0" \
+ "splashimage=66000000\0" \
+ "loadsplash= " \
+ "for prefix in ${boot_prefixes}; do " \
+ "if test -e mmc 0 ${prefix}boot.bmp; then " \
+ "load mmc 0 ${splashimage} ${prefix}boot.bmp; " \
+ "bmp d ${splashimage}; " \
+ "fi; " \
+ "done\0" \
"boot_scripts=boot.scr.uimg boot.scr\0" \
"boot_script_dhcp=boot.scr.uimg\0" \
BOOTENV_BOOT_TARGETS \
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 02d7be0849..cbdea20d08 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -284,6 +284,16 @@ extern int soft_i2c_gpio_scl;
#endif /* CONFIG_VIDEO */
+#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif
+
/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_PHY_ADDR 1
@@ -442,6 +442,11 @@ extern int soft_i2c_gpio_scl;
#define CONSOLE_STDIN_SETTINGS \
"preboot=usb start\0" \
"stdin=serial,usbkbd\0"
+#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
+#define CONSOLE_STDIN_SETTINGS \
+ "preboot=run loadsplash; usb start\0" \
+ "stdin=serial,usbkbd\0"
+#endif
#else
#define CONSOLE_STDIN_SETTINGS \
"stdin=serial\0"

54
layers/meta-balena-allwinner/recipes-core/images/resin-image.inc
View file

@ -8,7 +8,7 @@ IMAGE_FSTYPES_append_orangepi-plus2 = " resinos-img"
RESIN_IMAGE_BOOTLOADER_orangepi-plus2 = "u-boot"
RESIN_BOOT_PARTITION_FILES_orangepi-plus2 = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun8i-h3-orangepi-plus.dtb:/dtb/sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus.dtb:/dtb/sun8i-h3-orangepi-plus.dtb \
u-boot-sunxi-with-spl.bin: \
"
IMAGE_CMD_resinos-img_append_orangepi-plus2 () {
@ -26,7 +26,7 @@ IMAGE_FSTYPES_append_orange-pi-one = " resinos-img"
RESIN_IMAGE_BOOTLOADER_orange-pi-one = "u-boot"
RESIN_BOOT_PARTITION_FILES_orange-pi-one = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun8i-h3-orangepi-one.dtb:/dtb/sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-one.dtb:/dtb/sun8i-h3-orangepi-one.dtb \
u-boot-sunxi-with-spl.bin: \
"
IMAGE_CMD_resinos-img_append_orange-pi-one () {
@ -45,7 +45,7 @@ IMAGE_FSTYPES_append_bananapi-m1-plus = " resinos-img"
RESIN_IMAGE_BOOTLOADER_bananapi-m1-plus = "u-boot"
RESIN_BOOT_PARTITION_FILES_bananapi-m1-plus = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun7i-a20-bananapi-m1-plus.dtb:/dtb/sun7i-a20-bananapi-m1-plus.dtb \
sun7i-a20-bananapi-m1-plus.dtb:/dtb/sun7i-a20-bananapi-m1-plus.dtb\
u-boot-sunxi-with-spl.bin: \
"
IMAGE_CMD_resinos-img_append_bananapi-m1-plus () {
@ -63,26 +63,26 @@ IMAGE_FSTYPES_append_orange-pi-lite = " resinos-img"
RESIN_IMAGE_BOOTLOADER_orange-pi-lite = "u-boot"
RESIN_BOOT_PARTITION_FILES_orange-pi-lite = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun8i-h3-orangepi-lite.dtb:/dtb/sun8i-h3-orangepi-lite.dtb \
uImage-sun8i-h3-fixup.scr:/dtb/overlay/sun8i-h3-fixup.scr \
uImage-sun8i-h3-analog-codec.dtbo:/dtb/overlay/sun8i-h3-analog-codec.dtbo \
uImage-sun8i-h3-cir.dtbo:/dtb/overlay/sun8i-h3-cir.dtbo \
uImage-sun8i-h3-i2c0.dtbo:/dtb/overlay/sun8i-h3-i2c0.dtbo \
uImage-sun8i-h3-i2c1.dtbo:/dtb/overlay/sun8i-h3-i2c1.dtbo \
uImage-sun8i-h3-i2c2.dtbo:/dtb/overlay/sun8i-h3-i2c2.dtbo \
uImage-sun8i-h3-pps-gpio.dtbo:/dtb/overlay/sun8i-h3-pps-gpio.dtbo \
uImage-sun8i-h3-pwm.dtbo:/dtb/overlay/sun8i-h3-pwm.dtbo \
uImage-sun8i-h3-spdif-out.dtbo:/dtb/overlay/sun8i-h3-spdif-out.dtbo \
uImage-sun8i-h3-spi-add-cs1.dtbo:/dtb/overlay/sun8i-h3-spi-add-cs1.dtbo \
uImage-sun8i-h3-spi-jedec-nor.dtbo:/dtb/overlay/sun8i-h3-spi-jedec-nor.dtbo \
uImage-sun8i-h3-spi-spidev.dtbo:/dtb/overlay/sun8i-h3-spi-spidev.dtbo \
uImage-sun8i-h3-uart1.dtbo:/dtb/overlay/sun8i-h3-uart1.dtbo \
uImage-sun8i-h3-uart2.dtbo:/dtb/overlay/sun8i-h3-uart2.dtbo \
uImage-sun8i-h3-uart3.dtbo:/dtb/overlay/sun8i-h3-uart3.dtbo \
uImage-sun8i-h3-usbhost0.dtbo:/dtb/overlay/sun8i-h3-usbhost0.dtbo \
uImage-sun8i-h3-usbhost2.dtbo:/dtb/overlay/sun8i-h3-usbhost1.dtbo \
uImage-sun8i-h3-usbhost3.dtbo:/dtb/overlay/sun8i-h3-usbhost2.dtbo \
uImage-sun8i-h3-w1-gpio.dtbo:/dtb/overlay/sun8i-h3-w1-gpio.dtbo \
sun8i-h3-orangepi-lite.dtb:/dtb/sun8i-h3-orangepi-lite.dtb \
sun8i-h3-fixup.scr:/dtb/overlay/sun8i-h3-fixup.scr \
sun8i-h3-analog-codec.dtbo:/dtb/overlay/sun8i-h3-analog-codec.dtbo \
sun8i-h3-cir.dtbo:/dtb/overlay/sun8i-h3-cir.dtbo \
sun8i-h3-i2c0.dtbo:/dtb/overlay/sun8i-h3-i2c0.dtbo \
sun8i-h3-i2c1.dtbo:/dtb/overlay/sun8i-h3-i2c1.dtbo \
sun8i-h3-i2c2.dtbo:/dtb/overlay/sun8i-h3-i2c2.dtbo \
sun8i-h3-pps-gpio.dtbo:/dtb/overlay/sun8i-h3-pps-gpio.dtbo \
sun8i-h3-pwm.dtbo:/dtb/overlay/sun8i-h3-pwm.dtbo \
sun8i-h3-spdif-out.dtbo:/dtb/overlay/sun8i-h3-spdif-out.dtbo \
sun8i-h3-spi-add-cs1.dtbo:/dtb/overlay/sun8i-h3-spi-add-cs1.dtbo \
sun8i-h3-spi-jedec-nor.dtbo:/dtb/overlay/sun8i-h3-spi-jedec-nor.dtbo \
sun8i-h3-spi-spidev.dtbo:/dtb/overlay/sun8i-h3-spi-spidev.dtbo \
sun8i-h3-uart1.dtbo:/dtb/overlay/sun8i-h3-uart1.dtbo \
sun8i-h3-uart2.dtbo:/dtb/overlay/sun8i-h3-uart2.dtbo \
sun8i-h3-uart3.dtbo:/dtb/overlay/sun8i-h3-uart3.dtbo \
sun8i-h3-usbhost0.dtbo:/dtb/overlay/sun8i-h3-usbhost0.dtbo \
sun8i-h3-usbhost2.dtbo:/dtb/overlay/sun8i-h3-usbhost1.dtbo \
sun8i-h3-usbhost3.dtbo:/dtb/overlay/sun8i-h3-usbhost2.dtbo \
sun8i-h3-w1-gpio.dtbo:/dtb/overlay/sun8i-h3-w1-gpio.dtbo \
boot.scr:/boot.scr \
armbianEnv.txt:/ \
"
@ -103,13 +103,13 @@ IMAGE_FSTYPES_append_orange-pi-zero = " resinos-img"
RESIN_IMAGE_BOOTLOADER_orange-pi-zero = "u-boot"
RESIN_BOOT_PARTITION_FILES_orange-pi-zero = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun8i-h2-plus-orangepi-zero.dtb:/dtb/sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h2-plus-orangepi-zero.dtb:/dtb/sun8i-h2-plus-orangepi-zero.dtb \
u-boot-sunxi-with-spl.bin: \
"
IMAGE_CMD_resinos-img_append_orange-pi-zero () {
# Orange Pi Zero needs uboot written at a specific location
dd if=${DEPLOY_DIR_IMAGE}/u-boot-sunxi-with-spl.bin of=${RESIN_RAW_IMG} conv=notrunc seek=8 bs=1024
}
}
#
# nanopi-neo-air
@ -121,9 +121,9 @@ IMAGE_FSTYPES_append_nanopi-neo-air = " resinos-img"
RESIN_IMAGE_BOOTLOADER_nanopi-neo-air = "u-boot"
RESIN_BOOT_PARTITION_FILES_nanopi-neo-air = " \
${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
uImage-sun8i-h3-nanopi-neo-air.dtb:/dtb/sun8i-h3-nanopi-neo-air.dtb \
boot.scr:/boot.scr \
sun8i-h3-nanopi-neo-air.dtb:/dtb/sun8i-h3-nanopi-neo-air.dtb \
u-boot-sunxi-with-spl.bin: \
boot.scr:/boot.scr \
"
IMAGE_CMD_resinos-img_append_nanopi-neo-air () {

55
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0001-clk-sunxi-ng-Set-maximum-M-1-for-H3-pll-cpux-clock.patch Normal file
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@ -0,0 +1,55 @@
From 5b367397da1947fcbf6ed1091c351808218e59bc Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 12 Jan 2017 16:34:57 +0100
Subject: [PATCH 01/82] clk: sunxi-ng: Set maximum M = 1 for H3 pll-cpux clock
When using M factor greater than 1 system is experiencing
occasional lockups.
This change was verified to fix lockups with PLL stress
tester available at https://github.com/megous/h3-firmware.
Note that M factor must not be used outside the kernel
either, so for example u-boot needs a similar patch.
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 77ed0b0ba681..8d47742def49 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -30,15 +30,21 @@
#include "ccu-sun8i-h3.h"
-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
- "osc24M", 0x000,
- 8, 5, /* N */
- 4, 2, /* K */
- 0, 2, /* M */
- 16, 2, /* P */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static struct ccu_nkmp pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT(8, 5),
+ .k = _SUNXI_CCU_MULT(4, 2),
+ .m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
+ .p = _SUNXI_CCU_DIV(16, 2),
+ .common = {
+ .reg = 0x000,
+ .hw.init = CLK_HW_INIT("pll-cpux",
+ "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
--
2.20.1

76
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0002-clk-sunxi-ng-Allow-to-limit-the-use-of-NKMP-clock-s-.patch Normal file
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@ -0,0 +1,76 @@
From 9b15c5248e430f418621414f876170f08ca0a2cd Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 12 Jan 2017 16:37:24 +0100
Subject: [PATCH 02/82] clk: sunxi-ng: Allow to limit the use of NKMP clock's P
factor
Some SoCs mandate the maximum clock rate for which the use
of postdivider P factor is allowed. Allow to configure maximum
clock rate.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 13 ++++++++-----
drivers/clk/sunxi-ng/ccu_nkmp.h | 1 +
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 1ad53d1016a3..080bf4a4ace6 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -33,16 +33,19 @@ static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
}
static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
- struct _ccu_nkmp *nkmp)
+ struct _ccu_nkmp *nkmp, struct ccu_nkmp *_nkmp)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
- unsigned long _n, _k, _m, _p;
+ unsigned long _n, _k, _m, _p, _max_p;
+
+ _max_p = (_nkmp->max_rate_for_p == 0 || rate <= _nkmp->max_rate_for_p) ?
+ nkmp->max_p : nkmp->min_p;
for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) {
- for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
+ for (_p = nkmp->min_p; _p <= _max_p; _p <<= 1) {
unsigned long tmp_rate;
tmp_rate = ccu_nkmp_calc_rate(parent,
@@ -146,7 +149,7 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
- ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
+ ccu_nkmp_find_best(*parent_rate, rate, &_nkmp, nkmp);
rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
_nkmp.m, _nkmp.p);
@@ -177,7 +180,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
- ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
+ ccu_nkmp_find_best(parent_rate, rate, &_nkmp, nkmp);
if (nkmp->n.width)
n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index 6940503e7fc4..bbea3e5ed6fb 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -33,6 +33,7 @@ struct ccu_nkmp {
struct ccu_mult_internal k;
struct ccu_div_internal m;
struct ccu_div_internal p;
+ unsigned long max_rate_for_p;
unsigned int fixed_post_div;
--
2.20.1

29
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0003-clk-sunxi-ng-Limit-pll_cpux-P-factor-for-rates-288MH.patch Normal file
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@ -0,0 +1,29 @@
From d46f1f53618ceffa33a5920802a9247337fd3ff3 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 5 Apr 2017 15:43:48 +0200
Subject: [PATCH 03/82] clk: sunxi-ng: Limit pll_cpux P factor for rates >
288MHz on H3
Datasheet for H3 mandates that CPUX PLL must not use postdivider
(P factor must be 1) for clock rates above 288MHz.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 8d47742def49..7cc9467f373f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -37,6 +37,7 @@ static struct ccu_nkmp pll_cpux_clk = {
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV_MAX(0, 2, 1),
.p = _SUNXI_CCU_DIV(16, 2),
+ .max_rate_for_p = 288000000,
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux",
--
2.20.1

295
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0004-thermal-sun8i_ths-Add-support-for-the-thermal-sensor.patch Normal file
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@ -0,0 +1,295 @@
From e4092ba9553a4680f2b28334f87e2c97a084f95e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 25 Jun 2016 21:51:05 +0200
Subject: [PATCH 04/82] thermal: sun8i_ths: Add support for the thermal sensor
on Allwinner H3
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds support for the sun8i thermal sensor on
Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman <megous@megous.com>
---
drivers/thermal/Kconfig | 7 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/sun8i_ths.c | 239 ++++++++++++++++++++++++++++++++++++
3 files changed, 247 insertions(+)
create mode 100644 drivers/thermal/sun8i_ths.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 0e69edc77d18..5125c5e8f7ce 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -420,6 +420,13 @@ depends on ARCH_BCM || ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
source "drivers/thermal/broadcom/Kconfig"
endmenu
+config SUN8I_THS
+ tristate "Thermal sensor driver for Allwinner H3"
+ depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+ depends on OF
+ help
+ Enable this to support thermal reporting on some newer Allwinner SoCs.
+
menu "Texas Instruments thermal drivers"
depends on ARCH_HAS_BANDGAP || COMPILE_TEST
depends on HAS_IOMEM
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 610344eb3e03..dc8a24fddba9 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -61,3 +61,4 @@ obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o
+obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o
diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
new file mode 100644
index 000000000000..cfe7d1073b8c
--- /dev/null
+++ b/drivers/thermal/sun8i_ths.c
@@ -0,0 +1,239 @@
+/*
+ * Thermal sensor driver for Allwinner H3 SoC
+ *
+ * Copyright (C) 2016 Ondřej Jirman
+ * Based on the work of Josef Gajdusek <atx@atx.name>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+#include <linux/printk.h>
+
+#define THS_H3_CTRL0 0x00
+#define THS_H3_CTRL2 0x40
+#define THS_H3_INT_CTRL 0x44
+#define THS_H3_STAT 0x48
+#define THS_H3_FILTER 0x70
+#define THS_H3_CDATA 0x74
+#define THS_H3_DATA 0x80
+
+#define THS_H3_CTRL0_SENSOR_ACQ0(x) (x)
+#define THS_H3_CTRL2_SENSE_EN BIT(0)
+#define THS_H3_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
+#define THS_H3_INT_CTRL_DATA_IRQ_EN BIT(8)
+#define THS_H3_INT_CTRL_THERMAL_PER(x) ((x) << 12)
+#define THS_H3_STAT_DATA_IRQ_STS BIT(8)
+#define THS_H3_FILTER_TYPE(x) ((x) << 0)
+#define THS_H3_FILTER_EN BIT(2)
+
+#define THS_H3_CLK_IN 40000000 /* Hz */
+#define THS_H3_DATA_PERIOD 330 /* ms */
+
+#define THS_H3_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
+#define THS_H3_FILTER_DIV (1 << (THS_H3_FILTER_TYPE_VALUE + 1))
+#define THS_H3_INT_CTRL_THERMAL_PER_VALUE \
+ (THS_H3_DATA_PERIOD * (THS_H3_CLK_IN / 1000) / THS_H3_FILTER_DIV / 4096 - 1)
+#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
+#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+
+struct sun8i_ths_data {
+ struct reset_control *reset;
+ struct clk *clk;
+ struct clk *busclk;
+ void __iomem *regs;
+ struct thermal_zone_device *tzd;
+ u32 temp;
+};
+
+static int sun8i_ths_get_temp(void *_data, int *out)
+{
+ struct sun8i_ths_data *data = _data;
+
+ if (data->temp == 0)
+ return -EBUSY;
+
+ /* Formula and parameters from the Allwinner 3.4 kernel */
+ *out = 217000 - (int)((data->temp * 1000000) / 8253);
+ return 0;
+}
+
+static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data)
+{
+ struct sun8i_ths_data *data = _data;
+
+ writel(THS_H3_STAT_DATA_IRQ_STS, data->regs + THS_H3_STAT);
+
+ data->temp = readl(data->regs + THS_H3_DATA);
+ if (data->temp)
+ thermal_zone_device_update(data->tzd, THERMAL_EVENT_TEMP_SAMPLE);
+
+ return IRQ_HANDLED;
+}
+
+static void sun8i_ths_h3_init(struct sun8i_ths_data *data)
+{
+ writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE),
+ data->regs + THS_H3_CTRL0);
+ writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE),
+ data->regs + THS_H3_FILTER);
+ writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) |
+ THS_H3_CTRL2_SENSE_EN,
+ data->regs + THS_H3_CTRL2);
+ writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) |
+ THS_H3_INT_CTRL_DATA_IRQ_EN,
+ data->regs + THS_H3_INT_CTRL);
+}
+
+static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
+ .get_temp = sun8i_ths_get_temp,
+};
+
+static int sun8i_ths_probe(struct platform_device *pdev)
+{
+ struct sun8i_ths_data *data;
+ struct resource *res;
+ int ret;
+ int irq;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no memory resources defined\n");
+ return -EINVAL;
+ }
+
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs)) {
+ ret = PTR_ERR(data->regs);
+ dev_err(&pdev->dev, "failed to ioremap THS registers: %d\n", ret);
+ return ret;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
+ return irq;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ sun8i_ths_irq_thread, IRQF_ONESHOT,
+ dev_name(&pdev->dev), data);
+ if (ret)
+ return ret;
+
+ data->busclk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(data->busclk)) {
+ ret = PTR_ERR(data->busclk);
+ dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret);
+ return ret;
+ }
+
+ data->clk = devm_clk_get(&pdev->dev, "ths");
+ if (IS_ERR(data->clk)) {
+ ret = PTR_ERR(data->clk);
+ dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret);
+ return ret;
+ }
+
+ data->reset = devm_reset_control_get(&pdev->dev, "ahb");
+ if (IS_ERR(data->reset)) {
+ ret = PTR_ERR(data->reset);
+ dev_err(&pdev->dev, "failed to get reset: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_deassert(data->reset);
+ if (ret) {
+ dev_err(&pdev->dev, "reset deassert failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(data->busclk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret);
+ goto err_assert_reset;
+ }
+
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret);
+ goto err_disable_bus;
+ }
+
+ ret = clk_set_rate(data->clk, THS_H3_CLK_IN);
+ if (ret)
+ goto err_disable_ths;
+
+ data->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, data,
+ &sun8i_ths_thermal_ops);
+ if (IS_ERR(data->tzd)) {
+ ret = PTR_ERR(data->tzd);
+ dev_err(&pdev->dev, "failed to register thermal zone: %d\n",
+ ret);
+ goto err_disable_ths;
+ }
+
+ sun8i_ths_h3_init(data);
+
+ platform_set_drvdata(pdev, data);
+ return 0;
+
+err_disable_ths:
+ clk_disable_unprepare(data->clk);
+err_disable_bus:
+ clk_disable_unprepare(data->busclk);
+err_assert_reset:
+ reset_control_assert(data->reset);
+ return ret;
+}
+
+static int sun8i_ths_remove(struct platform_device *pdev)
+{
+ struct sun8i_ths_data *data = platform_get_drvdata(pdev);
+
+ reset_control_assert(data->reset);
+ clk_disable_unprepare(data->clk);
+ clk_disable_unprepare(data->busclk);
+ return 0;
+}
+
+static const struct of_device_id sun8i_ths_id_table[] = {
+ { .compatible = "allwinner,sun8i-h3-ths", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sun8i_ths_id_table);
+
+static struct platform_driver sun8i_ths_driver = {
+ .probe = sun8i_ths_probe,
+ .remove = sun8i_ths_remove,
+ .driver = {
+ .name = "sun8i_ths",
+ .of_match_table = sun8i_ths_id_table,
+ },
+};
+
+module_platform_driver(sun8i_ths_driver);
+
+MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
+MODULE_DESCRIPTION("Thermal sensor driver for Allwinner H3 SoC");
+MODULE_LICENSE("GPL v2");
--
2.20.1

498
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0005-thermal-sun8i-Add-support-for-A83T-thermal-sensors.patch Normal file
View file

@ -0,0 +1,498 @@
From 9da4c28e6a7963f67e2ca05098683445a1571538 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 17:15:54 +0100
Subject: [PATCH 05/82] thermal: sun8i: Add support for A83T thermal sensors
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/thermal/sun8i_ths.c | 371 ++++++++++++++++++++++++++----------
1 file changed, 274 insertions(+), 97 deletions(-)
diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
index cfe7d1073b8c..2fda940da4cc 100644
--- a/drivers/thermal/sun8i_ths.c
+++ b/drivers/thermal/sun8i_ths.c
@@ -1,5 +1,5 @@
/*
- * Thermal sensor driver for Allwinner H3 SoC
+ * Thermal sensor driver for Allwinner SUN8I SoC
*
* Copyright (C) 2016 Ondřej Jirman
* Based on the work of Josef Gajdusek <atx@atx.name>
@@ -26,79 +26,174 @@
#include <linux/thermal.h>
#include <linux/printk.h>
-#define THS_H3_CTRL0 0x00
-#define THS_H3_CTRL2 0x40
-#define THS_H3_INT_CTRL 0x44
-#define THS_H3_STAT 0x48
-#define THS_H3_FILTER 0x70
-#define THS_H3_CDATA 0x74
-#define THS_H3_DATA 0x80
-
-#define THS_H3_CTRL0_SENSOR_ACQ0(x) (x)
-#define THS_H3_CTRL2_SENSE_EN BIT(0)
-#define THS_H3_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
-#define THS_H3_INT_CTRL_DATA_IRQ_EN BIT(8)
-#define THS_H3_INT_CTRL_THERMAL_PER(x) ((x) << 12)
-#define THS_H3_STAT_DATA_IRQ_STS BIT(8)
-#define THS_H3_FILTER_TYPE(x) ((x) << 0)
-#define THS_H3_FILTER_EN BIT(2)
-
-#define THS_H3_CLK_IN 40000000 /* Hz */
-#define THS_H3_DATA_PERIOD 330 /* ms */
-
-#define THS_H3_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
-#define THS_H3_FILTER_DIV (1 << (THS_H3_FILTER_TYPE_VALUE + 1))
-#define THS_H3_INT_CTRL_THERMAL_PER_VALUE \
- (THS_H3_DATA_PERIOD * (THS_H3_CLK_IN / 1000) / THS_H3_FILTER_DIV / 4096 - 1)
-#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
-#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+#define THS_SUN8I_CTRL0 0x00
+#define THS_SUN8I_CTRL2 0x40
+#define THS_SUN8I_INT_CTRL 0x44
+#define THS_SUN8I_STAT 0x48
+#define THS_SUN8I_FILTER 0x70
+#define THS_SUN8I_CDATA01 0x74
+#define THS_SUN8I_CDATA2 0x78
+#define THS_SUN8I_DATA0 0x80
+#define THS_SUN8I_DATA1 0x84
+#define THS_SUN8I_DATA2 0x88
+
+#define THS_SUN8I_CTRL0_SENSOR_ACQ0(x) (x)
+#define THS_SUN8I_CTRL2_SENSE_EN0 BIT(0)
+#define THS_SUN8I_CTRL2_SENSE_EN1 BIT(1)
+#define THS_SUN8I_CTRL2_SENSE_EN2 BIT(2)
+#define THS_SUN8I_CTRL2_SENSOR_ACQ1(x) ((x) << 16)
+#define THS_SUN8I_INT_CTRL_DATA0_IRQ_EN BIT(8)
+#define THS_SUN8I_INT_CTRL_DATA1_IRQ_EN BIT(9)
+#define THS_SUN8I_INT_CTRL_DATA2_IRQ_EN BIT(10)
+#define THS_SUN8I_INT_CTRL_THERMAL_PER(x) ((x) << 12)
+#define THS_SUN8I_STAT_DATA0_IRQ_STS BIT(8)
+#define THS_SUN8I_STAT_DATA1_IRQ_STS BIT(9)
+#define THS_SUN8I_STAT_DATA2_IRQ_STS BIT(10)
+#define THS_SUN8I_STAT_CLEAR 0x777
+#define THS_SUN8I_FILTER_TYPE(x) ((x) << 0)
+#define THS_SUN8I_FILTER_EN BIT(2)
+
+#define THS_SUN8I_CLK_IN 40000000 /* Hz */
+#define THS_SUN8I_DATA_PERIOD 330 /* ms */
+#define THS_SUN8I_FILTER_TYPE_VALUE 2 /* average over 2^(n+1) samples */
+
+//XXX: this formula doesn't work for A83T very well
+//XXX: A83T is getting slower readings out of this (1s interval?)
+//perhaps configure this in sun8i_ths_desc
+#define THS_SUN8I_FILTER_DIV (1 << (THS_SUN8I_FILTER_TYPE_VALUE + 1))
+#define THS_SUN8I_INT_CTRL_THERMAL_PER_VALUE \
+ (THS_SUN8I_DATA_PERIOD * (THS_SUN8I_CLK_IN / 1000) / \
+ THS_SUN8I_FILTER_DIV / 4096 - 1)
+
+#define THS_SUN8I_CTRL0_SENSOR_ACQ0_VALUE 0x3f /* 16us */
+#define THS_SUN8I_CTRL2_SENSOR_ACQ1_VALUE 0x3f
+
+#define SUN8I_THS_MAX_TZDS 3
+
+struct sun8i_ths_sensor_desc {
+ u32 data_int_en;
+ u32 data_int_flag;
+ u32 data_offset;
+ u32 sense_en;
+};
+
+struct sun8i_ths_desc {
+ int num_sensors;
+ struct sun8i_ths_sensor_desc *sensors;
+ int (*calc_temp)(u32 reg_val);
+ bool has_cal1;
+};
+
+struct sun8i_ths_tzd {
+ struct sun8i_ths_data *data;
+ struct thermal_zone_device *tzd;
+ u32 temp;
+};
struct sun8i_ths_data {
+ struct device *dev;
struct reset_control *reset;
struct clk *clk;
struct clk *busclk;
void __iomem *regs;
- struct thermal_zone_device *tzd;
- u32 temp;
+ void __iomem *cal_regs;
+ struct sun8i_ths_desc *desc;
+ struct sun8i_ths_tzd tzds[SUN8I_THS_MAX_TZDS];
};
+static int sun8i_ths_calc_temp_h3(u32 reg_val)
+{
+ uint64_t temp = (uint64_t)reg_val * 1000000ll;
+
+ do_div(temp, 8253);
+
+ return 217000 - (int)temp;
+}
+
+static int sun8i_ths_calc_temp_a83t(u32 reg_val)
+{
+ uint64_t temp = (uint64_t)reg_val * 1000000ll;
+
+ do_div(temp, 14186);
+
+ return 192000 - (int)temp;
+}
+
static int sun8i_ths_get_temp(void *_data, int *out)
{
- struct sun8i_ths_data *data = _data;
+ struct sun8i_ths_tzd *tzd = _data;
+ struct sun8i_ths_data *data = tzd->data;
- if (data->temp == 0)
+ if (tzd->temp == 0)
return -EBUSY;
- /* Formula and parameters from the Allwinner 3.4 kernel */
- *out = 217000 - (int)((data->temp * 1000000) / 8253);
+ *out = data->desc->calc_temp(tzd->temp);
return 0;
}
static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data)
{
struct sun8i_ths_data *data = _data;
-
- writel(THS_H3_STAT_DATA_IRQ_STS, data->regs + THS_H3_STAT);
-
- data->temp = readl(data->regs + THS_H3_DATA);
- if (data->temp)
- thermal_zone_device_update(data->tzd, THERMAL_EVENT_TEMP_SAMPLE);
+ struct sun8i_ths_tzd *tzd;
+ struct sun8i_ths_sensor_desc *zdesc;
+ int i;
+ u32 status;
+
+ status = readl(data->regs + THS_SUN8I_STAT);
+ writel(THS_SUN8I_STAT_CLEAR, data->regs + THS_SUN8I_STAT);
+
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ tzd = &data->tzds[i];
+ zdesc = &data->desc->sensors[i];
+
+ if (status & zdesc->data_int_flag) {
+ tzd->temp = readl(data->regs + zdesc->data_offset);
+ if (tzd->temp)
+ thermal_zone_device_update(tzd->tzd,
+ THERMAL_EVENT_TEMP_SAMPLE);
+ }
+ }
return IRQ_HANDLED;
}
-static void sun8i_ths_h3_init(struct sun8i_ths_data *data)
+static void sun8i_ths_init(struct sun8i_ths_data *data)
{
- writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE),
- data->regs + THS_H3_CTRL0);
- writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE),
- data->regs + THS_H3_FILTER);
- writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) |
- THS_H3_CTRL2_SENSE_EN,
- data->regs + THS_H3_CTRL2);
- writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) |
- THS_H3_INT_CTRL_DATA_IRQ_EN,
- data->regs + THS_H3_INT_CTRL);
+ int i;
+ u32 int_ctrl = 0;
+ u32 ctrl2 = 0;
+
+ writel(THS_SUN8I_CTRL0_SENSOR_ACQ0(THS_SUN8I_CTRL0_SENSOR_ACQ0_VALUE),
+ data->regs + THS_SUN8I_CTRL0);
+ writel(THS_SUN8I_FILTER_EN | THS_SUN8I_FILTER_TYPE(THS_SUN8I_FILTER_TYPE_VALUE),
+ data->regs + THS_SUN8I_FILTER);
+
+ ctrl2 |= THS_SUN8I_CTRL2_SENSOR_ACQ1(THS_SUN8I_CTRL2_SENSOR_ACQ1_VALUE);
+ int_ctrl |= THS_SUN8I_INT_CTRL_THERMAL_PER(THS_SUN8I_INT_CTRL_THERMAL_PER_VALUE);
+
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ ctrl2 |= data->desc->sensors[i].sense_en;
+ int_ctrl |= data->desc->sensors[i].data_int_en;
+ }
+
+ if (data->cal_regs) {
+ u32 cal0, cal1;
+
+ cal0 = readl(data->cal_regs);
+ if (cal0)
+ writel(cal0, data->regs + THS_SUN8I_CDATA01);
+
+ if (data->desc->has_cal1) {
+ cal1 = readl(data->cal_regs + 4);
+ if (cal1)
+ writel(cal1, data->regs + THS_SUN8I_CDATA2);
+ }
+ }
+
+ writel(ctrl2, data->regs + THS_SUN8I_CTRL2);
+
+ /* enable interrupts */
+ writel(int_ctrl, data->regs + THS_SUN8I_INT_CTRL);
}
static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
@@ -108,100 +203,135 @@ static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = {
static int sun8i_ths_probe(struct platform_device *pdev)
{
struct sun8i_ths_data *data;
+ struct device *dev = &pdev->dev;
struct resource *res;
- int ret;
- int irq;
+ int ret, irq, i;
- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->desc = (struct sun8i_ths_desc *)of_device_get_match_data(dev);
+ if (data->desc == NULL)
+ return -EINVAL;
+
+ data->dev = dev;
+ platform_set_drvdata(pdev, data);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ths");
if (!res) {
- dev_err(&pdev->dev, "no memory resources defined\n");
+ dev_err(dev, "no memory resources defined\n");
return -EINVAL;
}
- data->regs = devm_ioremap_resource(&pdev->dev, res);
+ data->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(data->regs)) {
ret = PTR_ERR(data->regs);
- dev_err(&pdev->dev, "failed to ioremap THS registers: %d\n", ret);
+ dev_err(dev, "failed to ioremap THS registers: %d\n", ret);
return ret;
}
+ /*XXX: use SRAM device in the future, instead of direct access to regs */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "calibration");
+ if (res) {
+ data->cal_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->cal_regs)) {
+ ret = PTR_ERR(data->cal_regs);
+ dev_err(dev, "failed to ioremap calibration SRAM: %d\n", ret);
+ return ret;
+ }
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
- dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
+ dev_err(dev, "failed to get IRQ: %d\n", irq);
return irq;
}
- ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ ret = devm_request_threaded_irq(dev, irq, NULL,
sun8i_ths_irq_thread, IRQF_ONESHOT,
- dev_name(&pdev->dev), data);
+ dev_name(dev), data);
if (ret)
return ret;
- data->busclk = devm_clk_get(&pdev->dev, "ahb");
+ data->busclk = devm_clk_get(dev, "ahb");
if (IS_ERR(data->busclk)) {
ret = PTR_ERR(data->busclk);
- dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret);
- return ret;
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get ahb clk: %d\n", ret);
+ return ret;
+ }
+
+ data->busclk = NULL;
}
- data->clk = devm_clk_get(&pdev->dev, "ths");
+ data->clk = devm_clk_get(dev, "ths");
if (IS_ERR(data->clk)) {
ret = PTR_ERR(data->clk);
- dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret);
- return ret;
+ if (ret != -ENOENT) {
+ dev_err(dev, "failed to get ths clk: %d\n", ret);
+ return ret;
+ }
+
+ data->clk = NULL;
}
- data->reset = devm_reset_control_get(&pdev->dev, "ahb");
+ data->reset = devm_reset_control_get_optional(dev, "ahb");
if (IS_ERR(data->reset)) {
ret = PTR_ERR(data->reset);
- dev_err(&pdev->dev, "failed to get reset: %d\n", ret);
+ dev_err(dev, "failed to get reset: %d\n", ret);
return ret;
}
ret = reset_control_deassert(data->reset);
if (ret) {
- dev_err(&pdev->dev, "reset deassert failed: %d\n", ret);
+ dev_err(dev, "reset deassert failed: %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(data->busclk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret);
- goto err_assert_reset;
+ if (data->busclk) {
+ ret = clk_prepare_enable(data->busclk);
+ if (ret) {
+ dev_err(dev, "failed to enable bus clk: %d\n", ret);
+ goto err_assert_reset;
+ }
}
- ret = clk_prepare_enable(data->clk);
- if (ret) {
- dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret);
- goto err_disable_bus;
- }
+ if (data->clk) {
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable ths clk: %d\n", ret);
+ goto err_disable_bus;
+ }
- ret = clk_set_rate(data->clk, THS_H3_CLK_IN);
- if (ret)
- goto err_disable_ths;
-
- data->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, data,
- &sun8i_ths_thermal_ops);
- if (IS_ERR(data->tzd)) {
- ret = PTR_ERR(data->tzd);
- dev_err(&pdev->dev, "failed to register thermal zone: %d\n",
- ret);
- goto err_disable_ths;
+ ret = clk_set_rate(data->clk, THS_SUN8I_CLK_IN);
+ if (ret)
+ goto err_disable_ths;
}
- sun8i_ths_h3_init(data);
+ for (i = 0; i < data->desc->num_sensors; i++) {
+ data->tzds[i].data = data;
+ data->tzds[i].tzd =
+ devm_thermal_zone_of_sensor_register(dev, i,
+ &data->tzds[i],
+ &sun8i_ths_thermal_ops);
+ if (IS_ERR(data->tzds[i].tzd)) {
+ ret = PTR_ERR(data->tzds[i].tzd);
+ dev_err(dev,
+ "failed to register thermal zone: %d\n", ret);
+ goto err_disable_ths;
+ }
+ }
- platform_set_drvdata(pdev, data);
+ sun8i_ths_init(data);
return 0;
err_disable_ths:
- clk_disable_unprepare(data->clk);
+ if (data->clk)
+ clk_disable_unprepare(data->clk);
err_disable_bus:
- clk_disable_unprepare(data->busclk);
+ if (data->busclk)
+ clk_disable_unprepare(data->busclk);
err_assert_reset:
reset_control_assert(data->reset);
return ret;
@@ -212,13 +342,60 @@ static int sun8i_ths_remove(struct platform_device *pdev)
struct sun8i_ths_data *data = platform_get_drvdata(pdev);
reset_control_assert(data->reset);
- clk_disable_unprepare(data->clk);
- clk_disable_unprepare(data->busclk);
+ if (data->clk)
+ clk_disable_unprepare(data->clk);
+ if (data->busclk)
+ clk_disable_unprepare(data->busclk);
return 0;
}
+struct sun8i_ths_sensor_desc sun8i_ths_h3_sensors[] = {
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA0_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA0_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA0,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN0,
+ },
+};
+
+struct sun8i_ths_sensor_desc sun8i_ths_a83t_sensors[] = {
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA0_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA0_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA0,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN0,
+ },
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA1_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA1_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA1,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN1,
+ },
+ {
+ .data_int_en = THS_SUN8I_INT_CTRL_DATA2_IRQ_EN,
+ .data_int_flag = THS_SUN8I_STAT_DATA2_IRQ_STS,
+ .data_offset = THS_SUN8I_DATA2,
+ .sense_en = THS_SUN8I_CTRL2_SENSE_EN2,
+ },
+};
+
+static const struct sun8i_ths_desc sun8i_ths_h3_desc = {
+ .num_sensors = ARRAY_SIZE(sun8i_ths_h3_sensors),
+ .sensors = sun8i_ths_h3_sensors,
+ .calc_temp = sun8i_ths_calc_temp_h3,
+ .has_cal1 = false,
+};
+
+static const struct sun8i_ths_desc sun8i_ths_a83t_desc = {
+ .num_sensors = ARRAY_SIZE(sun8i_ths_a83t_sensors),
+ .sensors = sun8i_ths_a83t_sensors,
+ .calc_temp = sun8i_ths_calc_temp_a83t,
+ .has_cal1 = true,
+};
+
static const struct of_device_id sun8i_ths_id_table[] = {
- { .compatible = "allwinner,sun8i-h3-ths", },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_ths_h3_desc },
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_ths_a83t_desc },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun8i_ths_id_table);
@@ -235,5 +412,5 @@ static struct platform_driver sun8i_ths_driver = {
module_platform_driver(sun8i_ths_driver);
MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
-MODULE_DESCRIPTION("Thermal sensor driver for Allwinner H3 SoC");
+MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SUN8I SoCs");
MODULE_LICENSE("GPL v2");
--
2.20.1

52
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0006-dt-bindings-document-sun8i_ths-H3-thermal-sensor-dri.patch Normal file
View file

@ -0,0 +1,52 @@
From 4e3d17aa91541ce9ad705432e6ef353efabeb06e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 25 Jun 2016 00:02:04 +0200
Subject: [PATCH 06/82] dt-bindings: document sun8i_ths - H3 thermal sensor
driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds the binding documentation for the
sun8i_ths driver. This is a driver for thermal sensor
found in Allwinner H3 SoC.
Signed-off-by: Ondřej Jirman <megous@megous.com>
---
.../devicetree/bindings/thermal/sun8i-ths.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
new file mode 100644
index 000000000000..ba1288165e90
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
@@ -0,0 +1,24 @@
+* Thermal sensor driver for Allwinner H3 SoC
+
+Required properties:
+- compatible : "allwinner,sun8i-h3-ths"
+- reg : Address range of the thermal sensor registers
+- resets : Must contain phandles to reset controls matching the entries
+ of the names
+- reset-names : Must include the name "ahb"
+- clocks : Must contain phandles to clock controls matching the entries
+ of the names
+- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
+ clock
+
+Example:
+ths: ths@01c25000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bus_rst 136>;
+ reset-names = "ahb";
+ clocks = <&bus_gates 72>, <&ths_clk>;
+ clock-names = "ahb", "ths";
+};
--
2.20.1

50
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0007-ARM-dts-sunxi-h3-h5-Add-thermal-sensor-node-to-H3-H5.patch Normal file
View file

@ -0,0 +1,50 @@
From af866a2756362500a2e7a4d0cf600e266b5f5c4c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 26 Feb 2017 16:05:58 +0100
Subject: [PATCH 07/82] ARM: dts: sunxi-h3-h5: Add thermal sensor node to H3/H5
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc6131315c47..13fe5e316136 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -488,6 +488,19 @@
};
};
+ ths: ths@1c25000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>,
+ <0x01c14234 0x4>;
+ reg-names = "ths", "calibration";
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "ahb", "ths";
+ };
+
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
@@ -855,4 +868,12 @@
};
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <330>;
+ polling-delay = <1000>;
+ thermal-sensors = <&ths 0>;
+ };
+ };
};
--
2.20.1

24
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0008-cpufreq-dt-platdev-Add-allwinner-sun50i-h5-compatibl.patch Normal file
View file

@ -0,0 +1,24 @@
From 1d78fb6bf60b011bd60ebc9d6ef9499f91c29267 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 12:58:43 +0200
Subject: [PATCH 08/82] cpufreq: dt-platdev: Add allwinner,sun50i-h5 compatible
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index fe14c57de6ca..afb511aa5050 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -29,6 +29,7 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "allwinner,sun8i-a23", },
{ .compatible = "allwinner,sun8i-a83t", },
{ .compatible = "allwinner,sun8i-h3", },
+ { .compatible = "allwinner,sun50i-h5", },
{ .compatible = "apm,xgene-shadowcat", },
--
2.20.1

32
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0009-ARM-dts-sun8i-Increase-max-CPUX-voltage-to-1.4V-on-O.patch Normal file
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@ -0,0 +1,32 @@
From 3ef8fd9d164316d26eb99afec111e0431c2f2c69 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sun, 13 May 2018 21:00:43 +0200
Subject: [PATCH 09/82] ARM: dts: sun8i: Increase max CPUX voltage to 1.4V on
Orange Pi PC
When using thermal regulation we can afford to go higher. Also add
regulator-ramp-delay, because regulator takes some time to change
voltage.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 46240334128f..83f1866ed9e7 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -204,7 +204,8 @@
* Use 1.0V as the minimum voltage instead.
*/
regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1300000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <200>;
regulator-boot-on;
regulator-always-on;
};
--
2.20.1

51
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0010-ARM-dts-sun8i-h3-Add-clock-frequency.patch Normal file
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@ -0,0 +1,51 @@
From 0d1194aaf2b2ebc571cf01d2353d252c12146d2e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 27 Jun 2016 16:08:26 +0200
Subject: [PATCH 10/82] ARM: dts: sun8i-h3: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index f0096074a467..cb19ff797606 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -78,6 +78,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@1 {
@@ -88,6 +89,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@2 {
@@ -98,6 +100,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
cpu@3 {
@@ -108,6 +111,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ clock-frequency = <1200000000>;
};
};
--
2.20.1

51
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0011-arm64-dts-sun50i-h5-Add-clock-frequency.patch Normal file
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@ -0,0 +1,51 @@
From 6328da39df61f962190870089aaa171a7f8aab2c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 13:04:25 +0200
Subject: [PATCH 11/82] arm64: dts: sun50i-h5: Add clock-frequency
To avoid error messages during boot.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 62d646baac3c..4452ab873dec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,7 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@1 {
@@ -59,6 +60,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@2 {
@@ -66,6 +68,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
cpu@3 {
@@ -73,6 +76,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clock-frequency = <1200000000>;
};
};
--
2.20.1

85
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0012-ARM-dts-sunxi-h3-h5-Move-CPU-OPP-table-to-dtsi-share.patch Normal file
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@ -0,0 +1,85 @@
From d4028daf51824eb792fb3c9cc77553ff1edc5d68 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 00:56:50 +0200
Subject: [PATCH 12/82] ARM: dts: sunxi-h3-h5: Move CPU OPP table to dtsi
shared by H3/H5
It is identical for H3 and H5, so it better live there.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 23 -----------------------
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 23 +++++++++++++++++++++++
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index cb19ff797606..261ca0356358 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -43,29 +43,6 @@
#include "sunxi-h3-h5.dtsi"
/ {
- cpu0_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@648000000 {
- opp-hz = /bits/ 64 <648000000>;
- opp-microvolt = <1040000 1040000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp@816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1100000 1100000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
-
- opp@1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1200000 1200000 1300000>;
- clock-latency-ns = <244144>; /* 8 32k periods */
- };
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 13fe5e316136..539b69fecbe9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -105,6 +105,29 @@
};
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@648000000 {
+ opp-hz = /bits/ 64 <648000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1100000 1100000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
de: display-engine {
compatible = "allwinner,sun8i-h3-display-engine";
allwinner,pipelines = <&mixer0>;
--
2.20.1

116
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0013-ARM-dts-sunxi-h3-h5-Add-more-CPU-OPP-for-H3-H5.patch Normal file
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@ -0,0 +1,116 @@
From 9e05f3d014b05df39a55dfd6a08d4bd18a301307 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:13:01 +0200
Subject: [PATCH 13/82] ARM: dts: sunxi-h3-h5: Add more CPU OPP for H3/H5
These OPPs can be used with better cooling and/or thermal regulation.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 78 ++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 539b69fecbe9..f47c22b622f9 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,24 @@
compatible = "operating-points-v2";
opp-shared;
+ opp@120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1040000 1040000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1040000 1040000 1300000>;
@@ -121,11 +139,71 @@
clock-latency-ns = <244144>; /* 8 32k periods */
};
+ opp@960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-microvolt = <1200000 1200000 1300000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
opp@1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000 1200000 1300000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+ opp@1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1320000 1320000 1320000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1224000000 {
+ opp-hz = /bits/ 64 <1224000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1340000 1340000 1340000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-microvolt = <1400000 1400000 1400000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp@1368000000 {
+ opp-hz = /bits/ 64 <1368000000>;
+ opp-microvolt = <1400000 1400000 1400000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
};
de: display-engine {
--
2.20.1

86
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0014-ARM-dts-sunxi-h3-h5-Add-thermal-zone-trip-points.patch Normal file
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@ -0,0 +1,86 @@
From 6914945e888f1206df560ff36375e7257ce38970 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:16:06 +0200
Subject: [PATCH 14/82] ARM: dts: sunxi-h3-h5: Add thermal zone trip points
This enables passive cooling by downregulating CPU voltage/frequency.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 4 +++-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 21 ++++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 261ca0356358..af76a6d250b3 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -54,8 +54,10 @@
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
- #cooling-cells = <2>;
clock-frequency = <1200000000>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
};
cpu@1 {
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index f47c22b622f9..3b8b2234ab4d 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -975,6 +976,26 @@
polling-delay-passive = <330>;
polling-delay = <1000>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-warm {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-warm-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 4452ab873dec..60fc84a1fb44 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -53,6 +53,9 @@
reg = <0>;
enable-method = "psci";
clock-frequency = <1200000000>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
};
cpu@1 {
--
2.20.1

53
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0015-arm64-dts-sun50i-h5-Enable-cpufreq-dt-on-H5-CPU.patch Normal file
View file

@ -0,0 +1,53 @@
From 25be6ff78bebfd869a3be0017715f101bd75bb64 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Mon, 14 May 2018 01:19:06 +0200
Subject: [PATCH 15/82] arm64: dts: sun50i-h5: Enable cpufreq-dt on H5 CPU
Uses OPPs shared with H3.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 60fc84a1fb44..acd90f390e88 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -52,6 +52,9 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
#cooling-cells = <2>;
cooling-min-level = <0>;
@@ -63,6 +66,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
@@ -71,6 +75,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
@@ -79,6 +84,7 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
clock-frequency = <1200000000>;
};
};
--
2.20.1

63
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0016-arm64-dts-sun50i-h5-orange-pi-pc2-Setup-CPUX-voltage.patch Normal file
View file

@ -0,0 +1,63 @@
From 2f3ebd02a475c51f0ee4ac20fd9462f7f8cad314 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 30 Mar 2017 13:01:10 +0200
Subject: [PATCH 16/82] arm64: dts: sun50i-h5-orange-pi-pc2: Setup CPUX voltage
regulator
Orange Pi PC2 features sy8106a regulator just like Orange Pi PC.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 3e0d5a9c096d..af8e3fe26e20 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -124,6 +124,10 @@
};
};
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
&codec {
allwinner,audio-routing =
"Line Out", "LINEOUT",
@@ -219,6 +223,31 @@
};
};
+&r_i2c {
+ status = "okay";
+
+ reg_vdd_cpux: regulator@65 {
+ compatible = "silergy,sy8106a";
+ reg = <0x65>;
+ regulator-name = "vdd-cpux";
+ silergy,fixed-microvolt = <1200000>;
+ /*
+ * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
+ * however both the Armbian DVFS table and the official one
+ * have operating points with voltage under 1.1V, and both
+ * DVFS table are known to work properly at the lowest
+ * operating point.
+ *
+ * Use 1.0V as the minimum voltage instead.
+ */
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <200>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.20.1

127
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0017-Input-edt-ft5x06-Add-support-for-regulator.patch Normal file
View file

@ -0,0 +1,127 @@
From 997e53ee52efc4a0602bf298125a7c9758abf15c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:08 +0200
Subject: [PATCH 17/82] Input: edt-ft5x06 - Add support for regulator
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add the support of regulator to use it as VCC source.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/input/touchscreen/edt-ft5x06.txt | 1 +
drivers/input/touchscreen/edt-ft5x06.c | 43 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index da2dc5d6c98b..987faeb2fe4a 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -28,6 +28,7 @@ Required properties:
Optional properties:
- reset-gpios: GPIO specification for the RESET input
- wake-gpios: GPIO specification for the WAKE input
+ - vcc-supply: Regulator that supplies the touchscreen
- pinctrl-names: should be "default"
- pinctrl-0: a phandle pointing to the pin settings for the
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 1e18ca0d1b4e..dcde719094f7 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -39,6 +39,7 @@
#include <linux/input/mt.h>
#include <linux/input/touchscreen.h>
#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
#define WORK_REGISTER_THRESHOLD 0x00
#define WORK_REGISTER_REPORT_RATE 0x08
@@ -91,6 +92,7 @@ struct edt_ft5x06_ts_data {
struct touchscreen_properties prop;
u16 num_x;
u16 num_y;
+ struct regulator *vcc;
struct gpio_desc *reset_gpio;
struct gpio_desc *wake_gpio;
@@ -963,6 +965,13 @@ edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data *tsdata)
}
}
+static void edt_ft5x06_disable_regulator(void *arg)
+{
+ struct edt_ft5x06_ts_data *data = arg;
+
+ regulator_disable(data->vcc);
+}
+
static int edt_ft5x06_ts_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -991,6 +1000,28 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
tsdata->max_support_points = chip_data->max_support_points;
+ tsdata->vcc = devm_regulator_get(&client->dev, "vcc");
+ if (IS_ERR(tsdata->vcc)) {
+ error = PTR_ERR(tsdata->vcc);
+ if (error != -EPROBE_DEFER)
+ dev_err(&client->dev, "failed to request regulator: %d\n",
+ error);
+ return error;
+ }
+
+ error = regulator_enable(tsdata->vcc);
+ if (error < 0) {
+ dev_err(&client->dev, "failed to enable vcc: %d\n",
+ error);
+ return error;
+ }
+
+ error = devm_add_action_or_reset(&client->dev,
+ edt_ft5x06_disable_regulator,
+ tsdata);
+ if (error)
+ return error;
+
tsdata->reset_gpio = devm_gpiod_get_optional(&client->dev,
"reset", GPIOD_OUT_HIGH);
if (IS_ERR(tsdata->reset_gpio)) {
@@ -1120,9 +1151,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client *client)
static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+ else
+ regulator_disable(tsdata->vcc);
return 0;
}
@@ -1130,9 +1164,18 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
+ int ret;
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+ else {
+ ret = regulator_enable(tsdata->vcc);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable vcc: %d\n", ret);
+ return ret;
+ }
+ }
return 0;
}
--
2.20.1

50
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0018-Input-edt-ft5x06-Set-wake-reset-values-on-resume-sus.patch Normal file
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@ -0,0 +1,50 @@
From 6ff7153330ff8a6c3427e6445e5015620d687c81 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:09 +0200
Subject: [PATCH 18/82] Input: edt-ft5x06 - Set wake/reset values on
resume/suspend
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
drivers/input/touchscreen/edt-ft5x06.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index dcde719094f7..dad2f1f8bf89 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1158,6 +1158,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
else
regulator_disable(tsdata->vcc);
+ if (tsdata->wake_gpio)
+ gpiod_set_value(tsdata->wake_gpio, 0);
+
+ if (tsdata->reset_gpio)
+ gpiod_set_value(tsdata->reset_gpio, 1);
+
return 0;
}
@@ -1177,6 +1183,12 @@ static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
}
}
+ if (tsdata->wake_gpio)
+ gpiod_set_value(tsdata->wake_gpio, 1);
+
+ if (tsdata->reset_gpio)
+ gpiod_set_value(tsdata->reset_gpio, 0);
+
return 0;
}
--
2.20.1

47
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0019-arm-dts-sun8i-a83t-a711-Add-touchscreen-node.patch Normal file
View file

@ -0,0 +1,47 @@
From 0e03253586345216dfb55cdd9b8f038023e0d9bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?= <mylene.josserand@bootlin.com>
Date: Wed, 25 Jul 2018 09:34:10 +0200
Subject: [PATCH 19/82] arm: dts: sun8i: a83t: a711: Add touchscreen node
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148cc1..dc7b94a6c068 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -156,6 +156,22 @@
status = "okay";
};
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&reg_ldo_io0>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

86
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0020-power-supply-axp20x_usb_power-add-function-to-get-ma.patch Normal file
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@ -0,0 +1,86 @@
From 84a6ce439660f26a06219cdf1613f87a6395fdbd Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 14:15:59 +0200
Subject: [PATCH 20/82] power: supply: axp20x_usb_power: add function to get
max current
To prepare for a new PMIC, factor out the code responsible of returning
the maximum current to axp20x_get_current_max.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/power/supply/axp20x_usb_power.c | 51 ++++++++++++++-----------
1 file changed, 29 insertions(+), 22 deletions(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 42001df4bd13..464d4abd3798 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -63,6 +63,34 @@ static irqreturn_t axp20x_usb_power_irq(int irq, void *devid)
return IRQ_HANDLED;
}
+static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
+
+ if (ret)
+ return ret;
+
+ switch (v & AXP20X_VBUS_CLIMIT_MASK) {
+ case AXP20X_VBUC_CLIMIT_100mA:
+ if (power->axp20x_id == AXP221_ID)
+ *val = -1; /* No 100mA limit */
+ else
+ *val = 100000;
+ break;
+ case AXP20X_VBUC_CLIMIT_500mA:
+ *val = 500000;
+ break;
+ case AXP20X_VBUC_CLIMIT_900mA:
+ *val = 900000;
+ break;
+ case AXP20X_VBUC_CLIMIT_NONE:
+ *val = -1;
+ break;
+ }
+ return 0;
+}
+
static int axp20x_usb_power_get_property(struct power_supply *psy,
enum power_supply_property psp, union power_supply_propval *val)
{
@@ -101,28 +129,7 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
val->intval = ret * 1700; /* 1 step = 1.7 mV */
return 0;
case POWER_SUPPLY_PROP_CURRENT_MAX:
- ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
- if (ret)
- return ret;
-
- switch (v & AXP20X_VBUS_CLIMIT_MASK) {
- case AXP20X_VBUC_CLIMIT_100mA:
- if (power->axp20x_id == AXP221_ID)
- val->intval = -1; /* No 100mA limit */
- else
- val->intval = 100000;
- break;
- case AXP20X_VBUC_CLIMIT_500mA:
- val->intval = 500000;
- break;
- case AXP20X_VBUC_CLIMIT_900mA:
- val->intval = 900000;
- break;
- case AXP20X_VBUC_CLIMIT_NONE:
- val->intval = -1;
- break;
- }
- return 0;
+ return axp20x_get_current_max(power, &val->intval);
case POWER_SUPPLY_PROP_CURRENT_NOW:
if (IS_ENABLED(CONFIG_AXP20X_ADC)) {
ret = iio_read_channel_processed(power->vbus_i,
--
2.20.1

135
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0021-power-supply-axp20x_usb_power-add-support-for-AXP813.patch Normal file
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@ -0,0 +1,135 @@
From 5c2f08f5428ed5239b5e90a308e2f77cbc8238b0 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:03:42 +0200
Subject: [PATCH 21/82] power: supply: axp20x_usb_power: add support for AXP813
This adds support for AXP813 PMIC. It is almost the same as AXP22X but
has a different current limit.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/power/supply/axp20x_usb_power.c | 66 ++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 464d4abd3798..4b04fb8f496c 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -40,6 +40,11 @@
#define AXP20X_VBUC_CLIMIT_100mA 2
#define AXP20X_VBUC_CLIMIT_NONE 3
+#define AXP813_VBUC_CLIMIT_900mA 0
+#define AXP813_VBUC_CLIMIT_1500mA 1
+#define AXP813_VBUC_CLIMIT_2000mA 2
+#define AXP813_VBUC_CLIMIT_2500mA 3
+
#define AXP20X_ADC_EN1_VBUS_CURR BIT(2)
#define AXP20X_ADC_EN1_VBUS_VOLT BIT(3)
@@ -63,6 +68,31 @@ static irqreturn_t axp20x_usb_power_irq(int irq, void *devid)
return IRQ_HANDLED;
}
+static int axp813_get_current_max(struct axp20x_usb_power *power, int *val)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
+
+ if (ret)
+ return ret;
+
+ switch (v & AXP20X_VBUS_CLIMIT_MASK) {
+ case AXP813_VBUC_CLIMIT_900mA:
+ *val = 900000;
+ break;
+ case AXP813_VBUC_CLIMIT_1500mA:
+ *val = 1500000;
+ break;
+ case AXP813_VBUC_CLIMIT_2000mA:
+ *val = 2000000;
+ break;
+ case AXP813_VBUC_CLIMIT_2500mA:
+ *val = 2500000;
+ break;
+ }
+ return 0;
+}
+
static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
{
unsigned int v;
@@ -129,6 +159,8 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
val->intval = ret * 1700; /* 1 step = 1.7 mV */
return 0;
case POWER_SUPPLY_PROP_CURRENT_MAX:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_get_current_max(power, &val->intval);
return axp20x_get_current_max(power, &val->intval);
case POWER_SUPPLY_PROP_CURRENT_NOW:
if (IS_ENABLED(CONFIG_AXP20X_ADC)) {
@@ -220,6 +252,31 @@ static int axp20x_usb_power_set_voltage_min(struct axp20x_usb_power *power,
return -EINVAL;
}
+static int axp813_usb_power_set_current_max(struct axp20x_usb_power *power,
+ int intval)
+{
+ int val;
+
+ switch (intval) {
+ case 900000:
+ return regmap_update_bits(power->regmap,
+ AXP20X_VBUS_IPSOUT_MGMT,
+ AXP20X_VBUS_CLIMIT_MASK,
+ AXP813_VBUC_CLIMIT_900mA);
+ case 1500000:
+ case 2000000:
+ case 2500000:
+ val = (intval - 1000000) / 500000;
+ return regmap_update_bits(power->regmap,
+ AXP20X_VBUS_IPSOUT_MGMT,
+ AXP20X_VBUS_CLIMIT_MASK, val);
+ default:
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
static int axp20x_usb_power_set_current_max(struct axp20x_usb_power *power,
int intval)
{
@@ -254,6 +311,9 @@ static int axp20x_usb_power_set_property(struct power_supply *psy,
return axp20x_usb_power_set_voltage_min(power, val->intval);
case POWER_SUPPLY_PROP_CURRENT_MAX:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_set_current_max(power,
+ val->intval);
return axp20x_usb_power_set_current_max(power, val->intval);
default:
@@ -388,7 +448,8 @@ static int axp20x_usb_power_probe(struct platform_device *pdev)
usb_power_desc = &axp20x_usb_power_desc;
irq_names = axp20x_irq_names;
} else if (power->axp20x_id == AXP221_ID ||
- power->axp20x_id == AXP223_ID) {
+ power->axp20x_id == AXP223_ID ||
+ power->axp20x_id == AXP813_ID) {
usb_power_desc = &axp22x_usb_power_desc;
irq_names = axp22x_irq_names;
} else {
@@ -434,6 +495,9 @@ static const struct of_device_id axp20x_usb_power_match[] = {
}, {
.compatible = "x-powers,axp223-usb-power-supply",
.data = (void *)AXP223_ID,
+ }, {
+ .compatible = "x-powers,axp813-usb-power-supply",
+ .data = (void *)AXP813_ID,
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, axp20x_usb_power_match);
--
2.20.1

26
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0022-ARM-dtsi-axp813-add-USB-power-supply-node.patch Normal file
View file

@ -0,0 +1,26 @@
From 8d81c934be105c53309f66057cabaf5cb496aec7 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:06:28 +0200
Subject: [PATCH 22/82] ARM: dtsi: axp813: add USB power supply node
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
arch/arm/boot/dts/axp81x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index 043c717dcef1..f32a8ba53b85 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -166,4 +166,8 @@
status = "disabled";
};
};
+
+ usb_power_supply: usb-power-supply {
+ compatible = "x-powers,axp813-usb-power-supply";
+ };
};
--
2.20.1

27
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0023-mfd-axp20x-add-USB-power-supply-mfd-cell-to-AXP813.patch Normal file
View file

@ -0,0 +1,27 @@
From 95a44a737d3a50a67eabad266aeb7b8d763ef5d2 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Wed, 23 Aug 2017 15:07:14 +0200
Subject: [PATCH 23/82] mfd: axp20x: add USB power supply mfd cell to AXP813
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/mfd/axp20x.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index f8e0fa97bb31..ac8da970bdfe 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -787,6 +787,9 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-battery-power-supply",
.of_compatible = "x-powers,axp813-battery-power-supply",
+ }, {
+ .name = "axp20x-usb-power-supply",
+ .of_compatible = "x-powers,axp813-usb-power-supply",
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
--
2.20.1

54
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0024-mfd-axp20x-add-regulator-userspace-consumer-to-mfd-c.patch Normal file
View file

@ -0,0 +1,54 @@
From b77e60c6a2797ada240b1d42b896b70853e2b1af Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@free-electrons.com>
Date: Thu, 10 Aug 2017 09:40:21 +0200
Subject: [PATCH 24/82] mfd: axp20x: add regulator-userspace-consumer to mfd
cells of AXP813
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
drivers/mfd/axp20x.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index ac8da970bdfe..95f36a7e3cd4 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -24,6 +24,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include <linux/regulator/userspace-consumer.h>
#include <linux/mfd/axp20x.h>
#include <linux/mfd/core.h>
#include <linux/of_device.h>
@@ -771,6 +772,16 @@ static const struct mfd_cell axp809_cells[] = {
},
};
+static struct regulator_bulk_data vcc_vb = {
+ .supply = "vcc-vb",
+};
+
+static struct regulator_userspace_consumer_data vcc_vb_data = {
+ .name = "vcc-vb",
+ .num_supplies = 1,
+ .supplies = &vcc_vb,
+};
+
static const struct mfd_cell axp813_cells[] = {
{
.name = "axp221-pek",
@@ -790,6 +801,10 @@ static const struct mfd_cell axp813_cells[] = {
}, {
.name = "axp20x-usb-power-supply",
.of_compatible = "x-powers,axp813-usb-power-supply",
+ }, {
+ .name = "reg-userspace-consumer",
+ .platform_data = &vcc_vb_data,
+ .pdata_size = sizeof(vcc_vb_data),
}, {
.name = "axp20x-ac-power-supply",
.of_compatible = "x-powers,axp813-ac-power-supply",
--
2.20.1

188
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0025-power-supply-axp20x-usb-power-Support-input-current-.patch Normal file
View file

@ -0,0 +1,188 @@
From 49675ccdafd63d0eee2fb0a57bd39fcb07a83bae Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 14 Nov 2017 02:09:43 +0100
Subject: [PATCH 25/82] power: supply: axp20x-usb-power: Support input current
limit
Allow to set input current limit directly when autodetection fails
on incorrectly wired tablets, like TBS A711, that don't have
D+/D- pins connected, and can't detect the usb power supply type.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/power/supply/axp20x_usb_power.c | 104 +++++++++++++++++++++++-
include/linux/mfd/axp20x.h | 1 +
2 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
index 4b04fb8f496c..3bc2e1f7ab83 100644
--- a/drivers/power/supply/axp20x_usb_power.c
+++ b/drivers/power/supply/axp20x_usb_power.c
@@ -49,6 +49,8 @@
#define AXP20X_ADC_EN1_VBUS_VOLT BIT(3)
#define AXP20X_VBUS_MON_VBUS_VALID BIT(3)
+#define AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK GENMASK(7, 4)
+#define AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET 4
struct axp20x_usb_power {
struct device_node *np;
@@ -93,6 +95,50 @@ static int axp813_get_current_max(struct axp20x_usb_power *power, int *val)
return 0;
}
+static int
+axp813_usb_power_get_input_current_limit(struct axp20x_usb_power *power,
+ int *intval)
+{
+ unsigned int v;
+ int ret = regmap_read(power->regmap, AXP813_CHRG_CTRL3, &v);
+
+ if (ret)
+ return ret;
+
+ v &= AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK;
+ v >>= AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET;
+
+ switch (v) {
+ case 0:
+ *intval = 100000;
+ return 0;
+ case 1:
+ *intval = 500000;
+ return 0;
+ case 2:
+ *intval = 900000;
+ return 0;
+ case 3:
+ *intval = 1500000;
+ return 0;
+ case 4:
+ *intval = 2000000;
+ return 0;
+ case 5:
+ *intval = 2500000;
+ return 0;
+ case 6:
+ *intval = 3000000;
+ return 0;
+ case 7:
+ *intval = 3500000;
+ return 0;
+ default:
+ *intval = 4000000;
+ return 0;
+ }
+}
+
static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val)
{
unsigned int v;
@@ -219,6 +265,11 @@ static int axp20x_usb_power_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_ONLINE:
val->intval = !!(input & AXP20X_PWR_STATUS_VBUS_USED);
break;
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_get_input_current_limit(power,
+ &val->intval);
+ /* fallthrough */
default:
return -EINVAL;
}
@@ -252,6 +303,50 @@ static int axp20x_usb_power_set_voltage_min(struct axp20x_usb_power *power,
return -EINVAL;
}
+static int
+axp813_usb_power_set_input_current_limit(struct axp20x_usb_power *power,
+ int intval)
+{
+ unsigned int reg;
+
+ switch (intval) {
+ case 100000:
+ reg = 0;
+ break;
+ case 500000:
+ reg = 1;
+ break;
+ case 900000:
+ reg = 2;
+ break;
+ case 1500000:
+ reg = 3;
+ break;
+ case 2000000:
+ reg = 4;
+ break;
+ case 2500000:
+ reg = 5;
+ break;
+ case 3000000:
+ reg = 6;
+ break;
+ case 3500000:
+ reg = 7;
+ break;
+ case 4000000:
+ reg = 8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(power->regmap,
+ AXP813_CHRG_CTRL3,
+ AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_MASK,
+ reg << AXP813_CHRG_CTRL3_VBUS_CUR_LIMIT_OFFSET);
+}
+
static int axp813_usb_power_set_current_max(struct axp20x_usb_power *power,
int intval)
{
@@ -316,6 +411,11 @@ static int axp20x_usb_power_set_property(struct power_supply *psy,
val->intval);
return axp20x_usb_power_set_current_max(power, val->intval);
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
+ if (power->axp20x_id == AXP813_ID)
+ return axp813_usb_power_set_input_current_limit(power,
+ val->intval);
+ /* fallthrough */
default:
return -EINVAL;
}
@@ -327,7 +427,8 @@ static int axp20x_usb_power_prop_writeable(struct power_supply *psy,
enum power_supply_property psp)
{
return psp == POWER_SUPPLY_PROP_VOLTAGE_MIN ||
- psp == POWER_SUPPLY_PROP_CURRENT_MAX;
+ psp == POWER_SUPPLY_PROP_CURRENT_MAX ||
+ psp == POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT;
}
static enum power_supply_property axp20x_usb_power_properties[] = {
@@ -346,6 +447,7 @@ static enum power_supply_property axp22x_usb_power_properties[] = {
POWER_SUPPLY_PROP_ONLINE,
POWER_SUPPLY_PROP_VOLTAGE_MIN,
POWER_SUPPLY_PROP_CURRENT_MAX,
+ POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
};
static const struct power_supply_desc axp20x_usb_power_desc = {
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 517e60eecbcb..1c968a2e31f7 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -133,6 +133,7 @@ enum axp20x_variants {
/* Other DCDC regulator control registers are the same as AXP803 */
#define AXP813_DCDC7_V_OUT 0x26
+#define AXP813_CHRG_CTRL3 0x35
/* Interrupt */
#define AXP152_IRQ1_EN 0x40
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0026-mfd-axp20x-Make-AXP22X_CHRG_CTRL3-because-it-is-upda.patch Normal file
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@ -0,0 +1,28 @@
From 22b15d77f99612906a02c96b9b926233d187605f Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 16 Nov 2017 00:30:19 +0100
Subject: [PATCH 26/82] mfd: axp20x: Make AXP22X_CHRG_CTRL3 because it is
updated by charger det.
Charger detection updates this to reflect allowed current.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/mfd/axp20x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 95f36a7e3cd4..81bf6ee4d8bb 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -131,6 +131,7 @@ static const struct regmap_range axp288_volatile_ranges[] = {
regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
+ regmap_reg_range(AXP22X_CHRG_CTRL3, AXP22X_CHRG_CTRL3),
regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
--
2.20.1

37
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0027-arm-dts-sun8i-a83t-a711-update-brightness-levels-to-.patch Normal file
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@ -0,0 +1,37 @@
From 5e76e10095d6370a3c7235543acda9b4f256d246 Mon Sep 17 00:00:00 2001
From: Tomas Novotny <tomas@novotny.cz>
Date: Tue, 24 Oct 2017 15:07:42 +0200
Subject: [PATCH 27/82] arm: dts: sun8i: a83t: a711: update brightness levels
to fit the device
The function is exponential with base of 1.32 and some offset and
tweaks. The lowest values produce no output, so we are starting at 8.
The default brigtness is a bit lower than maximum to boot with reduced
backlight.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index dc7b94a6c068..bd7e231e3aba 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -65,8 +65,11 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
- brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
- default-brightness-level = <9>;
+ brightness-levels = <0 8 9 10 11 13 15 17 19 21 23 25 28
+ 31 34 37 40 44 48 52 56 61 67 72 78
+ 84 91 98 106 115 124 133 143 154
+ 166 179 192 207 223 239 255>;
+ default-brightness-level = <39>;
};
panel {
--
2.20.1

2406
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0028-media-sun6i-csi-Add-support-for-Allwinner-CSI.patch Normal file
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File diff suppressed because it is too large Load diff

30
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0029-MAINTAINERS-Add-entry-for-Himax-HM5065.patch Normal file
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@ -0,0 +1,30 @@
From 143f5c46be05234ca2618eb4515b9b1d2f329770 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 21:31:35 +0200
Subject: [PATCH 29/82] MAINTAINERS: Add entry for Himax HM5065
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 11a59e82d92e..93f4ff7d6eba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6611,6 +6611,12 @@ S: Supported
F: Documentation/scsi/hptiop.txt
F: drivers/scsi/hptiop.c
+HIMAX HM5065 SENSOR DRIVER
+M: Ondrej Jirman <kernel@xff.cz>
+L: linux-media@vger.kernel.org
+S: Supported
+F: drivers/media/i2c/hm5065.c
+
HIPPI
M: Jes Sorensen <jes@trained-monkey.org>
L: linux-hippi@sunsite.dk
--
2.20.1

71
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0030-media-dt-bindings-Add-bindings-for-Himax-HM5065-came.patch Normal file
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@ -0,0 +1,71 @@
From 086f56910cfcc26939c56dfd143c7ee3dc24cff1 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:30:39 +0200
Subject: [PATCH 30/82] media: dt-bindings: Add bindings for Himax HM5065
camera sensor
HM5065 is 5MP CMOS sensor...
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../devicetree/bindings/media/i2c/hm5065.txt | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.txt
diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.txt b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
new file mode 100644
index 000000000000..68ad7f529e18
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
@@ -0,0 +1,48 @@
+* Himax HM5065 CSI camera sensor
+
+Required Properties:
+- compatible: should be "himax,hm5065"
+- clocks: reference to the external input clock for the sensor.
+- clock-names: should be "xclk".
+- IOVDD-supply: Digital I/O voltage supply, 2.8 volts
+- AVDD-supply: Analog voltage supply, 2.8 volts
+- DVDD-supply: Digital core voltage supply, 1.8 volts
+- AFVDD-supply: Auto focus voltage supply, 2.8 volts
+
+Optional Properties (one or both must be configured):
+- reset-gpios: reference to the GPIO connected to the reset pin, if any.
+ This is an active low signal to the HM5065.
+- chipenable-gpios: reference to the GPIO connected to the CE pin,
+ if any. This is an active high signal to the HM5065.
+
+The device node must contain one 'port' child node for its digital output
+video port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+&i2c1 {
+ hm5065: camera@1f {
+ compatible = "himax,hm5065";
+ reg = <0x1f>;
+ clocks = <&ccu CLK_CSI_MCLK>;
+ clock-names = "xclk";
+ IOVDD-supply = <&reg_dldo3>;
+ AVDD-supply = <&reg_dldo4>;
+ DVDD-supply = <&reg_eldo3>;
+ AFVDD-supply = <&reg_dldo3>;
+ reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
+ chipenable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
+
+ port {
+ hm5065_ep: endpoint {
+ remote-endpoint = <&csi0_hm5065_ep>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+};
--
2.20.1

53
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0031-ARM-dts-sun8i-a83t-Add-CSI0-node-for-cmos-sensor-int.patch Normal file
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@ -0,0 +1,53 @@
From 7fe79d7ef105939f10903d87c44b8ea4da3bc4ae Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:46:55 +0200
Subject: [PATCH 31/82] ARM: dts: sun8i-a83t: Add CSI0 node for cmos sensor
interface driver
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 00a02b037320..66f035ead79a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -636,6 +636,20 @@
#reset-cells = <1>;
};
+ csi0: csi@01cb0000 {
+ compatible = "allwinner,sun8i-a83t-csi";
+ reg = <0x01cb0000 0x1000>; /* manual says 0x40000 size */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-a83t-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
@@ -649,6 +663,13 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ csi0_pins: csi0-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE10", "PE11", "PE12", "PE13";
+ function = "csi";
+ };
+
emac_rgmii_pins: emac-rgmii-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD11", "PD12", "PD13", "PD14", "PD18",
--
2.20.1

38
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0032-ARM-dts-sun8i-a83t-tbs-a711-Force-dvdd-csi-r-f-regul.patch Normal file
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@ -0,0 +1,38 @@
From ac8826aeb1f157a76b1f1d31b13eb557d3f96108 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:53:26 +0200
Subject: [PATCH 32/82] ARM: dts: sun8i-a83t-tbs-a711: Force dvdd-csi-r/f
regulators to 1.8V
This is required by camera sensors that are connected to them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index bd7e231e3aba..7936405862c1 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -353,7 +353,7 @@
};
&reg_eldo1 {
- regulator-min-microvolt = <1200000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-r";
};
@@ -365,7 +365,7 @@
};
&reg_eldo3 {
- regulator-min-microvolt = <1200000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-f";
};
--
2.20.1

42
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0033-ARM-dts-sun8i-a83t-tbs-a711-Use-i2c-gpio-to-communic.patch Normal file
View file

@ -0,0 +1,42 @@
From 0ba507d286fc521e71ba048d81c7d1d751012bb8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 30 Sep 2017 02:51:09 +0200
Subject: [PATCH 33/82] ARM: dts: sun8i-a83t-tbs-a711: Use i2c-gpio to
communicate with cameras
Camera sensors are connected via I2C to PE14/PE15 pins on A83T.
Unfortunately while the A83T datasheet suggests TWI2 I2C controller
can be configured to have SDA/SCL on these pins, this configuration
doesn't work in reality. We need to either use CCI I2C controller
that is part of the CSI module, or as is done in this patch, use GPIO
based bitbanging I2C driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 7936405862c1..8a0a8d39eb21 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -72,6 +72,16 @@
default-brightness-level = <39>;
};
+ i2c_gpio: i2c-gpio {
+ compatible = "i2c-gpio";
+ /* PE15 = sda, PE14 = scl */
+ sda-gpios = <&pio 4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pio 4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <1>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
panel {
compatible = "tbs,a711-panel", "panel-lvds";
backlight = <&backlight>;
--
2.20.1

79
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0034-ARM-dts-sun8i-a83t-tbs-a711-Add-rear-camera-sensor-H.patch Normal file
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@ -0,0 +1,79 @@
From 5436d28adbf6268496e20b4c43c43a59f597c340 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Tue, 10 Oct 2017 05:26:49 +0200
Subject: [PATCH 34/82] ARM: dts: sun8i-a83t-tbs-a711: Add rear camera sensor
(HM5065)
Sensor is connected via parallel bus to CSI0 and via I2C bus to
PE14/PE15 pins. Enable CSI0 module and add the node for HM5065
camera sensor.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 43 +++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 8a0a8d39eb21..9a87ce651224 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -149,6 +149,23 @@
cpu-supply = <&reg_dcdc3>;
};
+&csi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi0_pins>;
+
+ port {
+ csi0_hm5065_ep: endpoint {
+ remote-endpoint = <&hm5065_ep>;
+ bus-width = <8>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+};
+
&de {
status = "okay";
};
@@ -185,6 +202,32 @@
};
};
+&i2c_gpio {
+ hm5065: camera@1f {
+ compatible = "himax,hm5065";
+ reg = <0x1f>;
+ clocks = <&ccu CLK_CSI_MCLK>;
+ clock-names = "xclk";
+ IOVDD-supply = <&reg_dldo3>;
+ AVDD-supply = <&reg_dldo4>;
+ DVDD-supply = <&reg_eldo3>;
+ AFVDD-supply = <&reg_dldo3>;
+ reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
+ chipenable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
+
+ port {
+ hm5065_ep: endpoint {
+ remote-endpoint = <&csi0_hm5065_ep>;
+ bus-width = <8>;
+ data-active = <1>;
+ pclk-sample = <1>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

28
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0035-ARM-dts-sun8i-a83t-tbs-a711-Reduce-camera-IOVDD-volt.patch Normal file
View file

@ -0,0 +1,28 @@
From 0f0c62c90fc072355b2118d118715492710b8735 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 8 Nov 2017 04:55:15 +0100
Subject: [PATCH 35/82] ARM: dts: sun8i-a83t-tbs-a711: Reduce camera IOVDD
voltage
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 9a87ce651224..1a711a28f682 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -389,8 +389,8 @@
};
&reg_dldo3 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
regulator-name = "vdd-csi";
};
--
2.20.1

32
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0036-ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch Normal file
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@ -0,0 +1,32 @@
From acfec807289ebf7c2af8aaf75aaa67159d549734 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Wed, 8 Nov 2017 21:57:45 +0100
Subject: [PATCH 36/82] ARM: dts: sun8i-a83t-tbs-a711: Add flash led support
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1a711a28f682..c8278e173f50 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -60,6 +60,15 @@
stdout-path = "serial0:115200n8";
};
+ leds {
+ compatible = "gpio-leds";
+
+ flash_led {
+ label = "flash";
+ gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
--
2.20.1

2380
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0037-media-hm5065-Add-subdev-driver-for-Himax-HM5065-came.patch Normal file
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34
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0038-arm-dts-sun8i-a83t-a711-Enable-I2C1.patch Normal file
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@ -0,0 +1,34 @@
From dd149592ded2be2ebbe64ee83bcb34054470cf07 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 9 Nov 2017 23:05:13 +0100
Subject: [PATCH 38/82] arm: dts: sun8i: a83t: a711: Enable I2C1
The A711 has some sensors connected to I2C1. Enable only the bus for the
moment.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index c8278e173f50..8e9f0de3d0c0 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -237,6 +237,13 @@
};
};
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
--
2.20.1

35
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0039-ARM-dts-sun8i-a83t-tbs-a711-Enable-BMA250-accelerome.patch Normal file
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@ -0,0 +1,35 @@
From 69c8e0651bb68ab80b0fc4033b8ca5e87b8bb164 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:20:43 +0100
Subject: [PATCH 39/82] ARM: dts: sun8i-a83t-tbs-a711: Enable BMA250
accelerometer IIO
It's already supported in mainline kernel.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 8e9f0de3d0c0..2427bf3461d7 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -242,6 +242,14 @@
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ };
};
&mmc0 {
--
2.20.1

36
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0040-ARM-dts-sun8i-a83t-tbs-a711-Enable-LTR-501-ALS-IIO.patch Normal file
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@ -0,0 +1,36 @@
From 113d3049c946e68e32fdec6f64672fe4cd181cc8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:21:55 +0100
Subject: [PATCH 40/82] ARM: dts: sun8i-a83t-tbs-a711: Enable LTR-501-ALS IIO
It's already supported in mainline kernel. Though, the driver didn't
have OF compativles table.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 2427bf3461d7..6acc678d1b5b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -250,6 +250,15 @@
interrupt-parent = <&pio>;
interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
};
+
+ /* Light Sensor */
+ ltr501: ltr501@23 {
+ status = "disabled"; /* no output */
+ compatible = "ltr,ltr501";
+ reg = <0x23>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 12 IRQ_TYPE_EDGE_FALLING>; /* PG12 */
+ };
};
&mmc0 {
--
2.20.1

68
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0041-iio-ltr501-Add-OF-compatibles.patch Normal file
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@ -0,0 +1,68 @@
From e4548a8a5ad34919a94b282369212b661e1d4382 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:23:01 +0100
Subject: [PATCH 41/82] iio: ltr501: Add OF compatibles
So that driver can be configured from DTS.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/iio/light/ltr501.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/light/ltr501.c b/drivers/iio/light/ltr501.c
index 830a2d45aa4d..bdb296dcb7c0 100644
--- a/drivers/iio/light/ltr501.c
+++ b/drivers/iio/light/ltr501.c
@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/acpi.h>
+#include <linux/of.h>
#include <linux/iio/iio.h>
#include <linux/iio/events.h>
@@ -1558,6 +1559,7 @@ static int ltr501_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(ltr501_pm_ops, ltr501_suspend, ltr501_resume);
+#ifdef CONFIG_ACPI
static const struct acpi_device_id ltr_acpi_match[] = {
{"LTER0501", ltr501},
{"LTER0559", ltr559},
@@ -1565,6 +1567,7 @@ static const struct acpi_device_id ltr_acpi_match[] = {
{ },
};
MODULE_DEVICE_TABLE(acpi, ltr_acpi_match);
+#endif
static const struct i2c_device_id ltr501_id[] = {
{ "ltr501", ltr501},
@@ -1574,11 +1577,22 @@ static const struct i2c_device_id ltr501_id[] = {
};
MODULE_DEVICE_TABLE(i2c, ltr501_id);
+#ifdef CONFIG_OF
+static const struct of_device_id ltr501_of_match[] = {
+ { .compatible = "ltr,ltr501", .data = (void*)ltr501 },
+ { .compatible = "ltr,ltr559", .data = (void*)ltr559 },
+ { .compatible = "ltr,ltr301", .data = (void*)ltr301 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ltr501_of_match);
+#endif
+
static struct i2c_driver ltr501_driver = {
.driver = {
- .name = LTR501_DRV_NAME,
- .pm = &ltr501_pm_ops,
+ .name = LTR501_DRV_NAME,
+ .pm = &ltr501_pm_ops,
.acpi_match_table = ACPI_PTR(ltr_acpi_match),
+ .of_match_table = of_match_ptr(ltr501_of_match)
},
.probe = ltr501_probe,
.remove = ltr501_remove,
--
2.20.1

46
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0042-ARM-dts-sun8i-a83t-tbs-a711-Enable-AK8963-magnetomet.patch Normal file
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@ -0,0 +1,46 @@
From 2a3460a07d4ef36bd754c83dce9b6b7ea9844aa3 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 13:24:58 +0100
Subject: [PATCH 42/82] ARM: dts: sun8i-a83t-tbs-a711: Enable AK8963
magnetometer
Though the chip is probably broken on my tablet. It doesn't respond
on I2C 0x0d address.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 6acc678d1b5b..ec986498114e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -251,6 +251,24 @@
interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
};
+ /* Magnetic Sensor */
+ ak8963: ak8963@0d {
+ status = "disabled"; /* broken */
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ interrupt-parent = <&pio>;
+ interrupts = <1 2 IRQ_TYPE_EDGE_RISING>; /* PB2 */
+ mount-matrix = /* x0 */ "-0.984807753012208",
+ /* y0 */ "0",
+ /* z0 */ "-0.173648177666930",
+ /* x1 */ "0",
+ /* y1 */ "-1",
+ /* z1 */ "0",
+ /* x2 */ "-0.173648177666930",
+ /* y2 */ "0",
+ /* z2 */ "0.984807753012208";
+ };
+
/* Light Sensor */
ltr501: ltr501@23 {
status = "disabled"; /* no output */
--
2.20.1

107
layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline-4.19/0000-0043-nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch Normal file
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@ -0,0 +1,107 @@
From 8df4a460c0459b0ba6a20634adc4ecb60b8e89d5 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 10 Nov 2017 14:29:26 +0100
Subject: [PATCH 43/82] nfc: pn544: Add support for VBAT/PVDD regulators
Regulators are required, so this can't go into mainline as is.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/nfc/pn544/i2c.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/nfc/pn544/i2c.c b/drivers/nfc/pn544/i2c.c
index d0207f8e68b7..5d0a20d3f9c8 100644
--- a/drivers/nfc/pn544/i2c.c
+++ b/drivers/nfc/pn544/i2c.c
@@ -27,6 +27,7 @@
#include <linux/nfc.h>
#include <linux/firmware.h>
#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
#include <asm/unaligned.h>
@@ -70,6 +71,14 @@ MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
#define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
+/* regulator supplies */
+static const char * const pn544_supply_names[] = {
+ "PVDD", /* Digital Core (1.8V) supply */
+ "VBAT", /* Analog (2.9V-5.5V) supply */
+};
+
+#define PN544_NUM_SUPPLIES ARRAY_SIZE(pn544_supply_names)
+
/*
* Exposed through the 4 most significant bytes
* from the HCI SW_VERSION first byte, a.k.a.
@@ -161,6 +170,7 @@ struct pn544_i2c_phy {
struct i2c_client *i2c_dev;
struct nfc_hci_dev *hdev;
+ struct regulator_bulk_data supplies[PN544_NUM_SUPPLIES];
struct gpio_desc *gpiod_en;
struct gpio_desc *gpiod_fw;
@@ -250,9 +260,14 @@ static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
static int pn544_hci_i2c_enable(void *phy_id)
{
struct pn544_i2c_phy *phy = phy_id;
+ int ret;
pr_info("%s\n", __func__);
+ ret = regulator_bulk_enable(PN544_NUM_SUPPLIES, phy->supplies);
+ if (ret)
+ return ret;
+
pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
phy->powered = 1;
@@ -274,6 +289,8 @@ static void pn544_hci_i2c_disable(void *phy_id)
gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
usleep_range(10000, 15000);
+ regulator_bulk_disable(PN544_NUM_SUPPLIES, phy->supplies);
+
phy->powered = 0;
}
@@ -380,7 +397,7 @@ static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
(len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
- nfc_err(&client->dev, "invalid len byte\n");
+ nfc_err(&client->dev, "invalid len byte %hhx\n", len);
r = -EBADMSG;
goto flush;
}
@@ -883,7 +900,7 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
{
struct device *dev = &client->dev;
struct pn544_i2c_phy *phy;
- int r = 0;
+ int r = 0, i;
dev_dbg(&client->dev, "%s\n", __func__);
dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
@@ -908,6 +925,14 @@ static int pn544_hci_i2c_probe(struct i2c_client *client,
if (r)
dev_dbg(dev, "Unable to add GPIO mapping table\n");
+ for (i = 0; i < PN544_NUM_SUPPLIES; i++)
+ phy->supplies[i].supply = pn544_supply_names[i];
+
+ r = devm_regulator_bulk_get(&client->dev, PN544_NUM_SUPPLIES,
+ phy->supplies);
+ if (r)
+ return r;
+
/* Get EN GPIO */
phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(phy->gpiod_en)) {
--
2.20.1

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