diff --git a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
new file mode 100644
index 0000000..c7beab9
--- /dev/null
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
@@ -0,0 +1,32 @@
+From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Tue, 20 Dec 2016 11:25:12 +0100
+Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
+
+Kernel would lower the divider on first CLK change and cause the
+lock up.
+---
+ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
+index 50fb302a19..91aa2a0478 100644
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
+ 	int k = 1;
+ 	int m = 1;
+ 
+-	if (clk > 1152000000) {
+-		k = 2;
+-	} else if (clk > 768000000) {
++	if (clk >= 1368000000) {
+ 		k = 3;
+-		m = 2;
++	} else if (clk >= 768000000) {
++		k = 2;
+ 	}
+ 
+ 	/* Switch to 24MHz clock while changing PLL1 */
+-- 
+2.11.0
diff --git a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_%.bbappend b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_%.bbappend
new file mode 100644
index 0000000..b9dac99
--- /dev/null
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_%.bbappend
@@ -0,0 +1,9 @@
+RESIN_EXTERNAL_MMC = "0"
+RESIN_INTERNAL_MMC = "1"
+UBOOT_KCONFIG_SUPPORT = "1"
+inherit resin-u-boot
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+SRC_URI_append = " \
+    file://0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch \
+    "
\ No newline at end of file