moved to u-boot 2017.07

2017-07-27 13:38:15 +02:00 · 2017-07-27 13:38:15 +02:00 · 180b9e22d9
commit 180b9e22d9
parent b84ecd8f4c
44 changed files with 363408 additions and 21 deletions
--- a/layers/meta-resin-allwinner/conf/machine/nanopi-neo-air.conf
+++ b/layers/meta-resin-allwinner/conf/machine/nanopi-neo-air.conf
@ -4,10 +4,10 @@
 require conf/machine/include/sun8i.inc
-PREFERRED_VERSION_linux = "4.11.0+git%"
+PREFERRED_VERSION_linux = "4.11%"
-PREFERRED_VERSION_u-boot = "v2017.03%"
+PREFERRED_VERSION_u-boot = "v2017.07%"
-KERNEL_DEVICETREE = "sun8i-h3-nanopi-neo.dtb \ 
+KERNEL_DEVICETREE = "sun8i-h3-nanopi-neo-air.dtb \ 
 overlay/sun8i-h3-analog-codec.dtbo \
 overlay/sun8i-h3-cir.dtbo \
 overlay/sun8i-h3-fixup.scr \
@ -31,6 +31,6 @@ overlay/sun8i-h3-w1-gpio.dtbo \
 MACHINE_EXTRA_RRECOMMENDS += "linux-firmware-ap6212"
-UBOOT_MACHINE = "nanopi_air_defconfig"
+UBOOT_MACHINE = "nanopi_neo_air_defconfig"
 DEFAULTTUNE = "cortexa7hf-neon-vfpv4"
--- a/layers/meta-resin-allwinner/conf/machine/orange-pi-lite.conf
+++ b/layers/meta-resin-allwinner/conf/machine/orange-pi-lite.conf
@ -4,7 +4,7 @@
 require conf/machine/include/sun8i.inc
-PREFERRED_VERSION_linux = "4.11.0+git%"
+PREFERRED_VERSION_linux = "4.11%"
 PREFERRED_VERSION_u-boot = "v2017.03%"
 KERNEL_DEVICETREE = "sun8i-h3-orangepi-lite.dtb \ 
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot/armbianEnv.txt
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot/armbianEnv.txt
@ -2,7 +2,7 @@ verbosity=1
 console=serial
 overlay_prefix=sun8i-h3
 rootfstype=ext4
-overlays=uart1 i2c0 spi-spidev
+overlays=uart1 i2c0 spi-spidev analog-codec
 param_w1_pin=PA20
 param_w1_pin_int_pullup=1
 param_uart1_rtscts=1
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.03.bbappend
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.03.bbappend
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07.bb
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07.bb
@ -0,0 +1,61 @@
 DESCRIPTION="Upstream's U-boot configured for sunxi devices"
 require recipes-bsp/u-boot/u-boot.inc
 FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot_2017.07:"
 DEPENDS += "dtc-native"
 LICENSE = "GPLv2"
 LIC_FILES_CHKSUM = "\
 file://Licenses/Exceptions;md5=338a7cb1e52d0d1951f83e15319a3fe7 \
 file://Licenses/bsd-2-clause.txt;md5=6a31f076f5773aabd8ff86191ad6fdd5 \
 file://Licenses/bsd-3-clause.txt;md5=4a1190eac56a9db675d58ebe86eaf50c \
 file://Licenses/eCos-2.0.txt;md5=b338cb12196b5175acd3aa63b0a0805c \
 file://Licenses/gpl-2.0.txt;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
 file://Licenses/ibm-pibs.txt;md5=c49502a55e35e0a8a1dc271d944d6dba \
 file://Licenses/isc.txt;md5=ec65f921308235311f34b79d844587eb \
 file://Licenses/lgpl-2.0.txt;md5=5f30f0716dfdd0d91eb439ebec522ec2 \
 file://Licenses/lgpl-2.1.txt;md5=4fbd65380cdd255951079008b364516c \
 file://Licenses/x11.txt;md5=b46f176c847b8742db02126fb8af92e2 \
 "
 COMPATIBLE_MACHINE = "(sun4i|sun5i|sun7i|sun8i)"
 DEFAULT_PREFERENCE_sun4i="1"
 DEFAULT_PREFERENCE_sun5i="1"
 DEFAULT_PREFERENCE_sun7i="1"
 DEFAULT_PREFERENCE_sun8i="1"
 SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
           file://h3-Fix-PLL1-setup-to-never-use-dividers.patch \
           file://h3-enable-power-led.patch \ 
           file://h3-set-safe-axi_apb-clock-dividers.patch \
           file://h3-adjust-dram-frequency.patch \
           file://enable-DT-overlays-support.patch \
           file://fix-sunxi-gpio-driver.patch \
           file://add-nanopi-air-emmc.patch \
           file://adjust-nanopi-neo-cpufreq.patch \
           file://emac-gmac-fixes.patch \
           file://sun8i-set-machid.patch \
           file://boot.cmd \
           file://armbianEnv.txt \
           "
 SRCREV = "d85ca029f257b53a96da6c2fb421e78a003a9943"
 PV = "v2017.07+git${SRCPV}"
 PE = "2"
 S = "${WORKDIR}/git"
 SPL_BINARY="u-boot-sunxi-with-spl.bin"
 UBOOT_ENV_SUFFIX = "scr"
 UBOOT_ENV = "boot"
 do_compile_append() {
    ${B}/tools/mkimage -C none -A arm -T script -d ${WORKDIR}/boot.cmd ${WORKDIR}/${UBOOT_ENV_BINARY}
 }
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07.bbappend
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07.bbappend
@ -0,0 +1,8 @@
 RESIN_EXTERNAL_MMC = "0"
 RESIN_INTERNAL_MMC = "1"
 UBOOT_KCONFIG_SUPPORT = "1"
 inherit resin-u-boot
 do_deploy_append() {
    install -m 0644 ${WORKDIR}/armbianEnv.txt ${DEPLOYDIR}/armbianEnv.txt
 }
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/add-nanopi-air-emmc.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/add-nanopi-air-emmc.patch
@ -0,0 +1,12 @@
 diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
 index 9598bd5cd5..aedbac75c8 100644
 --- a/configs/nanopi_neo_air_defconfig
 +++ b/configs/nanopi_neo_air_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
 CONFIG_SPL=y
 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/adjust-nanopi-neo-cpufreq.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/adjust-nanopi-neo-cpufreq.patch
@ -0,0 +1,12 @@
 diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
 index 89f5687884..2cbceb54f1 100644
 --- a/configs/nanopi_neo_defconfig
 +++ b/configs/nanopi_neo_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_CONSOLE_MUX=y
 CONFIG_SPL=y
 +CONFIG_SYS_CLK_FREQ=480000000
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/armbianEnv.txt
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/armbianEnv.txt
@ -0,0 +1,7 @@
 verbosity=1
 console=serial
 overlay_prefix=sun8i-h3
 rootfstype=ext4
 overlays=uart1 i2c0 spi-spidev analog-codec
 param_uart1_rtscts=1
 param_spidev_spi_bus=0
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/boot.cmd
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/boot.cmd
@ -0,0 +1,75 @@
 # DO NOT EDIT THIS FILE
 #
 # Please edit /boot/armbianEnv.txt to set supported parameters
 #
 setenv load_addr "0x44000000"
 setenv overlay_error "false"
 # default values
 setenv rootdev "/dev/mmcblk0p2"
 setenv verbosity "1"
 setenv console "both"
 setenv disp_mem_reserves "off"
 setenv disp_mode "1920x1080p60"
 setenv rootfstype "ext4"
 setenv docker_optimizations "on"
 # Print boot source
 itest.b *0x28 == 0x00 && echo "U-boot loaded from SD"
 itest.b *0x28 == 0x02 && echo "U-boot loaded from eMMC or secondary SD"
 itest.b *0x28 == 0x03 && echo "U-boot loaded from SPI"
 echo "Boot script loaded from ${devtype}"
 if test -e ${devtype} 0 ${prefix}armbianEnv.txt; then
 	load ${devtype} 0 ${load_addr} ${prefix}armbianEnv.txt
 	env import -t ${load_addr} ${filesize}
 fi
 if test "${logo}" = "disabled"; then setenv logo "logo.nologo"; fi
 if test "${console}" = "display" || test "${console}" = "both"; then setenv consoleargs "console=tty1"; fi
 if test "${console}" = "serial" || test "${console}" = "both"; then setenv consoleargs "${consoleargs} console=ttyS0,115200"; fi
 # get PARTUUID of first partition on SD/eMMC it was loaded from
 # mmc 0 is always mapped to device u-boot (2016.09+) was loaded from
 if test "${devtype}" = "mmc"; then part uuid mmc 0:1 partuuid; fi
 setenv bootargs "root=${rootdev} rootwait rootfstype=${rootfstype} ${consoleargs} hdmi.audio=EDID:0 disp.screen0_output_mode=${disp_mode} panic=10 consoleblank=0 loglevel=${verbosity} ubootpart=${partuuid} ubootsource=${devtype} ${extraargs} ${extraboardargs}"
 if test "${disp_mem_reserves}" = "off"; then setenv bootargs "${bootargs} sunxi_ve_mem_reserve=0 sunxi_g2d_mem_reserve=0 sunxi_fb_mem_reserve=16"; fi
 if test "${docker_optimizations}" = "on"; then setenv bootargs "${bootargs} cgroup_enable=memory swapaccount=1"; fi
 echo "Found mainline kernel configuration"
 load ${devtype} 0 ${fdt_addr_r} ${prefix}dtb/${fdtfile}
 fdt addr ${fdt_addr_r}
 fdt resize 65536
 for overlay_file in ${overlays}; do
 	if load ${devtype} 0 ${load_addr} ${prefix}dtb/overlay/${overlay_prefix}-${overlay_file}.dtbo; then
 		echo "Applying kernel provided DT overlay ${overlay_prefix}-${overlay_file}.dtbo"
 		fdt apply ${load_addr} || setenv overlay_error "true"
 	fi
 done
 for overlay_file in ${user_overlays}; do
 	if load ${devtype} 0 ${load_addr} ${prefix}overlay-user/${overlay_file}.dtbo; then
 		echo "Applying user provided DT overlay ${overlay_file}.dtbo"
 		fdt apply ${load_addr} || setenv overlay_error "true"
 	fi
 done
 if test "${overlay_error}" = "true"; then
 	echo "Error applying DT overlays, restoring original DT"
 	load ${devtype} 0 ${fdt_addr_r} ${prefix}dtb/${fdtfile}
 else
 	if load ${devtype} 0 ${load_addr} ${prefix}dtb/overlay/${overlay_prefix}-fixup.scr; then
 		echo "Applying kernel provided DT fixup script (${overlay_prefix}-fixup.scr)"
 		source ${load_addr}
 	fi
 	if test -e ${devtype} 0 ${prefix}fixup.scr; then
 		load ${devtype} 0 ${load_addr} ${prefix}fixup.scr
 		echo "Applying user provided fixup script (fixup.scr)"
 		source ${load_addr}
 	fi
 fi
 load ${devtype} 0 ${kernel_addr_r} ${prefix}uImage
 bootm ${kernel_addr_r} - ${fdt_addr_r}
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/emac-gmac-fixes.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/emac-gmac-fixes.patch
@ -0,0 +1,74 @@
 diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
 index a373319a2b..096510b787 100644
 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
 +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -24,7 +24,7 @@ void sdelay(unsigned long);
 void return_to_fel(uint32_t lr, uint32_t sp);
 /* Board / SoC level designware gmac init */
 -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
 +#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
 void eth_init_board(void);
 #else
 static inline void eth_init_board(void) {}
 diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
 index 43766e0ef4..34a2786f30 100644
 --- a/board/sunxi/Makefile
 +++ b/board/sunxi/Makefile
@@ -9,7 +9,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 obj-y	+= board.o
 -obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
 +obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 diff --git a/drivers/net/Makefile b/drivers/net/Makefile
 index aedb2cc90d..c5dd52bee2 100644
 --- a/drivers/net/Makefile
 +++ b/drivers/net/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_DNET) += dnet.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
 -obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
 +obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
 obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
 obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
 index 64a190059a..3e789c5bf0 100644
 --- a/include/configs/sunxi-common.h
 +++ b/include/configs/sunxi-common.h
@@ -285,13 +285,13 @@ extern int soft_i2c_gpio_scl;
 #endif /* CONFIG_VIDEO */
 /* Ethernet support */
 -#ifdef CONFIG_SUNXI_EMAC
 +#ifdef CONFIG_SUN4I_EMAC
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_PHYLIB
 #endif
 -#ifdef CONFIG_SUNXI_GMAC
 +#ifdef CONFIG_SUN7I_GMAC
 #define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
 index ed349b9e6b..4fc89ca8eb 100644
 --- a/scripts/config_whitelist.txt
 +++ b/scripts/config_whitelist.txt
@@ -2797,8 +2797,8 @@ CONFIG_STV0991_HZ
 CONFIG_STV0991_HZ_CLOCK
 CONFIG_ST_SMI
 CONFIG_SUNXI_AHCI
 -CONFIG_SUNXI_EMAC
 -CONFIG_SUNXI_GMAC
 +CONFIG_SUN4I_EMAC
 +CONFIG_SUN7I_GMAC
 CONFIG_SUNXI_GPIO
 CONFIG_SUNXI_MAX_FB_SIZE
 CONFIG_SUNXI_USB_PHYS
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/enable-DT-overlays-support.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/enable-DT-overlays-support.patch
@ -0,0 +1,13 @@
 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
 index 0ed36cded..822ebb812 100644
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
@@ -578,6 +578,8 @@ config ARCH_SUNXI
 	select CMD_GPIO
 	select CMD_MMC if MMC
 	select CMD_USB if DISTRO_DEFAULTS
 +	select OF_LIBFDT
 +	select OF_LIBFDT_OVERLAY
 	select DM
 	select DM_ETH
 	select DM_GPIO
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/fix-sunxi-gpio-driver.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/fix-sunxi-gpio-driver.patch
@ -0,0 +1,38 @@
 The sunxi GPIO driver is missing some compatible strings for recent
 SoCs. While most of the sunxi GPIO code seems to not rely on this (and
 so works anyway), the sunxi_name_to_gpio() function does and fails at
 the moment (for instance when resolving the MMC CD pin name).
 Add the compatible strings for the A64, H5 and V3s, which were missing
 from the list. This now covers all pinctrl nodes in our own DTs.
 Strictly speaking the V3s has only ports B, C, E, F and G, but I think
 the other SoCs have gaps in there as well and for the pin number
 computation this does not matter.
 Signed-off-by: Andre Przywara <andre.przywara at arm.com>
 ---
 drivers/gpio/sunxi_gpio.c | 4 ++++
 1 file changed, 4 insertions(+)
 diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
 index b47cc66..d20a7e7 100644
 --- a/drivers/gpio/sunxi_gpio.c
 +++ b/drivers/gpio/sunxi_gpio.c
@@ -353,12 +353,16 @@ static const struct udevice_id sunxi_gpio_ids[] = {
 	ID("allwinner,sun8i-a83t-pinctrl",	a_all),
 	ID("allwinner,sun8i-h3-pinctrl",	a_all),
 	ID("allwinner,sun8i-r40-pinctrl",	a_all),
 +	ID("allwinner,sun8i-v3s-pinctrl",	a_all),
 	ID("allwinner,sun9i-a80-pinctrl",	a_all),
 +	ID("allwinner,sun50i-a64-pinctrl",	a_all),
 +	ID("allwinner,sun50i-h5-pinctrl",	a_all),
 	ID("allwinner,sun6i-a31-r-pinctrl",	l_2),
 	ID("allwinner,sun8i-a23-r-pinctrl",	l_1),
 	ID("allwinner,sun8i-a83t-r-pinctrl",	l_1),
 	ID("allwinner,sun8i-h3-r-pinctrl",	l_1),
 	ID("allwinner,sun9i-a80-r-pinctrl",	l_3),
 +	ID("allwinner,sun50i-a64-r-pinctrl",	l_1),
 	{ }
 };
 -- 
 2.9.0
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-Fix-PLL1-setup-to-never-use-dividers.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-Fix-PLL1-setup-to-never-use-dividers.patch
@ -0,0 +1,33 @@
 From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
 From: Ondrej Jirman <megous@megous.com>
 Date: Tue, 20 Dec 2016 11:25:12 +0100
 Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
 Kernel would lower the divider on first CLK change and cause the
 lock up.
 ---
 arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)
 diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
 index 50fb302a19..91aa2a0478 100644
 --- a/arch/arm/mach-sunxi/clock_sun6i.c
 +++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
 	int k = 1;
 	int m = 1;
 -	if (clk > 1152000000) {
 -		k = 2;
 -	} else if (clk > 768000000) {
 +	if (clk >= 1368000000) {
 		k = 3;
 -		m = 2;
 +	} else if (clk >= 768000000) {
 +		k = 2;
 	}
 	/* Switch to 24MHz clock while changing PLL1 */
 -- 
 2.11.0
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-adjust-dram-frequency.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-adjust-dram-frequency.patch
@ -0,0 +1,65 @@
 diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
 index a72d506..2c49525 100644
 --- a/configs/orangepi_lite_defconfig
 +++ b/configs/orangepi_lite_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
 -CONFIG_DRAM_CLK=672
 +CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
 diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
 index 5a7aba1..3ba4009 100644
 --- a/configs/orangepi_one_defconfig
 +++ b/configs/orangepi_one_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
 -CONFIG_DRAM_CLK=672
 +CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
 index 2374f1d..579bc70 100644
 --- a/configs/orangepi_plus2e_defconfig
 +++ b/configs/orangepi_plus2e_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
 -CONFIG_DRAM_CLK=672
 +CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
 index f2ed941..e8219bb 100644
 --- a/configs/orangepi_plus_defconfig
 +++ b/configs/orangepi_plus_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN8I_H3=y
 -CONFIG_DRAM_CLK=672
 +CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
 index ac44937..0e761b6 100644
 --- a/configs/orangepi_zero_defconfig
 +++ b/configs/orangepi_zero_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_MACH_SUN8I_H3=y
 -CONFIG_DRAM_CLK=672
 +CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-enable-power-led.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-enable-power-led.patch
@ -0,0 +1,17 @@
 diff --git a/board/sunxi/board.c b/board/sunxi/board.c
 index 3cf3614..89cf7f5 100644
 --- a/board/sunxi/board.c
 +++ b/board/sunxi/board.c
@@ -478,6 +478,11 @@ void sunxi_board_init(void)
 	int power_failed = 0;
 	unsigned long ramsize;
 +#ifdef CONFIG_MACH_SUN8I_H3
 +	/* turn on power LED (PL10) on H3 boards */
 +	gpio_direction_output(SUNXI_GPL(10), 1);
 +#endif
 +
 #ifdef CONFIG_SY8106A_POWER
 	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
 #endif
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-set-safe-axi_apb-clock-dividers.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/h3-set-safe-axi_apb-clock-dividers.patch
@ -0,0 +1,42 @@
 diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
 index 15272c9..cedddc2 100644
 --- a/arch/arm/mach-sunxi/clock_sun6i.c
 +++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
 	sdelay(200);
 	/* Switch CPU to PLL1 */
 -	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 -	       ATB_DIV_2 << ATB_DIV_SHIFT |
 +	writel(AXI_DIV_4 << AXI_DIV_SHIFT |
 +	       ATB_DIV_4 << ATB_DIV_SHIFT |
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_axi_cfg);
 }
 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 index f2990db..b3a8575 100644
 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
 +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -180,6 +180,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
 #define CCM_PLL1_CTRL_P(n)		(((n) & 0x3) << 16)
 #define CCM_PLL1_CTRL_EN		(0x1 << 31)
 +#define CCM_PLL1_CTRL_LOCK		(0x1 << 28)
 #define CCM_PLL3_CTRL_M_SHIFT		0
 #define CCM_PLL3_CTRL_M_MASK		(0xf << CCM_PLL3_CTRL_M_SHIFT)
 diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
 index cedddc2..3fe9305 100644
 --- a/arch/arm/mach-sunxi/clock_sun6i.c
 +++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk)
 	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 -	sdelay(200);
 +
 +	while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
 +		;
 	/* Switch CPU to PLL1 */
 	writel(AXI_DIV_4 << AXI_DIV_SHIFT |
--- a/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/sun8i-set-machid.patch
+++ b/layers/meta-resin-allwinner/recipes-bsp/u-boot/u-boot_2017.07/sun8i-set-machid.patch
@ -0,0 +1,11 @@
 diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
 index a4c3fb69e..47ce2e9e6 100644
 --- a/include/configs/sun8i.h
 +++ b/include/configs/sun8i.h
@@ -30,4 +30,6 @@
  */
 #include <configs/sunxi-common.h>
 +#define CONFIG_MACH_TYPE	(0x1029)
 +
 #endif /* __CONFIG_H */
--- a/layers/meta-resin-allwinner/recipes-core/images/resin-image.bbappend
+++ b/layers/meta-resin-allwinner/recipes-core/images/resin-image.bbappend
@ -47,7 +47,7 @@ IMAGE_FSTYPES_append_nanopi-neo-air = " resinos-img"
 RESIN_IMAGE_BOOTLOADER_nanopi-neo-air = "u-boot"
 RESIN_BOOT_PARTITION_FILES_nanopi-neo-air = " \
    ${KERNEL_IMAGETYPE}${KERNEL_INITRAMFS}-${MACHINE}.bin:/${KERNEL_IMAGETYPE} \
-    uImage-sun8i-h3-nanopi-neo.dtb:/dtb/sun8i-h3-nanopi-neo.dtb \
+    uImage-sun8i-h3-nanopi-neo-air.dtb:/dtb/sun8i-h3-nanopi-neo-air.dtb \
    uImage-sun8i-h3-fixup.scr:/dtb/overlay/sun8i-h3-fixup.scr \
    uImage-sun8i-h3-analog-codec.dtbo:/dtb/overlay/sun8i-h3-analog-codec.dtbo \
    uImage-sun8i-h3-cir.dtbo:/dtb/overlay/sun8i-h3-cir.dtbo \
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-BergMicro-SPI-flashes.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-BergMicro-SPI-flashes.patch
@ -0,0 +1,18 @@
 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
 index d0fc165..4510c2d 100644
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -809,6 +809,13 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
 +	/* BergMicro Flashes */
 +	{ "bg25q80", INFO(0xe04014, 0, 64 * 1024,  16, SECT_4K) },
 +	{ "bg25q16", INFO(0xe04015, 0, 64 * 1024,  32, SECT_4K) },
 +	{ "bg25q32", INFO(0xe04016, 0, 64 * 1024,  64, SECT_4K) },
 +	{ "bg25q64", INFO(0xe04017, 0, 64 * 1024, 128, SECT_4K) },
 +	{ "bg25q128", INFO(0xe04018, 0, 64 * 1024, 256, SECT_4K) },
 +
 	/* EON -- en25xxx */
 	{ "en25f32",    INFO(0x1c3116, 0, 64 * 1024,   64, SECT_4K) },
 	{ "en25p32",    INFO(0x1c2016, 0, 64 * 1024,   64, 0) },
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-ad9834-dt-bindings.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-ad9834-dt-bindings.patch
@ -0,0 +1,174 @@
 diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c
 index 19216af1..e839d23a 100644
 --- a/drivers/staging/iio/frequency/ad9834.c
 +++ b/drivers/staging/iio/frequency/ad9834.c
@@ -13,11 +13,14 @@
 #include <linux/slab.h>
 #include <linux/sysfs.h>
 #include <linux/list.h>
 +#include <linux/of.h>
 +#include <linux/of_device.h>
 #include <linux/spi/spi.h>
 #include <linux/regulator/consumer.h>
 #include <linux/err.h>
 #include <linux/module.h>
 #include <asm/div64.h>
 +#include <linux/clk.h>
 #include <linux/iio/iio.h>
 #include <linux/iio/sysfs.h>
@@ -316,14 +319,81 @@ static const struct iio_info ad9833_info = {
 	.driver_module = THIS_MODULE,
 };
 +#if defined(CONFIG_OF)
 +static struct ad9834_platform_data *ad9834_parse_dt(struct spi_device *spi)
 +{
 +	struct ad9834_platform_data *pdata;
 +	struct device_node *np = spi->dev.of_node;
 +
 +	pdata = devm_kzalloc(&spi->dev, sizeof(*pdata), GFP_KERNEL);
 +	if (!pdata)
 +		return ERR_PTR(-ENOMEM);
 +
 +	pdata->freq0 = 134000;
 +	of_property_read_u32(np, "freq0", &pdata->freq0);
 +
 +	pdata->freq1 = 134000;
 +	of_property_read_u32(np, "freq1", &pdata->freq1);
 +
 +	pdata->phase0 = 0;
 +	of_property_read_u16(np, "phase0", &pdata->phase0);
 +
 +	pdata->phase1 = 0;
 +	of_property_read_u16(np, "phase1", &pdata->phase1);
 +
 +	pdata->en_div2 = of_property_read_bool(np, "en_div2");
 +	pdata->en_signbit_msb_out = of_property_read_bool(np,
 +					"en_signbit_msb_out");
 +
 +	return pdata;
 +}
 +#else
 +static struct ad9834_platform_data *ad9834_parse_dt(struct spi_device *spi)
 +{
 +	return NULL;
 +}
 +#endif
 +
 +static const struct of_device_id ad9834_of_match[] = {
 +	{
 +		.compatible	= "adi,ad9833",
 +		.data		= (void *)ID_AD9833,
 +	},
 +	{
 +		.compatible	= "adi,ad9834",
 +		.data		= (void *)ID_AD9834,
 +	},
 +	{
 +		.compatible	= "adi,ad9837",
 +		.data		= (void *)ID_AD9837,
 +	},
 +	{
 +		.compatible	= "adi,ad9838",
 +		.data		= (void *)ID_AD9838,
 +	},
 +	{ }
 +};
 +MODULE_DEVICE_TABLE(of, ad9834_of_match);
 +
 static int ad9834_probe(struct spi_device *spi)
 {
 -	struct ad9834_platform_data *pdata = dev_get_platdata(&spi->dev);
 +	const struct of_device_id *of_id = of_match_device(ad9834_of_match,
 +							   &spi->dev);
 +	struct ad9834_platform_data *pdata;
 	struct ad9834_state *st;
 	struct iio_dev *indio_dev;
 	struct regulator *reg;
 +	struct clk *clk = NULL;
 	int ret;
 +	if (!pdata && spi->dev.of_node) {
 +		pdata = ad9834_parse_dt(spi);
 +		if (IS_ERR(pdata))
 +			return PTR_ERR(pdata);
 +	} else {
 +		pdata = spi->dev.platform_data;
 +	}
 +
 	if (!pdata) {
 		dev_dbg(&spi->dev, "no platform data?\n");
 		return -ENODEV;
@@ -346,9 +416,30 @@ static int ad9834_probe(struct spi_device *spi)
 	}
 	spi_set_drvdata(spi, indio_dev);
 	st = iio_priv(indio_dev);
 -	st->mclk = pdata->mclk;
 +
 +	if (!pdata->mclk) {
 +		clk = devm_clk_get(&spi->dev, NULL);
 +		if (IS_ERR(clk))
 +			return -EPROBE_DEFER;
 +
 +		ret = clk_prepare_enable(clk);
 +		if (ret < 0)
 +			return ret;
 +	}
 +
 +	if (clk) {
 +		st->clk = clk;
 +		st->mclk = clk_get_rate(clk);
 +	} else {
 +		st->mclk = pdata->mclk;
 +	}
 +
 +	if (of_id)
 +		st->devid = (enum ad9834_supported_device_ids)of_id->data;
 +	else
 +		st->devid = spi_get_device_id(spi)->driver_data;
 +
 	st->spi = spi;
 -	st->devid = spi_get_device_id(spi)->driver_data;
 	st->reg = reg;
 	indio_dev->dev.parent = &spi->dev;
 	indio_dev->name = spi_get_device_id(spi)->name;
@@ -421,6 +512,9 @@ static int ad9834_probe(struct spi_device *spi)
 error_disable_reg:
 	regulator_disable(reg);
 +if (clk)
 +		clk_disable_unprepare(clk);
 +
 	return ret;
 }
@@ -431,6 +525,8 @@ static int ad9834_remove(struct spi_device *spi)
 	iio_device_unregister(indio_dev);
 	regulator_disable(st->reg);
 +if (st->clk)
 +		clk_disable_unprepare(st->clk);
 	return 0;
 }
@@ -447,6 +543,7 @@ MODULE_DEVICE_TABLE(spi, ad9834_id);
 static struct spi_driver ad9834_driver = {
 	.driver = {
 		.name	= "ad9834",
 +		.of_match_table = of_match_ptr(ad9834_of_match),
 	},
 	.probe		= ad9834_probe,
 	.remove		= ad9834_remove,
 diff --git a/drivers/staging/iio/frequency/ad9834.h b/drivers/staging/iio/frequency/ad9834.h
 index 40fdd5da..fd9cccf3 100644
 --- a/drivers/staging/iio/frequency/ad9834.h
 +++ b/drivers/staging/iio/frequency/ad9834.h
@@ -53,6 +53,7 @@
 struct ad9834_state {
 	struct spi_device		*spi;
 	struct regulator		*reg;
 +	struct clk				*clk;
 	unsigned int			mclk;
 	unsigned short			control;
 	unsigned short			devid;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-configfs-overlay-for-v4.11.x.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-configfs-overlay-for-v4.11.x.patch
@ -0,0 +1,360 @@
 diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
 index bc07ad3..e9da9cf 100644
 --- a/drivers/of/Kconfig
 +++ b/drivers/of/Kconfig
@@ -113,6 +113,13 @@ config OF_OVERLAY
 	  While this option is selected automatically when needed, you can
 	  enable it manually to improve device tree unit test coverage.
 +config OF_CONFIGFS
 +        bool "Device Tree Overlay ConfigFS interface"
 +        select CONFIGFS_FS
 +        depends on OF_OVERLAY
 +        help
 +          Enable a simple user-space driven DT overlay interface.
 +
 config OF_NUMA
 	bool
 diff --git a/drivers/of/Makefile b/drivers/of/Makefile
 index d7efd9d..a06cc35 100644
 --- a/drivers/of/Makefile
 +++ b/drivers/of/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
 obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
 obj-$(CONFIG_OF_RESOLVE)  += resolver.o
 obj-$(CONFIG_OF_OVERLAY) += overlay.o
 +obj-$(CONFIG_OF_CONFIGFS) += configfs.o
 obj-$(CONFIG_OF_NUMA) += of_numa.o
 obj-$(CONFIG_OF_UNITTEST) += unittest-data/
 diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
 new file mode 100644
 index 0000000..68f889d
 --- /dev/null
 +++ b/drivers/of/configfs.c
@@ -0,0 +1,311 @@
 +/*
 + * Configfs entries for device-tree
 + *
 + * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * as published by the Free Software Foundation; either version
 + * 2 of the License, or (at your option) any later version.
 + */
 +#include <linux/ctype.h>
 +#include <linux/cpu.h>
 +#include <linux/module.h>
 +#include <linux/of.h>
 +#include <linux/of_fdt.h>
 +#include <linux/spinlock.h>
 +#include <linux/slab.h>
 +#include <linux/proc_fs.h>
 +#include <linux/configfs.h>
 +#include <linux/types.h>
 +#include <linux/stat.h>
 +#include <linux/limits.h>
 +#include <linux/file.h>
 +#include <linux/vmalloc.h>
 +#include <linux/firmware.h>
 +#include <linux/sizes.h>
 +
 +#include "of_private.h"
 +
 +struct cfs_overlay_item {
 +	struct config_item	item;
 +
 +	char			path[PATH_MAX];
 +
 +	const struct firmware	*fw;
 +	struct device_node	*overlay;
 +	int			ov_id;
 +
 +	void			*dtbo;
 +	int			dtbo_size;
 +};
 +
 +static int create_overlay(struct cfs_overlay_item *overlay, void *blob)
 +{
 +	int err;
 +
 +	/* unflatten the tree */
 +	of_fdt_unflatten_tree(blob, NULL, &overlay->overlay);
 +	if (overlay->overlay == NULL) {
 +		pr_err("%s: failed to unflatten tree\n", __func__);
 +		err = -EINVAL;
 +		goto out_err;
 +	}
 +	pr_debug("%s: unflattened OK\n", __func__);
 +
 +	/* mark it as detached */
 +	of_node_set_flag(overlay->overlay, OF_DETACHED);
 +
 +	/* perform resolution */
 +	err = of_resolve_phandles(overlay->overlay);
 +	if (err != 0) {
 +		pr_err("%s: Failed to resolve tree\n", __func__);
 +		goto out_err;
 +	}
 +	pr_debug("%s: resolved OK\n", __func__);
 +
 +	err = of_overlay_create(overlay->overlay);
 +	if (err < 0) {
 +		pr_err("%s: Failed to create overlay (err=%d)\n",
 +				__func__, err);
 +		goto out_err;
 +	}
 +	overlay->ov_id = err;
 +
 +out_err:
 +	return err;
 +}
 +
 +static inline struct cfs_overlay_item *to_cfs_overlay_item(
 +		struct config_item *item)
 +{
 +	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
 +}
 +
 +static ssize_t cfs_overlay_item_path_show(struct config_item *item,
 +		char *page)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +	return sprintf(page, "%s\n", overlay->path);
 +}
 +
 +static ssize_t cfs_overlay_item_path_store(struct config_item *item,
 +		const char *page, size_t count)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +	const char *p = page;
 +	char *s;
 +	int err;
 +
 +	/* if it's set do not allow changes */
 +	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
 +		return -EPERM;
 +
 +	/* copy to path buffer (and make sure it's always zero terminated */
 +	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
 +	overlay->path[sizeof(overlay->path) - 1] = '\0';
 +
 +	/* strip trailing newlines */
 +	s = overlay->path + strlen(overlay->path);
 +	while (s > overlay->path && *--s == '\n')
 +		*s = '\0';
 +
 +	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
 +
 +	err = request_firmware(&overlay->fw, overlay->path, NULL);
 +	if (err != 0)
 +		goto out_err;
 +
 +	err = create_overlay(overlay, (void *)overlay->fw->data);
 +	if (err != 0)
 +		goto out_err;
 +
 +	return count;
 +
 +out_err:
 +
 +	release_firmware(overlay->fw);
 +	overlay->fw = NULL;
 +
 +	overlay->path[0] = '\0';
 +	return err;
 +}
 +
 +static ssize_t cfs_overlay_item_status_show(struct config_item *item,
 +		char *page)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +
 +	return sprintf(page, "%s\n",
 +			overlay->ov_id >= 0 ? "applied" : "unapplied");
 +}
 +
 +CONFIGFS_ATTR(cfs_overlay_item_, path);
 +CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
 +
 +static struct configfs_attribute *cfs_overlay_attrs[] = {
 +	&cfs_overlay_item_attr_path,
 +	&cfs_overlay_item_attr_status,
 +	NULL,
 +};
 +
 +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
 +		void *buf, size_t max_count)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +
 +	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
 +			buf, max_count);
 +
 +	if (overlay->dtbo == NULL)
 +		return 0;
 +
 +	/* copy if buffer provided */
 +	if (buf != NULL) {
 +		/* the buffer must be large enough */
 +		if (overlay->dtbo_size > max_count)
 +			return -ENOSPC;
 +
 +		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
 +	}
 +
 +	return overlay->dtbo_size;
 +}
 +
 +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
 +		const void *buf, size_t count)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +	int err;
 +
 +	/* if it's set do not allow changes */
 +	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
 +		return -EPERM;
 +
 +	/* copy the contents */
 +	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
 +	if (overlay->dtbo == NULL)
 +		return -ENOMEM;
 +
 +	overlay->dtbo_size = count;
 +
 +	err = create_overlay(overlay, overlay->dtbo);
 +	if (err != 0)
 +		goto out_err;
 +
 +	return count;
 +
 +out_err:
 +	kfree(overlay->dtbo);
 +	overlay->dtbo = NULL;
 +	overlay->dtbo_size = 0;
 +
 +	return err;
 +}
 +
 +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
 +
 +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
 +	&cfs_overlay_item_attr_dtbo,
 +	NULL,
 +};
 +
 +static void cfs_overlay_release(struct config_item *item)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +
 +	if (overlay->ov_id >= 0)
 +		of_overlay_destroy(overlay->ov_id);
 +	if (overlay->fw)
 +		release_firmware(overlay->fw);
 +	/* kfree with NULL is safe */
 +	kfree(overlay->dtbo);
 +	kfree(overlay);
 +}
 +
 +static struct configfs_item_operations cfs_overlay_item_ops = {
 +	.release	= cfs_overlay_release,
 +};
 +
 +static struct config_item_type cfs_overlay_type = {
 +	.ct_item_ops	= &cfs_overlay_item_ops,
 +	.ct_attrs	= cfs_overlay_attrs,
 +	.ct_bin_attrs	= cfs_overlay_bin_attrs,
 +	.ct_owner	= THIS_MODULE,
 +};
 +
 +static struct config_item *cfs_overlay_group_make_item(
 +		struct config_group *group, const char *name)
 +{
 +	struct cfs_overlay_item *overlay;
 +
 +	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
 +	if (!overlay)
 +		return ERR_PTR(-ENOMEM);
 +	overlay->ov_id = -1;
 +
 +	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
 +	return &overlay->item;
 +}
 +
 +static void cfs_overlay_group_drop_item(struct config_group *group,
 +		struct config_item *item)
 +{
 +	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 +
 +	config_item_put(&overlay->item);
 +}
 +
 +static struct configfs_group_operations overlays_ops = {
 +	.make_item	= cfs_overlay_group_make_item,
 +	.drop_item	= cfs_overlay_group_drop_item,
 +};
 +
 +static struct config_item_type overlays_type = {
 +	.ct_group_ops   = &overlays_ops,
 +	.ct_owner       = THIS_MODULE,
 +};
 +
 +static struct configfs_group_operations of_cfs_ops = {
 +	/* empty - we don't allow anything to be created */
 +};
 +
 +static struct config_item_type of_cfs_type = {
 +	.ct_group_ops   = &of_cfs_ops,
 +	.ct_owner       = THIS_MODULE,
 +};
 +
 +struct config_group of_cfs_overlay_group;
 +
 +static struct configfs_subsystem of_cfs_subsys = {
 +	.su_group = {
 +		.cg_item = {
 +			.ci_namebuf = "device-tree",
 +			.ci_type = &of_cfs_type,
 +		},
 +	},
 +	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
 +};
 +
 +static int __init of_cfs_init(void)
 +{
 +	int ret;
 +
 +	pr_info("%s\n", __func__);
 +
 +	config_group_init(&of_cfs_subsys.su_group);
 +	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
 +			&overlays_type);
 +	configfs_add_default_group(&of_cfs_overlay_group,
 +			&of_cfs_subsys.su_group);
 +
 +	ret = configfs_register_subsystem(&of_cfs_subsys);
 +	if (ret != 0) {
 +		pr_err("%s: failed to register subsys\n", __func__);
 +		goto out;
 +	}
 +	pr_info("%s: OK\n", __func__);
 +out:
 +	return ret;
 +}
 +late_initcall(of_cfs_init);
 diff --git a/drivers/of/fdt_address.c b/drivers/of/fdt_address.c
 index dca8f9b..ec7e167 100644
 --- a/drivers/of/fdt_address.c
 +++ b/drivers/of/fdt_address.c
@@ -161,7 +161,7 @@ static int __init fdt_translate_one(const void *blob, int parent,
  * that can be mapped to a cpu physical address). This is not really specified
  * that way, but this is traditionally the way IBM at least do things
  */
 -static u64 __init fdt_translate_address(const void *blob, int node_offset)
 +u64 __init fdt_translate_address(const void *blob, int node_offset)
 {
 	int parent, len;
 	const struct of_bus *bus, *pbus;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-dvfs-emac-nanopi.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-dvfs-emac-nanopi.patch
@ -0,0 +1,103 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
 index 2216e68d..143ebc06 100644
 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -48,6 +48,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 +#include <dt-bindings/thermal/thermal.h>
 / {
 	aliases {
@@ -88,12 +89,90 @@
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
 		};
 	};
 +
 +	vdd_cpux: gpio-regulator {
 +		compatible = "regulator-gpio";
 +		regulator-name = "vdd-cpux";
 +		regulator-type = "voltage";
 +		regulator-boot-on;
 +		regulator-always-on;
 +		regulator-min-microvolt = <1100000>;
 +		regulator-max-microvolt = <1300000>;
 +		regulator-ramp-delay = <50>; /* 4ms */
 +		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
 +		gpios-states = <0x1>;
 +		states = <1100000 0x0
 +			  1300000 0x1>;
 +	};
 +};
 +
 +&cpu0 {
 +	operating-points = <
 +		1008000	1300000
 +		816000	1100000
 +		624000	1100000
 +		480000	1100000
 +		312000	1100000
 +		240000	1100000
 +		120000	1100000
 +		>;
 +	#cooling-cells = <2>;
 +	cooling-min-level = <0>;
 +	cooling-max-level = <6>;
 +	cpu0-supply = <&vdd_cpux>;
 +};
 +
 +&cpu_thermal {
 +	trips {
 +		cpu_warm: cpu_warm {
 +			temperature = <65000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_hot: cpu_hot {
 +			temperature = <75000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_very_hot: cpu_very_hot {
 +			temperature = <90000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_crit: cpu_crit {
 +			temperature = <105000>;
 +			hysteresis = <2000>;
 +			type = "critical";
 +		};
 +	};
 +
 +	cooling-maps {
 +		cpu_warm_limit_cpu {
 +			trip = <&cpu_warm>;
 +			cooling-device = <&cpu0 THERMAL_NO_LIMIT 1>;
 +		};
 +		cpu_hot_limit_cpu {
 +			trip = <&cpu_hot>;
 +			cooling-device = <&cpu0 2 3>;
 +		};
 +		cpu_very_hot_limit_cpu {
 +			trip = <&cpu_very_hot>;
 +			cooling-device = <&cpu0 5 THERMAL_NO_LIMIT>;
 +		};
 +	};
 };
 &ehci3 {
 	status = "okay";
 };
 +&emac {
 +	phy-handle = <&int_mii_phy>;
 +	phy-mode = "mii";
 +	allwinner,leds-active-low;
 +	status = "okay";
 +};
 +
 &mmc0 {
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-emac-pwr-en-orangepi-plus2e.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-emac-pwr-en-orangepi-plus2e.patch
@ -0,0 +1,36 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 index 5851a47a..c2f1baa2 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
@@ -50,4 +50,31 @@
 / {
 	model = "Xunlong Orange Pi Plus 2E";
 	compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3";
 +
 +	reg_gmac_3v3: gmac-3v3 {
 +		compatible = "regulator-fixed";
 +		regulator-name = "gmac-3v3";
 +		regulator-min-microvolt = <3300000>;
 +		regulator-max-microvolt = <3300000>;
 +		startup-delay-us = <100000>;
 +		enable-active-high;
 +		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
 +	};
 +};
 +
 +&mdio {
 +	ext_rgmii_phy: ethernet-phy@1 {
 +		reg = <0>;
 +	};
 +};
 +
 +&emac {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&emac_rgmii_pins>;
 +	phy-supply = <&reg_gmac_3v3>;
 +	phy-handle = <&ext_rgmii_phy>;
 +	phy-mode = "rgmii";
 +
 +	allwinner,leds-active-low;
 +	status = "okay";
 };
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-fix-dts-for-opi-zero-emac.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-fix-dts-for-opi-zero-emac.patch
@ -0,0 +1,20 @@
 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
 index e94f196..69a4840 100644
 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
 +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -104,6 +104,15 @@
 	status = "okay";
 };
 +&emac {
 +	pinctrl-names = "default";
 +	phy-supply = <&reg_vcc3v3>;
 +	phy-handle = <&int_mii_phy>;
 +	phy-mode = "mii";
 +	allwinner,leds-active-low;
 +	status = "okay";
 +};
 +
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-h3-overlays.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-h3-overlays.patch
@ -0,0 +1,999 @@
 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
 index 01180849..81523d5a 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
@@ -1016,4 +1017,7 @@ dtstree		:= $(srctree)/$(src)
 dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
 always		:= $(dtb-y)
 +subdir-y	:= overlay
 clean-files	:= *.dtb
 +
 +dts-dirs += overlay
 diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
 new file mode 100644
 index 00000000..f9ca2574
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,28 @@
 +dtbo-$(CONFIG_MACH_SUN8I) += \
 +	sun8i-h3-analog-codec.dtbo \
 +	sun8i-h3-cir.dtbo \
 +	sun8i-h3-i2c0.dtbo \
 +	sun8i-h3-i2c1.dtbo \
 +	sun8i-h3-i2c2.dtbo \
 +	sun8i-h3-pps-gpio.dtbo \
 +	sun8i-h3-pwm.dtbo \
 +	sun8i-h3-spdif-out.dtbo \
 +	sun8i-h3-spi-add-cs1.dtbo \
 +	sun8i-h3-spi-jedec-nor.dtbo \
 +	sun8i-h3-spi-spidev.dtbo \
 +	sun8i-h3-uart1.dtbo \
 +	sun8i-h3-uart2.dtbo \
 +	sun8i-h3-uart3.dtbo \
 +	sun8i-h3-usbhost0.dtbo \
 +	sun8i-h3-usbhost2.dtbo \
 +	sun8i-h3-usbhost3.dtbo \
 +	sun8i-h3-w1-gpio.dtbo
 +
 +scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
 +
 +dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
 +
 +targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
 +
 +always		:= $(dtbo-y) $(scr-y) $(dtbotxt-y)
 +clean-files	:= *.dtbo *.scr
 diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
 new file mode 100644
 index 00000000..0ae207a1
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
@@ -0,0 +1,245 @@
 +This document describes overlays provided in the kernel packages
 +For generic Armbian overlays documentation please see
 +https://docs.armbian.com/User-Guide_Allwinner_overlays/
 +
 +### Platform:
 +
 +sun8i-h3 (Allwinner H3)
 +
 +### Platform details:
 +
 +Supported pin banks: PA, PC, PD, PG
 +
 +Both SPI controllers have only one hardware CS pin exposed,
 +adding fixed software (GPIO) chip selects is possible with a separate overlay
 +
 +### Provided overlays:
 +
 +- analog-codec
 +- cir
 +- i2c0
 +- i2c1
 +- i2c2
 +- pps-gpio
 +- pwm
 +- spdif-out
 +- spi-add-cs1
 +- spi-jedec-nor
 +- spi-spidev
 +- uart1
 +- uart2
 +- uart3
 +- usbhost0
 +- usbhost2
 +- usbhost3
 +- w1-gpio
 +
 +### Overlay details:
 +
 +### analog-codec
 +
 +Activates SoC analog codec driver that provides Line Out and Mic In
 +functionality
 +
 +### cir
 +
 +Activates CIR (Infrared remote) receiver
 +
 +CIR pin: PL11
 +
 +### i2c0
 +
 +Activates TWI/I2C bus 0
 +
 +I2C0 pins (SCL, SDA): PA11, PA12
 +
 +### i2c1
 +
 +Activates TWI/I2C bus 1
 +
 +I2C1 pins (SCL, SDA): PA18, PA19
 +
 +### i2c2
 +
 +Activates TWI/I2C bus 2
 +
 +I2C2 pins (SCL, SDA): PE12, PE13
 +
 +On most board this bus is wired to Camera (CSI) socket
 +
 +### pps-gpio
 +
 +Activates pulse-per-second GPIO client
 +
 +Parameters:
 +
 +param_pps_pin (pin)
 +	Pin PPS source is connected to
 +	Optional
 +	Default: PD14
 +
 +param_pps_falling_edge (bool)
 +	Assert by falling edge
 +	Optional
 +	Default: 0
 +	When set (to 1), assert is indicated by a falling edge
 +		(instead of by a rising edge)
 +
 +### pwm
 +
 +Activates hardware PWM controller
 +
 +PWM pin: PA5
 +
 +Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
 +UART0 and kernel console on ttyS0 will be disabled
 +
 +### spdif-out
 +
 +Activates SPDIF/Toslink audio output
 +
 +SPDIF pin: PA17
 +
 +### spi-add-cs1
 +
 +Adds support for using SPI chip select 1 with GPIO for both SPI controllers
 +Respective GPIO will be claimed only if controller is enabled by another
 +overlay
 +This overlay is required for using chip select 1 with other SPI overlays
 +Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
 +it can be changed by using an edited copy of this overlay
 +A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
 +
 +SPI 0 pins (CS1): PA21
 +SPI 1 pins (CS1): PA10
 +
 +### spi-jedec-nor
 +
 +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
 +supported by the kernel SPI NOR driver
 +
 +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
 +
 +Parameters:
 +
 +param_spinor_spi_bus (int)
 +	SPI bus to activate SPI NOR flash support on
 +	Required
 +	Supported values: 0, 1
 +
 +param_spinor_spi_cs (int)
 +	SPI chip select number
 +	Optional
 +	Default: 0
 +	Supported values: 0, 1
 +	Using chip select 1 requires using "spi-add-cs1" overlay
 +
 +param_spinor_max_freq (int)
 +	Maximum SPI frequency
 +	Optional
 +	Default: 1000000
 +	Range: 3000 - 100000000
 +
 +### spi-spidev
 +
 +Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
 +where X is the bus number and Y is the CS number
 +
 +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
 +
 +Parameters:
 +
 +param_spidev_spi_bus (int)
 +	SPI bus to activate SPIdev support on
 +	Required
 +	Supported values: 0, 1
 +
 +param_spidev_spi_cs (int)
 +	SPI chip select number
 +	Optional
 +	Default: 0
 +	Supported values: 0, 1
 +	Using chip select 1 requires using "spi-add-cs1" overlay
 +
 +param_spidev_max_freq (int)
 +	Maximum SPIdev frequency
 +	Optional
 +	Default: 1000000
 +	Range: 3000 - 100000000
 +
 +### uart1
 +
 +Activates serial port 1 (/dev/ttyS1)
 +
 +UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
 +
 +Parameters:
 +
 +param_uart1_rtscts (bool)
 +	Enable RTS and CTS pins
 +	Optional
 +	Default: 0
 +	Set to 1 to enable
 +
 +### uart2
 +
 +Activates serial port 2 (/dev/ttyS2)
 +
 +UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
 +
 +Parameters:
 +
 +param_uart2_rtscts (bool)
 +	Enable RTS and CTS pins
 +	Optional
 +	Default: 0
 +	Set to 1 to enable CTS and RTS pins
 +
 +### uart3
 +
 +Activates serial port 3 (/dev/ttyS3)
 +
 +UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
 +
 +Parameters:
 +
 +param_uart3_rtscts (bool)
 +	Enable RTS and CTS pins
 +	Optional
 +	Default: 0
 +	Set to 1 to enable CTS and RTS pins
 +
 +### usbhost0
 +
 +Activates USB host controller 0
 +
 +### usbhost2
 +
 +Activates USB host controller 2
 +
 +### usbhost3
 +
 +Activates USB host controller 3
 +
 +### w1-gpio
 +
 +Activates 1-Wire GPIO master
 +Requires an external pull-up resistor on the data pin
 +or enabling the internal pull-up
 +
 +Parameters:
 +
 +param_w1_pin (pin)
 +	Data pin for 1-Wire master
 +	Optional
 +	Default: PD14
 +
 +param_w1_pin_int_pullup (bool)
 +	Enable internal pull-up for the data pin
 +	Optional
 +	Default: 0
 +	Set to 1 to enable the pull-up
 +	This option should not be used with multiple devices, parasite power setup
 +		or long wires -	please use external pull-up resistor instead
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
 new file mode 100644
 index 00000000..36dbc31a
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
@@ -0,0 +1,17 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&codec>;
 +		__overlay__ {
 +			allwinner,audio-routing =
 +				"Line Out", "LINEOUT",
 +				"MIC1", "Mic",
 +				"Mic",  "MBIAS";
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
 new file mode 100644
 index 00000000..9b62fd2b
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
@@ -0,0 +1,15 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&ir>;
 +		__overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&ir_pins_a>;
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
 new file mode 100644
 index 00000000..744889c6
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
@@ -0,0 +1,110 @@
 +# overlays fixup script
 +# implements (or rather substitutes) overlay arguments functionality
 +# using u-boot scripting, environment variables and "fdt" command
 +
 +# setexpr test_var ${tmp_bank} - A
 +# works only for hex numbers (A-F)
 +
 +setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
 +setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
 +test "${tmp_bank}" = "A" && setenv tmp_bank 0;
 +test "${tmp_bank}" = "C" && setenv tmp_bank 2;
 +test "${tmp_bank}" = "D" && setenv tmp_bank 3;
 +test "${tmp_bank}" = "G" && setenv tmp_bank 6'
 +
 +if test -n "${param_spinor_spi_bus}"; then
 +	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
 +	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
 +	fdt set /soc/${tmp_spi_path} status "okay"
 +	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
 +	if test -n "${param_spinor_max_freq}"; then
 +		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
 +	fi
 +	if test "${param_spinor_spi_cs}" = "1"; then
 +		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
 +	fi
 +	env delete tmp_spi_path
 +fi
 +
 +if test -n "${param_spidev_spi_bus}"; then
 +	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
 +	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
 +	fdt set /soc/${tmp_spi_path} status "okay"
 +	fdt set /soc/${tmp_spi_path}/spidev status "okay"
 +	if test -n "${param_spidev_max_freq}"; then
 +		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
 +	fi
 +	if test "${param_spidev_spi_cs}" = "1"; then
 +		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
 +	fi
 +	env delete tmp_spi_path
 +fi
 +
 +if test -n "${param_pps_pin}"; then
 +	setenv tmp_bank "${param_pps_pin}"
 +	setenv tmp_pin "${param_pps_pin}"
 +	run decompose_pin
 +	fdt set /soc/pinctrl@01c20800/pps_pins pins "${param_pps_pin}"
 +	fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
 +	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
 +	env delete tmp_pin tmp_bank tmp_phandle
 +fi
 +
 +if test "${param_pps_falling_edge}" = "1"; then
 +	fdt set /pps@0 assert-falling-edge
 +fi
 +
 +for f in ${overlays}; do
 +	if test "${f}" = "pwm"; then
 +		setenv bootargs_new ""
 +		for arg in ${bootargs}; do
 +			if test "${arg}" = "console=ttyS0,115200"; then
 +				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
 +			else
 +				setenv bootargs_new "${bootargs_new} ${arg}"
 +			fi
 +		done
 +		setenv bootargs "${bootargs_new}"
 +	fi
 +done
 +
 +if test -n "${param_w1_pin}"; then
 +	setenv tmp_bank "${param_w1_pin}"
 +	setenv tmp_pin "${param_w1_pin}"
 +	run decompose_pin
 +	fdt set /soc/pinctrl@01c20800/w1_pins pins "${param_w1_pin}"
 +	fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
 +	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
 +	env delete tmp_pin tmp_bank tmp_phandle
 +fi
 +
 +if test "${param_w1_pin_int_pullup}" = "1"; then
 +	fdt set /soc/pinctrl@01c20800/w1_pins bias-pull-up
 +fi
 +
 +if test "${param_uart1_rtscts}" = "1"; then
 +	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart1 phandle
 +	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart1_rts_cts phandle
 +	fdt set /soc/serial@01c28400 pinctrl-names "default" "default"
 +	fdt set /soc/serial@01c28400 pinctrl-0 "<${tmp_phandle1}>"
 +	fdt set /soc/serial@01c28400 pinctrl-1 "<${tmp_phandle2}>"
 +	env delete tmp_phandle1 tmp_phandle2
 +fi
 +
 +if test "${param_uart2_rtscts}" = "1"; then
 +	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart2 phandle
 +	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart2_rts_cts phandle
 +	fdt set /soc/serial@01c28800 pinctrl-names "default" "default"
 +	fdt set /soc/serial@01c28800 pinctrl-0 "<${tmp_phandle1}>"
 +	fdt set /soc/serial@01c28800 pinctrl-1 "<${tmp_phandle2}>"
 +	env delete tmp_phandle1 tmp_phandle2
 +fi
 +
 +if test "${param_uart3_rtscts}" = "1"; then
 +	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart3 phandle
 +	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart3_rts_cts phandle
 +	fdt set /soc/serial@01c28c00 pinctrl-names "default" "default"
 +	fdt set /soc/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>"
 +	fdt set /soc/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>"
 +	env delete tmp_phandle1 tmp_phandle2
 +fi
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
 new file mode 100644
 index 00000000..b457ac71
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			i2c0 = "/soc/i2c@01c2ac00";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&i2c0>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
 new file mode 100644
 index 00000000..fd0928a1
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			i2c1 = "/soc/i2c@01c2b000";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&i2c1>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
 new file mode 100644
 index 00000000..25b75b71
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			i2c2 = "/soc/i2c@01c2b400";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&i2c2>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
 new file mode 100644
 index 00000000..16a737b0
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
@@ -0,0 +1,29 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&pio>;
 +		__overlay__ {
 +			pps_pins: pps_pins {
 +				pins = "PD14";
 +				function = "gpio_in";
 +			};
 +		};
 +	};
 +
 +	fragment@1 {
 +		target-path = "/";
 +		__overlay__ {
 +			pps@0 {
 +				compatible = "pps-gpio";
 +				pinctrl-names = "default";
 +				pinctrl-0 = <&pps_pins>;
 +				gpios = <&pio 3 14 0>; /* PD14 */
 +				status = "okay";
 +			};
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
 new file mode 100644
 index 00000000..ed3b8e60
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
@@ -0,0 +1,39 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/chosen";
 +		__overlay__ {
 +			/delete-property/ stdout-path;
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&uart0>;
 +		__overlay__ {
 +			status = "disabled";
 +		};
 +	};
 +
 +	fragment@2 {
 +		target = <&pio>;
 +		__overlay__ {
 +			pwm0_pin: pwm0 {
 +				pins = "PA5";
 +				function = "pwm0";
 +			};
 +		};
 +	};
 +
 +	fragment@3 {
 +		target = <&pwm>;
 +		__overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&pwm0_pin>;
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
 new file mode 100644
 index 00000000..c7c01411
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
@@ -0,0 +1,38 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&spdif>;
 +		__overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&spdif_tx_pins_a>;
 +			status = "okay";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target-path = "/";
 +		__overlay__ {
 +			sound {
 +				compatible = "simple-audio-card";
 +				simple-audio-card,name = "On-board SPDIF";
 +
 +				simple-audio-card,cpu {
 +					sound-dai = <&spdif>;
 +				};
 +
 +				simple-audio-card,codec {
 +					sound-dai = <&spdif_out>;
 +				};
 +			};
 +
 +			spdif_out: spdif-out {
 +				#sound-dai-cells = <0>;
 +				compatible = "linux,spdif-dit";
 +			};
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
 new file mode 100644
 index 00000000..bd8e2561
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
@@ -0,0 +1,41 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&pio>;
 +		__overlay__ {
 +			spi0_cs1: spi0_cs1 {
 +				pins = "PA21";
 +				function = "gpio_out";
 +				output-high;
 +			};
 +
 +			spi1_cs1: spi1_cs1 {
 +				pins = "PA10";
 +				function = "gpio_out";
 +				output-high;
 +			};
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&spi0>;
 +		__overlay__ {
 +			pinctrl-names = "default", "default";
 +			pinctrl-1 = <&spi0_cs1>;
 +			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
 +		};
 +	};
 +
 +	fragment@2 {
 +		target = <&spi1>;
 +		__overlay__ {
 +			pinctrl-names = "default", "default";
 +			pinctrl-1 = <&spi1_cs1>;
 +			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
 new file mode 100644
 index 00000000..ad22a71a
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
@@ -0,0 +1,42 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			spi0 = "/soc/spi@01c68000";
 +			spi1 = "/soc/spi@01c69000";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&spi0>;
 +		__overlay__ {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			spiflash {
 +				compatible = "jedec,spi-nor";
 +				reg = <0>;
 +				spi-max-frequency = <1000000>;
 +				status = "disabled";
 +			};
 +		};
 +	};
 +
 +	fragment@2 {
 +		target = <&spi1>;
 +		__overlay__ {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			spiflash {
 +				compatible = "jedec,spi-nor";
 +				reg = <0>;
 +				spi-max-frequency = <1000000>;
 +				status = "disabled";
 +			};
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
 new file mode 100644
 index 00000000..180979e0
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
@@ -0,0 +1,42 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			spi0 = "/soc/spi@01c68000";
 +			spi1 = "/soc/spi@01c69000";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&spi0>;
 +		__overlay__ {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			spidev {
 +				compatible = "spidev";
 +				status = "disabled";
 +				reg = <0>;
 +				spi-max-frequency = <1000000>;
 +			};
 +		};
 +	};
 +
 +	fragment@2 {
 +		target = <&spi1>;
 +		__overlay__ {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			spidev {
 +				compatible = "spidev";
 +				status = "disabled";
 +				reg = <0>;
 +				spi-max-frequency = <1000000>;
 +			};
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
 new file mode 100644
 index 00000000..8a4f7e49
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
@@ -0,0 +1,22 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			serial1 = "/soc/serial@01c28400";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&uart1>;
 +		 __overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&uart1_pins>;
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
 new file mode 100644
 index 00000000..499a1b49
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
@@ -0,0 +1,22 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			serial2 = "/soc/serial@01c28800";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&uart2>;
 +		 __overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&uart2_pins>;
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
 new file mode 100644
 index 00000000..b5734c5b
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
@@ -0,0 +1,22 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target-path = "/aliases";
 +		__overlay__ {
 +			serial3 = "/soc/serial@01c28c00";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&uart3>;
 +		 __overlay__ {
 +			pinctrl-names = "default";
 +			pinctrl-0 = <&uart3_pins>;
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
 new file mode 100644
 index 00000000..ff1d82fd
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&ehci0>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&ohci0>;
 +		 __overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
 new file mode 100644
 index 00000000..bf0c4f59
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&ehci2>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&ohci2>;
 +		 __overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
 new file mode 100644
 index 00000000..f737075b
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
@@ -0,0 +1,20 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&ehci3>;
 +		__overlay__ {
 +			status = "okay";
 +		};
 +	};
 +
 +	fragment@1 {
 +		target = <&ohci3>;
 +		 __overlay__ {
 +			status = "okay";
 +		};
 +	};
 +};
 diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
 new file mode 100644
 index 00000000..f4ccb7fb
 --- /dev/null
 +++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
@@ -0,0 +1,29 @@
 +/dts-v1/;
 +/plugin/;
 +
 +/ {
 +	compatible = "allwinner,sun8i-h3";
 +
 +	fragment@0 {
 +		target = <&pio>;
 +		__overlay__ {
 +			w1_pins: w1_pins {
 +				pins = "PD14";
 +				function = "gpio_in";
 +			};
 +		};
 +	};
 +
 +	fragment@1 {
 +		target-path = "/";
 +		__overlay__ {
 +			onewire@0 {
 +				compatible = "w1-gpio";
 +				pinctrl-names = "default";
 +				pinctrl-0 = <&w1_pins>;
 +				gpios = <&pio 3 14 0>; /* PD14 */
 +				status = "okay";
 +			};
 +		};
 +	};
 +};
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-h3-simplefb.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-h3-simplefb.patch
@ -0,0 +1,37 @@
 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 index c3e22263..b5845ad8 100644
 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -49,6 +49,32 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 +        chosen {
 +                #address-cells = <1>;
 +                #size-cells = <1>;
 +                ranges;
 +
 +                simplefb_hdmi: framebuffer@0 {
 +                        compatible = "allwinner,simple-framebuffer",
 +                                     "simple-framebuffer";
 +                        allwinner,pipeline = "mixer0-lcd0-hdmi";
 +                        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_BUS_DE>,
 +                                 <&ccu CLK_BUS_HDMI>, <&ccu CLK_DE>,
 +                                 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
 +                        status = "disabled";
 +                };
 +
 +                simplefb_tv: framebuffer@1 {
 +                        compatible = "allwinner,simple-framebuffer",
 +                                     "simple-framebuffer";
 +                        allwinner,pipeline = "de0-lcd1-tve0";
 +                        clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_BUS_DE>,
 +                                 <&ccu CLK_BUS_TVE>, <&ccu CLK_DE>,
 +                                 <&ccu CLK_TCON0>, <&ccu CLK_TVE>;
 +                        status = "disabled";
 +                };
 +        };
 +
 	clocks {
 		#address-cells = <1>;
 		#size-cells = <1>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-nanopi-neoair.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-nanopi-neoair.patch
@ -0,0 +1,112 @@
 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
 old mode 100644
 new mode 100755
 index 81523d5..6f8b2cb
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
@@ -868,6 +868,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-h3-beelink-x2.dtb \
 	sun8i-h3-nanopi-m1.dtb	\
 	sun8i-h3-nanopi-neo.dtb \
 +	sun8i-h3-nanopi-neo-air.dtb \
 	sun8i-h3-orangepi-2.dtb \
 	sun8i-h3-orangepi-lite.dtb \
 	sun8i-h3-orangepi-one.dtb \
 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
 new file mode 100755
 index 0000000..9160d42
 --- /dev/null
 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -0,0 +1,92 @@
 +/*
 + * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
 + *
 + * This file is dual-licensed: you can use it either under the terms
 + * of the GPL or the X11 license, at your option. Note that this dual
 + * licensing only applies to this file, and not this project as a
 + * whole.
 + *
 + *  a) This file is free software; you can redistribute it and/or
 + *     modify it under the terms of the GNU General Public License as
 + *     published by the Free Software Foundation; either version 2 of the
 + *     License, or (at your option) any later version.
 + *
 + *     This file is distributed in the hope that it will be useful,
 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + *     GNU General Public License for more details.
 + *
 + * Or, alternatively,
 + *
 + *  b) Permission is hereby granted, free of charge, to any person
 + *     obtaining a copy of this software and associated documentation
 + *     files (the "Software"), to deal in the Software without
 + *     restriction, including without limitation the rights to use,
 + *     copy, modify, merge, publish, distribute, sublicense, and/or
 + *     sell copies of the Software, and to permit persons to whom the
 + *     Software is furnished to do so, subject to the following
 + *     conditions:
 + *
 + *     The above copyright notice and this permission notice shall be
 + *     included in all copies or substantial portions of the Software.
 + *
 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 + *     OTHER DEALINGS IN THE SOFTWARE.
 + */
 +
 +#include "sun8i-h3-nanopi.dtsi"
 +
 +/ {
 +	model = "FriendlyARM NanoPi NEO";
 +	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
 +
 + 	aliases {
 +		serial3 = &uart3;
 + 	};
 +
 +	wifi_pwrseq: wifi_pwrseq {
 +		compatible = "mmc-pwrseq-simple";
 +		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
 +	};
 +};
 +
 +&mmc1 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&mmc1_pins_a>;
 +	vmmc-supply = <&reg_vcc3v3>;
 +	vqmmc-supply = <&reg_vcc3v3>;
 +	mmc-pwrseq = <&wifi_pwrseq>;
 +	bus-width = <4>;
 +	non-removable;
 +	status = "okay";
 +
 +	brcmf: bcrmf@1 {
 +		reg = <1>;
 +		compatible = "brcm,bcm4329-fmac";
 +		interrupt-parent = <&pio>;
 +		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
 +		interrupt-names = "host-wake";
 +	};
 +};
 +
 +&mmc2 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&mmc2_8bit_pins>;
 +	vmmc-supply = <&reg_vcc3v3>;
 +	vqmmc-supply = <&reg_vcc3v3>;
 +	bus-width = <8>;
 +	non-removable;
 +	status = "okay";
 +};
 +
 +&uart3 { /* Connected to AP6212 on Neo Air */
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&uart3_pins>;
 +	status = "okay";
 +};
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-orangepi-zeroplus.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-orangepi-zeroplus.patch
@ -0,0 +1,126 @@
 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
 index 01180849..99c1809a 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
@@ -875,6 +875,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
 +	sun8i-h3-orangepi-zeroplus.dtb \
 	sun8i-r16-parrot.dtb \
 	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zeroplus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zeroplus.dts
 new file mode 100644
 index 00000000..f89d1207
 --- /dev/null
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zeroplus.dts
@@ -0,0 +1,108 @@
 +
 +#include "sun8i-h2-plus-orangepi-zero.dts"
 +
 +/ {
 +	model = "Xunlong Orange Pi Zero Plus";
 +	compatible = "xunlong,orangepi-zeroplus", "allwinner,sun8i-h3";
 +
 +	aliases {
 +		ethernet1 = &brcmf;
 +	};
 +
 +	/delete-node/ reg_vcc_wifi;
 +
 +	wifi_pwrseq: wifi_pwrseq {
 +		compatible = "mmc-pwrseq-simple";
 +		pinctrl-names = "default";
 +		pinctrl-0 = <&wifi_pwrseq_pin_orangepi>;
 +		reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>;
 +		post-power-on-delay-ms = <50>;
 +	};
 +
 +	reg_usb1_vbus: usb1-vbus {
 +		compatible = "regulator-fixed";
 +		pinctrl-names = "default";
 +		pinctrl-0 = <&usb1_vbus_pin_a>;
 +		regulator-name = "usb1-vbus";
 +		regulator-min-microvolt = <5000000>;
 +		regulator-max-microvolt = <5000000>;
 +		regulator-boot-on;
 +		enable-active-high;
 +		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
 +		status = "okay";
 +	};
 +};
 +
 +&ehci2 {
 +	status = "okay";
 +};
 +
 +&ehci3 {
 +	status = "okay";
 +};
 +
 +&mmc1 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&mmc1_pins_a>;
 +	vmmc-supply = <&reg_vcc3v3>;
 +	vqmmc-supply = <&reg_vcc3v3>;
 +	mmc-pwrseq = <&wifi_pwrseq>;
 +	bus-width = <4>;
 +	non-removable;
 +	status = "okay";
 +
 +	/delete-node/ sdio_wifi@1;
 +
 +	brcmf: bcrmf@1 {
 +		reg = <1>;
 +		compatible = "brcm,bcm4329-fmac";
 +		interrupt-parent = <&r_pio>;
 +		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */
 +		interrupt-names = "host-wake";
 +	};
 +};
 +
 +&mmc2 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&mmc2_8bit_pins>;
 +	vmmc-supply = <&reg_vcc3v3>;
 +	bus-width = <8>;
 +	non-removable;
 +	cap-mmc-hw-reset;
 +	status = "okay";
 +};
 +
 +&ohci0 {
 +	status = "okay";
 +};
 +
 +&ohci1 {
 +	status = "okay";
 +};
 +
 +&pio {
 +        wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 {
 +                allwinner,pins = "PA9";
 +                allwinner,function = "gpio_out";
 +                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 +                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +        };
 +};
 +
 +&r_pio {
 +	wifi_wake: wifi_wake@0 {
 +		allwinner,pins = "PL7";
 +		allwinner,function = "irq";
 +		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 +	};
 +};
 +
 +&spi0 {
 +        /delete-node/ spi-flash@0;
 +};
 +
 +&usbphy {
 +	usb1_vbus-supply = <&reg_usb1_vbus>;
 +	status = "okay";
 +};
 +
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-overlay-compilation-support.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-overlay-compilation-support.patch
@ -0,0 +1,133 @@
 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
 index ab30cc63..cc176797 100644
 --- a/arch/arm/Makefile
 +++ b/arch/arm/Makefile
@@ -339,6 +339,12 @@ $(INSTALL_TARGETS):
 %.dtb: | scripts
 	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 +%.dtbo: | scripts
 +	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 +
 +%.scr: | scripts
 +	$(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@
 +
 PHONY += dtbs dtbs_install
 dtbs: prepare scripts
 diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
 index 3c79f859..eaaeb17e 100644
 --- a/arch/arm/boot/.gitignore
 +++ b/arch/arm/boot/.gitignore
@@ -3,4 +3,5 @@ zImage
 xipImage
 bootpImage
 uImage
 -*.dtb
 +*.dtb*
 +*.scr
 diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
 index b9a4a934..54e3c38d 100644
 --- a/arch/arm64/Makefile
 +++ b/arch/arm64/Makefile
@@ -119,6 +119,12 @@ zinstall install:
 %.dtb: scripts
 	$(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
 +%.dtbo: | scripts
 +	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 +
 +%.scr: | scripts
 +	$(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@
 +
 PHONY += dtbs dtbs_install
 dtbs: prepare scripts
 diff --git a/arch/arm64/boot/dts/.gitignore b/arch/arm64/boot/dts/.gitignore
 index b60ed208..5d65b54b 100644
 --- a/arch/arm64/boot/dts/.gitignore
 +++ b/arch/arm64/boot/dts/.gitignore
@@ -1 +1,2 @@
 -*.dtb
 +*.dtb*
 +*.scr
 diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
 index a1be75d0..ad8dc1c9 100644
 --- a/scripts/Makefile.dtbinst
 +++ b/scripts/Makefile.dtbinst
@@ -27,6 +27,9 @@ ifeq ("$(dtbinst-root)", "$(obj)")
 endif
 dtbinst-files	:= $(dtb-y)
 +dtboinst-files	:= $(dtbo-y)
 +script-files	:= $(scr-y)
 +readme-files	:= $(dtbotxt-y)
 dtbinst-dirs	:= $(dts-dirs)
 # Helper targets for Installing DTBs into the boot directory
@@ -35,15 +38,24 @@ quiet_cmd_dtb_install =	INSTALL $<
 install-dir = $(patsubst $(dtbinst-root)%,$(INSTALL_DTBS_PATH)%,$(obj))
 -$(dtbinst-files) $(dtbinst-dirs): | __dtbs_install_prep
 +$(dtbinst-files) $(dtboinst-files) $(readme-files) $(script-files) $(dtbinst-dirs): | __dtbs_install_prep
 $(dtbinst-files): %.dtb: $(obj)/%.dtb
 	$(call cmd,dtb_install,$(install-dir))
 +$(dtboinst-files): %.dtbo: $(obj)/%.dtbo
 +	$(call cmd,dtb_install,$(install-dir))
 +
 +$(script-files): %.scr: $(obj)/%.scr
 +	$(call cmd,dtb_install,$(install-dir))
 +
 +$(readme-files): %: $(src)/%
 +	$(call cmd,dtb_install,$(install-dir))
 +
 $(dtbinst-dirs):
 	$(Q)$(MAKE) $(dtbinst)=$(obj)/$@
 -PHONY += $(dtbinst-files) $(dtbinst-dirs)
 -__dtbs_install: $(dtbinst-files) $(dtbinst-dirs)
 +PHONY += $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
 +__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
 .PHONY: $(PHONY)
 diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
 index 0a07f901..5ccd3490 100644
 --- a/scripts/Makefile.lib
 +++ b/scripts/Makefile.lib
@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
 # ---------------------------------------------------------------------------
 DTC ?= $(objtree)/scripts/dtc/dtc
 +# Overlay support
 +DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
 +
 # Disable noisy checks by default
 ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),)
 DTC_FLAGS += -Wno-unit_address_vs_reg
@@ -312,6 +315,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
 $(obj)/%.dtb: $(src)/%.dts FORCE
 	$(call if_changed_dep,dtc)
 +quiet_cmd_dtco = DTCO    $@
 +cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
 +	$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
 +	$(DTC) -O dtb -o $@ -b 0 \
 +		-i $(dir $<) $(DTC_FLAGS) \
 +		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
 +	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
 +
 +$(obj)/%.dtbo: $(src)/%.dts FORCE
 +	$(call if_changed_dep,dtco)
 +
 +quiet_cmd_scr = MKIMAGE $@
 +cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
 +
 +$(obj)/%.scr: $(src)/%.scr-cmd FORCE
 +	$(call if_changed,scr)
 +
 dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
 # Bzip2
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-realtek-8189fs-driver.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-realtek-8189fs-driver.patch
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-spi-aliases.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-spi-aliases.patch
@ -0,0 +1,16 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
 index ea74f58..d1aced2 100644
 --- a/arch/arm/boot/dts/sun8i-h3.dtsi
 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -43,6 +43,11 @@
 #include "sunxi-h3-h5.dtsi"
 / {
 +        aliases {
 +               spi0 = &spi0;
 +               spi1 = &spi1;
 +        };
 +
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-spi-flash-opi-zero.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-spi-flash-opi-zero.patch
@ -0,0 +1,40 @@
 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
 index e94f196b..9967fa66 100644
 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
 +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -144,6 +144,35 @@
 	status = "okay";
 };
 +&spi0 {
 +	status = "okay";
 +        spi-flash@0 {
 +                #address-cells = <1>;
 +                #size-cells = <0>;
 +                compatible = "jedec,spi-nor";
 +                reg = <0>; /* Chip select 0 */
 +                spi-max-frequency = <10000000>;
 +                status = "okay";
 +                partitions {
 +                        compatible = "fixed-partitions";
 +                        #address-cells = <1>;
 +                        #size-cells = <1>;
 +                        partition@0 {
 +                                label = "uboot";
 +                                reg = <0x0 0x100000>;
 +                        };
 +                        partition@100000 {
 +                                label = "env";
 +                                reg = <0x100000 0x100000>;
 +                        };
 +                        partition@200000 {
 +                                label = "data";
 +                                reg = <0x200000 0x200000>;
 +                        };
 +                };
 +        };
 +};
 +
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-thermal-otg-wireless-opi-lite.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-thermal-otg-wireless-opi-lite.patch
@ -0,0 +1,130 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
 index 22b99b40..cc4e5398 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -47,6 +47,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 +#include <dt-bindings/thermal/thermal.h>
 / {
 	model = "Xunlong Orange Pi Lite";
@@ -90,6 +91,82 @@
 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
 		};
 	};
 +
 +	wifi_pwrseq: wifi_pwrseq {
 +		compatible = "mmc-pwrseq-simple";
 +		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
 +	};
 +
 +	vdd_cpux: gpio-regulator {
 +		compatible = "regulator-gpio";
 +		regulator-name = "vdd-cpux";
 +		regulator-type = "voltage";
 +		regulator-boot-on;
 +		regulator-always-on;
 +		regulator-min-microvolt = <1100000>;
 +		regulator-max-microvolt = <1300000>;
 +		regulator-ramp-delay = <50>; /* 4ms */
 +		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
 +		gpios-states = <0x1>;
 +		states = <1100000 0x0
 +			  1300000 0x1>;
 +	};
 +};
 +
 +&cpu0 {
 +	operating-points = <
 +		1008000	1300000
 +		816000	1100000
 +		624000	1100000
 +		480000	1100000
 +		312000	1100000
 +		240000	1100000
 +		120000	1100000
 +		>;
 +	#cooling-cells = <2>;
 +	cooling-min-level = <0>;
 +	cooling-max-level = <6>;
 +	cpu0-supply = <&vdd_cpux>;
 +};
 +
 +&cpu_thermal {
 +	trips {
 +		cpu_warm: cpu_warm {
 +			temperature = <65000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_hot: cpu_hot {
 +			temperature = <75000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_very_hot: cpu_very_hot {
 +			temperature = <90000>;
 +			hysteresis = <2000>;
 +			type = "passive";
 +		};
 +		cpu_crit: cpu_crit {
 +			temperature = <105000>;
 +			hysteresis = <2000>;
 +			type = "critical";
 +		};
 +	};
 +
 +	cooling-maps {
 +		cpu_warm_limit_cpu {
 +			trip = <&cpu_warm>;
 +			cooling-device = <&cpu0 THERMAL_NO_LIMIT 1>;
 +		};
 +		cpu_hot_limit_cpu {
 +			trip = <&cpu_hot>;
 +			cooling-device = <&cpu0 2 3>;
 +		};
 +		cpu_very_hot_limit_cpu {
 +			trip = <&cpu_very_hot>;
 +			cooling-device = <&cpu0 5 THERMAL_NO_LIMIT>;
 +		};
 +	};
 };
 &ehci1 {
@@ -120,6 +197,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 +	mmc-pwrseq = <&wifi_pwrseq>;
 	bus-width = <4>;
 	non-removable;
 	status = "okay";
@@ -160,13 +238,25 @@
 	};
 };
 +&reg_usb0_vbus {
 +	gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
 +	status = "okay";
 +};
 +
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
 	status = "okay";
 };
 +&usb_otg {
 +	dr_mode = "otg";
 +	status = "okay";
 +};
 +
 &usbphy {
 -	/* USB VBUS is always on */
 +	/* USB VBUS is always on except for the OTG port */
 	status = "okay";
 +	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
 +	usb0_vbus-supply = <&reg_usb0_vbus>;
 };
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-uart-rts-cts-pins.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-uart-rts-cts-pins.patch
@ -0,0 +1,25 @@
 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 index c3e22263..6e00fec3 100644
 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -465,10 +491,20 @@
 				function = "uart2";
 			};
 +			uart2_rts_cts_pins: uart2_rts_cts {
 +				pins = "PA2", "PA3";
 +				function = "uart2";
 +			};
 +
 			uart3_pins: uart3 {
 				pins = "PA13", "PA14";
 				function = "uart3";
 			};
 +
 +			uart3_rts_cts_pins: uart3_rts_cts {
 +				pins = "PA15", "PA16";
 +				function = "uart3";
 +			};
 		};
 		ths: ths@01c25000 {
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-wifi-pwrseq-opi-pc-plus.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/add-wifi-pwrseq-opi-pc-plus.patch
@ -0,0 +1,23 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
 index 8b93f5c7..db8c3fb4 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -51,12 +51,18 @@
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
 		ethernet1 = &rtl8189ftv;
 	};
 +
 +	wifi_pwrseq: wifi_pwrseq {
 +		compatible = "mmc-pwrseq-simple";
 +		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
 +	};
 };
 &mmc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 +	mmc-pwrseq = <&wifi_pwrseq>;
 	bus-width = <4>;
 	non-removable;
 	status = "okay";
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/enable-1200mhz-on-small-orangepis.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/enable-1200mhz-on-small-orangepis.patch
@ -0,0 +1,26 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
 index 63c5498..c585618 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -122,7 +122,7 @@
 &cpu0 {
 	operating-points = <
 -		1008000	1300000
 +		1200000	1300000
 		816000	1100000
 		624000	1100000
 		480000	1100000
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
 index 87e495f..fb85217 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -115,7 +115,7 @@
 &cpu0 {
 	operating-points = <
 -		1008000	1300000
 +		1200000	1300000
 		816000	1100000
 		624000	1100000
 		480000	1100000
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/enable-codec-opi-2.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/enable-codec-opi-2.patch
@ -0,0 +1,19 @@
 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
 index 50e7e770..16845848 100644
 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -107,6 +107,14 @@
 	};
 };
 +&codec {
 +	allwinner,audio-routing =
 +		"Line Out", "LINEOUT",
 +		"MIC1", "Mic",
 +		"Mic",  "MBIAS";
 +	status = "okay";
 +};
 +
 &de {
 	status = "okay";
 };
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/fix-i2c2-reg-property.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/fix-i2c2-reg-property.patch
@ -0,0 +1,13 @@
 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 index 5b82d160..bccfb98f 100644
 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
 +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -560,7 +560,7 @@
 		i2c2: i2c@01c2b400 {
 			compatible = "allwinner,sun6i-a31-i2c";
 -			reg = <0x01c2b000 0x400>;
 +			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C2>;
 			resets = <&ccu RST_BUS_I2C2>;
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/resolve-crypto-deps.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/resolve-crypto-deps.patch
@ -0,0 +1,198 @@
 From b56f5cbc7e08ec7d31c42fc41e5247677f20b143 Mon Sep 17 00:00:00 2001
 From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
 Date: Tue, 14 Feb 2017 21:51:01 +0000
 Subject: crypto: arm/aes-neonbs - resolve fallback cipher at runtime
 Currently, the bit sliced NEON AES code for ARM has a link time
 dependency on the scalar ARM asm implementation, which it uses as a
 fallback to perform CBC encryption and the encryption of the initial
 XTS tweak.
 The bit sliced NEON code is both fast and time invariant, which makes
 it a reasonable default on hardware that supports it. However, the
 ARM asm code it pulls in is not time invariant, and due to the way it
 is linked in, cannot be overridden by the new generic time invariant
 driver. In fact, it will not be used at all, given that the ARM asm
 code registers itself as a cipher with a priority that exceeds the
 priority of the fixed time cipher.
 So remove the link time dependency, and allocate the fallback cipher
 via the crypto API. Note that this requires this driver's module_init
 call to be replaced with late_initcall, so that the (possibly generic)
 fallback cipher is guaranteed to be available when the builtin test
 is performed at registration time.
 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
 ---
 arch/arm/crypto/Kconfig           |  2 +-
 arch/arm/crypto/aes-neonbs-glue.c | 60 +++++++++++++++++++++++++++++----------
 2 files changed, 46 insertions(+), 16 deletions(-)
 diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
 index a8fce93..b9adedc 100644
 --- a/arch/arm/crypto/Kconfig
 +++ b/arch/arm/crypto/Kconfig
@@ -73,7 +73,7 @@ config CRYPTO_AES_ARM_BS
 	depends on KERNEL_MODE_NEON
 	select CRYPTO_BLKCIPHER
 	select CRYPTO_SIMD
 -	select CRYPTO_AES_ARM
 +	select CRYPTO_AES
 	help
 	  Use a faster and more secure NEON based implementation of AES in CBC,
 	  CTR and XTS modes
 diff --git a/arch/arm/crypto/aes-neonbs-glue.c b/arch/arm/crypto/aes-neonbs-glue.c
 index 2920b96..c763779 100644
 --- a/arch/arm/crypto/aes-neonbs-glue.c
 +++ b/arch/arm/crypto/aes-neonbs-glue.c
@@ -42,9 +42,6 @@ asmlinkage void aesbs_xts_encrypt(u8 out[], u8 const in[], u8 const rk[],
 asmlinkage void aesbs_xts_decrypt(u8 out[], u8 const in[], u8 const rk[],
 				  int rounds, int blocks, u8 iv[]);
 -asmlinkage void __aes_arm_encrypt(const u32 rk[], int rounds, const u8 in[],
 -				  u8 out[]);
 -
 struct aesbs_ctx {
 	int	rounds;
 	u8	rk[13 * (8 * AES_BLOCK_SIZE) + 32] __aligned(AES_BLOCK_SIZE);
@@ -52,12 +49,12 @@ struct aesbs_ctx {
 struct aesbs_cbc_ctx {
 	struct aesbs_ctx	key;
 -	u32			enc[AES_MAX_KEYLENGTH_U32];
 +	struct crypto_cipher	*enc_tfm;
 };
 struct aesbs_xts_ctx {
 	struct aesbs_ctx	key;
 -	u32			twkey[AES_MAX_KEYLENGTH_U32];
 +	struct crypto_cipher	*tweak_tfm;
 };
 static int aesbs_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
@@ -132,20 +129,18 @@ static int aesbs_cbc_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
 	ctx->key.rounds = 6 + key_len / 4;
 -	memcpy(ctx->enc, rk.key_enc, sizeof(ctx->enc));
 -
 	kernel_neon_begin();
 	aesbs_convert_key(ctx->key.rk, rk.key_enc, ctx->key.rounds);
 	kernel_neon_end();
 -	return 0;
 +	return crypto_cipher_setkey(ctx->enc_tfm, in_key, key_len);
 }
 static void cbc_encrypt_one(struct crypto_skcipher *tfm, const u8 *src, u8 *dst)
 {
 	struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
 -	__aes_arm_encrypt(ctx->enc, ctx->key.rounds, src, dst);
 +	crypto_cipher_encrypt_one(ctx->enc_tfm, dst, src);
 }
 static int cbc_encrypt(struct skcipher_request *req)
@@ -181,6 +176,23 @@ static int cbc_decrypt(struct skcipher_request *req)
 	return err;
 }
 +static int cbc_init(struct crypto_tfm *tfm)
 +{
 +	struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
 +
 +	ctx->enc_tfm = crypto_alloc_cipher("aes", 0, 0);
 +	if (IS_ERR(ctx->enc_tfm))
 +		return PTR_ERR(ctx->enc_tfm);
 +	return 0;
 +}
 +
 +static void cbc_exit(struct crypto_tfm *tfm)
 +{
 +	struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
 +
 +	crypto_free_cipher(ctx->enc_tfm);
 +}
 +
 static int ctr_encrypt(struct skcipher_request *req)
 {
 	struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
@@ -228,7 +240,6 @@ static int aesbs_xts_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
 			    unsigned int key_len)
 {
 	struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm);
 -	struct crypto_aes_ctx rk;
 	int err;
 	err = xts_verify_key(tfm, in_key, key_len);
@@ -236,15 +247,30 @@ static int aesbs_xts_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
 		return err;
 	key_len /= 2;
 -	err = crypto_aes_expand_key(&rk, in_key + key_len, key_len);
 +	err = crypto_cipher_setkey(ctx->tweak_tfm, in_key + key_len, key_len);
 	if (err)
 		return err;
 -	memcpy(ctx->twkey, rk.key_enc, sizeof(ctx->twkey));
 -
 	return aesbs_setkey(tfm, in_key, key_len);
 }
 +static int xts_init(struct crypto_tfm *tfm)
 +{
 +	struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm);
 +
 +	ctx->tweak_tfm = crypto_alloc_cipher("aes", 0, 0);
 +	if (IS_ERR(ctx->tweak_tfm))
 +		return PTR_ERR(ctx->tweak_tfm);
 +	return 0;
 +}
 +
 +static void xts_exit(struct crypto_tfm *tfm)
 +{
 +	struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm);
 +
 +	crypto_free_cipher(ctx->tweak_tfm);
 +}
 +
 static int __xts_crypt(struct skcipher_request *req,
 		       void (*fn)(u8 out[], u8 const in[], u8 const rk[],
 				  int rounds, int blocks, u8 iv[]))
@@ -256,7 +282,7 @@ static int __xts_crypt(struct skcipher_request *req,
 	err = skcipher_walk_virt(&walk, req, true);
 -	__aes_arm_encrypt(ctx->twkey, ctx->key.rounds, walk.iv, walk.iv);
 +	crypto_cipher_encrypt_one(ctx->tweak_tfm, walk.iv, walk.iv);
 	kernel_neon_begin();
 	while (walk.nbytes >= AES_BLOCK_SIZE) {
@@ -309,6 +335,8 @@ static struct skcipher_alg aes_algs[] = { {
 	.base.cra_ctxsize	= sizeof(struct aesbs_cbc_ctx),
 	.base.cra_module	= THIS_MODULE,
 	.base.cra_flags		= CRYPTO_ALG_INTERNAL,
 +	.base.cra_init		= cbc_init,
 +	.base.cra_exit		= cbc_exit,
 	.min_keysize		= AES_MIN_KEY_SIZE,
 	.max_keysize		= AES_MAX_KEY_SIZE,
@@ -342,6 +370,8 @@ static struct skcipher_alg aes_algs[] = { {
 	.base.cra_ctxsize	= sizeof(struct aesbs_xts_ctx),
 	.base.cra_module	= THIS_MODULE,
 	.base.cra_flags		= CRYPTO_ALG_INTERNAL,
 +	.base.cra_init		= xts_init,
 +	.base.cra_exit		= xts_exit,
 	.min_keysize		= 2 * AES_MIN_KEY_SIZE,
 	.max_keysize		= 2 * AES_MAX_KEY_SIZE,
@@ -402,5 +432,5 @@ unregister_simds:
 	return err;
 }
 -module_init(aes_init);
 +late_initcall(aes_init);
 module_exit(aes_exit);
 -- 
 cgit v1.1
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/scripts-dtc-import-updates.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/scripts-dtc-import-updates.patch
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/spi-sun6i-allow-large-transfers.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/spi-sun6i-allow-large-transfers.patch
@ -0,0 +1,190 @@
 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
 index e3114832..03a773a9 100644
 --- a/drivers/spi/spi-sun6i.c
 +++ b/drivers/spi/spi-sun6i.c
@@ -46,13 +46,19 @@
 #define SUN6I_TFR_CTL_XCH			BIT(31)
 #define SUN6I_INT_CTL_REG		0x10
 +#define SUN6I_INT_CTL_RF_RDY			BIT(0)
 +#define SUN6I_INT_CTL_TF_ERQ			BIT(4)
 #define SUN6I_INT_CTL_RF_OVF			BIT(8)
 #define SUN6I_INT_CTL_TC			BIT(12)
 #define SUN6I_INT_STA_REG		0x14
 #define SUN6I_FIFO_CTL_REG		0x18
 +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK	0xff
 +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS	0
 #define SUN6I_FIFO_CTL_RF_RST			BIT(15)
 +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK	0xff
 +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS	16
 #define SUN6I_FIFO_CTL_TF_RST			BIT(31)
 #define SUN6I_FIFO_STA_REG		0x1c
@@ -68,14 +74,16 @@
 #define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 #define SUN6I_CLK_CTL_DRS			BIT(12)
 +#define SUN6I_MAX_XFER_SIZE		0xffffff
 +
 #define SUN6I_BURST_CNT_REG		0x30
 -#define SUN6I_BURST_CNT(cnt)			((cnt) & 0xffffff)
 +#define SUN6I_BURST_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)
 #define SUN6I_XMIT_CNT_REG		0x34
 -#define SUN6I_XMIT_CNT(cnt)			((cnt) & 0xffffff)
 +#define SUN6I_XMIT_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)
 #define SUN6I_BURST_CTL_CNT_REG		0x38
 -#define SUN6I_BURST_CTL_CNT_STC(cnt)		((cnt) & 0xffffff)
 +#define SUN6I_BURST_CTL_CNT_STC(cnt)		((cnt) & SUN6I_MAX_XFER_SIZE)
 #define SUN6I_TXDATA_REG		0x200
 #define SUN6I_RXDATA_REG		0x300
@@ -105,6 +113,31 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 	writel(value, sspi->base_addr + reg);
 }
 +static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
 +{
 +	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 +
 +	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
 +
 +	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
 +}
 +
 +static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
 +{
 +	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
 +
 +	reg |= mask;
 +	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 +}
 +
 +static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
 +{
 +	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
 +
 +	reg &= ~mask;
 +	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
 +}
 +
 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 {
 	u32 reg, cnt;
@@ -127,10 +160,13 @@ static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 {
 +	u32 cnt;
 	u8 byte;
 -	if (len > sspi->len)
 -		len = sspi->len;
 +	/* See how much data we can fit */
 +	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
 +
 +	len = min3(len, (int)cnt, sspi->len);
 	while (len--) {
 		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
@@ -158,9 +194,7 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
 {
 -	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 -
 -	return sspi->fifo_depth - 1;
 +	return SUN6I_MAX_XFER_SIZE - 1;
 }
 static int sun6i_spi_transfer_one(struct spi_master *master,
@@ -170,12 +204,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 	struct sun6i_spi *sspi = spi_master_get_devdata(master);
 	unsigned int mclk_rate, div, timeout;
 	unsigned int start, end, tx_time;
 +	unsigned int trig_level;
 	unsigned int tx_len = 0;
 	int ret = 0;
 	u32 reg;
 -	/* We don't support transfer larger than the FIFO */
 -	if (tfr->len > sspi->fifo_depth)
 +	if (tfr->len > SUN6I_MAX_XFER_SIZE)
 		return -EINVAL;
 	reinit_completion(&sspi->done);
@@ -191,6 +225,17 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 	/*
 +	 * Setup FIFO interrupt trigger level
 +	 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
 +	 * value used in old generation of Allwinner SPI controller.
 +	 * (See spi-sun4i.c)
 +	 */
 +	trig_level = sspi->fifo_depth / 4 * 3;
 +	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 +			(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
 +			(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
 +
 +	/*
 	 * Setup the transfer control register: Chip Select,
 	 * polarities, etc.
 	 */
@@ -274,6 +319,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 	/* Enable the interrupts */
 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 +	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
 +					 SUN6I_INT_CTL_RF_RDY);
 +	if (tx_len > sspi->fifo_depth)
 +		sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
 	/* Start the transfer */
 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
@@ -293,8 +342,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 		goto out;
 	}
 -	sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
 -
 out:
 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
@@ -309,10 +356,33 @@ static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 	/* Transfer complete */
 	if (status & SUN6I_INT_CTL_TC) {
 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 +		sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
 		complete(&sspi->done);
 		return IRQ_HANDLED;
 	}
 +	/* Receive FIFO 3/4 full */
 +	if (status & SUN6I_INT_CTL_RF_RDY) {
 +		sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 +		/* Only clear the interrupt _after_ draining the FIFO */
 +		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
 +		return IRQ_HANDLED;
 +	}
 +
 +	/* Transmit FIFO 3/4 empty */
 +	if (status & SUN6I_INT_CTL_TF_ERQ) {
 +		sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 +
 +		if (!sspi->len)
 +			/* nothing left to transmit */
 +			sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
 +
 +		/* Only clear the interrupt _after_ re-seeding the FIFO */
 +		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
 +
 +		return IRQ_HANDLED;
 +	}
 +
 	return IRQ_NONE;
 }
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/spidev-remove-warnings.patch
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux-4.11.5/spidev-remove-warnings.patch
@ -0,0 +1,21 @@
 diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
 index 9e2e099b..a065943d 100644
 --- a/drivers/spi/spidev.c
 +++ b/drivers/spi/spidev.c
@@ -749,13 +749,11 @@ static int spidev_probe(struct spi_device *spi)
 	/*
 	 * spidev should never be referenced in DT without a specific
 -	 * compatible string, it is a Linux implementation thing
 -	 * rather than a description of the hardware.
 +	 * compatible string, but people don't care and use DT overlays
 +	 * to activate SPIdev on demand
 	 */
 	if (spi->dev.of_node && !of_match_device(spidev_dt_ids, &spi->dev)) {
 -		dev_err(&spi->dev, "buggy DT: spidev listed directly in DT\n");
 -		WARN_ON(spi->dev.of_node &&
 -			!of_match_device(spidev_dt_ids, &spi->dev));
 +		dev_info(&spi->dev, "probing from DT");
 	}
 	spidev_probe_acpi(spi);
--- a/layers/meta-resin-allwinner/recipes-kernel/linux/linux_%.bbappend
+++ b/layers/meta-resin-allwinner/recipes-kernel/linux/linux_%.bbappend
@ -2,27 +2,38 @@ inherit kernel-resin
 SRC_URI_remove = "git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git;protocol=git;branch=master"
-FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+FILESEXTRAPATHS_prepend := "${THISDIR}/linux-4.11.5:"
 PV = "4.11.0+git${SRCPV}"
 SRCREV_pn-${PN} = "22521549cdcd4d701cf3079c3a822bda5324df9c"
 SRC_URI_append = "git://github.com/megous/linux.git;protocol=git;branch=orange-pi-4.11 \
-    file://411-fix-i2c2-reg-property.patch \
+    file://add-ad9834-dt-bindings.patch \
-    file://411-add-thermal-otg-wireless-opi-lite.patch \
+    file://add-BergMicro-SPI-flashes.patch \
-    file://411-enable-1200mhz-on-small-orangepis.patch \
+    file://add-configfs-overlay-for-v4.11.x.patch \
-    file://411-add-spi-aliases.patch \
+    file://add-dvfs-emac-nanopi.patch \
-    file://411-add-uart-rts-cts-pins.patch \
+    file://add-emac-pwr-en-orangepi-plus2e.patch \
-    file://411-add-configfs-overlay-for-v4.11.x.patch \
+    file://add-fix-dts-for-opi-zero-emac.patch \
-    file://411-add-h3-overlays.patch \
+    file://add-h3-overlays.patch \
-    file://411-add-overlay-compilation-support.patch \
+    file://add-h3-simplefb.patch \
-    file://411-scripts-dtc-import-updates.patch \
+    file://add-nanopi-neoair.patch \
-    file://411-add-ad9834-dt-bindings.patch \
+    file://add-orangepi-zeroplus.patch \
-    file://411-add-nanopi-neoair.patch \
+    file://add-overlay-compilation-support.patch \
-    file://411-add-dvfs-emac-nanopi.patch \
+    file://add-spi-aliases.patch \
    file://add-spi-flash-opi-zero.patch \
    file://add-thermal-otg-wireless-opi-lite.patch \
    file://add-uart-rts-cts-pins.patch \
    file://add-wifi-pwrseq-opi-pc-plus.patch \
    file://enable-1200mhz-on-small-orangepis.patch \
    file://enable-codec-opi-2.patch \
    file://fix-i2c2-reg-property.patch \
    file://resolve-crypto-deps.patch \
    file://scripts-dtc-import-updates.patch \
    file://spidev-remove-warnings.patch \
    file://spi-sun6i-allow-large-transfers.patch \
 "
 SRC_URI_append_orange-pi-lite = " \
-    file://411-add-realtek-8189fs-driver.patch \
+    file://add-realtek-8189fs-driver.patch \
 "
 RESIN_CONFIGS_append = " \