diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-configfs-overlay.patch b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-configfs-overlay.patch new file mode 100644 index 0000000..5868c27 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-configfs-overlay.patch @@ -0,0 +1,326 @@ +diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig +index bc07ad3..e9da9cf 100644 +--- a/drivers/of/Kconfig ++++ b/drivers/of/Kconfig +@@ -113,6 +113,13 @@ config OF_OVERLAY + While this option is selected automatically when needed, you can + enable it manually to improve device tree unit test coverage. + ++config OF_CONFIGFS ++ bool "Device Tree Overlay ConfigFS interface" ++ select CONFIGFS_FS ++ depends on OF_OVERLAY ++ help ++ Enable a simple user-space driven DT overlay interface. ++ + config OF_NUMA + bool + +diff --git a/drivers/of/Makefile b/drivers/of/Makefile +index d7efd9d..a06cc35 100644 +--- a/drivers/of/Makefile ++++ b/drivers/of/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_OF_PCI_IRQ) += of_pci_irq.o + obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o + obj-$(CONFIG_OF_RESOLVE) += resolver.o + obj-$(CONFIG_OF_OVERLAY) += overlay.o ++obj-$(CONFIG_OF_CONFIGFS) += configfs.o + obj-$(CONFIG_OF_NUMA) += of_numa.o + + obj-$(CONFIG_OF_UNITTEST) += unittest-data/ +diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c +new file mode 100644 +index 0000000..68f889d +--- /dev/null ++++ b/drivers/of/configfs.c +@@ -0,0 +1,277 @@ ++/* ++ * Configfs entries for device-tree ++ * ++ * Copyright (C) 2013 - Pantelis Antoniou ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "of_private.h" ++ ++struct cfs_overlay_item { ++ struct config_item item; ++ ++ char path[PATH_MAX]; ++ ++ const struct firmware *fw; ++ struct device_node *overlay; ++ int ov_id; ++ ++ void *dtbo; ++ int dtbo_size; ++}; ++ ++static inline struct cfs_overlay_item *to_cfs_overlay_item( ++ struct config_item *item) ++{ ++ return item ? container_of(item, struct cfs_overlay_item, item) : NULL; ++} ++ ++static ssize_t cfs_overlay_item_path_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ return sprintf(page, "%s\n", overlay->path); ++} ++ ++static ssize_t cfs_overlay_item_path_store(struct config_item *item, ++ const char *page, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ const char *p = page; ++ char *s; ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy to path buffer (and make sure it's always zero terminated */ ++ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); ++ overlay->path[sizeof(overlay->path) - 1] = '\0'; ++ ++ /* strip trailing newlines */ ++ s = overlay->path + strlen(overlay->path); ++ while (s > overlay->path && *--s == '\n') ++ *s = '\0'; ++ ++ pr_debug("%s: path is '%s'\n", __func__, overlay->path); ++ ++ err = request_firmware(&overlay->fw, overlay->path, NULL); ++ if (err != 0) ++ goto out_err; ++ ++ err = of_overlay_fdt_apply((void *)overlay->fw->data, ++ (u32)overlay->fw->size, &overlay->ov_id); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ ++ release_firmware(overlay->fw); ++ overlay->fw = NULL; ++ ++ overlay->path[0] = '\0'; ++ return err; ++} ++ ++static ssize_t cfs_overlay_item_status_show(struct config_item *item, ++ char *page) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ return sprintf(page, "%s\n", ++ overlay->ov_id > 0 ? "applied" : "unapplied"); ++} ++ ++CONFIGFS_ATTR(cfs_overlay_item_, path); ++CONFIGFS_ATTR_RO(cfs_overlay_item_, status); ++ ++static struct configfs_attribute *cfs_overlay_attrs[] = { ++ &cfs_overlay_item_attr_path, ++ &cfs_overlay_item_attr_status, ++ NULL, ++}; ++ ++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, ++ void *buf, size_t max_count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ pr_debug("%s: buf=%p max_count=%zu\n", __func__, ++ buf, max_count); ++ ++ if (overlay->dtbo == NULL) ++ return 0; ++ ++ /* copy if buffer provided */ ++ if (buf != NULL) { ++ /* the buffer must be large enough */ ++ if (overlay->dtbo_size > max_count) ++ return -ENOSPC; ++ ++ memcpy(buf, overlay->dtbo, overlay->dtbo_size); ++ } ++ ++ return overlay->dtbo_size; ++} ++ ++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, ++ const void *buf, size_t count) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ int err; ++ ++ /* if it's set do not allow changes */ ++ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) ++ return -EPERM; ++ ++ /* copy the contents */ ++ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); ++ if (overlay->dtbo == NULL) ++ return -ENOMEM; ++ ++ overlay->dtbo_size = count; ++ ++ err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size, ++ &overlay->ov_id); ++ if (err != 0) ++ goto out_err; ++ ++ return count; ++ ++out_err: ++ kfree(overlay->dtbo); ++ overlay->dtbo = NULL; ++ overlay->dtbo_size = 0; ++ overlay->ov_id = 0; ++ ++ return err; ++} ++ ++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); ++ ++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { ++ &cfs_overlay_item_attr_dtbo, ++ NULL, ++}; ++ ++static void cfs_overlay_release(struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ if (overlay->ov_id > 0) ++ of_overlay_remove(&overlay->ov_id); ++ if (overlay->fw) ++ release_firmware(overlay->fw); ++ /* kfree with NULL is safe */ ++ kfree(overlay->dtbo); ++ kfree(overlay); ++} ++ ++static struct configfs_item_operations cfs_overlay_item_ops = { ++ .release = cfs_overlay_release, ++}; ++ ++static struct config_item_type cfs_overlay_type = { ++ .ct_item_ops = &cfs_overlay_item_ops, ++ .ct_attrs = cfs_overlay_attrs, ++ .ct_bin_attrs = cfs_overlay_bin_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *cfs_overlay_group_make_item( ++ struct config_group *group, const char *name) ++{ ++ struct cfs_overlay_item *overlay; ++ ++ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); ++ if (!overlay) ++ return ERR_PTR(-ENOMEM); ++ ++ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); ++ return &overlay->item; ++} ++ ++static void cfs_overlay_group_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); ++ ++ config_item_put(&overlay->item); ++} ++ ++static struct configfs_group_operations overlays_ops = { ++ .make_item = cfs_overlay_group_make_item, ++ .drop_item = cfs_overlay_group_drop_item, ++}; ++ ++static struct config_item_type overlays_type = { ++ .ct_group_ops = &overlays_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_group_operations of_cfs_ops = { ++ /* empty - we don't allow anything to be created */ ++}; ++ ++static struct config_item_type of_cfs_type = { ++ .ct_group_ops = &of_cfs_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++struct config_group of_cfs_overlay_group; ++ ++static struct configfs_subsystem of_cfs_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = "device-tree", ++ .ci_type = &of_cfs_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), ++}; ++ ++static int __init of_cfs_init(void) ++{ ++ int ret; ++ ++ pr_info("%s\n", __func__); ++ ++ config_group_init(&of_cfs_subsys.su_group); ++ config_group_init_type_name(&of_cfs_overlay_group, "overlays", ++ &overlays_type); ++ configfs_add_default_group(&of_cfs_overlay_group, ++ &of_cfs_subsys.su_group); ++ ++ ret = configfs_register_subsystem(&of_cfs_subsys); ++ if (ret != 0) { ++ pr_err("%s: failed to register subsys\n", __func__); ++ goto out; ++ } ++ pr_info("%s: OK\n", __func__); ++out: ++ return ret; ++} ++late_initcall(of_cfs_init); +diff --git a/drivers/of/fdt_address.c b/drivers/of/fdt_address.c +index dca8f9b..ec7e167 100644 +--- a/drivers/of/fdt_address.c ++++ b/drivers/of/fdt_address.c +@@ -161,7 +161,7 @@ static int __init fdt_translate_one(const void *blob, int parent, + * that can be mapped to a cpu physical address). This is not really specified + * that way, but this is traditionally the way IBM at least do things + */ +-static u64 __init fdt_translate_address(const void *blob, int node_offset) ++u64 __init fdt_translate_address(const void *blob, int node_offset) + { + int parent, len; + const struct of_bus *bus, *pbus; diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-overlay-compilation-support.patch b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-overlay-compilation-support.patch new file mode 100644 index 0000000..bd6256c --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-add-overlay-compilation-support.patch @@ -0,0 +1,84 @@ +diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore +index 3c79f859..4e5c1d59 100644 +--- a/arch/arm/boot/.gitignore ++++ b/arch/arm/boot/.gitignore +@@ -3,3 +3,5 @@ zImage + xipImage + bootpImage + uImage ++*.dtb* ++*.scr +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 34614a48..8a8313d6 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -20,6 +20,9 @@ include scripts/Kbuild.include + include $(src)/Makefile + + dtbinst-files := $(sort $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS), $(dtb-))) ++dtboinst-files := $(dtbo-y) ++script-files := $(scr-y) ++readme-files := $(dtbotxt-y) + dtbinst-dirs := $(subdir-y) $(subdir-m) + + # Helper targets for Installing DTBs into the boot directory +@@ -32,10 +35,19 @@ install-dir = $(patsubst $(dtbinst-root)%,$(INSTALL_DTBS_PATH)%,$(obj)) + $(dtbinst-files): %.dtb: $(obj)/%.dtb + $(call cmd,dtb_install,$(install-dir)) + ++$(dtboinst-files): %.dtbo: $(obj)/%.dtbo ++ $(call cmd,dtb_install,$(install-dir)) ++ ++$(script-files): %.scr: $(obj)/%.scr ++ $(call cmd,dtb_install,$(install-dir)) ++ ++$(readme-files): %: $(src)/% ++ $(call cmd,dtb_install,$(install-dir)) ++ + $(dtbinst-dirs): + $(Q)$(MAKE) $(dtbinst)=$(obj)/$@ + +-PHONY += $(dtbinst-files) $(dtbinst-dirs) +-__dtbs_install: $(dtbinst-files) $(dtbinst-dirs) ++PHONY += $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs) ++__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs) + + .PHONY: $(PHONY) +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 58c05e5d..2b95dda9 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ + # --------------------------------------------------------------------------- + DTC ?= $(objtree)/scripts/dtc/dtc + ++# Overlay support ++DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg ++ + # Disable noisy checks by default + ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),) + DTC_FLAGS += -Wno-unit_address_vs_reg \ +@@ -324,6 +327,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ + $(obj)/%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + ++quiet_cmd_dtco = DTCO $@ ++cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ ++ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ ++ $(DTC) -O dtb -o $@ -b 0 \ ++ -i $(dir $<) $(DTC_FLAGS) \ ++ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ ++ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ++ ++$(obj)/%.dtbo: $(src)/%.dts FORCE ++ $(call if_changed_dep,dtco) ++ ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-sunxi-overlays.patch b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-sunxi-overlays.patch new file mode 100644 index 0000000..5d00263 --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-kernel/linux/files/general-sunxi-overlays.patch @@ -0,0 +1,6900 @@ +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 965a7c0..71a672e 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1213,3 +1213,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-bmc-opp-zaius.dtb \ + aspeed-bmc-portwell-neptune.dtb \ + aspeed-bmc-quanta-q71l.dtb ++ ++subdir-y := overlay +diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile +new file mode 100644 +index 0000000..39d6a27 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/Makefile +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtbo-$(CONFIG_MACH_SUN4I) += \ ++ sun4i-a10-analog-codec.dtbo \ ++ sun4i-a10-can.dtbo \ ++ sun4i-a10-i2c1.dtbo \ ++ sun4i-a10-i2c2.dtbo \ ++ sun4i-a10-nand.dtbo \ ++ sun4i-a10-pps-gpio.dtbo \ ++ sun4i-a10-pwm.dtbo \ ++ sun4i-a10-spdif-out.dtbo \ ++ sun4i-a10-spi-jedec-nor.dtbo \ ++ sun4i-a10-spi-spidev.dtbo \ ++ sun4i-a10-uart2.dtbo \ ++ sun4i-a10-uart3.dtbo \ ++ sun4i-a10-uart4.dtbo \ ++ sun4i-a10-uart5.dtbo \ ++ sun4i-a10-uart6.dtbo \ ++ sun4i-a10-uart7.dtbo \ ++ sun4i-a10-w1-gpio.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN5I) += \ ++ sun5i-a13-analog-codec.dtbo \ ++ sun5i-a13-i2c1.dtbo \ ++ sun5i-a13-i2c2.dtbo \ ++ sun5i-a13-nand.dtbo \ ++ sun5i-a13-pwm.dtbo \ ++ sun5i-a13-spi0.dtbo \ ++ sun5i-a13-spi1.dtbo \ ++ sun5i-a13-spi2.dtbo \ ++ sun5i-a13-spi-jedec-nor.dtbo \ ++ sun5i-a13-spi-spidev.dtbo \ ++ sun5i-a13-uart0.dtbo \ ++ sun5i-a13-uart1.dtbo \ ++ sun5i-a13-uart2.dtbo \ ++ sun5i-a13-uart3.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN7I) += \ ++ sun7i-a20-analog-codec.dtbo \ ++ sun7i-a20-can.dtbo \ ++ sun7i-a20-i2c1.dtbo \ ++ sun7i-a20-i2c2.dtbo \ ++ sun7i-a20-i2c3.dtbo \ ++ sun7i-a20-i2c4.dtbo \ ++ sun7i-a20-mmc2.dtbo \ ++ sun7i-a20-nand.dtbo \ ++ sun7i-a20-pps-gpio.dtbo \ ++ sun7i-a20-pwm.dtbo \ ++ sun7i-a20-spdif-out.dtbo \ ++ sun7i-a20-spi-add-cs1.dtbo \ ++ sun7i-a20-spi-jedec-nor.dtbo \ ++ sun7i-a20-spi-spidev.dtbo \ ++ sun7i-a20-uart2.dtbo \ ++ sun7i-a20-uart3.dtbo \ ++ sun7i-a20-uart4.dtbo \ ++ sun7i-a20-uart5.dtbo \ ++ sun7i-a20-uart6.dtbo \ ++ sun7i-a20-uart7.dtbo \ ++ sun7i-a20-w1-gpio.dtbo ++ ++dtbo-$(CONFIG_MACH_SUN8I) += \ ++ sun8i-h3-analog-codec.dtbo \ ++ sun8i-h3-cir.dtbo \ ++ sun8i-h3-i2c0.dtbo \ ++ sun8i-h3-i2c1.dtbo \ ++ sun8i-h3-i2c2.dtbo \ ++ sun8i-h3-pps-gpio.dtbo \ ++ sun8i-h3-pwm.dtbo \ ++ sun8i-h3-spdif-out.dtbo \ ++ sun8i-h3-spi-add-cs1.dtbo \ ++ sun8i-h3-spi-jedec-nor.dtbo \ ++ sun8i-h3-spi-spidev.dtbo \ ++ sun8i-h3-uart1.dtbo \ ++ sun8i-h3-uart2.dtbo \ ++ sun8i-h3-uart3.dtbo \ ++ sun8i-h3-usbhost0.dtbo \ ++ sun8i-h3-usbhost1.dtbo \ ++ sun8i-h3-usbhost2.dtbo \ ++ sun8i-h3-usbhost3.dtbo \ ++ sun8i-h3-w1-gpio.dtbo ++ ++scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr ++scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr ++scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr ++scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr ++ ++dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays ++dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays ++dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays ++dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays +diff --git a/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +new file mode 100644 +index 0000000..e0795f1 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +@@ -0,0 +1,278 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun4i-a10 (Allwinner A10) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- nand ++- pps-gpio ++- pwm ++- spdif-out ++- spi0 ++- spi1 ++- spi2 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0, PWM1): PB2, PI3 ++ ++Parameters: ++ ++param_pwm_pins (string) ++ PWM pins activated with this overlay ++ Optional ++ Default: both ++ Supported values: 0, 1, both ++ If set to 0 only PWM0 can be used, ++ if set to 1 then only PWM1 can be used, ++ if set to both (default), both PWM0 and PWM1 can be used ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used ++ ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 ++ ++Parameters: ++ ++param_uart3_pins (char) ++ Determines what pins UART 3 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays +new file mode 100644 +index 0000000..9f9653f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun5i-a13-overlays +@@ -0,0 +1,172 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun5i-a13 (Allwinner A13) ++ ++### Platform details: ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- i2c1 ++- i2c2 ++- nand ++- pwm ++- spi0 ++- spi1 ++- spi2 ++- spi-jedec-nor ++- spi-spidev ++- uart0 ++- uart1 ++- uart2 ++- uart3 ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides HP Out and Mic In ++functionality ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB15, PB16 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB17, PB18 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0): PB2 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9 ++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart 0 ++ ++Activates serial port 0 (/dev/ttyS0) ++ ++UART 0 pins (TX, RX): PF2, PF4 ++ ++### uart 1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins a (TX, RX): PE10, PE11 ++UART 1 pins b (TX, RX): PG3, PG4 ++ ++Parameters: ++ ++param_uart1_pins (char) ++ UART 1 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins UART 1 is exposed on if UART 1 is used ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins +diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +new file mode 100644 +index 0000000..362f879 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +@@ -0,0 +1,348 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun7i-a20 (Allwinner A20) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- i2c3 ++- i2c4 ++- i2s0 ++- i2s1 ++- mmc2 ++- nand ++- pps-gpio ++- pwm ++- spdif-out ++- spi0 ++- spi1 ++- spi2 ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### i2c3 ++ ++Activates TWI/I2C bus 3 ++ ++I2C3 pins (SCL, SDA): PI0, PI1 ++ ++### i2c4 ++ ++Activates TWI/I2C bus 4 ++ ++I2C4 pins (SCL, SDA): PI2, PI3 ++ ++### i2s0 ++ ++Activates SoC I2S controller 0 ++ ++I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12 ++ ++### i2s1 ++ ++Activates SoC I2S controller 1 ++ ++I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17 ++ ++### mmc2 ++ ++Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC ++or tSD instead of NAND storage. ++ ++MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11 ++ ++Parameters: ++ ++param_mmc2_cd_pin (pin) ++ SD/MMC 2 card detect pin ++ Optional ++ Default: PH0 ++ ++param_mmc2_non_removable (bool) ++ Option for non-removable storage options on MMC 2 controller (eMMC or tSD) ++ Optional ++ Default: 0 ++ Set to 1 to use this option ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pins (PWM0, PWM1): PB2, PI3 ++ ++Parameters: ++ ++param_pwm_pins (string) ++ PWM pins activated with this overlay ++ Optional ++ Default: both ++ Supported values: 0, 1, both ++ If set to 0 only PWM0 can be used, ++ if set to 1 then only PWM1 can be used, ++ if set to both (default), both PWM0 and PWM1 can be used ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi0 ++ ++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++ ++### spi1 ++ ++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++ ++### spi2 ++ ++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it ++ ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used ++ ++### spi-add-cs1 ++ ++Activates SPI chip select 1 on SPI controller 0 ++This overlay is required for using chip select 1 with other SPI overlays ++ ++SPI 0 CS1 pin: PI14 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number for SPI NOR connected to SPI bus 0 ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number for SPIdev on SPI bus 0 ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3 ++ ++Parameters: ++ ++param_uart3_pins (char) ++ Determines what pins UART 3 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays +new file mode 100644 +index 0000000..3029734 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays +@@ -0,0 +1,250 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun8i-h3 (Allwinner H3) ++ ++### Platform details: ++ ++Supported pin banks: PA, PC, PD, PG ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++### Provided overlays: ++ ++- analog-codec ++- cir ++- i2c0 ++- i2c1 ++- i2c2 ++- pps-gpio ++- pwm ++- spdif-out ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- usbhost0 ++- usbhost1 ++- usbhost2 ++- usbhost3 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++### cir ++ ++Activates CIR (Infrared remote) receiver ++ ++CIR pin: PL11 ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PA11, PA12 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PA18, PA19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PE12, PE13 ++ ++On most board this bus is wired to Camera (CSI) socket ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD14 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pin: PA5 ++ ++Pin PA5 is used as UART0 RX by default, so if this overlay is activated, ++UART0 and kernel console on ttyS0 will be disabled ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PA17 ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another ++overlay ++This overlay is required for using chip select 1 with other SPI overlays ++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but ++it can be changed by using an edited copy of this overlay ++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) ++ ++SPI 0 pins (CS1): PA21 ++SPI 1 pins (CS1): PA10 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### usbhost0 ++ ++Activates USB host controller 0 ++ ++### usbhost1 ++ ++Activates USB host controller 1 ++ ++### usbhost2 ++ ++Activates USB host controller 2 ++ ++### usbhost3 ++ ++Activates USB host controller 3 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD14 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +new file mode 100644 +index 0000000..9254e22 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-can.dts b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +new file mode 100644 +index 0000000..1a9511d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&can0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_ph_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +new file mode 100644 +index 0000000..d80f2fc +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +@@ -0,0 +1,124 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/spi2_cs0@1 phandle ++ fdt set /soc@1c00000/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc@1c00000/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test "${param_pwm_pins}" = "0"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/pwm0@0 ++ fdt set /soc@1c00000/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_pwm_pins}" = "1"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/pwm1@0 ++ fdt set /soc@1c00000/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc@1c00000/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc@1c00000/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart2@0 phandle ++ fdt set /soc@1c00000/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_pins}" = "b"; then ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart3_pins_b phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart3_pins_b_rts_cts phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ else ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart3_pins_b phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++ fi ++else ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart3_pins_a phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart3_pins_a_rts_cts phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ fi ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart4@1 phandle ++ fdt set /soc@1c00000/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +new file mode 100644 +index 0000000..4c104bf +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +new file mode 100644 +index 0000000..1c2c3e9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +new file mode 100644 +index 0000000..f0d4c2f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +@@ -0,0 +1,103 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ function = "nand0"; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ pins = "PC4"; ++ function = "nand0"; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ pins = "PC3"; ++ function = "nand0"; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ pins = "PC17"; ++ function = "nand0"; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ pins = "PC18"; ++ function = "nand0"; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ pins = "PC6"; ++ function = "nand0"; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ pins = "PC7"; ++ function = "nand0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +new file mode 100644 +index 0000000..6031fc5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts +new file mode 100644 +index 0000000..ba88500 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +new file mode 100644 +index 0000000..234dfc8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +new file mode 100644 +index 0000000..ee4ff6f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +new file mode 100644 +index 0000000..5667aec +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts +new file mode 100644 +index 0000000..cad50d8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi0.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts +new file mode 100644 +index 0000000..8c606d6 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts +new file mode 100644 +index 0000000..145f285 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi2.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +new file mode 100644 +index 0000000..89bb44d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a: uart2@0 { ++ pins = "PI16", "PI17", "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +new file mode 100644 +index 0000000..f599d92 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +@@ -0,0 +1,47 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a: uart3@0 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_a_rts_cts: uart3@1 { ++ pins = "PG8", "PG9"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b: uart3@2 { ++ pins = "PH0", "PH1"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b_rts_cts: uart3@3 { ++ pins = "PH2", "PH3"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +new file mode 100644 +index 0000000..b5e562a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc@1c00000/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart4_pins_a: uart4@0 { ++ pins = "PG10", "PG11"; ++ function = "uart4"; ++ }; ++ ++ uart4_pins_b: uart4@1 { ++ pins = "PH4", "PH5"; ++ function = "uart4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +new file mode 100644 +index 0000000..12c3f96 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@1c00000/serial@1c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart5_pins_a: uart5@0 { ++ pins = "PH6", "PH7"; ++ function = "uart5"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +new file mode 100644 +index 0000000..6be41d5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@1c00000/serial@1c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart6_pins_a: uart6@0 { ++ pins = "PI12", "PI13"; ++ function = "uart6"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +new file mode 100644 +index 0000000..967f6af +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@1c00000/serial@1c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart7_pins_a: uart7@0 { ++ pins = "PI20", "PI21"; ++ function = "uart7"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +new file mode 100644 +index 0000000..41da08c +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts +new file mode 100644 +index 0000000..60e2717 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a13"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd +new file mode 100644 +index 0000000..9589767 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-fixup.scr-cmd +@@ -0,0 +1,48 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_uart1_pins}" = "b"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c28400/uart1@1 phandle ++ fdt set /soc@1c00000/serial@1c28400 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart2@0 phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart2-cts-rts@0 phandle ++ fdt set /soc@1c00000/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart3@0 phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart3-cts-rts@0 phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts +new file mode 100644 +index 0000000..444c32c +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts +new file mode 100644 +index 0000000..7a30681 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts +new file mode 100644 +index 0000000..0c5fc89 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-nand.dts +@@ -0,0 +1,60 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, <&nand_rb0_pin>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts +new file mode 100644 +index 0000000..54f5d51 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts +new file mode 100644 +index 0000000..8cebb0b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ spi1 = "/soc/spi@1c06000"; ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts +new file mode 100644 +index 0000000..ced1a0e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ spi1 = "/soc/spi@1c06000"; ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts +new file mode 100644 +index 0000000..b23a754 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi0.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_pins_a: spi0@0 { ++ pins = "PC0", "PC1", "PC2"; ++ function = "spi0"; ++ }; ++ ++ spi0_cs0_pins_a: spi0-cs0@0 { ++ pins = "PC3"; ++ function = "spi0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts +new file mode 100644 +index 0000000..cc0af5d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi1.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ spi1_pins_a: spi1@0 { ++ pins = "PG10", "PG11", "PG12"; ++ function = "spi1"; ++ }; ++ ++ spi1_cs0_pins_a: spi1-cs0@0 { ++ pins = "PG9"; ++ function = "spi1"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ }; ++ }; ++ ++ ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts +new file mode 100644 +index 0000000..6cf5c41 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-spi2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts +new file mode 100644 +index 0000000..6edad42 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart0.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart0 = "/soc@1c00000/serial@1c28000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart0_pa_pins: uart0@0 { ++ pins = "PF2", "PF4"; ++ function = "uart0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pa_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts +new file mode 100644 +index 0000000..675b701 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart1 = "/soc@1c00000/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pe_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts +new file mode 100644 +index 0000000..b3c4e3d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pd_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts +new file mode 100644 +index 0000000..15c25d0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun5i-a13-uart3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun5i-a13"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts +new file mode 100644 +index 0000000..e1a70c5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts +new file mode 100644 +index 0000000..65aebcd +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&can0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +new file mode 100644 +index 0000000..db3cec8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +@@ -0,0 +1,143 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spiflash reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000" ++ test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000" ++ fdt set /soc@1c00000/${tmp_spi_path} status "okay" ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc@1c00000/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/spi2_cs0@1 phandle ++ fdt set /soc@1c00000/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc@1c00000/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test "${param_pwm_pins}" = "0"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/pwm0@0 ++ fdt set /soc@1c00000/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_pwm_pins}" = "1"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/pwm1@0 ++ fdt set /soc@1c00000/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc@1c00000/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test -n "${param_mmc2_cd_pin}"; then ++ setenv tmp_bank "${param_mmc2_cd_pin}" ++ setenv tmp_pin "${param_mmc2_cd_pin}" ++ run decompose_pin ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800 phandle ++ fdt set /soc@1c00000/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>" ++fi ++ ++if test "${param_mmc2_non_removable}" = "1"; then ++ fdt rm /soc@1c00000/mmc@1c11000 cd-gpios ++ fdt set /soc@1c00000/mmc@1c11000 non-removable ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc@1c00000/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart2@0 phandle ++ fdt set /soc@1c00000/serial@1c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_pins}" = "b"; then ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart3_pins_b phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart3_pins_b_rts_cts phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ else ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart3_pins_b phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++ fi ++else ++ if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@1c00000/pinctrl@1c20800/uart3_pins_a_2 phandle ++ fdt get value tmp_phandle2 /soc@1c00000/pinctrl@1c20800/uart3_pins_a_rts_cts phandle ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@1c00000/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++ fi ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc@1c00000/pinctrl@1c20800/uart4@1 phandle ++ fdt set /soc@1c00000/serial@1c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts +new file mode 100644 +index 0000000..c5f6e97 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@1c00000/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts +new file mode 100644 +index 0000000..fa93d1e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@1c00000/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts +new file mode 100644 +index 0000000..945795c +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c3 = "/soc@1c00000/i2c@1c2b800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +new file mode 100644 +index 0000000..4fcf08c +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c4 = "/soc@1c00000/i2c@1c2c000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ i2c4_pins_a: i2c4@0 { ++ pins = "PI2", "PI3"; ++ function = "i2c4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts +new file mode 100644 +index 0000000..1a19a24 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s0.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ i2s0_pins: i2s0 { ++ pins = "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11", "PB12"; ++ function = "i2s0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts +new file mode 100644 +index 0000000..e6f0a22 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2s1.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ i2s1_pins: i2s1 { ++ pins = "PA9", "PA14", "PA15", "PA16", "PA17"; ++ function = "i2s1"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts +new file mode 100644 +index 0000000..ede92f2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-mmc2.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&mmc2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 7 0 1>; /* PH0, active low */ ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts +new file mode 100644 +index 0000000..ffa49cc +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts +@@ -0,0 +1,103 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ function = "nand0"; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ pins = "PC4"; ++ function = "nand0"; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ pins = "PC3"; ++ function = "nand0"; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ pins = "PC17"; ++ function = "nand0"; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ pins = "PC18"; ++ function = "nand0"; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ pins = "PC6"; ++ function = "nand0"; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ pins = "PC7"; ++ function = "nand0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +new file mode 100644 +index 0000000..fe3e2bd +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts +new file mode 100644 +index 0000000..b0cfe4d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-pwm.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts +new file mode 100644 +index 0000000..11a0939 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts +new file mode 100644 +index 0000000..c0a4ba2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-add-cs1.dts +@@ -0,0 +1,16 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ pinctrl-2 = <&spi0_cs1_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts +new file mode 100644 +index 0000000..b91097e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +new file mode 100644 +index 0000000..a3073b2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +@@ -0,0 +1,57 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts +new file mode 100644 +index 0000000..cad50d8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi0.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc@1c00000/spi@1c05000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pi_pins>; ++ pinctrl-1 = <&spi0_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts +new file mode 100644 +index 0000000..f0218eb +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc@1c00000/spi@1c06000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts +new file mode 100644 +index 0000000..effba42 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi2.dts +@@ -0,0 +1,23 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi2 = "/soc@1c00000/spi@1c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi2>; ++ __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pb_pins>; ++ pinctrl-1 = <&spi2_pb_cs0_pin>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts +new file mode 100644 +index 0000000..79d1dca +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc@1c00000/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts +new file mode 100644 +index 0000000..703acbc +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc@1c00000/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a_2: uart3@2 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_a_rts_cts: uart3@1 { ++ pins = "PG8", "PG9"; ++ function = "uart3"; ++ }; ++ ++ uart3_pins_b_rts_cts: uart3@3 { ++ pins = "PH2", "PH3"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts +new file mode 100644 +index 0000000..1918034 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc@1c00000/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pg_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +new file mode 100644 +index 0000000..a1369ee +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@1c00000/serial@1c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +new file mode 100644 +index 0000000..fb9efe2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@1c00000/serial@1c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +new file mode 100644 +index 0000000..bbdca3e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@1c00000/serial@1c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pi_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +new file mode 100644 +index 0000000..7d77606 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts +new file mode 100644 +index 0000000..36dbc31 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts +new file mode 100644 +index 0000000..bf4a0ea +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ir>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd +new file mode 100644 +index 0000000..142b7e5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1_rts_cts phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2_rts_cts phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_rts_cts phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts +new file mode 100644 +index 0000000..a36ac86 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts +new file mode 100644 +index 0000000..258c86d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts +new file mode 100644 +index 0000000..a1e3284 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +new file mode 100644 +index 0000000..16a737b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts +new file mode 100644 +index 0000000..ed3b8e6 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/chosen"; ++ __overlay__ { ++ /delete-property/ stdout-path; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ pwm0_pin: pwm0 { ++ pins = "PA5"; ++ function = "pwm0"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts +new file mode 100644 +index 0000000..35b2d56 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts +new file mode 100644 +index 0000000..bd8e256 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts +new file mode 100644 +index 0000000..95fa5f2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts +new file mode 100644 +index 0000000..575c970 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts +new file mode 100644 +index 0000000..3c10d4d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts +new file mode 100644 +index 0000000..f16e618 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts +new file mode 100644 +index 0000000..b1aef57 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts +new file mode 100644 +index 0000000..6bd8aed +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts +new file mode 100644 +index 0000000..4c7222b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost1.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts +new file mode 100644 +index 0000000..2b83ec9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts +new file mode 100644 +index 0000000..e2f28ab +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&ehci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts +new file mode 100644 +index 0000000..f4ccb7f +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index fa35163..89df4ff 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -31,3 +31,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb ++ ++subdir-y := $(dts-dirs) overlay +diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile +new file mode 100644 +index 0000000..9b6528e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile +@@ -0,0 +1,58 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtbo-$(CONFIG_ARCH_SUNXI) += \ ++ sun50i-a64-i2c0.dtbo \ ++ sun50i-a64-i2c1.dtbo \ ++ sun50i-a64-pps-gpio.dtbo \ ++ sun50i-a64-spi-add-cs1.dtbo \ ++ sun50i-a64-spi-jedec-nor.dtbo \ ++ sun50i-a64-spi-spidev.dtbo \ ++ sun50i-a64-uart1.dtbo \ ++ sun50i-a64-uart2.dtbo \ ++ sun50i-a64-uart3.dtbo \ ++ sun50i-a64-uart4.dtbo \ ++ sun50i-a64-w1-gpio.dtbo \ ++ sun50i-h5-analog-codec.dtbo \ ++ sun50i-h5-cir.dtbo \ ++ sun50i-h5-i2c0.dtbo \ ++ sun50i-h5-i2c1.dtbo \ ++ sun50i-h5-i2c2.dtbo \ ++ sun50i-h5-pps-gpio.dtbo \ ++ sun50i-h5-pwm.dtbo \ ++ sun50i-h5-spdif-out.dtbo \ ++ sun50i-h5-spi-add-cs1.dtbo \ ++ sun50i-h5-spi-jedec-nor.dtbo \ ++ sun50i-h5-spi-spidev.dtbo \ ++ sun50i-h5-uart1.dtbo \ ++ sun50i-h5-uart2.dtbo \ ++ sun50i-h5-uart3.dtbo \ ++ sun50i-h5-usbhost0.dtbo \ ++ sun50i-h5-usbhost1.dtbo \ ++ sun50i-h5-usbhost2.dtbo \ ++ sun50i-h5-usbhost3.dtbo \ ++ sun50i-h5-w1-gpio.dtbo \ ++ sun50i-h6-i2c0.dtbo \ ++ sun50i-h6-i2c1.dtbo \ ++ sun50i-h6-i2c2.dtbo \ ++ sun50i-h6-ruart.dtbo \ ++ sun50i-h6-spi-add-cs1.dtbo \ ++ sun50i-h6-spi-jedec-nor.dtbo \ ++ sun50i-h6-spi-spidev.dtbo \ ++ sun50i-h6-spi-spidev1.dtbo \ ++ sun50i-h6-uart1.dtbo \ ++ sun50i-h6-uart2.dtbo \ ++ sun50i-h6-uart3.dtbo \ ++ sun50i-h6-w1-gpio.dtbo ++ ++scr-$(CONFIG_ARCH_SUNXI) += \ ++ sun50i-a64-fixup.scr \ ++ sun50i-h5-fixup.scr \ ++ sun50i-h6-fixup.scr ++ ++dtbotxt-$(CONFIG_ARCH_SUNXI) += \ ++ README.sun50i-a64-overlays \ ++ README.sun50i-h5-overlays ++ ++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++ ++always := $(dtbo-y) $(scr-y) $(dtbotxt-y) ++clean-files := *.dtbo *.scr +diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +new file mode 100644 +index 0000000..cd9dbc6 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays +@@ -0,0 +1,196 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/Hardware_Allwinner_overlays/ ++ ++### Platform: ++ ++sun50i-a64 (Allwinner A64) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PH ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available ++on supported boards, so this controller is not supported in provided overlays ++ ++### Provided overlays: ++ ++- i2c0 ++- i2c1 ++- pps-gpio ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- w1-gpio ++ ++### Overlay details: ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PH0, PH1 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PH2, PH3 ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD4 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another overlay ++This overlay is required for using chip select 1 with other SPI overlays ++ ++SPI 0 pins (CS1): PB6 ++SPI 1 pins (CS1): PD6 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX): PD0, PD1 ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires external pull-up resistor on data pin ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD4 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays +new file mode 100644 +index 0000000..1ac7fbc +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays +@@ -0,0 +1,250 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/User-Guide_Allwinner_overlays/ ++ ++### Platform: ++ ++sun50i-h5 (Allwinner H5) ++ ++### Platform details: ++ ++Supported pin banks: PA, PC, PD, PG ++ ++Both SPI controllers have only one hardware CS pin exposed, ++adding fixed software (GPIO) chip selects is possible with a separate overlay ++ ++### Provided overlays: ++ ++- analog-codec ++- cir ++- i2c0 ++- i2c1 ++- i2c2 ++- pps-gpio ++- pwm ++- spdif-out ++- spi-add-cs1 ++- spi-jedec-nor ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- usbhost0 ++- usbhost1 ++- usbhost2 ++- usbhost3 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++### cir ++ ++Activates CIR (Infrared remote) receiver ++ ++CIR pin: PL11 ++ ++### i2c0 ++ ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PA11, PA12 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PA18, PA19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PE12, PE13 ++ ++On most board this bus is wired to Camera (CSI) socket ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD14 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### pwm ++ ++Activates hardware PWM controller ++ ++PWM pin: PA5 ++ ++Pin PA5 is used as UART0 RX by default, so if this overlay is activated, ++UART0 and kernel console on ttyS0 will be disabled ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PA17 ++ ++### spi-add-cs1 ++ ++Adds support for using SPI chip select 1 with GPIO for both SPI controllers ++Respective GPIO will be claimed only if controller is enabled by another ++overlay ++This overlay is required for using chip select 1 with other SPI overlays ++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but ++it can be changed by using an edited copy of this overlay ++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO) ++ ++SPI 0 pins (CS1): PA21 ++SPI 1 pins (CS1): PA10 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1 ++ ++param_spinor_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number ++ ++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 ++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 ++ ++Parameters: ++ ++param_spidev_spi_bus (int) ++ SPI bus to activate SPIdev support on ++ Required ++ Supported values: 0, 1 ++ ++param_spidev_spi_cs (int) ++ SPI chip select number ++ Optional ++ Default: 0 ++ Supported values: 0, 1 ++ Using chip select 1 requires using "spi-add-cs1" overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart1 ++ ++Activates serial port 1 (/dev/ttyS1) ++ ++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart1_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### usbhost0 ++ ++Activates USB host controller 0 ++ ++### usbhost1 ++ ++Activates USB host controller 1 ++ ++### usbhost2 ++ ++Activates USB host controller 2 ++ ++### usbhost3 ++ ++Activates USB host controller 3 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires an external pull-up resistor on the data pin ++or enabling the internal pull-up ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PD14 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd +new file mode 100644 +index 0000000..36df83c +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd +@@ -0,0 +1,95 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|H)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"; ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>"; ++ fi ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1_rts_cts_pins phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2_rts_cts_pins phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart4_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart4 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart4_rts_cts phandle ++ fdt set /soc/serial@1c29000 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c29000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts +new file mode 100644 +index 0000000..37bdb2c +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ i2c0_pins: i2c0_pins { ++ pins = "PH0", "PH1"; ++ function = "i2c0"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts +new file mode 100644 +index 0000000..b2483c9 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts +new file mode 100644 +index 0000000..5fa161c +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD4"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 4 0>; /* PD4 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts +new file mode 100644 +index 0000000..4432aac +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PB6"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 1 6 0>; /* PB6 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 3 6 0>; /* PD6 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts +new file mode 100644 +index 0000000..31d73e5 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dts +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts +new file mode 100644 +index 0000000..70d90a2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts +new file mode 100644 +index 0000000..4d8dac1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts +new file mode 100644 +index 0000000..36475fd +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins: uart2_pins { ++ pins = "PB0", "PB1"; ++ function = "uart2"; ++ }; ++ ++ uart2_rts_cts_pins: uart2_rts_cts_pins { ++ pins = "PB2", "PB3"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts +new file mode 100644 +index 0000000..a103a75 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins: uart3_pins { ++ pins = "PD0", "PD1"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts +new file mode 100644 +index 0000000..6e4702b +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dts +@@ -0,0 +1,37 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc/serial@1c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart4_pins: uart4_pins { ++ pins = "PD2", "PD3"; ++ function = "uart4"; ++ }; ++ ++ uart4_rts_cts_pins: uart4_rts_cts_pins { ++ pins = "PD4", "PD5"; ++ function = "uart4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts +new file mode 100644 +index 0000000..d230469 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-a64"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD4"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 4 0>; /* PD4 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts +new file mode 100644 +index 0000000..aaa66d5 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT", ++ "MIC1", "Mic", ++ "Mic", "MBIAS"; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts +new file mode 100644 +index 0000000..90c264a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ir>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd +new file mode 100644 +index 0000000..f7b89ae +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1_rts_cts phandle ++ fdt set /soc/serial@1c28400 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2_rts_cts phandle ++ fdt set /soc/serial@1c28800 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_rts_cts phandle ++ fdt set /soc/serial@1c28c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts +new file mode 100644 +index 0000000..87fbd7e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@1c2ac00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts +new file mode 100644 +index 0000000..6008b9a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@1c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts +new file mode 100644 +index 0000000..2980dbf +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@1c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts +new file mode 100644 +index 0000000..46e0675 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts +new file mode 100644 +index 0000000..6d12e84 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dts +@@ -0,0 +1,39 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/chosen"; ++ __overlay__ { ++ /delete-property/ stdout-path; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ pwm0_pin: pwm0 { ++ pins = "PA5"; ++ function = "pwm0"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pin>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts +new file mode 100644 +index 0000000..65bc51b +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pin>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts +new file mode 100644 +index 0000000..8e3eab2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts +new file mode 100644 +index 0000000..5a45808 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts +new file mode 100644 +index 0000000..9b5b0f2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@1c68000"; ++ spi1 = "/soc/spi@1c69000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts +new file mode 100644 +index 0000000..92e3eb4 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@1c28400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts +new file mode 100644 +index 0000000..521a01d +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@1c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_rts_cts: uart2_rts_cts { ++ pins = "PA2", "PA3"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts +new file mode 100644 +index 0000000..639e15d +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@1c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_rts_cts: uart3_rts_cts { ++ pins = "PA15", "PA16"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts +new file mode 100644 +index 0000000..c1d79c2 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts +new file mode 100644 +index 0000000..2b4f245 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts +new file mode 100644 +index 0000000..54800e7 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts +new file mode 100644 +index 0000000..a99524e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dts +@@ -0,0 +1,27 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&ehci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ohci3>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&usbphy>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts +new file mode 100644 +index 0000000..6e99626 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h5"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +new file mode 100644 +index 0000000..5f00458 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd +@@ -0,0 +1,110 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "A" && setenv tmp_bank 0; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6' ++ ++if test -n "${param_spinor_spi_bus}"; then ++ test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay" ++ if test -n "${param_spinor_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>" ++ fi ++ if test "${param_spinor_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spidev_spi_bus}"; then ++ test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000" ++ test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000" ++ fdt set /soc/${tmp_spi_path} status "okay" ++ fdt set /soc/${tmp_spi_path}/spidev status "okay" ++ if test -n "${param_spidev_max_freq}"; then ++ fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ fi ++ if test "${param_spidev_spi_cs}" = "1"; then ++ fdt set /soc/${tmp_spi_path}/spidev reg "<1>" ++ fi ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++for f in ${overlays}; do ++ if test "${f}" = "pwm"; then ++ setenv bootargs_new "" ++ for arg in ${bootargs}; do ++ if test "${arg}" = "console=ttyS0,115200"; then ++ echo "Warning: Disabling ttyS0 console due to enabled PWM overlay" ++ else ++ setenv bootargs_new "${bootargs_new} ${arg}" ++ fi ++ done ++ setenv bootargs "${bootargs_new}" ++ fi ++done ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@300b000 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart1_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1_rts_cts phandle ++ fdt set /soc/serial@5000400 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2_rts_cts phandle ++ fdt set /soc/serial@5000800 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3 phandle ++ fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3_rts_cts phandle ++ fdt set /soc/serial@5000c00 pinctrl-names "default" "default" ++ fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts +new file mode 100644 +index 0000000..7e7ee8c +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc/i2c@5002000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts +new file mode 100644 +index 0000000..1117698 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc/i2c@5002400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts +new file mode 100644 +index 0000000..b627529 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dts +@@ -0,0 +1,20 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc/i2c@5002800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts +new file mode 100644 +index 0000000..6430cb0 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&r_uart>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts +new file mode 100644 +index 0000000..0fa060f +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dts +@@ -0,0 +1,41 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ spi0_cs1: spi0_cs1 { ++ pins = "PA10"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ ++ spi1_cs1: spi1_cs1 { ++ pins = "PA21"; ++ function = "gpio_out"; ++ output-high; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi0_cs1>; ++ cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-1 = <&spi1_cs1>; ++ cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */ ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts +new file mode 100644 +index 0000000..4f81dbb +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts +new file mode 100644 +index 0000000..bac3adc +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@5010000"; ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts +new file mode 100644 +index 0000000..e194484 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts +@@ -0,0 +1,30 @@ ++// Enable the spidev interface ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ /* Path to the SPI controller nodes */ ++ spi1 = "/soc/spi@5011000"; ++ }; ++ }; ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev@0 { ++ compatible = "spidev"; ++ reg = <0x0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts +new file mode 100644 +index 0000000..44aa94e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial1 = "/soc/serial@5000400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts +new file mode 100644 +index 0000000..7a1860e +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial2 = "/soc/serial@5000800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_rts_cts: uart2_rts_cts { ++ pins = "PD21", "PD22"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts +new file mode 100644 +index 0000000..770219a +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dts +@@ -0,0 +1,32 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial3 = "/soc/serial@5000c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_rts_cts: uart3_rts_cts { ++ pins = "PD25", "PD26"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts +new file mode 100644 +index 0000000..3043c87 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dts +@@ -0,0 +1,29 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "allwinner,sun50i-h6"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PC9"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 2 9 0>; /* PC9 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 26e6af4..65b9435 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -65,6 +65,9 @@ real-objs-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y) + extra-y += $(dtb-y) + extra-$(CONFIG_OF_ALL_DTBS) += $(dtb-) + ++# Overlay targets ++extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) ++ + # Add subdir path + + extra-y := $(addprefix $(obj)/,$(extra-y)) + diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/files/0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch b/layers/meta-balena-allwinner/recipes-kernel/linux/files/nanopi-neo-air/0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch similarity index 100% rename from layers/meta-balena-allwinner/recipes-kernel/linux/files/0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch rename to layers/meta-balena-allwinner/recipes-kernel/linux/files/nanopi-neo-air/0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/files/nanopi-neo-air/board-nanopiair-h3-camera-wifi-bluetooth-otg.patch b/layers/meta-balena-allwinner/recipes-kernel/linux/files/nanopi-neo-air/board-nanopiair-h3-camera-wifi-bluetooth-otg.patch new file mode 100644 index 0000000..f19a6fa --- /dev/null +++ b/layers/meta-balena-allwinner/recipes-kernel/linux/files/nanopi-neo-air/board-nanopiair-h3-camera-wifi-bluetooth-otg.patch @@ -0,0 +1,175 @@ +diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +index 6246d3ef..a2b6e0b2 100644 +--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts ++++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +@@ -75,10 +75,69 @@ + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en_npi>; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ post-power-on-delay-ms = <200>; + }; ++ rfkill_bt { ++ compatible = "rfkill-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_pwr_pin>; ++ reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ ++ clocks = <&osc32k>; ++ clock-frequency = <32768>; ++ rfkill-name = "sunxi-bt"; ++ rfkill-type = "bluetooth"; ++ }; ++ ++ cam_xclk: cam-xclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "cam-xclk"; ++ }; ++ ++ reg_cam_avdd: cam-avdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-avdd"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dovdd: cam-dovdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-dovdd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ reg_cam_dvdd: cam-dvdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam500b-dvdd"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ vin-supply = <®_vcc3v3>; ++ }; ++ + }; + ++&pio { ++ bt_pwr_pin: bt_pwr_pin@0 { ++ pins = "PG13"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&r_pio { ++ wifi_en_npi: wifi_en_pin { ++ pins = "PL7"; ++ function = "gpio_out"; ++ }; ++ }; ++ + &mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; +@@ -103,12 +162,100 @@ + }; + }; + ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ drive-strength = <40>; ++ /* eMMC is missing pull-ups */ ++ bias-pull-up; ++}; ++ ++&csi { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Parallel bus endpoint */ ++ csi_from_ov5640: endpoint { ++ remote-endpoint = <&ov5640_to_csi>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ clocks = <&cam_xclk>; ++ clock-names = "xclk"; ++ ++ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; ++ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; ++ AVDD-supply = <®_cam_avdd>; ++ DOVDD-supply = <®_cam_dovdd>; ++ DVDD-supply = <®_cam_dvdd>; ++ ++ port { ++ ov5640_to_csi: endpoint { ++ remote-endpoint = <&csi_from_ov5640>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++ }; ++}; ++ ++&i2c2_pins { ++ bias-pull-up; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; + }; + ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ + &usbphy { + /* USB VBUS is always on */ + status = "okay"; diff --git a/layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline_%.bbappend b/layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline_%.bbappend index 2ca4047..0a6a397 100644 --- a/layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline_%.bbappend +++ b/layers/meta-balena-allwinner/recipes-kernel/linux/linux-mainline_%.bbappend @@ -7,7 +7,16 @@ SRC_URI_remove = "file://0003-ARM-dts-nanopi-neo-air-Add-WiFi-eMMC.patch" FILESEXTRAPATHS_prepend := "${THISDIR}/files:" -SRC_URI_append_nanopi-neo-air = " file://0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch" +SRC_URI_append_nanopi-neo-air = " \ + file://nanopi-neo-air/0001-linux-mainline-Add-back-eMMC-support-for-Nanopi-Neo-.patch \ + file://nanopi-neo-air/board-nanopiair-h3-camera-wifi-bluetooth-otg.patch \ +" + +SRC_URI_append = " \ + file://general-add-configfs-overlay.patch \ + file://general-add-overlay-compilation-support.patch \ + file://general-sunxi-overlays.patch \ +" RESIN_CONFIGS_append = " axp_power" RESIN_CONFIGS_DEPS[axp_power] = "\