diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 01180849..81523d5a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1016,4 +1017,7 @@ dtstree		:= $(srctree)/$(src)
 dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
 
 always		:= $(dtb-y)
+subdir-y	:= overlay
 clean-files	:= *.dtb
+
+dts-dirs += overlay
diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
new file mode 100644
index 00000000..f9ca2574
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/Makefile
@@ -0,0 +1,28 @@
+dtbo-$(CONFIG_MACH_SUN8I) += \
+	sun8i-h3-analog-codec.dtbo \
+	sun8i-h3-cir.dtbo \
+	sun8i-h3-i2c0.dtbo \
+	sun8i-h3-i2c1.dtbo \
+	sun8i-h3-i2c2.dtbo \
+	sun8i-h3-pps-gpio.dtbo \
+	sun8i-h3-pwm.dtbo \
+	sun8i-h3-spdif-out.dtbo \
+	sun8i-h3-spi-add-cs1.dtbo \
+	sun8i-h3-spi-jedec-nor.dtbo \
+	sun8i-h3-spi-spidev.dtbo \
+	sun8i-h3-uart1.dtbo \
+	sun8i-h3-uart2.dtbo \
+	sun8i-h3-uart3.dtbo \
+	sun8i-h3-usbhost0.dtbo \
+	sun8i-h3-usbhost2.dtbo \
+	sun8i-h3-usbhost3.dtbo \
+	sun8i-h3-w1-gpio.dtbo
+
+scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
+
+dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
+
+targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
+
+always		:= $(dtbo-y) $(scr-y) $(dtbotxt-y)
+clean-files	:= *.dtbo *.scr
diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
new file mode 100644
index 00000000..0ae207a1
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays
@@ -0,0 +1,245 @@
+This document describes overlays provided in the kernel packages
+For generic Armbian overlays documentation please see
+https://docs.armbian.com/User-Guide_Allwinner_overlays/
+
+### Platform:
+
+sun8i-h3 (Allwinner H3)
+
+### Platform details:
+
+Supported pin banks: PA, PC, PD, PG
+
+Both SPI controllers have only one hardware CS pin exposed,
+adding fixed software (GPIO) chip selects is possible with a separate overlay
+
+### Provided overlays:
+
+- analog-codec
+- cir
+- i2c0
+- i2c1
+- i2c2
+- pps-gpio
+- pwm
+- spdif-out
+- spi-add-cs1
+- spi-jedec-nor
+- spi-spidev
+- uart1
+- uart2
+- uart3
+- usbhost0
+- usbhost2
+- usbhost3
+- w1-gpio
+
+### Overlay details:
+
+### analog-codec
+
+Activates SoC analog codec driver that provides Line Out and Mic In
+functionality
+
+### cir
+
+Activates CIR (Infrared remote) receiver
+
+CIR pin: PL11
+
+### i2c0
+
+Activates TWI/I2C bus 0
+
+I2C0 pins (SCL, SDA): PA11, PA12
+
+### i2c1
+
+Activates TWI/I2C bus 1
+
+I2C1 pins (SCL, SDA): PA18, PA19
+
+### i2c2
+
+Activates TWI/I2C bus 2
+
+I2C2 pins (SCL, SDA): PE12, PE13
+
+On most board this bus is wired to Camera (CSI) socket
+
+### pps-gpio
+
+Activates pulse-per-second GPIO client
+
+Parameters:
+
+param_pps_pin (pin)
+	Pin PPS source is connected to
+	Optional
+	Default: PD14
+
+param_pps_falling_edge (bool)
+	Assert by falling edge
+	Optional
+	Default: 0
+	When set (to 1), assert is indicated by a falling edge
+		(instead of by a rising edge)
+
+### pwm
+
+Activates hardware PWM controller
+
+PWM pin: PA5
+
+Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
+UART0 and kernel console on ttyS0 will be disabled
+
+### spdif-out
+
+Activates SPDIF/Toslink audio output
+
+SPDIF pin: PA17
+
+### spi-add-cs1
+
+Adds support for using SPI chip select 1 with GPIO for both SPI controllers
+Respective GPIO will be claimed only if controller is enabled by another
+overlay
+This overlay is required for using chip select 1 with other SPI overlays
+Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
+it can be changed by using an edited copy of this overlay
+A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
+
+SPI 0 pins (CS1): PA21
+SPI 1 pins (CS1): PA10
+
+### spi-jedec-nor
+
+Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
+supported by the kernel SPI NOR driver
+
+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
+
+Parameters:
+
+param_spinor_spi_bus (int)
+	SPI bus to activate SPI NOR flash support on
+	Required
+	Supported values: 0, 1
+
+param_spinor_spi_cs (int)
+	SPI chip select number
+	Optional
+	Default: 0
+	Supported values: 0, 1
+	Using chip select 1 requires using "spi-add-cs1" overlay
+
+param_spinor_max_freq (int)
+	Maximum SPI frequency
+	Optional
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### spi-spidev
+
+Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
+where X is the bus number and Y is the CS number
+
+SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
+SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
+
+Parameters:
+
+param_spidev_spi_bus (int)
+	SPI bus to activate SPIdev support on
+	Required
+	Supported values: 0, 1
+
+param_spidev_spi_cs (int)
+	SPI chip select number
+	Optional
+	Default: 0
+	Supported values: 0, 1
+	Using chip select 1 requires using "spi-add-cs1" overlay
+
+param_spidev_max_freq (int)
+	Maximum SPIdev frequency
+	Optional
+	Default: 1000000
+	Range: 3000 - 100000000
+
+### uart1
+
+Activates serial port 1 (/dev/ttyS1)
+
+UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
+
+Parameters:
+
+param_uart1_rtscts (bool)
+	Enable RTS and CTS pins
+	Optional
+	Default: 0
+	Set to 1 to enable
+
+### uart2
+
+Activates serial port 2 (/dev/ttyS2)
+
+UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
+
+Parameters:
+
+param_uart2_rtscts (bool)
+	Enable RTS and CTS pins
+	Optional
+	Default: 0
+	Set to 1 to enable CTS and RTS pins
+
+### uart3
+
+Activates serial port 3 (/dev/ttyS3)
+
+UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
+
+Parameters:
+
+param_uart3_rtscts (bool)
+	Enable RTS and CTS pins
+	Optional
+	Default: 0
+	Set to 1 to enable CTS and RTS pins
+
+### usbhost0
+
+Activates USB host controller 0
+
+### usbhost2
+
+Activates USB host controller 2
+
+### usbhost3
+
+Activates USB host controller 3
+
+### w1-gpio
+
+Activates 1-Wire GPIO master
+Requires an external pull-up resistor on the data pin
+or enabling the internal pull-up
+
+Parameters:
+
+param_w1_pin (pin)
+	Data pin for 1-Wire master
+	Optional
+	Default: PD14
+
+param_w1_pin_int_pullup (bool)
+	Enable internal pull-up for the data pin
+	Optional
+	Default: 0
+	Set to 1 to enable the pull-up
+	This option should not be used with multiple devices, parasite power setup
+		or long wires -	please use external pull-up resistor instead
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
new file mode 100644
index 00000000..36dbc31a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&codec>;
+		__overlay__ {
+			allwinner,audio-routing =
+				"Line Out", "LINEOUT",
+				"MIC1", "Mic",
+				"Mic",  "MBIAS";
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
new file mode 100644
index 00000000..9b62fd2b
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-cir.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&ir>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&ir_pins_a>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
new file mode 100644
index 00000000..744889c6
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd
@@ -0,0 +1,110 @@
+# overlays fixup script
+# implements (or rather substitutes) overlay arguments functionality
+# using u-boot scripting, environment variables and "fdt" command
+
+# setexpr test_var ${tmp_bank} - A
+# works only for hex numbers (A-F)
+
+setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
+setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
+test "${tmp_bank}" = "A" && setenv tmp_bank 0;
+test "${tmp_bank}" = "C" && setenv tmp_bank 2;
+test "${tmp_bank}" = "D" && setenv tmp_bank 3;
+test "${tmp_bank}" = "G" && setenv tmp_bank 6'
+
+if test -n "${param_spinor_spi_bus}"; then
+	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
+	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
+	fdt set /soc/${tmp_spi_path} status "okay"
+	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
+	if test -n "${param_spinor_max_freq}"; then
+		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
+	fi
+	if test "${param_spinor_spi_cs}" = "1"; then
+		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
+	fi
+	env delete tmp_spi_path
+fi
+
+if test -n "${param_spidev_spi_bus}"; then
+	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@01c68000"
+	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@01c69000"
+	fdt set /soc/${tmp_spi_path} status "okay"
+	fdt set /soc/${tmp_spi_path}/spidev status "okay"
+	if test -n "${param_spidev_max_freq}"; then
+		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
+	fi
+	if test "${param_spidev_spi_cs}" = "1"; then
+		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
+	fi
+	env delete tmp_spi_path
+fi
+
+if test -n "${param_pps_pin}"; then
+	setenv tmp_bank "${param_pps_pin}"
+	setenv tmp_pin "${param_pps_pin}"
+	run decompose_pin
+	fdt set /soc/pinctrl@01c20800/pps_pins pins "${param_pps_pin}"
+	fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
+	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
+	env delete tmp_pin tmp_bank tmp_phandle
+fi
+
+if test "${param_pps_falling_edge}" = "1"; then
+	fdt set /pps@0 assert-falling-edge
+fi
+
+for f in ${overlays}; do
+	if test "${f}" = "pwm"; then
+		setenv bootargs_new ""
+		for arg in ${bootargs}; do
+			if test "${arg}" = "console=ttyS0,115200"; then
+				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
+			else
+				setenv bootargs_new "${bootargs_new} ${arg}"
+			fi
+		done
+		setenv bootargs "${bootargs_new}"
+	fi
+done
+
+if test -n "${param_w1_pin}"; then
+	setenv tmp_bank "${param_w1_pin}"
+	setenv tmp_pin "${param_w1_pin}"
+	run decompose_pin
+	fdt set /soc/pinctrl@01c20800/w1_pins pins "${param_w1_pin}"
+	fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle
+	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
+	env delete tmp_pin tmp_bank tmp_phandle
+fi
+
+if test "${param_w1_pin_int_pullup}" = "1"; then
+	fdt set /soc/pinctrl@01c20800/w1_pins bias-pull-up
+fi
+
+if test "${param_uart1_rtscts}" = "1"; then
+	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart1 phandle
+	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart1_rts_cts phandle
+	fdt set /soc/serial@01c28400 pinctrl-names "default" "default"
+	fdt set /soc/serial@01c28400 pinctrl-0 "<${tmp_phandle1}>"
+	fdt set /soc/serial@01c28400 pinctrl-1 "<${tmp_phandle2}>"
+	env delete tmp_phandle1 tmp_phandle2
+fi
+
+if test "${param_uart2_rtscts}" = "1"; then
+	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart2 phandle
+	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart2_rts_cts phandle
+	fdt set /soc/serial@01c28800 pinctrl-names "default" "default"
+	fdt set /soc/serial@01c28800 pinctrl-0 "<${tmp_phandle1}>"
+	fdt set /soc/serial@01c28800 pinctrl-1 "<${tmp_phandle2}>"
+	env delete tmp_phandle1 tmp_phandle2
+fi
+
+if test "${param_uart3_rtscts}" = "1"; then
+	fdt get value tmp_phandle1 /soc/pinctrl@01c20800/uart3 phandle
+	fdt get value tmp_phandle2 /soc/pinctrl@01c20800/uart3_rts_cts phandle
+	fdt set /soc/serial@01c28c00 pinctrl-names "default" "default"
+	fdt set /soc/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>"
+	fdt set /soc/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>"
+	env delete tmp_phandle1 tmp_phandle2
+fi
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
new file mode 100644
index 00000000..b457ac71
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c0.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c0 = "/soc/i2c@01c2ac00";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c0>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
new file mode 100644
index 00000000..fd0928a1
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c1.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c1 = "/soc/i2c@01c2b000";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
new file mode 100644
index 00000000..25b75b71
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-i2c2.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			i2c2 = "/soc/i2c@01c2b400";
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c2>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
new file mode 100644
index 00000000..16a737b0
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			pps_pins: pps_pins {
+				pins = "PD14";
+				function = "gpio_in";
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+			pps@0 {
+				compatible = "pps-gpio";
+				pinctrl-names = "default";
+				pinctrl-0 = <&pps_pins>;
+				gpios = <&pio 3 14 0>; /* PD14 */
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
new file mode 100644
index 00000000..ed3b8e60
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-pwm.dts
@@ -0,0 +1,39 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/chosen";
+		__overlay__ {
+			/delete-property/ stdout-path;
+		};
+	};
+
+	fragment@1 {
+		target = <&uart0>;
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@2 {
+		target = <&pio>;
+		__overlay__ {
+			pwm0_pin: pwm0 {
+				pins = "PA5";
+				function = "pwm0";
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&pwm>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm0_pin>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
new file mode 100644
index 00000000..c7c01411
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spdif-out.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&spdif>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&spdif_tx_pins_a>;
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+			sound {
+				compatible = "simple-audio-card";
+				simple-audio-card,name = "On-board SPDIF";
+
+				simple-audio-card,cpu {
+					sound-dai = <&spdif>;
+				};
+
+				simple-audio-card,codec {
+					sound-dai = <&spdif_out>;
+				};
+			};
+
+			spdif_out: spdif-out {
+				#sound-dai-cells = <0>;
+				compatible = "linux,spdif-dit";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
new file mode 100644
index 00000000..bd8e2561
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-add-cs1.dts
@@ -0,0 +1,41 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			spi0_cs1: spi0_cs1 {
+				pins = "PA21";
+				function = "gpio_out";
+				output-high;
+			};
+
+			spi1_cs1: spi1_cs1 {
+				pins = "PA10";
+				function = "gpio_out";
+				output-high;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-1 = <&spi0_cs1>;
+			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			pinctrl-names = "default", "default";
+			pinctrl-1 = <&spi1_cs1>;
+			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
new file mode 100644
index 00000000..ad22a71a
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/soc/spi@01c68000";
+			spi1 = "/soc/spi@01c69000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spiflash {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
new file mode 100644
index 00000000..180979e0
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			spi0 = "/soc/spi@01c68000";
+			spi1 = "/soc/spi@01c69000";
+		};
+	};
+
+	fragment@1 {
+		target = <&spi0>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "spidev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&spi1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			spidev {
+				compatible = "spidev";
+				status = "disabled";
+				reg = <0>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
new file mode 100644
index 00000000..8a4f7e49
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart1.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial1 = "/soc/serial@01c28400";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart1>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart1_pins>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
new file mode 100644
index 00000000..499a1b49
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial2 = "/soc/serial@01c28800";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart2>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_pins>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
new file mode 100644
index 00000000..b5734c5b
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart3.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target-path = "/aliases";
+		__overlay__ {
+			serial3 = "/soc/serial@01c28c00";
+		};
+	};
+
+	fragment@1 {
+		target = <&uart3>;
+		 __overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart3_pins>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
new file mode 100644
index 00000000..ff1d82fd
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost0.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&ehci0>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&ohci0>;
+		 __overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
new file mode 100644
index 00000000..bf0c4f59
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost2.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&ehci2>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&ohci2>;
+		 __overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
new file mode 100644
index 00000000..f737075b
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-usbhost3.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&ehci3>;
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target = <&ohci3>;
+		 __overlay__ {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
new file mode 100644
index 00000000..f4ccb7fb
--- /dev/null
+++ b/arch/arm/boot/dts/overlay/sun8i-h3-w1-gpio.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+
+	fragment@0 {
+		target = <&pio>;
+		__overlay__ {
+			w1_pins: w1_pins {
+				pins = "PD14";
+				function = "gpio_in";
+			};
+		};
+	};
+
+	fragment@1 {
+		target-path = "/";
+		__overlay__ {
+			onewire@0 {
+				compatible = "w1-gpio";
+				pinctrl-names = "default";
+				pinctrl-0 = <&w1_pins>;
+				gpios = <&pio 3 14 0>; /* PD14 */
+				status = "okay";
+			};
+		};
+	};
+};
