From 0ab580b2eac299d7f73c2ff3e7bf590a3fc7ea6d Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Fri, 20 Apr 2018 04:05:28 +0200
Subject: [PATCH 68/82] ARM: dts: sun8i-a83t: Add clock-frequency to avoid boot
 warnings

Signed-off-by: Ondrej Jirman <megous@megous.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index bffcee058627..c09d8ee2f7c5 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -65,6 +65,7 @@
 			clocks = <&ccu CLK_C0CPUX>;
 			clock-names = "cpu";
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
@@ -77,6 +78,7 @@
 
 		cpu@1 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
@@ -86,6 +88,7 @@
 
 		cpu@2 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
@@ -95,6 +98,7 @@
 
 		cpu@3 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			cci-control-port = <&cci_control0>;
@@ -106,6 +110,7 @@
 			clocks = <&ccu CLK_C1CPUX>;
 			clock-names = "cpu";
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
@@ -118,6 +123,7 @@
 
 		cpu@101 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
@@ -127,6 +133,7 @@
 
 		cpu@102 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
@@ -136,6 +143,7 @@
 
 		cpu@103 {
 			compatible = "arm,cortex-a7";
+			clock-frequency = <1200000000>;
 			device_type = "cpu";
 			operating-points-v2 = <&cpu1_opp_table>;
 			cci-control-port = <&cci_control1>;
-- 
2.20.1

