209 lines
12 KiB
C++
209 lines
12 KiB
C++
#ifndef _KITELIB_SX127X_H
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#define _KITELIB_SX127X_H
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#include "TypeDef.h"
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#include "Module.h"
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// SX127x series common registers
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#define SX127X_REG_FIFO 0x00
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#define SX127X_REG_OP_MODE 0x01
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#define SX127X_REG_FRF_MSB 0x06
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#define SX127X_REG_FRF_MID 0x07
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#define SX127X_REG_FRF_LSB 0x08
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#define SX127X_REG_PA_CONFIG 0x09
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#define SX127X_REG_PA_RAMP 0x0A
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#define SX127X_REG_OCP 0x0B
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#define SX127X_REG_LNA 0x0C
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#define SX127X_REG_FIFO_ADDR_PTR 0x0D
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#define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
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#define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
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#define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
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#define SX127X_REG_IRQ_FLAGS_MASK 0x11
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#define SX127X_REG_IRQ_FLAGS 0x12
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#define SX127X_REG_RX_NB_BYTES 0x13
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#define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
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#define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
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#define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
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#define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
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#define SX127X_REG_MODEM_STAT 0x18
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#define SX127X_REG_PKT_SNR_VALUE 0x19
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#define SX127X_REG_PKT_RSSI_VALUE 0x1A
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#define SX127X_REG_RSSI_VALUE 0x1B
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#define SX127X_REG_HOP_CHANNEL 0x1C
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#define SX127X_REG_MODEM_CONFIG_1 0x1D
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#define SX127X_REG_MODEM_CONFIG_2 0x1E
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#define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
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#define SX127X_REG_PREAMBLE_MSB 0x20
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#define SX127X_REG_PREAMBLE_LSB 0x21
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#define SX127X_REG_PAYLOAD_LENGTH 0x22
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#define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
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#define SX127X_REG_HOP_PERIOD 0x24
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#define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
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#define SX127X_REG_FEI_MSB 0x28
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#define SX127X_REG_FEI_MID 0x29
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#define SX127X_REG_FEI_LSB 0x2A
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#define SX127X_REG_RSSI_WIDEBAND 0x2C
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#define SX127X_REG_DETECT_OPTIMIZE 0x31
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#define SX127X_REG_INVERT_IQ 0x33
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#define SX127X_REG_DETECTION_THRESHOLD 0x37
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#define SX127X_REG_SYNC_WORD 0x39
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#define SX127X_REG_DIO_MAPPING_1 0x40
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#define SX127X_REG_DIO_MAPPING_2 0x41
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#define SX127X_REG_VERSION 0x42
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// SX127x common modem settings
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// SX127X_REG_OP_MODE MSB LSB DESCRIPTION
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#define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
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#define SX127X_LORA 0b10000000 // 7 7 LoRa mode
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#define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
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#define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
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#define SX127X_SLEEP 0b00000000 // 2 0 sleep
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#define SX127X_STANDBY 0b00000001 // 2 0 standby
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#define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
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#define SX127X_TX 0b00000011 // 2 0 transmit
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#define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
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#define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
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#define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
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#define SX127X_CAD 0b00000111 // 2 0 channel activity detection
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// SX127X_REG_PA_CONFIG
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#define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
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#define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
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#define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
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// P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
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// SX127X_REG_OCP
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#define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
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#define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
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#define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
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// SX127X_REG_LNA
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#define SX127X_LNA_GAIN_0 0b00000000 // 7 5 LNA gain setting: not used
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#define SX127X_LNA_GAIN_1 0b00100000 // 7 5 max gain
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#define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
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#define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
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#define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
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#define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
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#define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
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#define SX127X_LNA_GAIN_7 0b11100000 // 7 5 not used
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#define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
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#define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
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// SX127X_REG_MODEM_CONFIG_2
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#define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
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#define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
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#define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
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#define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
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#define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
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#define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
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#define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
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#define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
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#define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
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#define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
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// SX127X_REG_SYMB_TIMEOUT_LSB
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#define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
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// SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
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#define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
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#define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
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// SX127X_REG_DETECT_OPTIMIZE
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#define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
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#define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
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// SX127X_REG_DETECTION_THRESHOLD
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#define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
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#define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
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// SX127X_REG_PA_DAC
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#define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
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#define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
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// SX127X_REG_HOP_PERIOD
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#define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
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#define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
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// SX127X_REG_DIO_MAPPING_1
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#define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
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#define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
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#define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
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#define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
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#define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
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#define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
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// SX127X_REG_IRQ_FLAGS
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#define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
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#define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
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#define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
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#define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
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#define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
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#define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
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#define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
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#define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
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// SX127X_REG_IRQ_FLAGS_MASK
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#define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
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#define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
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#define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
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#define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
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#define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
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#define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
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#define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
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#define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
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// SX127X_REG_FIFO_TX_BASE_ADDR
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#define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
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// SX127X_REG_FIFO_RX_BASE_ADDR
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#define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
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// SX127X_REG_SYNC_WORD
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#define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
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#define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
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class SX127x {
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public:
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// constructor
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SX127x(Module* mod);
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// public member variables
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float dataRate;
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int8_t lastPacketRSSI;
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float lastPacketSNR;
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// basic methods
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uint8_t begin(uint8_t syncWord);
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uint8_t transmit(uint8_t* data, size_t len);
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uint8_t transmit(const char* str);
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uint8_t transmit(String& str);
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uint8_t receive(uint8_t* data, size_t len);
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uint8_t receive(String& str, size_t len = 0);
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uint8_t scanChannel();
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uint8_t sleep();
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uint8_t standby();
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// configuration methods
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uint8_t setSyncWord(uint8_t syncWord);
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protected:
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Module* _mod;
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float _freq;
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float _bw;
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uint8_t _sf;
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uint8_t _cr;
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uint8_t _syncWord;
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int8_t _power;
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uint8_t tx(char* data, uint8_t length);
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uint8_t rxSingle(char* data, uint8_t* length);
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uint8_t setFrequencyRaw(float newFreq);
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uint8_t config();
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private:
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uint8_t setMode(uint8_t mode);
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void clearIRQFlags();
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};
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#endif
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