579 lines
14 KiB
C++
579 lines
14 KiB
C++
#include "CC1101.h"
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CC1101::CC1101(Module* module) : PhysicalLayer(CC1101_CRYSTAL_FREQ, CC1101_DIV_EXPONENT) {
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_mod = module;
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}
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int16_t CC1101::begin(float freq, float br, float rxBw, float freqDev, int8_t power) {
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// set module properties
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_mod->SPIreadCommand = CC1101_CMD_READ;
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_mod->SPIwriteCommand = CC1101_CMD_WRITE;
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_mod->init(USE_SPI, INT_0);
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// try to find the CC1101 chip
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uint8_t i = 0;
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bool flagFound = false;
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while((i < 10) && !flagFound) {
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uint8_t version = SPIreadRegister(CC1101_REG_VERSION);
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if(version == 0x14) {
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flagFound = true;
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} else {
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#ifdef RADIOLIB_DEBUG
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Serial.print(F("CC1101 not found! ("));
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Serial.print(i + 1);
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Serial.print(F(" of 10 tries) CC1101_REG_VERSION == "));
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char buffHex[7];
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sprintf(buffHex, "0x%04X", version);
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Serial.print(buffHex);
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Serial.print(F(", expected 0x0014"));
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Serial.println();
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#endif
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delay(1000);
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i++;
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}
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}
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if(!flagFound) {
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DEBUG_PRINTLN(F("No CC1101 found!"));
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SPI.end();
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return(ERR_CHIP_NOT_FOUND);
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} else {
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DEBUG_PRINTLN(F("Found CC1101! (match by CC1101_REG_VERSION == 0x14)"));
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}
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// configure settings not accessible by API
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int16_t state = config();
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if(state != ERR_NONE) {
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return(state);
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}
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// configure publicly accessible settings
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state = setFrequency(freq);
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if(state != ERR_NONE) {
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return(state);
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}
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state = setBitRate(br);
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if(state != ERR_NONE) {
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return(state);
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}
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state = setRxBandwidth(rxBw);
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if(state != ERR_NONE) {
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return(state);
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}
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state = setFrequencyDeviation(freqDev);
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if(state != ERR_NONE) {
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return(state);
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}
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state = setOutputPower(power);
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if(state != ERR_NONE) {
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return(state);
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}
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// flush FIFOs
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SPIsendCommand(CC1101_CMD_FLUSH_RX);
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SPIsendCommand(CC1101_CMD_FLUSH_TX);
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return(state);
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}
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int16_t CC1101::transmit(uint8_t* data, size_t len, uint8_t addr) {
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// start transmission
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int16_t state = startTransmit(data, len, addr);
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if(state != ERR_NONE) {
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return(state);
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}
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// wait for transmission start
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while(!digitalRead(_mod->getInt0()));
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// wait for transmission end
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while(digitalRead(_mod->getInt0()));
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// set mode to standby
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standby();
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// flush Tx FIFO
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SPIsendCommand(CC1101_CMD_FLUSH_TX);
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return(state);
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}
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int16_t CC1101::receive(uint8_t* data, size_t len) {
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// start reception
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int16_t state = startReceive();
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if(state != ERR_NONE) {
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return(state);
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}
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// wait for sync word
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while(!digitalRead(_mod->getInt0()));
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// wait for packet end
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while(digitalRead(_mod->getInt0()));
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// read packet data
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return(readData(data, len));
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}
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int16_t CC1101::standby() {
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SPIsendCommand(CC1101_CMD_IDLE);
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return(ERR_NONE);
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}
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int16_t CC1101::transmitDirect(uint32_t frf) {
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// user requested to start transmitting immediately (required for RTTY)
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if(frf != 0) {
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SPIwriteRegister(CC1101_REG_FREQ2, (frf & 0xFF0000) >> 16);
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SPIwriteRegister(CC1101_REG_FREQ1, (frf & 0x00FF00) >> 8);
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SPIwriteRegister(CC1101_REG_FREQ0, frf & 0x0000FF);
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SPIsendCommand(CC1101_CMD_TX);
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}
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// activate direct mode
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int16_t state = directMode();
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if(state != ERR_NONE) {
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return(state);
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}
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// start transmitting
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SPIsendCommand(CC1101_CMD_TX);
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return(state);
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}
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int16_t CC1101::receiveDirect() {
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// activate direct mode
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int16_t state = directMode();
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if(state != ERR_NONE) {
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return(state);
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}
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// start receiving
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SPIsendCommand(CC1101_CMD_RX);
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return(ERR_NONE);
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}
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int16_t CC1101::packetMode() {
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int16_t state = SPIsetRegValue(CC1101_REG_PKTCTRL1, CC1101_CRC_AUTOFLUSH_OFF | CC1101_APPEND_STATUS_ON | CC1101_ADR_CHK_NONE, 3, 0);
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state |= SPIsetRegValue(CC1101_REG_PKTCTRL0, CC1101_WHITE_DATA_OFF | CC1101_PKT_FORMAT_NORMAL, 6, 4);
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state |= SPIsetRegValue(CC1101_REG_PKTCTRL0, CC1101_CRC_ON | CC1101_LENGTH_CONFIG_VARIABLE, 2, 0);
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return(state);
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}
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void CC1101::setGdo0Action(void (*func)(void), uint8_t dir) {
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attachInterrupt(digitalPinToInterrupt(_mod->getInt0()), func, dir);
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}
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void CC1101::setGdo2Action(void (*func)(void), uint8_t dir) {
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attachInterrupt(digitalPinToInterrupt(_mod->getInt1()), func, dir);
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}
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int16_t CC1101::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
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// check packet length
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if(len > 63) {
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return(ERR_PACKET_TOO_LONG);
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}
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// set mode to standby
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standby();
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// flush Tx FIFO
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SPIsendCommand(CC1101_CMD_FLUSH_TX);
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// set GDO0 mapping
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int state = SPIsetRegValue(CC1101_REG_IOCFG0, CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED);
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if(state != ERR_NONE) {
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return(state);
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}
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// write packet length
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SPIwriteRegister(CC1101_REG_FIFO, len);
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// check address filtering
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uint8_t filter = SPIgetRegValue(CC1101_REG_PKTCTRL1, 1, 0);
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if(filter != CC1101_ADR_CHK_NONE) {
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SPIwriteRegister(CC1101_REG_FIFO, addr);
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}
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// write packet to FIFO
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SPIwriteRegisterBurst(CC1101_REG_FIFO, data, len);
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// set mode to transmit
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SPIsendCommand(CC1101_CMD_TX);
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return(state);
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}
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int16_t CC1101::startReceive() {
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// set mode to standby
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standby();
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// flush Rx FIFO
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SPIsendCommand(CC1101_CMD_FLUSH_RX);
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// set GDO0 mapping
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int state = SPIsetRegValue(CC1101_REG_IOCFG0, CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED);
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if(state != ERR_NONE) {
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return(state);
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}
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// set mode to receive
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SPIsendCommand(CC1101_CMD_RX);
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return(state);
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}
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int16_t CC1101::readData(uint8_t* data, size_t len) {
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// get packet length
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size_t length = SPIreadRegister(CC1101_REG_RXBYTES) - 2;
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// check address filtering
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uint8_t filter = SPIgetRegValue(CC1101_REG_PKTCTRL1, 1, 0);
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if(filter != CC1101_ADR_CHK_NONE) {
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SPIreadRegister(CC1101_REG_FIFO);
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}
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// read packet data
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if(len == 0) {
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// argument len equal to zero indicates String call, which means dynamically allocated data array
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// dispose of the original and create a new one
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delete[] data;
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data = new uint8_t[length + 1];
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}
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SPIreadRegisterBurst(CC1101_REG_FIFO, length, data);
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// read RSSI byte
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_rawRSSI = SPIgetRegValue(CC1101_REG_FIFO);
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// read LQI and CRC byte
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uint8_t val = SPIgetRegValue(CC1101_REG_FIFO);
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_rawLQI = val & 0x7F;
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// add terminating null
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data[length] = 0;
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// flush Rx FIFO
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SPIsendCommand(CC1101_CMD_FLUSH_RX);
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// set mode to standby
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standby();
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// check CRC
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if((val & 0b10000000) == 0b00000000) {
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return(ERR_CRC_MISMATCH);
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}
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return(ERR_NONE);
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}
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int16_t CC1101::setFrequency(float freq) {
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// check allowed frequency range
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if(!(((freq > 300.0) && (freq < 348.0)) ||
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((freq > 387.0) && (freq < 464.0)) ||
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((freq > 779.0) && (freq < 928.0)))) {
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return(ERR_INVALID_FREQUENCY);
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}
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// set mode to standby
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SPIsendCommand(CC1101_CMD_IDLE);
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//set carrier frequency
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uint32_t base = 1;
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uint32_t FRF = (freq * (base << 16)) / 26.0;
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int16_t state = SPIsetRegValue(CC1101_REG_FREQ2, (FRF & 0xFF0000) >> 16, 7, 0);
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state |= SPIsetRegValue(CC1101_REG_FREQ1, (FRF & 0x00FF00) >> 8, 7, 0);
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state |= SPIsetRegValue(CC1101_REG_FREQ0, FRF & 0x0000FF, 7, 0);
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if(state == ERR_NONE) {
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_freq = freq;
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}
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return(state);
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}
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int16_t CC1101::setBitRate(float br) {
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// check allowed bit rate range
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if(!((br >= 0.025) && (br <= 600.0))) {
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return(ERR_INVALID_BIT_RATE);
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}
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// set mode to standby
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SPIsendCommand(CC1101_CMD_IDLE);
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// calculate exponent and mantisa values
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uint8_t e = 0;
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uint8_t m = 0;
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getExpMant(br * 1000.0, 256, 28, 14, e, m);
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// set bit rate value
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int16_t state = SPIsetRegValue(CC1101_REG_MDMCFG4, e, 3, 0);
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state |= SPIsetRegValue(CC1101_REG_MDMCFG3, m);
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return(state);
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}
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int16_t CC1101::setRxBandwidth(float rxBw) {
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// check allowed bandwidth range
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if(!((rxBw >= 58.0) && (rxBw <= 812.0))) {
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return(ERR_INVALID_RX_BANDWIDTH);
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}
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// set mode to standby
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SPIsendCommand(CC1101_CMD_IDLE);
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// calculate exponent and mantisa values
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for(int8_t e = 3; e >= 0; e--) {
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for(int8_t m = 3; m >= 0; m --) {
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float point = (CC1101_CRYSTAL_FREQ * 1000000.0)/(8 * (m + 4) * ((uint32_t)1 << e));
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if(abs((rxBw * 1000.0) - point) <= 0.001) {
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// set Rx channel filter bandwidth
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return(SPIsetRegValue(CC1101_REG_MDMCFG4, (e << 6) | (m << 4), 7, 4));
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}
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}
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}
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return(ERR_UNKNOWN);
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}
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int16_t CC1101::setFrequencyDeviation(float freqDev) {
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// set frequency deviation to lowest available setting (required for RTTY)
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if(freqDev == 0.0) {
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int16_t state = SPIsetRegValue(CC1101_REG_DEVIATN, 0, 6, 4);
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state |= SPIsetRegValue(CC1101_REG_DEVIATN, 0, 2, 0);
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return(state);
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}
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// check allowed frequency deviation range
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if(!((freqDev >= 1.587) && (freqDev <= 380.8))) {
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return(ERR_INVALID_FREQUENCY_DEVIATION);
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}
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// set mode to standby
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SPIsendCommand(CC1101_CMD_IDLE);
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// calculate exponent and mantisa values
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uint8_t e = 0;
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uint8_t m = 0;
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getExpMant(freqDev * 1000.0, 8, 17, 7, e, m);
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// set frequency deviation value
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int16_t state = SPIsetRegValue(CC1101_REG_DEVIATN, (e << 4), 6, 4);
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state |= SPIsetRegValue(CC1101_REG_DEVIATN, m, 2, 0);
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return(state);
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}
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int16_t CC1101::setOutputPower(int8_t power) {
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// round to the known frequency settings
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uint8_t f;
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if(_freq < 374.0) {
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// 315 MHz
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f = 0;
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} else if(_freq < 650.5) {
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// 434 MHz
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f = 1;
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} else if(_freq < 891.5) {
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// 868 MHz
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f = 2;
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} else {
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// 915 MHz
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f = 3;
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}
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// get raw power setting
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uint8_t paTable[8][4] = {{0x12, 0x12, 0x03, 0x03},
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{0x0D, 0x0E, 0x0F, 0x0E},
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{0x1C, 0x1D, 0x1E, 0x1E},
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{0x34, 0x34, 0x27, 0x27},
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{0x51, 0x60, 0x50, 0x8E},
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{0x85, 0x84, 0x81, 0xCD},
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{0xCB, 0xC8, 0xCB, 0xC7},
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{0xC2, 0xC0, 0xC2, 0xC0}};
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uint8_t powerRaw;
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switch(power) {
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case -30:
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powerRaw = paTable[0][f];
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break;
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case -20:
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powerRaw = paTable[1][f];
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break;
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case -15:
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powerRaw = paTable[2][f];
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break;
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case -10:
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powerRaw = paTable[3][f];
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break;
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case 0:
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powerRaw = paTable[4][f];
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break;
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case 5:
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powerRaw = paTable[5][f];
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break;
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case 7:
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powerRaw = paTable[6][f];
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break;
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case 10:
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powerRaw = paTable[7][f];
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break;
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default:
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return(ERR_INVALID_OUTPUT_POWER);
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}
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// write raw power setting
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return(SPIsetRegValue(CC1101_REG_PATABLE, powerRaw));
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}
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int16_t CC1101::setSyncWord(uint8_t syncH, uint8_t syncL) {
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// set sync word
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int16_t state = SPIsetRegValue(CC1101_REG_SYNC1, syncH);
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state |= SPIsetRegValue(CC1101_REG_SYNC0, syncL);
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return(state);
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}
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int16_t CC1101::setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs) {
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if(!(numBroadcastAddrs > 0) && (numBroadcastAddrs <= 2)) {
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return(ERR_INVALID_NUM_BROAD_ADDRS);
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}
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// enable address filtering
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int16_t state = SPIsetRegValue(CC1101_REG_PKTCTRL1, numBroadcastAddrs + 0x01, 1, 0);
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if(state != ERR_NONE) {
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return(state);
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}
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// set node address
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return(SPIsetRegValue(CC1101_REG_ADDR, nodeAddr));
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}
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int16_t CC1101::disableAddressFiltering() {
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// disable address filtering
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int16_t state = _mod->SPIsetRegValue(CC1101_REG_PKTCTRL1, CC1101_ADR_CHK_NONE, 1, 0);
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if(state != ERR_NONE) {
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return(state);
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}
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// set node address to default (0x00)
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return(SPIsetRegValue(CC1101_REG_ADDR, 0x00));
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}
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float CC1101::getRSSI() {
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float rssi;
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if(_rawRSSI >= 128) {
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rssi = (((float)_rawRSSI - 256.0)/2.0) - 74.0;
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} else {
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rssi = (((float)_rawRSSI)/2.0) - 74.0;
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}
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return(rssi);
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}
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uint8_t CC1101::getLQI() {
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return(_rawLQI);
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}
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int16_t CC1101::config() {
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// enable automatic frequency synthesizer calibration
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int16_t state = SPIsetRegValue(CC1101_REG_MCSM0, CC1101_FS_AUTOCAL_IDLE_TO_RXTX, 5, 4);
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if(state != ERR_NONE) {
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return(state);
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}
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// set packet mode
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state = packetMode();
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return(state);
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}
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int16_t CC1101::directMode() {
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// set mode to standby
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SPIsendCommand(CC1101_CMD_IDLE);
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// set GDO0 and GDO2 mapping
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int16_t state = SPIsetRegValue(CC1101_REG_IOCFG0, CC1101_GDOX_SERIAL_CLOCK , 5, 0);
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state |= SPIsetRegValue(CC1101_REG_IOCFG2, CC1101_GDOX_SERIAL_DATA_SYNC , 5, 0);
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// set continuous mode
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state |= SPIsetRegValue(CC1101_REG_PKTCTRL0, CC1101_PKT_FORMAT_SYNCHRONOUS, 5, 4);
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return(state);
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}
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void CC1101::getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant) {
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// get table origin point (exp = 0, mant = 0)
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float origin = (mantOffset * CC1101_CRYSTAL_FREQ * 1000000.0)/((uint32_t)1 << divExp);
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// iterate over possible exponent values
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for(int8_t e = expMax; e >= 0; e--) {
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// get table column start value (exp = e, mant = 0);
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float intervalStart = ((uint32_t)1 << e) * origin;
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// check if target value is in this column
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if(target >= intervalStart) {
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// save exponent value
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exp = e;
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// calculate size of step between table rows
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float stepSize = intervalStart/(float)mantOffset;
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// get target point position (exp = e, mant = m)
|
|
mant = ((target - intervalStart) / stepSize);
|
|
|
|
// we only need the first match, terminate
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
int16_t CC1101::SPIgetRegValue(uint8_t reg, uint8_t msb, uint8_t lsb) {
|
|
// status registers require special command
|
|
if(reg > CC1101_REG_TEST0) {
|
|
reg |= CC1101_CMD_ACCESS_STATUS_REG;
|
|
}
|
|
|
|
return(_mod->SPIgetRegValue(reg, msb, lsb));
|
|
}
|
|
|
|
int16_t CC1101::SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb, uint8_t lsb, uint8_t checkInterval) {
|
|
// status registers require special command
|
|
if(reg > CC1101_REG_TEST0) {
|
|
reg |= CC1101_CMD_ACCESS_STATUS_REG;
|
|
}
|
|
|
|
return(_mod->SPIsetRegValue(reg, value, msb, lsb, checkInterval));
|
|
}
|
|
|
|
void CC1101::SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes) {
|
|
_mod->SPIreadRegisterBurst(reg | CC1101_CMD_BURST, numBytes, inBytes);
|
|
}
|
|
|
|
uint8_t CC1101::SPIreadRegister(uint8_t reg) {
|
|
// status registers require special command
|
|
if(reg > CC1101_REG_TEST0) {
|
|
reg |= CC1101_CMD_ACCESS_STATUS_REG;
|
|
}
|
|
|
|
return(_mod->SPIreadRegister(reg));
|
|
}
|
|
|
|
void CC1101::SPIwriteRegister(uint8_t reg, uint8_t data) {
|
|
// status registers require special command
|
|
if(reg > CC1101_REG_TEST0) {
|
|
reg |= CC1101_CMD_ACCESS_STATUS_REG;
|
|
}
|
|
|
|
return(_mod->SPIwriteRegister(reg, data));
|
|
}
|
|
|
|
void CC1101::SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len) {
|
|
_mod->SPIwriteRegisterBurst(reg | CC1101_CMD_BURST, data, len);
|
|
}
|
|
|
|
void CC1101::SPIsendCommand(uint8_t cmd) {
|
|
digitalWrite(_mod->getCs(), LOW);
|
|
SPI.beginTransaction(SPISettings(2000000, MSBFIRST, SPI_MODE0));
|
|
SPI.transfer(cmd);
|
|
SPI.endTransaction();
|
|
digitalWrite(_mod->getCs(), HIGH);
|
|
}
|