Commit graph

68 commits

Author SHA1 Message Date
jgromes
3734f23270 [SX128x] Renamed TRNG method 2021-07-18 10:18:03 +02:00
jgromes
48a80b22f5 [SX128x] Added direct reception dummies 2021-06-14 21:15:18 +02:00
jgromes
8be419f007 [SX128x] Added support for changing LoRa sync word (#311) 2021-06-13 14:44:52 +02:00
jgromes
0abfb5fe1b [SX128x] Clean up register map 2021-06-13 14:44:29 +02:00
jgromes
e9f1f940a2 [SX128x] Added low-level access macro 2021-03-13 19:57:44 +01:00
jgromes
3cc55806cf [SX128x] Added TRNG support 2020-09-13 17:53:07 +02:00
jgromes
4d00170612 [SX128x] Synced parameters of all FSK modules 2020-07-06 11:14:21 +02:00
jgromes
be346eb6aa [SX128x] Changed shaping datatype to uint8_t 2020-07-06 08:53:12 +02:00
jgromes
96f4bd667e [SX128x] Fixed exclusion macros 2020-07-04 21:18:13 +02:00
jgromes
b642fd1a8d [SX128x] Fixes from cppcheck scan 2020-07-04 14:54:01 +02:00
jgromes
515551e7bc [SX128x] Reworked driver exclusion 2020-06-30 10:44:08 +02:00
jgromes
5a3d7a7173 [SX128x] Implemented RF switch control 2020-06-18 16:36:02 +02:00
jgromes
1aef03c473 [SX128x] Added missing BLE modem check 2020-04-17 07:51:29 +02:00
jgromes
1592831e0c [SX128x] Implemented ranging 2020-04-12 13:47:56 +02:00
jgromes
a355a098e6 [SX128x] Added BLE modem support 2020-04-12 11:32:07 +02:00
jgromes
ff3225cd19 [SX128x] Added FLRC modem support 2020-04-12 11:05:16 +02:00
jgromes
5c0c7f32c3 [SX128x] Set default regulator mode to DC-DC 2020-04-09 12:10:38 +02:00
jgromes
55ad72e0e0 [SX128x] Added support for SX128x 2020-04-07 13:30:05 +02:00