15 commits

Author	SHA1	Message	Date
jgromes	a168f9ba41	[SX127x] Fixed data rate checking	2024-01-28 13:29:14 +01:00
jgromes	a4b148d609	[SX127x] Implemented data rate check	2024-01-27 18:45:37 +01:00
jgromes	34c861cfbe	[SX127x] Reworked macro configuration system	2023-11-27 21:14:33 +01:00
jgromes	10d225fadb	[SX127x] Allow alternate chip versions	2023-09-24 18:19:19 +02:00
jgromes	d5ce384bda	[SX127x] Implemented new common PHY methods	2023-07-06 11:17:29 +02:00
jgromes	cc8c8f2eed	[SX127x] General reformatting	2023-04-23 22:42:13 +02:00
jgromes	b9fb0893b3	[SX127x] Added missing explicit CRC configuration	2023-04-10 11:54:59 +02:00
jgromes	8c7b8a1b63	[SX127x] Update to 5.0.0	2021-11-14 11:42:12 +01:00
jgromes	498b638234	[SX127x] Reworked errata fix (#372)	2021-09-22 22:17:12 +02:00
jgromes	1e47f8bca3	[SX127x] Swap frequency and bandwidth config in LoRa begin (#251)	2021-02-13 18:14:07 +01:00
jgromes	bc613daf23	[SX127x] Moved non-configurable parameters config into base class	2021-02-07 17:51:55 +01:00
jgromes	e1141ca64c	[SX127x] Synced parameters of all LoRa modules	2020-07-06 11:48:14 +02:00
jgromes	3dd3a471e5	[SX127x] Reworked driver exclusion	2020-06-30 10:43:56 +02:00
jgromes	acd78cb6bb	[SX127x] Added assert macro	2020-01-13 16:37:31 +01:00
jgromes	915f3780cc	Reworked directory structure	2019-11-20 17:19:15 +01:00

Renamed from src/modules/SX1273.cpp (Browse further)