From eb9903f1838bd4a10ed5b3ce21a9e885a477fe22 Mon Sep 17 00:00:00 2001 From: jgromes Date: Sun, 14 Nov 2021 11:42:52 +0100 Subject: [PATCH] [Si443x] Update to 5.0.0 --- .../Si443x/Si443x_Receive/Si443x_Receive.ino | 8 +- .../Si443x_Receive_Interrupt.ino | 8 +- .../Si443x_Settings/Si443x_Settings.ino | 18 +- .../Si443x_Transmit/Si443x_Transmit.ino | 8 +- .../Si443x_Transmit_Interrupt.ino | 6 +- src/modules/Si443x/Si4430.cpp | 6 +- src/modules/Si443x/Si4431.cpp | 4 +- src/modules/Si443x/Si4432.cpp | 6 +- src/modules/Si443x/Si443x.cpp | 284 +++--- src/modules/Si443x/Si443x.h | 952 +++++++++--------- 10 files changed, 653 insertions(+), 647 deletions(-) diff --git a/examples/Si443x/Si443x_Receive/Si443x_Receive.ino b/examples/Si443x/Si443x_Receive/Si443x_Receive.ino index 846e46e3..b5ab2485 100644 --- a/examples/Si443x/Si443x_Receive/Si443x_Receive.ino +++ b/examples/Si443x/Si443x_Receive/Si443x_Receive.ino @@ -37,7 +37,7 @@ void setup() { // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); int state = radio.begin(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -59,7 +59,7 @@ void loop() { int state = radio.receive(byteArr, 8); */ - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { // packet was successfully received Serial.println(F("success!")); @@ -67,11 +67,11 @@ void loop() { Serial.print(F("[Si4432] Data:\t\t")); Serial.println(str); - } else if (state == ERR_RX_TIMEOUT) { + } else if (state == RADIOLIB_ERR_RX_TIMEOUT) { // timeout occurred while waiting for a packet Serial.println(F("timeout!")); - } else if (state == ERR_CRC_MISMATCH) { + } else if (state == RADIOLIB_ERR_CRC_MISMATCH) { // packet was received, but is malformed Serial.println(F("CRC error!")); diff --git a/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino b/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino index e890b08d..16c1af41 100644 --- a/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino +++ b/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino @@ -33,7 +33,7 @@ void setup() { // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); int state = radio.begin(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -48,7 +48,7 @@ void setup() { // start listening for packets Serial.print(F("[Si4432] Starting to listen ... ")); state = radio.startReceive(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -106,7 +106,7 @@ void loop() { int state = radio.readData(byteArr, 8); */ - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { // packet was successfully received Serial.println(F("[Si4432] Received packet!")); @@ -114,7 +114,7 @@ void loop() { Serial.print(F("[Si4432] Data:\t\t\t")); Serial.println(str); - } else if (state == ERR_CRC_MISMATCH) { + } else if (state == RADIOLIB_ERR_CRC_MISMATCH) { // packet was received, but is malformed Serial.println(F("CRC error!")); diff --git a/examples/Si443x/Si443x_Settings/Si443x_Settings.ino b/examples/Si443x/Si443x_Settings/Si443x_Settings.ino index cd420505..9823e97d 100644 --- a/examples/Si443x/Si443x_Settings/Si443x_Settings.ino +++ b/examples/Si443x/Si443x_Settings/Si443x_Settings.ino @@ -43,7 +43,7 @@ void setup() { // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); int state = radio1.begin(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -60,7 +60,7 @@ void setup() { // output power: 17 dBm // preamble length: 32 bits state = radio2.begin(868.0, 200.0, 60.0, 335.5, 17, 32); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -72,17 +72,17 @@ void setup() { // and check if the configuration was changed successfully // set carrier frequency to 433.5 MHz - if (radio1.setFrequency(433.5) == ERR_INVALID_FREQUENCY) { + if (radio1.setFrequency(433.5) == RADIOLIB_ERR_INVALID_FREQUENCY) { Serial.println(F("[Si4432] Selected frequency is invalid for this module!")); while (true); } // set bit rate to 100.0 kbps state = radio1.setBitRate(100.0); - if (state == ERR_INVALID_BIT_RATE) { + if (state == RADIOLIB_ERR_INVALID_BIT_RATE) { Serial.println(F("[Si4432] Selected bit rate is invalid for this module!")); while (true); - } else if (state == ERR_INVALID_BIT_RATE_BW_RATIO) { + } else if (state == RADIOLIB_ERR_INVALID_BIT_RATE_BW_RATIO) { Serial.println(F("[Si4432] Selected bit rate to bandwidth ratio is invalid!")); Serial.println(F("[Si4432] Increase receiver bandwidth to set this bit rate.")); while (true); @@ -90,19 +90,19 @@ void setup() { // set receiver bandwidth to 284.8 kHz state = radio1.setRxBandwidth(284.8); - if (state == ERR_INVALID_RX_BANDWIDTH) { + if (state == RADIOLIB_ERR_INVALID_RX_BANDWIDTH) { Serial.println(F("[Si4432] Selected receiver bandwidth is invalid for this module!")); while (true); } // set frequency deviation to 10.0 kHz - if (radio1.setFrequencyDeviation(10.0) == ERR_INVALID_FREQUENCY_DEVIATION) { + if (radio1.setFrequencyDeviation(10.0) == RADIOLIB_ERR_INVALID_FREQUENCY_DEVIATION) { Serial.println(F("[Si4432] Selected frequency deviation is invalid for this module!")); while (true); } // set output power to 2 dBm - if (radio1.setOutputPower(2) == ERR_INVALID_OUTPUT_POWER) { + if (radio1.setOutputPower(2) == RADIOLIB_ERR_INVALID_OUTPUT_POWER) { Serial.println(F("[Si4432] Selected output power is invalid for this module!")); while (true); } @@ -110,7 +110,7 @@ void setup() { // up to 4 bytes can be set as sync word // set sync word to 0x01234567 uint8_t syncWord[] = {0x01, 0x23, 0x45, 0x67}; - if (radio1.setSyncWord(syncWord, 4) == ERR_INVALID_SYNC_WORD) { + if (radio1.setSyncWord(syncWord, 4) == RADIOLIB_ERR_INVALID_SYNC_WORD) { Serial.println(F("[Si4432] Selected sync word is invalid for this module!")); while (true); } diff --git a/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino b/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino index ca267624..2eddf96e 100644 --- a/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino +++ b/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino @@ -35,7 +35,7 @@ void setup() { // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); int state = radio.begin(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -60,15 +60,15 @@ void loop() { int state = radio.transmit(byteArr, 8); */ - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { // the packet was successfully transmitted Serial.println(F(" success!")); - } else if (state == ERR_PACKET_TOO_LONG) { + } else if (state == RADIOLIB_ERR_PACKET_TOO_LONG) { // the supplied packet was longer than 256 bytes Serial.println(F(" too long!")); - } else if (state == ERR_TX_TIMEOUT) { + } else if (state == RADIOLIB_ERR_TX_TIMEOUT) { // timeout occured while transmitting packet Serial.println(F(" timeout!")); diff --git a/examples/Si443x/Si443x_Transmit_Interrupt/Si443x_Transmit_Interrupt.ino b/examples/Si443x/Si443x_Transmit_Interrupt/Si443x_Transmit_Interrupt.ino index 82c5364d..4703233a 100644 --- a/examples/Si443x/Si443x_Transmit_Interrupt/Si443x_Transmit_Interrupt.ino +++ b/examples/Si443x/Si443x_Transmit_Interrupt/Si443x_Transmit_Interrupt.ino @@ -30,7 +30,7 @@ Si4432 radio = new Module(10, 2, 9); //Si4432 radio = RadioShield.ModuleA; // save transmission state between loops -int transmissionState = ERR_NONE; +int transmissionState = RADIOLIB_ERR_NONE; void setup() { Serial.begin(9600); @@ -38,7 +38,7 @@ void setup() { // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); int state = radio.begin(); - if (state == ERR_NONE) { + if (state == RADIOLIB_ERR_NONE) { Serial.println(F("success!")); } else { Serial.print(F("failed, code ")); @@ -95,7 +95,7 @@ void loop() { // reset flag transmittedFlag = false; - if (transmissionState == ERR_NONE) { + if (transmissionState == RADIOLIB_ERR_NONE) { // packet was successfully sent Serial.println(F("transmission finished!")); diff --git a/src/modules/Si443x/Si4430.cpp b/src/modules/Si443x/Si4430.cpp index 9114ac4b..d6f40326 100644 --- a/src/modules/Si443x/Si4430.cpp +++ b/src/modules/Si443x/Si4430.cpp @@ -22,17 +22,17 @@ int16_t Si4430::begin(float freq, float br, float freqDev, float rxBw, int8_t po } int16_t Si4430::setFrequency(float freq) { - RADIOLIB_CHECK_RANGE(freq, 900.0, 960.0, ERR_INVALID_FREQUENCY); + RADIOLIB_CHECK_RANGE(freq, 900.0, 960.0, RADIOLIB_ERR_INVALID_FREQUENCY); // set frequency return(Si443x::setFrequencyRaw(freq)); } int16_t Si4430::setOutputPower(int8_t power) { - RADIOLIB_CHECK_RANGE(power, -8, 13, ERR_INVALID_OUTPUT_POWER); + RADIOLIB_CHECK_RANGE(power, -8, 13, RADIOLIB_ERR_INVALID_OUTPUT_POWER); // set output power - return(_mod->SPIsetRegValue(SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0)); } #endif diff --git a/src/modules/Si443x/Si4431.cpp b/src/modules/Si443x/Si4431.cpp index 6f406165..832ed432 100644 --- a/src/modules/Si443x/Si4431.cpp +++ b/src/modules/Si443x/Si4431.cpp @@ -22,10 +22,10 @@ int16_t Si4431::begin(float freq, float br, float freqDev, float rxBw, int8_t po } int16_t Si4431::setOutputPower(int8_t power) { - RADIOLIB_CHECK_RANGE(power, -8, 13, ERR_INVALID_OUTPUT_POWER); + RADIOLIB_CHECK_RANGE(power, -8, 13, RADIOLIB_ERR_INVALID_OUTPUT_POWER); // set output power - return(_mod->SPIsetRegValue(SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0)); } #endif diff --git a/src/modules/Si443x/Si4432.cpp b/src/modules/Si443x/Si4432.cpp index aef6dc53..06921add 100644 --- a/src/modules/Si443x/Si4432.cpp +++ b/src/modules/Si443x/Si4432.cpp @@ -22,17 +22,17 @@ int16_t Si4432::begin(float freq, float br, float freqDev, float rxBw, int8_t po } int16_t Si4432::setFrequency(float freq) { - RADIOLIB_CHECK_RANGE(freq, 240.0, 930.0, ERR_INVALID_FREQUENCY); + RADIOLIB_CHECK_RANGE(freq, 240.0, 930.0, RADIOLIB_ERR_INVALID_FREQUENCY); // set frequency return(Si443x::setFrequencyRaw(freq)); } int16_t Si4432::setOutputPower(int8_t power) { - RADIOLIB_CHECK_RANGE(power, -1, 20, ERR_INVALID_OUTPUT_POWER); + RADIOLIB_CHECK_RANGE(power, -1, 20, RADIOLIB_ERR_INVALID_OUTPUT_POWER); // set output power - return(_mod->SPIsetRegValue(SI443X_REG_TX_POWER, (uint8_t)((power + 1) / 3), 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 1) / 3), 2, 0)); } #endif diff --git a/src/modules/Si443x/Si443x.cpp b/src/modules/Si443x/Si443x.cpp index 69111f4a..5c485613 100644 --- a/src/modules/Si443x/Si443x.cpp +++ b/src/modules/Si443x/Si443x.cpp @@ -1,28 +1,32 @@ #include "Si443x.h" #if !defined(RADIOLIB_EXCLUDE_SI443X) -Si443x::Si443x(Module* mod) : PhysicalLayer(SI443X_FREQUENCY_STEP_SIZE, SI443X_MAX_PACKET_LENGTH) { +Si443x::Si443x(Module* mod) : PhysicalLayer(RADIOLIB_SI443X_FREQUENCY_STEP_SIZE, RADIOLIB_SI443X_MAX_PACKET_LENGTH) { _mod = mod; } +Module* Si443x::getMod() { + return(_mod); +} + int16_t Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen) { // set module properties - _mod->init(RADIOLIB_USE_SPI); - Module::pinMode(_mod->getIrq(), INPUT); - Module::pinMode(_mod->getRst(), OUTPUT); - Module::digitalWrite(_mod->getRst(), LOW); + _mod->init(); + _mod->pinMode(_mod->getIrq(), INPUT); + _mod->pinMode(_mod->getRst(), OUTPUT); + _mod->digitalWrite(_mod->getRst(), LOW); // try to find the Si443x chip if(!Si443x::findChip()) { RADIOLIB_DEBUG_PRINTLN(F("No Si443x found!")); - _mod->term(RADIOLIB_USE_SPI); - return(ERR_CHIP_NOT_FOUND); + _mod->term(); + return(RADIOLIB_ERR_CHIP_NOT_FOUND); } else { RADIOLIB_DEBUG_PRINTLN(F("M\tSi443x")); } // reset the device - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_SOFTWARE_RESET); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_SOFTWARE_RESET); // clear POR interrupt clearIRQFlags(); @@ -61,11 +65,11 @@ int16_t Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen) } void Si443x::reset() { - Module::pinMode(_mod->getRst(), OUTPUT); - Module::digitalWrite(_mod->getRst(), HIGH); - Module::delay(1); - Module::digitalWrite(_mod->getRst(), LOW); - Module::delay(100); + _mod->pinMode(_mod->getRst(), OUTPUT); + _mod->digitalWrite(_mod->getRst(), HIGH); + _mod->delay(1); + _mod->digitalWrite(_mod->getRst(), LOW); + _mod->delay(100); } int16_t Si443x::transmit(uint8_t* data, size_t len, uint8_t addr) { @@ -77,13 +81,13 @@ int16_t Si443x::transmit(uint8_t* data, size_t len, uint8_t addr) { RADIOLIB_ASSERT(state); // wait for transmission end or timeout - uint32_t start = Module::micros(); - while(Module::digitalRead(_mod->getIrq())) { - Module::yield(); - if(Module::micros() - start > timeout) { + uint32_t start = _mod->micros(); + while(_mod->digitalRead(_mod->getIrq())) { + _mod->yield(); + if(_mod->micros() - start > timeout) { standby(); clearIRQFlags(); - return(ERR_TX_TIMEOUT); + return(RADIOLIB_ERR_TX_TIMEOUT); } } @@ -98,19 +102,19 @@ int16_t Si443x::transmit(uint8_t* data, size_t len, uint8_t addr) { int16_t Si443x::receive(uint8_t* data, size_t len) { // calculate timeout (500 ms + 400 full 64-byte packets at current bit rate) - uint32_t timeout = 500000 + (1.0/(_br*1000.0))*(SI443X_MAX_PACKET_LENGTH*400.0); + uint32_t timeout = 500000 + (1.0/(_br*1000.0))*(RADIOLIB_SI443X_MAX_PACKET_LENGTH*400.0); // start reception int16_t state = startReceive(); RADIOLIB_ASSERT(state); // wait for packet reception or timeout - uint32_t start = Module::micros(); - while(Module::digitalRead(_mod->getIrq())) { - if(Module::micros() - start > timeout) { + uint32_t start = _mod->micros(); + while(_mod->digitalRead(_mod->getIrq())) { + if(_mod->micros() - start > timeout) { standby(); clearIRQFlags(); - return(ERR_RX_TIMEOUT); + return(RADIOLIB_ERR_RX_TIMEOUT); } } @@ -123,13 +127,13 @@ int16_t Si443x::sleep() { _mod->setRfSwitchState(LOW, LOW); // disable wakeup timer interrupt - int16_t state = _mod->SPIsetRegValue(SI443X_REG_INTERRUPT_ENABLE_1, 0x00); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, 0x00); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00); RADIOLIB_ASSERT(state); // enable wakeup timer to set mode to sleep - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_ENABLE_WAKEUP_TIMER); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_ENABLE_WAKEUP_TIMER); return(state); } @@ -138,7 +142,7 @@ int16_t Si443x::standby() { // set RF switch (if present) _mod->setRfSwitchState(LOW, LOW); - return(_mod->SPIsetRegValue(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_XTAL_ON, 7, 0, 10)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_XTAL_ON, 7, 0, 10)); } int16_t Si443x::transmitDirect(uint32_t frf) { @@ -152,10 +156,10 @@ int16_t Si443x::transmitDirect(uint32_t frf) { float newFreq = frf / 6400.0; // check high/low band - uint8_t bandSelect = SI443X_BAND_SELECT_LOW; + uint8_t bandSelect = RADIOLIB_SI443X_BAND_SELECT_LOW; uint8_t freqBand = (newFreq / 10) - 24; if(newFreq >= 480.0) { - bandSelect = SI443X_BAND_SELECT_HIGH; + bandSelect = RADIOLIB_SI443X_BAND_SELECT_HIGH; freqBand = (newFreq / 20) - 24; } @@ -163,15 +167,15 @@ int16_t Si443x::transmitDirect(uint32_t frf) { uint16_t freqCarrier = ((newFreq / (10 * ((bandSelect >> 5) + 1))) - freqBand - 24) * (uint32_t)64000; // update registers - _mod->SPIwriteRegister(SI443X_REG_FREQUENCY_BAND_SELECT, SI443X_SIDE_BAND_SELECT_LOW | bandSelect | freqBand); - _mod->SPIwriteRegister(SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8)); - _mod->SPIwriteRegister(SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF)); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, RADIOLIB_SI443X_SIDE_BAND_SELECT_LOW | bandSelect | freqBand); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8)); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF)); // start direct transmission directMode(); - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_TX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON); - return(ERR_NONE); + return(RADIOLIB_ERR_NONE); } // activate direct mode @@ -179,7 +183,7 @@ int16_t Si443x::transmitDirect(uint32_t frf) { RADIOLIB_ASSERT(state); // start transmitting - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_TX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON); return(state); } @@ -192,29 +196,29 @@ int16_t Si443x::receiveDirect() { RADIOLIB_ASSERT(state); // start receiving - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_RX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON); return(state); } int16_t Si443x::packetMode() { - int16_t state = _mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_2, SI443X_MODULATION_FSK, 1, 0); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0); RADIOLIB_ASSERT(state); - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_2, SI443X_TX_DATA_SOURCE_FIFO, 5, 4)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_FIFO, 5, 4)); } void Si443x::setIrqAction(void (*func)(void)) { - Module::attachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()), func, FALLING); + _mod->attachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()), func, FALLING); } void Si443x::clearIrqAction() { - Module::detachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq())); + _mod->detachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq())); } int16_t Si443x::startTransmit(uint8_t* data, size_t len, uint8_t addr) { // check packet length - if(len > SI443X_MAX_PACKET_LENGTH) { - return(ERR_PACKET_TOO_LONG); + if(len > RADIOLIB_SI443X_MAX_PACKET_LENGTH) { + return(RADIOLIB_ERR_PACKET_TOO_LONG); } // set mode to standby @@ -222,31 +226,31 @@ int16_t Si443x::startTransmit(uint8_t* data, size_t len, uint8_t addr) { RADIOLIB_ASSERT(state); // clear Tx FIFO - _mod->SPIsetRegValue(SI443X_REG_OP_FUNC_CONTROL_2, SI443X_TX_FIFO_RESET, 0, 0); - _mod->SPIsetRegValue(SI443X_REG_OP_FUNC_CONTROL_2, SI443X_TX_FIFO_CLEAR, 0, 0); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_RESET, 0, 0); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_CLEAR, 0, 0); // clear interrupt flags clearIRQFlags(); // set packet length /// \todo variable packet length - _mod->SPIwriteRegister(SI443X_REG_TRANSMIT_PACKET_LENGTH, len); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH, len); /// \todo use header as address field? (void)addr; // write packet to FIFO - _mod->SPIwriteRegisterBurst(SI443X_REG_FIFO_ACCESS, data, len); + _mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, data, len); // set RF switch (if present) _mod->setRfSwitchState(LOW, HIGH); // set interrupt mapping - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_1, SI443X_PACKET_SENT_ENABLED); - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_PACKET_SENT_ENABLED); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00); // set mode to transmit - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_TX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON); return(state); } @@ -257,8 +261,8 @@ int16_t Si443x::startReceive() { RADIOLIB_ASSERT(state); // clear Rx FIFO - _mod->SPIsetRegValue(SI443X_REG_OP_FUNC_CONTROL_2, SI443X_RX_FIFO_RESET, 1, 1); - _mod->SPIsetRegValue(SI443X_REG_OP_FUNC_CONTROL_2, SI443X_RX_FIFO_CLEAR, 1, 1); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_RESET, 1, 1); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_CLEAR, 1, 1); // clear interrupt flags clearIRQFlags(); @@ -267,11 +271,11 @@ int16_t Si443x::startReceive() { _mod->setRfSwitchState(HIGH, LOW); // set interrupt mapping - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_1, SI443X_VALID_PACKET_RECEIVED_ENABLED | SI443X_CRC_ERROR_ENABLED); - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_VALID_PACKET_RECEIVED_ENABLED | RADIOLIB_SI443X_CRC_ERROR_ENABLED); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00); // set mode to receive - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_RX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON); return(state); } @@ -282,12 +286,12 @@ int16_t Si443x::readData(uint8_t* data, size_t len) { // get packet length size_t length = len; - if(len == SI443X_MAX_PACKET_LENGTH) { + if(len == RADIOLIB_SI443X_MAX_PACKET_LENGTH) { length = getPacketLength(); } // read packet data - _mod->SPIreadRegisterBurst(SI443X_REG_FIFO_ACCESS, length, data); + _mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, length, data); // clear internal flag so getPacketLength can return the new packet length _packetLengthQueried = false; @@ -299,18 +303,18 @@ int16_t Si443x::readData(uint8_t* data, size_t len) { // clear interrupt flags clearIRQFlags(); - return(ERR_NONE); + return(RADIOLIB_ERR_NONE); } int16_t Si443x::setBitRate(float br) { - RADIOLIB_CHECK_RANGE(br, 0.123, 256.0, ERR_INVALID_BIT_RATE); + RADIOLIB_CHECK_RANGE(br, 0.123, 256.0, RADIOLIB_ERR_INVALID_BIT_RATE); // check high data rate - uint8_t dataRateMode = SI443X_LOW_DATA_RATE_MODE; + uint8_t dataRateMode = RADIOLIB_SI443X_LOW_DATA_RATE_MODE; uint8_t exp = 21; if(br >= 30.0) { // bit rate above 30 kbps - dataRateMode = SI443X_HIGH_DATA_RATE_MODE; + dataRateMode = RADIOLIB_SI443X_HIGH_DATA_RATE_MODE; exp = 16; } @@ -318,11 +322,11 @@ int16_t Si443x::setBitRate(float br) { uint16_t txDr = (br * ((uint32_t)1 << exp)) / 1000.0; // update registers - int16_t state = _mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, dataRateMode, 5, 5); - _mod->SPIwriteRegister(SI443X_REG_TX_DATA_RATE_1, (uint8_t)((txDr & 0xFF00) >> 8)); - _mod->SPIwriteRegister(SI443X_REG_TX_DATA_RATE_0, (uint8_t)(txDr & 0xFF)); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, dataRateMode, 5, 5); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_1, (uint8_t)((txDr & 0xFF00) >> 8)); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_0, (uint8_t)(txDr & 0xFF)); - if(state == ERR_NONE) { + if(state == RADIOLIB_ERR_NONE) { _br = br; } RADIOLIB_ASSERT(state); @@ -340,16 +344,16 @@ int16_t Si443x::setFrequencyDeviation(float freqDev) { newFreqDev = 0.625; } - RADIOLIB_CHECK_RANGE(newFreqDev, 0.625, 320.0, ERR_INVALID_FREQUENCY_DEVIATION); + RADIOLIB_CHECK_RANGE(newFreqDev, 0.625, 320.0, RADIOLIB_ERR_INVALID_FREQUENCY_DEVIATION); // calculate raw frequency deviation value uint16_t fdev = (uint16_t)(newFreqDev / 0.625); // update registers - int16_t state = _mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_2, (uint8_t)((fdev & 0x0100) >> 6), 2, 2); - _mod->SPIwriteRegister(SI443X_REG_FREQUENCY_DEVIATION, (uint8_t)(fdev & 0xFF)); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, (uint8_t)((fdev & 0x0100) >> 6), 2, 2); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_DEVIATION, (uint8_t)(fdev & 0xFF)); - if(state == ERR_NONE) { + if(state == RADIOLIB_ERR_NONE) { _freqDev = newFreqDev; } @@ -357,12 +361,12 @@ int16_t Si443x::setFrequencyDeviation(float freqDev) { } int16_t Si443x::setRxBandwidth(float rxBw) { - RADIOLIB_CHECK_RANGE(rxBw, 2.6, 620.7, ERR_INVALID_RX_BANDWIDTH); + RADIOLIB_CHECK_RANGE(rxBw, 2.6, 620.7, RADIOLIB_ERR_INVALID_RX_BANDWIDTH); // decide which approximation to use for decimation rate and filter tap calculation - uint8_t bypass = SI443X_BYPASS_DEC_BY_3_OFF; - uint8_t decRate = SI443X_IF_FILTER_DEC_RATE; - uint8_t filterSet = SI443X_IF_FILTER_COEFF_SET; + uint8_t bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_OFF; + uint8_t decRate = RADIOLIB_SI443X_IF_FILTER_DEC_RATE; + uint8_t filterSet = RADIOLIB_SI443X_IF_FILTER_COEFF_SET; // this is the "well-behaved" section - can be linearly approximated if((rxBw >= 2.6) && (rxBw <= 4.5)) { @@ -387,74 +391,74 @@ int16_t Si443x::setRxBandwidth(float rxBw) { // this is the "Lord help thee who tread 'ere" section - no way to approximate this mess /// \todo float tolerance equality as macro? } else if(fabs(rxBw - 142.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 1; filterSet = 4; } else if(fabs(rxBw - 167.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 1; filterSet = 5; } else if(fabs(rxBw - 181.1) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 1; filterSet = 6; } else if(fabs(rxBw - 191.5) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 15; } else if(fabs(rxBw - 225.1) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 1; } else if(fabs(rxBw - 248.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 2; } else if(fabs(rxBw - 269.3) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 3; } else if(fabs(rxBw - 284.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 4; } else if(fabs(rxBw -335.5) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 8; } else if(fabs(rxBw - 391.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 9; } else if(fabs(rxBw - 420.2) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 10; } else if(fabs(rxBw - 468.4) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 11; } else if(fabs(rxBw - 518.8) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 12; } else if(fabs(rxBw - 577.0) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 13; } else if(fabs(rxBw - 620.7) <= 0.001) { - bypass = SI443X_BYPASS_DEC_BY_3_ON; + bypass = RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON; decRate = 0; filterSet = 14; } else { - return(ERR_INVALID_RX_BANDWIDTH); + return(RADIOLIB_ERR_INVALID_RX_BANDWIDTH); } // shift decimation rate bits decRate <<= 4; // update register - int16_t state = _mod->SPIsetRegValue(SI443X_REG_IF_FILTER_BANDWIDTH, bypass | decRate | filterSet); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, bypass | decRate | filterSet); RADIOLIB_ASSERT(state); // update clock recovery @@ -464,18 +468,18 @@ int16_t Si443x::setRxBandwidth(float rxBw) { } int16_t Si443x::setSyncWord(uint8_t* syncWord, size_t len) { - RADIOLIB_CHECK_RANGE(len, 1, 4, ERR_INVALID_SYNC_WORD); + RADIOLIB_CHECK_RANGE(len, 1, 4, RADIOLIB_ERR_INVALID_SYNC_WORD); // set mode to standby int16_t state = standby(); RADIOLIB_ASSERT(state); // set sync word length - state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_2, (uint8_t)(len - 1) << 1, 2, 1); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, (uint8_t)(len - 1) << 1, 2, 1); RADIOLIB_ASSERT(state); // set sync word bytes - _mod->SPIwriteRegisterBurst(SI443X_REG_SYNC_WORD_3, syncWord, len); + _mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_SYNC_WORD_3, syncWord, len); return(state); } @@ -483,23 +487,23 @@ int16_t Si443x::setSyncWord(uint8_t* syncWord, size_t len) { int16_t Si443x::setPreambleLength(uint8_t preambleLen) { // Si443x configures preamble length in 4-bit nibbles if(preambleLen % 4 != 0) { - return(ERR_INVALID_PREAMBLE_LENGTH); + return(RADIOLIB_ERR_INVALID_PREAMBLE_LENGTH); } // set default preamble length uint8_t preLenNibbles = preambleLen / 4; - int16_t state = _mod->SPIsetRegValue(SI443X_REG_PREAMBLE_LENGTH, preLenNibbles); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_LENGTH, preLenNibbles); RADIOLIB_ASSERT(state); // set default preamble detection threshold to 5/8 of preamble length (in units of 4 bits) uint8_t preThreshold = 5*preLenNibbles / 8; - return(_mod->SPIsetRegValue(SI443X_REG_PREAMBLE_DET_CONTROL, preThreshold << 3, 7, 3)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_DET_CONTROL, preThreshold << 3, 7, 3)); } size_t Si443x::getPacketLength(bool update) { /// \todo variable length mode if(!_packetLengthQueried && update) { - _packetLength = _mod->SPIreadRegister(SI443X_REG_RECEIVED_PACKET_LENGTH); + _packetLength = _mod->SPIreadRegister(RADIOLIB_SI443X_REG_RECEIVED_PACKET_LENGTH); _packetLengthQueried = true; } @@ -515,13 +519,13 @@ int16_t Si443x::setEncoding(uint8_t encoding) { /// \todo - add inverted Manchester? switch(encoding) { case RADIOLIB_ENCODING_NRZ: - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, SI443X_MANCHESTER_INVERTED_OFF | SI443X_MANCHESTER_OFF | SI443X_WHITENING_OFF, 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0)); case RADIOLIB_ENCODING_MANCHESTER: - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, SI443X_MANCHESTER_INVERTED_OFF | SI443X_MANCHESTER_ON | SI443X_WHITENING_OFF, 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_ON | RADIOLIB_SI443X_WHITENING_OFF, 2, 0)); case RADIOLIB_ENCODING_WHITENING: - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, SI443X_MANCHESTER_INVERTED_OFF | SI443X_MANCHESTER_OFF | SI443X_WHITENING_ON, 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0)); default: - return(ERR_INVALID_ENCODING); + return(RADIOLIB_ERR_INVALID_ENCODING); } } @@ -533,14 +537,14 @@ int16_t Si443x::setDataShaping(uint8_t sh) { // set data shaping switch(sh) { case RADIOLIB_SHAPING_NONE: - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, SI443X_MANCHESTER_INVERTED_OFF | SI443X_MANCHESTER_OFF | SI443X_WHITENING_OFF, 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0)); case RADIOLIB_SHAPING_0_3: case RADIOLIB_SHAPING_0_5: case RADIOLIB_SHAPING_1_0: /// \todo implement fiter configuration - docs claim this should be possible, but seems undocumented - return(_mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, SI443X_MANCHESTER_INVERTED_OFF | SI443X_MANCHESTER_OFF | SI443X_WHITENING_ON, 2, 0)); + return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0)); default: - return(ERR_INVALID_ENCODING); + return(RADIOLIB_ERR_INVALID_ENCODING); } } @@ -550,15 +554,15 @@ void Si443x::setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn) { uint8_t Si443x::randomByte() { // set mode to Rx - _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_RX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON); // wait a bit for the RSSI reading to stabilise - Module::delay(10); + _mod->delay(10); // read RSSI value 8 times, always keep just the least significant bit uint8_t randByte = 0x00; for(uint8_t i = 0; i < 8; i++) { - randByte |= ((_mod->SPIreadRegister(SI443X_REG_RSSI) & 0x01) << i); + randByte |= ((_mod->SPIreadRegister(RADIOLIB_SI443X_REG_RSSI) & 0x01) << i); } // set mode to standby @@ -568,7 +572,7 @@ uint8_t Si443x::randomByte() { } int16_t Si443x::getChipVersion() { - return(_mod->SPIgetRegValue(SI443X_REG_DEVICE_VERSION)); + return(_mod->SPIgetRegValue(RADIOLIB_SI443X_REG_DEVICE_VERSION)); } void Si443x::setDirectAction(void (*func)(void)) { @@ -585,12 +589,12 @@ int16_t Si443x::setFrequencyRaw(float newFreq) { RADIOLIB_ASSERT(state); // check high/low band - uint8_t bandSelect = SI443X_BAND_SELECT_LOW; + uint8_t bandSelect = RADIOLIB_SI443X_BAND_SELECT_LOW; uint8_t freqBand = (newFreq / 10) - 24; uint8_t afcLimiter = 80; _freq = newFreq; if(newFreq >= 480.0) { - bandSelect = SI443X_BAND_SELECT_HIGH; + bandSelect = RADIOLIB_SI443X_BAND_SELECT_HIGH; freqBand = (newFreq / 20) - 24; afcLimiter = 40; } @@ -599,10 +603,10 @@ int16_t Si443x::setFrequencyRaw(float newFreq) { uint16_t freqCarrier = ((newFreq / (10 * ((bandSelect >> 5) + 1))) - freqBand - 24) * (uint32_t)64000; // update registers - state = _mod->SPIsetRegValue(SI443X_REG_FREQUENCY_BAND_SELECT, bandSelect | freqBand, 5, 0); - state |= _mod->SPIsetRegValue(SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8)); - state |= _mod->SPIsetRegValue(SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF)); - state |= _mod->SPIsetRegValue(SI443X_REG_AFC_LIMITER, afcLimiter); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, bandSelect | freqBand, 5, 0); + state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8)); + state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF)); + state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AFC_LIMITER, afcLimiter); return(state); } @@ -615,22 +619,22 @@ bool Si443x::findChip() { reset(); // check version register - uint8_t version = _mod->SPIreadRegister(SI443X_REG_DEVICE_VERSION); - if(version == SI443X_DEVICE_VERSION) { + uint8_t version = _mod->SPIreadRegister(RADIOLIB_SI443X_REG_DEVICE_VERSION); + if(version == RADIOLIB_SI443X_DEVICE_VERSION) { flagFound = true; } else { - #ifdef RADIOLIB_DEBUG + #if defined(RADIOLIB_DEBUG) RADIOLIB_DEBUG_PRINT(F("Si443x not found! (")); RADIOLIB_DEBUG_PRINT(i + 1); - RADIOLIB_DEBUG_PRINT(F(" of 10 tries) SI443X_REG_DEVICE_VERSION == ")); + RADIOLIB_DEBUG_PRINT(F(" of 10 tries) RADIOLIB_SI443X_REG_DEVICE_VERSION == ")); char buffHex[5]; sprintf(buffHex, "0x%02X", version); RADIOLIB_DEBUG_PRINT(buffHex); RADIOLIB_DEBUG_PRINT(F(", expected 0x00")); - RADIOLIB_DEBUG_PRINTLN(SI443X_DEVICE_VERSION, HEX); + RADIOLIB_DEBUG_PRINTLN(RADIOLIB_SI443X_DEVICE_VERSION, HEX); #endif - Module::delay(10); + _mod->delay(10); i++; } } @@ -640,7 +644,7 @@ bool Si443x::findChip() { void Si443x::clearIRQFlags() { uint8_t buff[2]; - _mod->SPIreadRegisterBurst(SI443X_REG_INTERRUPT_STATUS_1, 2, buff); + _mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_INTERRUPT_STATUS_1, 2, buff); } int16_t Si443x::config() { @@ -649,22 +653,22 @@ int16_t Si443x::config() { RADIOLIB_ASSERT(state); // disable POR and chip ready interrupts - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); + _mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00); // enable AGC - state = _mod->SPIsetRegValue(SI443X_REG_AGC_OVERRIDE_1, SI443X_AGC_GAIN_INCREASE_ON | SI443X_AGC_ON, 6, 5); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AGC_OVERRIDE_1, RADIOLIB_SI443X_AGC_GAIN_INCREASE_ON | RADIOLIB_SI443X_AGC_ON, 6, 5); RADIOLIB_ASSERT(state); // disable packet header - state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_2, SI443X_SYNC_WORD_TIMEOUT_OFF | SI443X_HEADER_LENGTH_HEADER_NONE, 7, 4); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, RADIOLIB_SI443X_SYNC_WORD_TIMEOUT_OFF | RADIOLIB_SI443X_HEADER_LENGTH_HEADER_NONE, 7, 4); RADIOLIB_ASSERT(state); // set antenna switching - _mod->SPIsetRegValue(SI443X_REG_GPIO0_CONFIG, SI443X_GPIOX_TX_STATE_OUT, 4, 0); - _mod->SPIsetRegValue(SI443X_REG_GPIO1_CONFIG, SI443X_GPIOX_RX_STATE_OUT, 4, 0); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO0_CONFIG, RADIOLIB_SI443X_GPIOX_TX_STATE_OUT, 4, 0); + _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_RX_STATE_OUT, 4, 0); // disable packet header checking - state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_1, SI443X_BROADCAST_ADDR_CHECK_NONE | SI443X_RECEIVED_HEADER_CHECK_NONE); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_1, RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_NONE | RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_NONE); RADIOLIB_ASSERT(state); return(state); @@ -672,9 +676,9 @@ int16_t Si443x::config() { int16_t Si443x::updateClockRecovery() { // get the parameters - uint8_t bypass = _mod->SPIgetRegValue(SI443X_REG_IF_FILTER_BANDWIDTH, 7, 7) >> 7; - uint8_t decRate = _mod->SPIgetRegValue(SI443X_REG_IF_FILTER_BANDWIDTH, 6, 4) >> 4; - uint8_t manch = _mod->SPIgetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_1, 1, 1) >> 1; + uint8_t bypass = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 7, 7) >> 7; + uint8_t decRate = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 6, 4) >> 4; + uint8_t manch = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, 1, 1) >> 1; // calculate oversampling ratio, NCO offset and clock recovery gain int8_t ndecExp = (int8_t)decRate - 3; @@ -707,39 +711,39 @@ int16_t Si443x::updateClockRecovery() { RADIOLIB_DEBUG_PRINTLN(crGain, HEX); // update oversampling ratio - int16_t state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((rxOsr_fixed & 0x0700) >> 3), 7, 5); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((rxOsr_fixed & 0x0700) >> 3), 7, 5); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_OVERSAMP_RATIO, (uint8_t)(rxOsr_fixed & 0x00FF)); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OVERSAMP_RATIO, (uint8_t)(rxOsr_fixed & 0x00FF)); RADIOLIB_ASSERT(state); // update NCO offset - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((ncoOff & 0x0F0000) >> 16), 3, 0); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((ncoOff & 0x0F0000) >> 16), 3, 0); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_OFFSET_1, (uint8_t)((ncoOff & 0x00FF00) >> 8)); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_1, (uint8_t)((ncoOff & 0x00FF00) >> 8)); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_OFFSET_0, (uint8_t)(ncoOff & 0x0000FF)); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_0, (uint8_t)(ncoOff & 0x0000FF)); RADIOLIB_ASSERT(state); // update clock recovery loop gain - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1, (uint8_t)((crGain & 0x0700) >> 8), 2, 0); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1, (uint8_t)((crGain & 0x0700) >> 8), 2, 0); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0, (uint8_t)(crGain & 0x00FF)); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0, (uint8_t)(crGain & 0x00FF)); RADIOLIB_ASSERT(state); return(state); } int16_t Si443x::directMode() { - int16_t state = _mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_2, SI443X_TX_DATA_SOURCE_GPIO, 5, 4); + int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_GPIO, 5, 4); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_GPIO1_CONFIG, SI443X_GPIOX_TX_RX_DATA_CLK_OUT, 4, 0); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_TX_RX_DATA_CLK_OUT, 4, 0); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_GPIO2_CONFIG, SI443X_GPIOX_TX_DATA_IN, 4, 0); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO2_CONFIG, RADIOLIB_SI443X_GPIOX_TX_DATA_IN, 4, 0); RADIOLIB_ASSERT(state); - state = _mod->SPIsetRegValue(SI443X_REG_MODULATION_MODE_CONTROL_2, SI443X_MODULATION_FSK, 1, 0); + state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0); return(state); } diff --git a/src/modules/Si443x/Si443x.h b/src/modules/Si443x/Si443x.h index cc9cf905..1072e289 100644 --- a/src/modules/Si443x/Si443x.h +++ b/src/modules/Si443x/Si443x.h @@ -10,540 +10,540 @@ #include "../../protocols/PhysicalLayer/PhysicalLayer.h" // Si443x physical layer properties -#define SI443X_FREQUENCY_STEP_SIZE 156.25 -#define SI443X_MAX_PACKET_LENGTH 64 +#define RADIOLIB_SI443X_FREQUENCY_STEP_SIZE 156.25 +#define RADIOLIB_SI443X_MAX_PACKET_LENGTH 64 // Si443x series common registers -#define SI443X_REG_DEVICE_TYPE 0x00 -#define SI443X_REG_DEVICE_VERSION 0x01 -#define SI443X_REG_DEVICE_STATUS 0x02 -#define SI443X_REG_INTERRUPT_STATUS_1 0x03 -#define SI443X_REG_INTERRUPT_STATUS_2 0x04 -#define SI443X_REG_INTERRUPT_ENABLE_1 0x05 -#define SI443X_REG_INTERRUPT_ENABLE_2 0x06 -#define SI443X_REG_OP_FUNC_CONTROL_1 0x07 -#define SI443X_REG_OP_FUNC_CONTROL_2 0x08 -#define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09 -#define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A -#define SI443X_REG_GPIO0_CONFIG 0x0B -#define SI443X_REG_GPIO1_CONFIG 0x0C -#define SI443X_REG_GPIO2_CONFIG 0x0D -#define SI443X_REG_IO_PORT_CONFIG 0x0E -#define SI443X_REG_ADC_CONFIG 0x0F -#define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10 -#define SI443X_REG_ADC_VALUE 0x11 -#define SI443X_REG_TEMP_SENSOR_CONTROL 0x12 -#define SI443X_REG_TEMP_VALUE_OFFSET 0x13 -#define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14 -#define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15 -#define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16 -#define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17 -#define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18 -#define SI443X_REG_LOW_DC_MODE_DURATION 0x19 -#define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A -#define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B -#define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C -#define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D -#define SI443X_REG_AFC_TIMING_CONTROL 0x1E -#define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F -#define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20 -#define SI443X_REG_CLOCK_REC_OFFSET_2 0x21 -#define SI443X_REG_CLOCK_REC_OFFSET_1 0x22 -#define SI443X_REG_CLOCK_REC_OFFSET_0 0x23 -#define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24 -#define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25 -#define SI443X_REG_RSSI 0x26 -#define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27 -#define SI443X_REG_ANTENNA_DIVERSITY_1 0x28 -#define SI443X_REG_ANTENNA_DIVERSITY_2 0x29 -#define SI443X_REG_AFC_LIMITER 0x2A -#define SI443X_REG_AFC_CORRECTION 0x2B -#define SI443X_REG_OOK_COUNTER_1 0x2C -#define SI443X_REG_OOK_COUNTER_2 0x2D -#define SI443X_REG_SLICER_PEAK_HOLD 0x2E -#define SI443X_REG_DATA_ACCESS_CONTROL 0x30 -#define SI443X_REG_EZMAC_STATUS 0x31 -#define SI443X_REG_HEADER_CONTROL_1 0x32 -#define SI443X_REG_HEADER_CONTROL_2 0x33 -#define SI443X_REG_PREAMBLE_LENGTH 0x34 -#define SI443X_REG_PREAMBLE_DET_CONTROL 0x35 -#define SI443X_REG_SYNC_WORD_3 0x36 -#define SI443X_REG_SYNC_WORD_2 0x37 -#define SI443X_REG_SYNC_WORD_1 0x38 -#define SI443X_REG_SYNC_WORD_0 0x39 -#define SI443X_REG_TRANSMIT_HEADER_3 0x3A -#define SI443X_REG_TRANSMIT_HEADER_2 0x3B -#define SI443X_REG_TRANSMIT_HEADER_1 0x3C -#define SI443X_REG_TRANSMIT_HEADER_0 0x3D -#define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E -#define SI443X_REG_CHECK_HEADER_3 0x3F -#define SI443X_REG_CHECK_HEADER_2 0x40 -#define SI443X_REG_CHECK_HEADER_1 0x41 -#define SI443X_REG_CHECK_HEADER_0 0x42 -#define SI443X_REG_HEADER_ENABLE_3 0x43 -#define SI443X_REG_HEADER_ENABLE_2 0x44 -#define SI443X_REG_HEADER_ENABLE_1 0x45 -#define SI443X_REG_HEADER_ENABLE_0 0x46 -#define SI443X_REG_RECEIVED_HEADER_3 0x47 -#define SI443X_REG_RECEIVED_HEADER_2 0x48 -#define SI443X_REG_RECEIVED_HEADER_1 0x49 -#define SI443X_REG_RECEIVED_HEADER_0 0x4A -#define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B -#define SI443X_REG_ADC8_CONTROL 0x4F -#define SI443X_REG_CHANNEL_FILTER_COEFF 0x60 -#define SI443X_REG_XOSC_CONTROL_TEST 0x62 -#define SI443X_REG_AGC_OVERRIDE_1 0x69 -#define SI443X_REG_TX_POWER 0x6D -#define SI443X_REG_TX_DATA_RATE_1 0x6E -#define SI443X_REG_TX_DATA_RATE_0 0x6F -#define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70 -#define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71 -#define SI443X_REG_FREQUENCY_DEVIATION 0x72 -#define SI443X_REG_FREQUENCY_OFFSET_1 0x73 -#define SI443X_REG_FREQUENCY_OFFSET_2 0x74 -#define SI443X_REG_FREQUENCY_BAND_SELECT 0x75 -#define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76 -#define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77 -#define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79 -#define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A -#define SI443X_REG_TX_FIFO_CONTROL_1 0x7C -#define SI443X_REG_TX_FIFO_CONTROL_2 0x7D -#define SI443X_REG_RX_FIFO_CONTROL 0x7E -#define SI443X_REG_FIFO_ACCESS 0x7F +#define RADIOLIB_SI443X_REG_DEVICE_TYPE 0x00 +#define RADIOLIB_SI443X_REG_DEVICE_VERSION 0x01 +#define RADIOLIB_SI443X_REG_DEVICE_STATUS 0x02 +#define RADIOLIB_SI443X_REG_INTERRUPT_STATUS_1 0x03 +#define RADIOLIB_SI443X_REG_INTERRUPT_STATUS_2 0x04 +#define RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1 0x05 +#define RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2 0x06 +#define RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1 0x07 +#define RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2 0x08 +#define RADIOLIB_SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09 +#define RADIOLIB_SI443X_REG_MCU_OUTPUT_CLOCK 0x0A +#define RADIOLIB_SI443X_REG_GPIO0_CONFIG 0x0B +#define RADIOLIB_SI443X_REG_GPIO1_CONFIG 0x0C +#define RADIOLIB_SI443X_REG_GPIO2_CONFIG 0x0D +#define RADIOLIB_SI443X_REG_IO_PORT_CONFIG 0x0E +#define RADIOLIB_SI443X_REG_ADC_CONFIG 0x0F +#define RADIOLIB_SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10 +#define RADIOLIB_SI443X_REG_ADC_VALUE 0x11 +#define RADIOLIB_SI443X_REG_TEMP_SENSOR_CONTROL 0x12 +#define RADIOLIB_SI443X_REG_TEMP_VALUE_OFFSET 0x13 +#define RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14 +#define RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15 +#define RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16 +#define RADIOLIB_SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17 +#define RADIOLIB_SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18 +#define RADIOLIB_SI443X_REG_LOW_DC_MODE_DURATION 0x19 +#define RADIOLIB_SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A +#define RADIOLIB_SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B +#define RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH 0x1C +#define RADIOLIB_SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D +#define RADIOLIB_SI443X_REG_AFC_TIMING_CONTROL 0x1E +#define RADIOLIB_SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F +#define RADIOLIB_SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20 +#define RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2 0x21 +#define RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_1 0x22 +#define RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_0 0x23 +#define RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24 +#define RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25 +#define RADIOLIB_SI443X_REG_RSSI 0x26 +#define RADIOLIB_SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27 +#define RADIOLIB_SI443X_REG_ANTENNA_DIVERSITY_1 0x28 +#define RADIOLIB_SI443X_REG_ANTENNA_DIVERSITY_2 0x29 +#define RADIOLIB_SI443X_REG_AFC_LIMITER 0x2A +#define RADIOLIB_SI443X_REG_AFC_CORRECTION 0x2B +#define RADIOLIB_SI443X_REG_OOK_COUNTER_1 0x2C +#define RADIOLIB_SI443X_REG_OOK_COUNTER_2 0x2D +#define RADIOLIB_SI443X_REG_SLICER_PEAK_HOLD 0x2E +#define RADIOLIB_SI443X_REG_DATA_ACCESS_CONTROL 0x30 +#define RADIOLIB_SI443X_REG_EZMAC_STATUS 0x31 +#define RADIOLIB_SI443X_REG_HEADER_CONTROL_1 0x32 +#define RADIOLIB_SI443X_REG_HEADER_CONTROL_2 0x33 +#define RADIOLIB_SI443X_REG_PREAMBLE_LENGTH 0x34 +#define RADIOLIB_SI443X_REG_PREAMBLE_DET_CONTROL 0x35 +#define RADIOLIB_SI443X_REG_SYNC_WORD_3 0x36 +#define RADIOLIB_SI443X_REG_SYNC_WORD_2 0x37 +#define RADIOLIB_SI443X_REG_SYNC_WORD_1 0x38 +#define RADIOLIB_SI443X_REG_SYNC_WORD_0 0x39 +#define RADIOLIB_SI443X_REG_TRANSMIT_HEADER_3 0x3A +#define RADIOLIB_SI443X_REG_TRANSMIT_HEADER_2 0x3B +#define RADIOLIB_SI443X_REG_TRANSMIT_HEADER_1 0x3C +#define RADIOLIB_SI443X_REG_TRANSMIT_HEADER_0 0x3D +#define RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E +#define RADIOLIB_SI443X_REG_CHECK_HEADER_3 0x3F +#define RADIOLIB_SI443X_REG_CHECK_HEADER_2 0x40 +#define RADIOLIB_SI443X_REG_CHECK_HEADER_1 0x41 +#define RADIOLIB_SI443X_REG_CHECK_HEADER_0 0x42 +#define RADIOLIB_SI443X_REG_HEADER_ENABLE_3 0x43 +#define RADIOLIB_SI443X_REG_HEADER_ENABLE_2 0x44 +#define RADIOLIB_SI443X_REG_HEADER_ENABLE_1 0x45 +#define RADIOLIB_SI443X_REG_HEADER_ENABLE_0 0x46 +#define RADIOLIB_SI443X_REG_RECEIVED_HEADER_3 0x47 +#define RADIOLIB_SI443X_REG_RECEIVED_HEADER_2 0x48 +#define RADIOLIB_SI443X_REG_RECEIVED_HEADER_1 0x49 +#define RADIOLIB_SI443X_REG_RECEIVED_HEADER_0 0x4A +#define RADIOLIB_SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B +#define RADIOLIB_SI443X_REG_ADC8_CONTROL 0x4F +#define RADIOLIB_SI443X_REG_CHANNEL_FILTER_COEFF 0x60 +#define RADIOLIB_SI443X_REG_XOSC_CONTROL_TEST 0x62 +#define RADIOLIB_SI443X_REG_AGC_OVERRIDE_1 0x69 +#define RADIOLIB_SI443X_REG_TX_POWER 0x6D +#define RADIOLIB_SI443X_REG_TX_DATA_RATE_1 0x6E +#define RADIOLIB_SI443X_REG_TX_DATA_RATE_0 0x6F +#define RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1 0x70 +#define RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2 0x71 +#define RADIOLIB_SI443X_REG_FREQUENCY_DEVIATION 0x72 +#define RADIOLIB_SI443X_REG_FREQUENCY_OFFSET_1 0x73 +#define RADIOLIB_SI443X_REG_FREQUENCY_OFFSET_2 0x74 +#define RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT 0x75 +#define RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76 +#define RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77 +#define RADIOLIB_SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79 +#define RADIOLIB_SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A +#define RADIOLIB_SI443X_REG_TX_FIFO_CONTROL_1 0x7C +#define RADIOLIB_SI443X_REG_TX_FIFO_CONTROL_2 0x7D +#define RADIOLIB_SI443X_REG_RX_FIFO_CONTROL 0x7E +#define RADIOLIB_SI443X_REG_FIFO_ACCESS 0x7F -// SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION -#define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register +// RADIOLIB_SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION +#define RADIOLIB_SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register -// SI443X_REG_DEVICE_VERSION -#define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register +// RADIOLIB_SI443X_REG_DEVICE_VERSION +#define RADIOLIB_SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register -// SI443X_REG_DEVICE_STATUS -#define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag -#define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag -#define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag -#define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag -#define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range) -#define SI443X_TX 0b00000010 // 1 0 power state: Tx -#define SI443X_RX 0b00000001 // 1 0 Rx -#define SI443X_IDLE 0b00000000 // 1 0 idle +// RADIOLIB_SI443X_REG_DEVICE_STATUS +#define RADIOLIB_SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag +#define RADIOLIB_SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag +#define RADIOLIB_SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag +#define RADIOLIB_SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag +#define RADIOLIB_SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range) +#define RADIOLIB_SI443X_TX 0b00000010 // 1 0 power state: Tx +#define RADIOLIB_SI443X_RX 0b00000001 // 1 0 Rx +#define RADIOLIB_SI443X_IDLE 0b00000000 // 1 0 idle -// SI443X_REG_INTERRUPT_STATUS_1 -#define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow -#define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full -#define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty -#define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full -#define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx -#define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done -#define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received -#define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed +// RADIOLIB_SI443X_REG_INTERRUPT_STATUS_1 +#define RADIOLIB_SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty +#define RADIOLIB_SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full +#define RADIOLIB_SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx +#define RADIOLIB_SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done +#define RADIOLIB_SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received +#define RADIOLIB_SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed -// SI443X_REG_INTERRUPT_STATUS_2 -#define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected -#define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected -#define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected -#define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold -#define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired -#define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected -#define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected -#define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected +// RADIOLIB_SI443X_REG_INTERRUPT_STATUS_2 +#define RADIOLIB_SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected +#define RADIOLIB_SI443X_VALID_RADIOLIB_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected +#define RADIOLIB_SI443X_INVALID_RADIOLIB_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected +#define RADIOLIB_SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold +#define RADIOLIB_SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired +#define RADIOLIB_SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected +#define RADIOLIB_SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected +#define RADIOLIB_SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected -// SI443X_REG_INTERRUPT_ENABLE_1 -#define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled -#define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled -#define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled -#define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled -#define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled -#define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled -#define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled -#define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled +// RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1 +#define RADIOLIB_SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled +#define RADIOLIB_SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled +#define RADIOLIB_SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled +#define RADIOLIB_SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled +#define RADIOLIB_SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled +#define RADIOLIB_SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled -// SI443X_REG_INTERRUPT_ENABLE_2 -#define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled -#define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled -#define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled -#define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled -#define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled -#define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled -#define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled -#define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled +// RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2 +#define RADIOLIB_SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled +#define RADIOLIB_SI443X_VALID_RADIOLIB_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled +#define RADIOLIB_SI443X_INVALID_RADIOLIB_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled +#define RADIOLIB_SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled +#define RADIOLIB_SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled +#define RADIOLIB_SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled +#define RADIOLIB_SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled +#define RADIOLIB_SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled -// SI443X_REG_OP_FUNC_CONTROL_1 -#define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values -#define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection -#define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer -#define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default) -#define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator -#define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode -#define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode -#define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode) -#define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode) -#define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode) +// RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1 +#define RADIOLIB_SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values +#define RADIOLIB_SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection +#define RADIOLIB_SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer +#define RADIOLIB_SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default) +#define RADIOLIB_SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator +#define RADIOLIB_SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode +#define RADIOLIB_SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode +#define RADIOLIB_SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode) +#define RADIOLIB_SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode) +#define RADIOLIB_SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode) -// SI443X_REG_OP_FUNC_CONTROL_2 -#define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default) -#define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low -#define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high -#define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high -#define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low -#define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high -#define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low -#define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high -#define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default) -#define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled -#define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default) -#define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled -#define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default) -#define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled -#define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first) -#define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second) -#define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first) -#define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second) +// RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2 +#define RADIOLIB_SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default) +#define RADIOLIB_SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low +#define RADIOLIB_SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high +#define RADIOLIB_SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high +#define RADIOLIB_SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low +#define RADIOLIB_SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high +#define RADIOLIB_SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low +#define RADIOLIB_SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high +#define RADIOLIB_SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default) +#define RADIOLIB_SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled +#define RADIOLIB_SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default) +#define RADIOLIB_SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default) +#define RADIOLIB_SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled +#define RADIOLIB_SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first) +#define RADIOLIB_SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second) +#define RADIOLIB_SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first) +#define RADIOLIB_SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second) -// SI443X_REG_XOSC_LOAD_CAPACITANCE -#define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration: -#define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT +// RADIOLIB_SI443X_REG_XOSC_LOAD_CAPACITANCE +#define RADIOLIB_SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration: +#define RADIOLIB_SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * RADIOLIB_SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * RADIOLIB_SI443X_XTAL_SHIFT -// SI443X_REG_MCU_OUTPUT_CLOCK -#define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default) -#define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128 -#define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256 -#define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512 -#define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default) -#define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled -#define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz -#define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz -#define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz -#define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz -#define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz -#define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz -#define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default) -#define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz +// RADIOLIB_SI443X_REG_MCU_OUTPUT_CLOCK +#define RADIOLIB_SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default) +#define RADIOLIB_SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128 +#define RADIOLIB_SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256 +#define RADIOLIB_SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512 +#define RADIOLIB_SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default) +#define RADIOLIB_SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz +#define RADIOLIB_SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default) +#define RADIOLIB_SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz -// SI443X_REG_GPIO0_CONFIG + SI443X_REG_GPIO1_CONFIG + SI443X_REG_GPIO2_CONFIG -#define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive) -#define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default) -#define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled -#define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default) -#define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default) -#define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default) -#define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output -#define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output -#define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output -#define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge -#define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge -#define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change -#define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input -#define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input -#define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input -#define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input -#define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output -#define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output -#define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output -#define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output -#define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode -#define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode -#define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input -#define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output -#define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output -#define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output -#define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output -#define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output -#define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1 -#define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2 -#define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output -#define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output -#define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output -#define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output -#define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD -#define SI443X_GPIOX_GND 0b00011110 // 4 0 GND +// RADIOLIB_SI443X_REG_GPIO0_CONFIG + RADIOLIB_SI443X_REG_GPIO1_CONFIG + RADIOLIB_SI443X_REG_GPIO2_CONFIG +#define RADIOLIB_SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive) +#define RADIOLIB_SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default) +#define RADIOLIB_SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled +#define RADIOLIB_SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default) +#define RADIOLIB_SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default) +#define RADIOLIB_SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default) +#define RADIOLIB_SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output +#define RADIOLIB_SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output +#define RADIOLIB_SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output +#define RADIOLIB_SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge +#define RADIOLIB_SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge +#define RADIOLIB_SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change +#define RADIOLIB_SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input +#define RADIOLIB_SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input +#define RADIOLIB_SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input +#define RADIOLIB_SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input +#define RADIOLIB_SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output +#define RADIOLIB_SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output +#define RADIOLIB_SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output +#define RADIOLIB_SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output +#define RADIOLIB_SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode +#define RADIOLIB_SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode +#define RADIOLIB_SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input +#define RADIOLIB_SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output +#define RADIOLIB_SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output +#define RADIOLIB_SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output +#define RADIOLIB_SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output +#define RADIOLIB_SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output +#define RADIOLIB_SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1 +#define RADIOLIB_SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2 +#define RADIOLIB_SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output +#define RADIOLIB_SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output +#define RADIOLIB_SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output +#define RADIOLIB_SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output +#define RADIOLIB_SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD +#define RADIOLIB_SI443X_GPIOX_GND 0b00011110 // 4 0 GND -// SI443X_REG_IO_PORT_CONFIG -#define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2 -#define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1 -#define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0 -#define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default) -#define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled -#define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2 -#define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1 -#define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0 +// RADIOLIB_SI443X_REG_IO_PORT_CONFIG +#define RADIOLIB_SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2 +#define RADIOLIB_SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1 +#define RADIOLIB_SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0 +#define RADIOLIB_SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default) +#define RADIOLIB_SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2 +#define RADIOLIB_SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1 +#define RADIOLIB_SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0 -// SI443X_REG_ADC_CONFIG -#define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement -#define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress -#define SI443X_ADC_DONE 0b10000000 // 7 7 done -#define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default) -#define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0 -#define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1 -#define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2 -#define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-) -#define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-) -#define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-) -#define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND -#define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default) -#define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3 -#define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2 -#define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain +// RADIOLIB_SI443X_REG_ADC_CONFIG +#define RADIOLIB_SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement +#define RADIOLIB_SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress +#define RADIOLIB_SI443X_ADC_DONE 0b10000000 // 7 7 done +#define RADIOLIB_SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default) +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0 +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1 +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2 +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-) +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-) +#define RADIOLIB_SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-) +#define RADIOLIB_SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND +#define RADIOLIB_SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default) +#define RADIOLIB_SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3 +#define RADIOLIB_SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2 +#define RADIOLIB_SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain -// SI443X_REG_ADC_SENSOR_AMP_OFFSET -#define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset +// RADIOLIB_SI443X_REG_ADC_SENSOR_AMP_OFFSET +#define RADIOLIB_SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset -// SI443X_REG_TEMP_SENSOR_CONTROL -#define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default) -#define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution -#define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution -#define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution -#define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled -#define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default) -#define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default) -#define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled -#define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value +// RADIOLIB_SI443X_REG_TEMP_SENSOR_CONTROL +#define RADIOLIB_SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default) +#define RADIOLIB_SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution +#define RADIOLIB_SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution +#define RADIOLIB_SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution +#define RADIOLIB_SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled +#define RADIOLIB_SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default) +#define RADIOLIB_SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default) +#define RADIOLIB_SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled +#define RADIOLIB_SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value -// SI443X_REG_WAKEUP_TIMER_PERIOD_1 -#define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent +// RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_1 +#define RADIOLIB_SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent -// SI443X_REG_WAKEUP_TIMER_PERIOD_2 + SI443X_REG_WAKEUP_TIMER_PERIOD_3 -#define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value: -#define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms +// RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_2 + RADIOLIB_SI443X_REG_WAKEUP_TIMER_PERIOD_3 +#define RADIOLIB_SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value: +#define RADIOLIB_SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * RADIOLIB_SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ RADIOLIB_SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms -// SI443X_REG_LOW_DC_MODE_DURATION -#define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms +// RADIOLIB_SI443X_REG_LOW_DC_MODE_DURATION +#define RADIOLIB_SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * RADIOLIB_SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ RADIOLIB_SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms -// SI443X_REG_LOW_BATT_DET_THRESHOLD -#define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V) +// RADIOLIB_SI443X_REG_LOW_BATT_DET_THRESHOLD +#define RADIOLIB_SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + RADIOLIB_SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V) -// SI443X_REG_IF_FILTER_BANDWIDTH -#define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default) -#define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled -#define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate -#define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection +// RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH +#define RADIOLIB_SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default) +#define RADIOLIB_SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled +#define RADIOLIB_SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate +#define RADIOLIB_SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection -// SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE -#define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default) -#define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled -#define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled -#define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default) -#define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting -#define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default) -#define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB -#define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb -#define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default) -#define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default) -#define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases +// RADIOLIB_SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE +#define RADIOLIB_SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default) +#define RADIOLIB_SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled +#define RADIOLIB_SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled +#define RADIOLIB_SI443X_AFC_ON 0b01000000 // 6 6 enabled (default) +#define RADIOLIB_SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting +#define RADIOLIB_SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default) +#define RADIOLIB_SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB +#define RADIOLIB_SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb +#define RADIOLIB_SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default) +#define RADIOLIB_SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default) +#define RADIOLIB_SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases -// SI443X_REG_AFC_TIMING_CONTROL -#define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching -#define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction -#define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time +// RADIOLIB_SI443X_REG_AFC_TIMING_CONTROL +#define RADIOLIB_SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching +#define RADIOLIB_SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction +#define RADIOLIB_SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time -// SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE -#define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value -#define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value +// RADIOLIB_SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE +#define RADIOLIB_SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value +#define RADIOLIB_SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value -// SI443X_REG_CLOCK_REC_OVERSAMP_RATIO -#define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit +// RADIOLIB_SI443X_REG_CLOCK_REC_OVERSAMP_RATIO +#define RADIOLIB_SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit -// SI443X_REG_CLOCK_REC_OFFSET_2 -#define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit -#define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold -#define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB +// RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2 +#define RADIOLIB_SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit +#define RADIOLIB_SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold +#define RADIOLIB_SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB -// SI443X_REG_CLOCK_REC_OFFSET_1 -#define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID +// RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_1 +#define RADIOLIB_SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID -// SI443X_REG_CLOCK_REC_OFFSET_0 -#define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB +// RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_0 +#define RADIOLIB_SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB -// SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 -#define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default) -#define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled -#define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default) -#define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled -#define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB +// RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 +#define RADIOLIB_SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default) +#define RADIOLIB_SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled +#define RADIOLIB_SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default) +#define RADIOLIB_SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB -// SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 -#define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB +// RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 +#define RADIOLIB_SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB -// SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD -#define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold +// RADIOLIB_SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD +#define RADIOLIB_SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold -// SI443X_REG_AFC_LIMITER -#define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value +// RADIOLIB_SI443X_REG_AFC_LIMITER +#define RADIOLIB_SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value -// SI443X_REG_OOK_COUNTER_1 -#define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default) -#define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled -#define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled -#define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default) -#define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled -#define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default) -#define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB +// RADIOLIB_SI443X_REG_OOK_COUNTER_1 +#define RADIOLIB_SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default) +#define RADIOLIB_SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled +#define RADIOLIB_SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled +#define RADIOLIB_SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default) +#define RADIOLIB_SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled +#define RADIOLIB_SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default) +#define RADIOLIB_SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB -// SI443X_REG_OOK_COUNTER_2 -#define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB +// RADIOLIB_SI443X_REG_OOK_COUNTER_2 +#define RADIOLIB_SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB -// SI443X_REG_SLICER_PEAK_HOLD -#define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time -#define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time +// RADIOLIB_SI443X_REG_SLICER_PEAK_HOLD +#define RADIOLIB_SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time +#define RADIOLIB_SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time -// SI443X_REG_DATA_ACCESS_CONTROL -#define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled -#define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default) -#define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default) -#define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled -#define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default) -#define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled -#define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default) -#define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled -#define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled -#define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default) -#define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled -#define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default) -#define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT -#define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default) -#define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16 -#define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva +// RADIOLIB_SI443X_REG_DATA_ACCESS_CONTROL +#define RADIOLIB_SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled +#define RADIOLIB_SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default) +#define RADIOLIB_SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default) +#define RADIOLIB_SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled +#define RADIOLIB_SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default) +#define RADIOLIB_SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled +#define RADIOLIB_SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default) +#define RADIOLIB_SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled +#define RADIOLIB_SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled +#define RADIOLIB_SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default) +#define RADIOLIB_SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled +#define RADIOLIB_SI443X_CRC_ON 0b00000100 // 2 2 enabled (default) +#define RADIOLIB_SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT +#define RADIOLIB_SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default) +#define RADIOLIB_SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16 +#define RADIOLIB_SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva -// SI443X_REG_EZMAC_STATUS -#define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones -#define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet -#define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet -#define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received -#define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed -#define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet -#define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent +// RADIOLIB_SI443X_REG_EZMAC_STATUS +#define RADIOLIB_SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones +#define RADIOLIB_SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet +#define RADIOLIB_SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet +#define RADIOLIB_SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received +#define RADIOLIB_SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed +#define RADIOLIB_SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet +#define RADIOLIB_SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent -// SI443X_REG_HEADER_CONTROL_1 -#define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default) -#define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0 -#define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1 -#define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2 -#define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3 -#define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none -#define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0 -#define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1 -#define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default) -#define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default) +// RADIOLIB_SI443X_REG_HEADER_CONTROL_1 +#define RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default) +#define RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0 +#define RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1 +#define RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2 +#define RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3 +#define RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none +#define RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0 +#define RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1 +#define RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default) +#define RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default) -// SI443X_REG_HEADER_CONTROL_2 -#define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default) -#define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled -#define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none -#define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3 -#define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2 -#define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default) -#define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0 -#define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default) -#define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled -#define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3 -#define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default) -#define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1 -#define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0 -#define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB +// RADIOLIB_SI443X_REG_HEADER_CONTROL_2 +#define RADIOLIB_SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default) +#define RADIOLIB_SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled +#define RADIOLIB_SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none +#define RADIOLIB_SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3 +#define RADIOLIB_SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2 +#define RADIOLIB_SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default) +#define RADIOLIB_SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0 +#define RADIOLIB_SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default) +#define RADIOLIB_SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3 +#define RADIOLIB_SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default) +#define RADIOLIB_SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1 +#define RADIOLIB_SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0 +#define RADIOLIB_SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB -// SI443X_REG_PREAMBLE_LENGTH -#define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits +// RADIOLIB_SI443X_REG_PREAMBLE_LENGTH +#define RADIOLIB_SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits -// SI443X_REG_PREAMBLE_DET_CONTROL -#define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits -#define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB +// RADIOLIB_SI443X_REG_PREAMBLE_DET_CONTROL +#define RADIOLIB_SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits +#define RADIOLIB_SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB -// SI443X_REG_SYNC_WORD_3 - SI443X_REG_SYNC_WORD_0 -#define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB) -#define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte -#define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte -#define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB) +// RADIOLIB_SI443X_REG_SYNC_WORD_3 - RADIOLIB_SI443X_REG_SYNC_WORD_0 +#define RADIOLIB_SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB) +#define RADIOLIB_SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte +#define RADIOLIB_SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte +#define RADIOLIB_SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB) -// SI443X_REG_CHANNEL_FILTER_COEFF -#define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles +// RADIOLIB_SI443X_REG_CHANNEL_FILTER_COEFF +#define RADIOLIB_SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles -// SI443X_REG_XOSC_CONTROL_TEST -#define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power -#define SI443X_STATE_READY 0b00100000 // 7 5 ready -#define SI443X_STATE_TUNE 0b01100000 // 7 5 tune -#define SI443X_STATE_TX 0b01000000 // 7 5 Tx -#define SI443X_STATE_RX 0b11100000 // 7 5 Rx +// RADIOLIB_SI443X_REG_XOSC_CONTROL_TEST +#define RADIOLIB_SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power +#define RADIOLIB_SI443X_STATE_READY 0b00100000 // 7 5 ready +#define RADIOLIB_SI443X_STATE_TUNE 0b01100000 // 7 5 tune +#define RADIOLIB_SI443X_STATE_TX 0b01000000 // 7 5 Tx +#define RADIOLIB_SI443X_STATE_RX 0b11100000 // 7 5 Rx -// SI443X_REG_AGC_OVERRIDE_1 -#define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default) -#define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled -#define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled -#define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default) -#define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default) -#define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB -#define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB +// RADIOLIB_SI443X_REG_AGC_OVERRIDE_1 +#define RADIOLIB_SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default) +#define RADIOLIB_SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled +#define RADIOLIB_SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled +#define RADIOLIB_SI443X_AGC_ON 0b00100000 // 5 5 enabled (default) +#define RADIOLIB_SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default) +#define RADIOLIB_SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB +#define RADIOLIB_SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = RADIOLIB_SI443X_PGA_GAIN_OVERRIDE * 3 dB -// SI443X_REG_TX_POWER -#define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled -#define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default) -#define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max +// RADIOLIB_SI443X_REG_TX_POWER +#define RADIOLIB_SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled +#define RADIOLIB_SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default) +#define RADIOLIB_SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max -// SI443X_REG_TX_DATA_RATE_1 + SI443X_REG_TX_DATA_RATE_0 -#define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or -#define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps) +// RADIOLIB_SI443X_REG_TX_DATA_RATE_1 + RADIOLIB_SI443X_REG_TX_DATA_RATE_0 +#define RADIOLIB_SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (RADIOLIB_SI443X_DATA_RATE / 2^16) in high data rate mode or +#define RADIOLIB_SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (RADIOLIB_SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps) -// SI443X_REG_MODULATION_MODE_CONTROL_1 -#define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default) -#define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps -#define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default) -#define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled -#define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low -#define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default) -#define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled -#define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default) -#define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default) -#define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled -#define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default) -#define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled +// RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1 +#define RADIOLIB_SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default) +#define RADIOLIB_SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps +#define RADIOLIB_SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default) +#define RADIOLIB_SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled +#define RADIOLIB_SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low +#define RADIOLIB_SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default) +#define RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled +#define RADIOLIB_SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default) +#define RADIOLIB_SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default) +#define RADIOLIB_SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled +#define RADIOLIB_SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default) +#define RADIOLIB_SI443X_WHITENING_ON 0b00000001 // 0 0 enabled -// SI443X_REG_MODULATION_MODE_CONTROL_2 -#define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default) -#define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin -#define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin -#define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin -#define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default) -#define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin -#define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO -#define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal -#define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default) -#define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled -#define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB -#define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default) -#define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK -#define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK -#define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK +// RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2 +#define RADIOLIB_SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default) +#define RADIOLIB_SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin +#define RADIOLIB_SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin +#define RADIOLIB_SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin +#define RADIOLIB_SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default) +#define RADIOLIB_SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin +#define RADIOLIB_SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO +#define RADIOLIB_SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal +#define RADIOLIB_SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default) +#define RADIOLIB_SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled +#define RADIOLIB_SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB +#define RADIOLIB_SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default) +#define RADIOLIB_SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK +#define RADIOLIB_SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK +#define RADIOLIB_SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK -// SI443X_REG_FREQUENCY_DEVIATION -#define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz +// RADIOLIB_SI443X_REG_FREQUENCY_DEVIATION +#define RADIOLIB_SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * RADIOLIB_SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz -// SI443X_REG_FREQUENCY_OFFSET_1 + SI443X_REG_FREQUENCY_OFFSET_2 -#define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset: -#define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz +// RADIOLIB_SI443X_REG_FREQUENCY_OFFSET_1 + RADIOLIB_SI443X_REG_FREQUENCY_OFFSET_2 +#define RADIOLIB_SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset: +#define RADIOLIB_SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (RADIOLIB_SI443X_BAND_SELECT + 1) * RADIOLIB_SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz -// SI443X_REG_FREQUENCY_BAND_SELECT -#define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default) -#define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency -#define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz -#define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default) -#define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select +// RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT +#define RADIOLIB_SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default) +#define RADIOLIB_SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency +#define RADIOLIB_SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz +#define RADIOLIB_SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default) +#define RADIOLIB_SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select -// SI443X_REG_NOM_CARRIER_FREQUENCY_1 + SI443X_REG_NOM_CARRIER_FREQUENCY_0 -#define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency: -#define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz] +// RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1 + RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0 +#define RADIOLIB_SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency: +#define RADIOLIB_SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (RADIOLIB_SI443X_BAND_SELECT + 1)*10*(RADIOLIB_SI443X_FREQUENCY_BAND_SELECT + 24) + (RADIOLIB_SI443X_NOM_CARRIER_FREQUENCY - RADIOLIB_SI443X_FREQUENCY_OFFSET)/6400 [MHz] -// SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL -#define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number +// RADIOLIB_SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL +#define RADIOLIB_SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number -// SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE -#define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size +// RADIOLIB_SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE +#define RADIOLIB_SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size -// SI443X_REG_TX_FIFO_CONTROL_1 -#define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold +// RADIOLIB_SI443X_REG_TX_FIFO_CONTROL_1 +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold -// SI443X_REG_TX_FIFO_CONTROL_2 -#define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold +// RADIOLIB_SI443X_REG_TX_FIFO_CONTROL_2 +#define RADIOLIB_SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold -// SI443X_REG_RX_FIFO_CONTROL -#define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold +// RADIOLIB_SI443X_REG_RX_FIFO_CONTROL +#define RADIOLIB_SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold /*! \class Si443x @@ -568,6 +568,8 @@ class Si443x: public PhysicalLayer { */ Si443x(Module* mod); + Module* getMod(); + // basic methods /*! @@ -793,7 +795,7 @@ class Si443x: public PhysicalLayer { uint8_t randomByte(); /*! - \brief Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. + \brief Read version SPI register. Should return RADIOLIB_SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. \returns Version register contents or \ref status_codes */