[SX128x] Implement staged modes
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jgromes
parent
a8bbdc6eaa
commit
c0bcc219a9
2 changed files with 130 additions and 131 deletions
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@ -513,70 +513,6 @@ void SX128x::clearPacketSentAction() {
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this->clearDio1Action();
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}
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int16_t SX128x::startTransmit(const uint8_t* data, size_t len, uint8_t addr) {
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// suppress unused variable warning
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(void)addr;
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// check packet length
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if(len > RADIOLIB_SX128X_MAX_PACKET_LENGTH) {
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return(RADIOLIB_ERR_PACKET_TOO_LONG);
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}
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// set packet Length
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int16_t state = RADIOLIB_ERR_NONE;
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uint8_t modem = getPacketType();
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if(modem == RADIOLIB_SX128X_PACKET_TYPE_LORA) {
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state = setPacketParamsLoRa(this->preambleLengthLoRa, this->headerType, len, this->crcLoRa, this->invertIQEnabled);
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} else if((modem == RADIOLIB_SX128X_PACKET_TYPE_GFSK) || (modem == RADIOLIB_SX128X_PACKET_TYPE_FLRC)) {
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state = setPacketParamsGFSK(this->preambleLengthGFSK, this->syncWordLen, this->syncWordMatch, this->crcGFSK, this->whitening, len);
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} else if(modem == RADIOLIB_SX128X_PACKET_TYPE_BLE) {
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state = setPacketParamsBLE(this->connectionState, this->crcBLE, this->bleTestPayload, this->whitening);
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} else {
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return(RADIOLIB_ERR_WRONG_MODEM);
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}
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RADIOLIB_ASSERT(state);
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// update output power
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state = setTxParams(this->power);
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RADIOLIB_ASSERT(state);
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// set buffer pointers
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state = setBufferBaseAddress();
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RADIOLIB_ASSERT(state);
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// write packet to buffer
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if(modem == RADIOLIB_SX128X_PACKET_TYPE_BLE) {
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// first 2 bytes of BLE payload are PDU header
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state = writeBuffer(const_cast<uint8_t*>(data), len, 2);
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RADIOLIB_ASSERT(state);
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} else {
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state = writeBuffer(const_cast<uint8_t*>(data), len);
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RADIOLIB_ASSERT(state);
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}
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// set DIO mapping
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state = setDioIrqParams(RADIOLIB_SX128X_IRQ_TX_DONE | RADIOLIB_SX128X_IRQ_RX_TX_TIMEOUT, RADIOLIB_SX128X_IRQ_TX_DONE);
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RADIOLIB_ASSERT(state);
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// clear interrupt flags
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state = clearIrqStatus();
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RADIOLIB_ASSERT(state);
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// set RF switch (if present)
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this->mod->setRfSwitchState(Module::MODE_TX);
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// start transmission
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state = setTx(RADIOLIB_SX128X_TX_TIMEOUT_NONE);
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RADIOLIB_ASSERT(state);
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// wait for BUSY to go low (= PA ramp up done)
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while(this->mod->hal->digitalRead(this->mod->getGpio())) {
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this->mod->hal->yield();
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}
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return(state);
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}
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int16_t SX128x::finishTransmit() {
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// clear interrupt flags
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clearIrqStatus();
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@ -589,49 +525,6 @@ int16_t SX128x::startReceive() {
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return(this->startReceive(RADIOLIB_SX128X_RX_TIMEOUT_INF, RADIOLIB_IRQ_RX_DEFAULT_FLAGS, RADIOLIB_IRQ_RX_DEFAULT_MASK, 0));
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}
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int16_t SX128x::startReceive(uint16_t timeout, RadioLibIrqFlags_t irqFlags, RadioLibIrqFlags_t irqMask, size_t len) {
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// in implicit header mode, use the provided length if it is nonzero
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// otherwise we trust the user has previously set the payload length manually
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if((this->headerType == RADIOLIB_SX128X_LORA_HEADER_IMPLICIT) && (len != 0)) {
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this->payloadLen = len;
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}
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// check active modem
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if(getPacketType() == RADIOLIB_SX128X_PACKET_TYPE_RANGING) {
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return(RADIOLIB_ERR_WRONG_MODEM);
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}
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// set DIO mapping
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if(timeout != RADIOLIB_SX128X_RX_TIMEOUT_INF) {
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irqMask |= (1UL << RADIOLIB_IRQ_TIMEOUT);
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}
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int16_t state = setDioIrqParams(getIrqMapped(irqFlags), getIrqMapped(irqMask));
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RADIOLIB_ASSERT(state);
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// set buffer pointers
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state = setBufferBaseAddress();
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RADIOLIB_ASSERT(state);
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// clear interrupt flags
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state = clearIrqStatus();
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RADIOLIB_ASSERT(state);
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// set implicit mode and expected len if applicable
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if((this->headerType == RADIOLIB_SX128X_LORA_HEADER_IMPLICIT) && (getPacketType() == RADIOLIB_SX128X_PACKET_TYPE_LORA)) {
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state = setPacketParamsLoRa(this->preambleLengthLoRa, this->headerType, this->payloadLen, this->crcLoRa, this->invertIQEnabled);
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RADIOLIB_ASSERT(state);
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}
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// set RF switch (if present)
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this->mod->setRfSwitchState(Module::MODE_RX);
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// set mode to receive
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state = setRx(timeout);
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return(state);
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}
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int16_t SX128x::readData(uint8_t* data, size_t len) {
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// check active modem
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if(getPacketType() == RADIOLIB_SX128X_PACKET_TYPE_RANGING) {
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@ -1493,6 +1386,128 @@ int16_t SX128x::invertIQ(bool enable) {
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return(setPacketParamsLoRa(this->preambleLengthLoRa, this->headerType, this->payloadLen, this->crcLoRa, this->invertIQEnabled));
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}
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int16_t SX128x::stageMode(RadioModeType_t mode, RadioModeConfig_t* cfg) {
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int16_t state;
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switch(mode) {
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case(RADIOLIB_RADIO_MODE_RX): {
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// in implicit header mode, use the provided length if it is nonzero
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// otherwise we trust the user has previously set the payload length manually
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if((this->headerType == RADIOLIB_SX128X_LORA_HEADER_IMPLICIT) && (cfg->receive.len != 0)) {
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this->payloadLen = cfg->receive.len;
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}
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// check active modem
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if(getPacketType() == RADIOLIB_SX128X_PACKET_TYPE_RANGING) {
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return(RADIOLIB_ERR_WRONG_MODEM);
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}
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// set DIO mapping
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if(cfg->receive.timeout != RADIOLIB_SX128X_RX_TIMEOUT_INF) {
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cfg->receive.irqMask |= (1UL << RADIOLIB_IRQ_TIMEOUT);
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}
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state = setDioIrqParams(getIrqMapped(cfg->receive.irqFlags), getIrqMapped(cfg->receive.irqMask));
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RADIOLIB_ASSERT(state);
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// set buffer pointers
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state = setBufferBaseAddress();
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RADIOLIB_ASSERT(state);
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// clear interrupt flags
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state = clearIrqStatus();
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RADIOLIB_ASSERT(state);
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// set implicit mode and expected len if applicable
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if((this->headerType == RADIOLIB_SX128X_LORA_HEADER_IMPLICIT) && (getPacketType() == RADIOLIB_SX128X_PACKET_TYPE_LORA)) {
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state = setPacketParamsLoRa(this->preambleLengthLoRa, this->headerType, this->payloadLen, this->crcLoRa, this->invertIQEnabled);
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RADIOLIB_ASSERT(state);
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}
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this->rxTimeout = cfg->receive.timeout;
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} break;
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case(RADIOLIB_RADIO_MODE_TX): {
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// check packet length
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if(cfg->transmit.len > RADIOLIB_SX128X_MAX_PACKET_LENGTH) {
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return(RADIOLIB_ERR_PACKET_TOO_LONG);
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}
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// set packet Length
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uint8_t modem = getPacketType();
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if(modem == RADIOLIB_SX128X_PACKET_TYPE_LORA) {
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state = setPacketParamsLoRa(this->preambleLengthLoRa, this->headerType, cfg->transmit.len, this->crcLoRa, this->invertIQEnabled);
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} else if((modem == RADIOLIB_SX128X_PACKET_TYPE_GFSK) || (modem == RADIOLIB_SX128X_PACKET_TYPE_FLRC)) {
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state = setPacketParamsGFSK(this->preambleLengthGFSK, this->syncWordLen, this->syncWordMatch, this->crcGFSK, this->whitening, cfg->transmit.len);
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} else if(modem == RADIOLIB_SX128X_PACKET_TYPE_BLE) {
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state = setPacketParamsBLE(this->connectionState, this->crcBLE, this->bleTestPayload, this->whitening);
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} else {
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return(RADIOLIB_ERR_WRONG_MODEM);
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}
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RADIOLIB_ASSERT(state);
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// update output power
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state = setTxParams(this->power);
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RADIOLIB_ASSERT(state);
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// set buffer pointers
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state = setBufferBaseAddress();
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RADIOLIB_ASSERT(state);
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// write packet to buffer
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if(modem == RADIOLIB_SX128X_PACKET_TYPE_BLE) {
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// first 2 bytes of BLE payload are PDU header
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state = writeBuffer(cfg->transmit.data, cfg->transmit.len, 2);
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RADIOLIB_ASSERT(state);
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} else {
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state = writeBuffer(cfg->transmit.data, cfg->transmit.len);
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RADIOLIB_ASSERT(state);
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}
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// set DIO mapping
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state = setDioIrqParams(RADIOLIB_SX128X_IRQ_TX_DONE | RADIOLIB_SX128X_IRQ_RX_TX_TIMEOUT, RADIOLIB_SX128X_IRQ_TX_DONE);
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RADIOLIB_ASSERT(state);
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// clear interrupt flags
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state = clearIrqStatus();
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RADIOLIB_ASSERT(state);
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} break;
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default:
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return(RADIOLIB_ERR_UNSUPPORTED);
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}
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this->stagedMode = mode;
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return(state);
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}
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int16_t SX128x::launchMode() {
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int16_t state;
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switch(this->stagedMode) {
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case(RADIOLIB_RADIO_MODE_RX): {
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this->mod->setRfSwitchState(Module::MODE_RX);
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state = setRx(this->rxTimeout);
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RADIOLIB_ASSERT(state);
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} break;
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case(RADIOLIB_RADIO_MODE_TX): {
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this->mod->setRfSwitchState(Module::MODE_TX);
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state = setTx(RADIOLIB_SX128X_TX_TIMEOUT_NONE);
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RADIOLIB_ASSERT(state);
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// wait for BUSY to go low (= PA ramp up done)
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while(this->mod->hal->digitalRead(this->mod->getGpio())) {
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this->mod->hal->yield();
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}
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} break;
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default:
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return(RADIOLIB_ERR_UNSUPPORTED);
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}
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this->stagedMode = RADIOLIB_RADIO_MODE_NONE;
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return(state);
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}
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#if !RADIOLIB_EXCLUDE_DIRECT_RECEIVE
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void SX128x::setDirectAction(void (*func)(void)) {
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// SX128x is unable to perform direct mode reception
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@ -354,6 +354,7 @@ class SX128x: public PhysicalLayer {
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using PhysicalLayer::transmit;
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using PhysicalLayer::receive;
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using PhysicalLayer::startTransmit;
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using PhysicalLayer::startReceive;
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using PhysicalLayer::readData;
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/*!
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@ -530,16 +531,6 @@ class SX128x: public PhysicalLayer {
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*/
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void clearPacketSentAction() override;
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/*!
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\brief Interrupt-driven binary transmit method.
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Overloads for string-based transmissions are implemented in PhysicalLayer.
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\param data Binary data to be sent.
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\param len Number of bytes to send.
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\param addr Address to send the data to. Unsupported, compatibility only.
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\returns \ref status_codes
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*/
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int16_t startTransmit(const uint8_t* data, size_t len, uint8_t addr = 0) override;
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/*!
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\brief Clean up after transmission is done.
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\returns \ref status_codes
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@ -554,20 +545,6 @@ class SX128x: public PhysicalLayer {
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*/
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int16_t startReceive() override;
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/*!
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\brief Interrupt-driven receive method. DIO1 will be activated when full packet is received.
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\param timeout Raw timeout value, expressed as multiples of 15.625 us. Defaults to
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RADIOLIB_SX128X_RX_TIMEOUT_INF for infinite timeout (Rx continuous mode),
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set to RADIOLIB_SX128X_RX_TIMEOUT_NONE for no timeout (Rx single mode).
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If timeout other than infinite is set, signal will be generated on DIO1.
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\param irqFlags Sets the IRQ flags, defaults to RX done, RX timeout, CRC error and header error.
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\param irqMask Sets the mask of IRQ flags that will trigger DIO1, defaults to RX done.
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\param len Only for PhysicalLayer compatibility, not used.
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\returns \ref status_codes
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*/
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int16_t startReceive(uint16_t timeout, RadioLibIrqFlags_t irqFlags = RADIOLIB_IRQ_RX_DEFAULT_FLAGS, RadioLibIrqFlags_t irqMask = RADIOLIB_IRQ_RX_DEFAULT_MASK, size_t len = 0);
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/*!
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\brief Reads the current IRQ status.
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\returns IRQ status bits
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@ -863,6 +840,12 @@ class SX128x: public PhysicalLayer {
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\returns \ref status_codes
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*/
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int16_t invertIQ(bool enable) override;
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/*! \copydoc PhysicalLayer::stageMode */
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int16_t stageMode(RadioModeType_t mode, RadioModeConfig_t* cfg) override;
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/*! \copydoc PhysicalLayer::launchMode */
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int16_t launchMode() override;
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#if !RADIOLIB_EXCLUDE_DIRECT_RECEIVE
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/*!
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@ -920,6 +903,7 @@ class SX128x: public PhysicalLayer {
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// common parameters
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uint8_t power = 0;
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uint32_t rxTimeout = 0;
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// cached LoRa parameters
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uint8_t invertIQEnabled = RADIOLIB_SX128X_LORA_IQ_STANDARD;
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