-
1 #if !defined(_RADIOLIB_SI443X_H) 2 #define _RADIOLIB_SI443X_H 4 #include "../../TypeDef.h" 6 #if !defined(RADIOLIB_EXCLUDE_SI443X) 8 #include "../../Module.h" 10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h" 13 #define SI443X_FREQUENCY_STEP_SIZE 156.25 14 #define SI443X_MAX_PACKET_LENGTH 64 17 #define SI443X_REG_DEVICE_TYPE 0x00 18 #define SI443X_REG_DEVICE_VERSION 0x01 19 #define SI443X_REG_DEVICE_STATUS 0x02 20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03 21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04 22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05 23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06 24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07 25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08 26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09 27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A 28 #define SI443X_REG_GPIO0_CONFIG 0x0B 29 #define SI443X_REG_GPIO1_CONFIG 0x0C 30 #define SI443X_REG_GPIO2_CONFIG 0x0D 31 #define SI443X_REG_IO_PORT_CONFIG 0x0E 32 #define SI443X_REG_ADC_CONFIG 0x0F 33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10 34 #define SI443X_REG_ADC_VALUE 0x11 35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12 36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13 37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14 38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15 39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16 40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17 41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18 42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19 43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A 44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B 45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C 46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D 47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E 48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F 49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20 50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21 51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22 52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23 53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24 54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25 55 #define SI443X_REG_RSSI 0x26 56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27 57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28 58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29 59 #define SI443X_REG_AFC_LIMITER 0x2A 60 #define SI443X_REG_AFC_CORRECTION 0x2B 61 #define SI443X_REG_OOK_COUNTER_1 0x2C 62 #define SI443X_REG_OOK_COUNTER_2 0x2D 63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E 64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30 65 #define SI443X_REG_EZMAC_STATUS 0x31 66 #define SI443X_REG_HEADER_CONTROL_1 0x32 67 #define SI443X_REG_HEADER_CONTROL_2 0x33 68 #define SI443X_REG_PREAMBLE_LENGTH 0x34 69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35 70 #define SI443X_REG_SYNC_WORD_3 0x36 71 #define SI443X_REG_SYNC_WORD_2 0x37 72 #define SI443X_REG_SYNC_WORD_1 0x38 73 #define SI443X_REG_SYNC_WORD_0 0x39 74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A 75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B 76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C 77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D 78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E 79 #define SI443X_REG_CHECK_HEADER_3 0x3F 80 #define SI443X_REG_CHECK_HEADER_2 0x40 81 #define SI443X_REG_CHECK_HEADER_1 0x41 82 #define SI443X_REG_CHECK_HEADER_0 0x42 83 #define SI443X_REG_HEADER_ENABLE_3 0x43 84 #define SI443X_REG_HEADER_ENABLE_2 0x44 85 #define SI443X_REG_HEADER_ENABLE_1 0x45 86 #define SI443X_REG_HEADER_ENABLE_0 0x46 87 #define SI443X_REG_RECEIVED_HEADER_3 0x47 88 #define SI443X_REG_RECEIVED_HEADER_2 0x48 89 #define SI443X_REG_RECEIVED_HEADER_1 0x49 90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A 91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B 92 #define SI443X_REG_ADC8_CONTROL 0x4F 93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60 94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62 95 #define SI443X_REG_AGC_OVERRIDE_1 0x69 96 #define SI443X_REG_TX_POWER 0x6D 97 #define SI443X_REG_TX_DATA_RATE_1 0x6E 98 #define SI443X_REG_TX_DATA_RATE_0 0x6F 99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70 100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71 101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72 102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73 103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74 104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75 105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76 106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77 107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79 108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A 109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C 110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D 111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E 112 #define SI443X_REG_FIFO_ACCESS 0x7F 115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register 118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register 121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag 122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag 123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag 124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag 125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range) 126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx 127 #define SI443X_RX 0b00000001 // 1 0 Rx 128 #define SI443X_IDLE 0b00000000 // 1 0 idle 131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow 132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full 133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty 134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full 135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx 136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done 137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received 138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed 141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected 142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected 143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected 144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold 145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired 146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected 147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected 148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected 151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled 152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled 153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled 154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled 155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled 156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled 157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled 158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled 161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled 162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled 163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled 164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled 165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled 166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled 167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled 168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled 171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values 172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection 173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer 174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default) 175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator 176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode 177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode 178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode) 179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode) 180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode) 183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default) 184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low 185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high 186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high 187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low 188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high 189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low 190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high 191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default) 192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled 193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default) 194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled 195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default) 196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled 197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first) 198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second) 199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first) 200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second) 203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration: 204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT 207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default) 208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128 209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256 210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512 211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default) 212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled 213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz 214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz 215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz 216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz 217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz 218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz 219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default) 220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz 223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive) 224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default) 225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled 226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default) 227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default) 228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default) 229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output 230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output 231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output 232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge 233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge 234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change 235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input 236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input 237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input 238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input 239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output 240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output 241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output 242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output 243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode 244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode 245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input 246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output 247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output 248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output 249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output 250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output 251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1 252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2 253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output 254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output 255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output 256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output 257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD 258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND 261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2 262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1 263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0 264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default) 265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled 266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2 267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1 268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0 271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement 272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress 273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done 274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default) 275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0 276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1 277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2 278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-) 279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-) 280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-) 281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND 282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default) 283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3 284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2 285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain 288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset 291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default) 292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution 293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution 294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution 295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled 296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default) 297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default) 298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled 299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value 302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent 305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value: 306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms 309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms 312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V) 315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default) 316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled 317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate 318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection 321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default) 322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled 323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled 324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default) 325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting 326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default) 327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB 328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb 329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default) 330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default) 331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases 334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching 335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction 336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time 339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value 340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value 343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit 346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit 347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold 348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB 351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID 354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB 357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default) 358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled 359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default) 360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled 361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB 364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB 367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold 370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value 373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default) 374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled 375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled 376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default) 377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled 378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default) 379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB 382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB 385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time 386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time 389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled 390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default) 391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default) 392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled 393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default) 394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled 395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default) 396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled 397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled 398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default) 399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled 400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default) 401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT 402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default) 403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16 404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva 407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones 408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet 409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet 410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received 411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed 412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet 413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent 416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default) 417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0 418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1 419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2 420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3 421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none 422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0 423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1 424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default) 425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default) 428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default) 429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled 430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none 431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3 432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2 433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default) 434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0 435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default) 436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled 437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3 438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default) 439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1 440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0 441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB 444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits 447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits 448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB 451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB) 452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte 453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte 454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB) 457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles 460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power 461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready 462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune 463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx 464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx 467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default) 468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled 469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled 470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default) 471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default) 472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB 473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB 476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled 477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default) 478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max 481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or 482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps) 485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default) 486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps 487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default) 488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled 489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low 490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default) 491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled 492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default) 493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default) 494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled 495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default) 496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled 499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default) 500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin 501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin 502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin 503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default) 504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin 505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO 506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal 507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default) 508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled 509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB 510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default) 511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK 512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK 513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK 516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz 519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset: 520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz 523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default) 524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency 525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz 526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default) 527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select 530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency: 531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz] 534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number 537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size 540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold 543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold 546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold 586 int16_t
begin(
float br,
float freqDev,
float rxBw, uint8_t preambleLen);
605 int16_t
transmit(uint8_t* data,
size_t len, uint8_t addr = 0)
override;
617 int16_t
receive(uint8_t* data,
size_t len)
override;
682 int16_t
startTransmit(uint8_t* data,
size_t len, uint8_t addr = 0)
override;
700 int16_t
readData(uint8_t* data,
size_t len)
override;
738 int16_t
setSyncWord(uint8_t* syncWord,
size_t len);
802 #ifndef RADIOLIB_GODMODE 811 size_t _packetLength = 0;
812 bool _packetLengthQueried =
false;
814 int16_t setFrequencyRaw(
float newFreq);
816 #ifndef RADIOLIB_GODMODE 820 void clearIRQFlags();
822 int16_t updateClockRecovery();
823 int16_t directMode();
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:364
+
1 #if !defined(_RADIOLIB_SI443X_H) 2 #define _RADIOLIB_SI443X_H 4 #include "../../TypeDef.h" 6 #if !defined(RADIOLIB_EXCLUDE_SI443X) 8 #include "../../Module.h" 10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h" 13 #define SI443X_FREQUENCY_STEP_SIZE 156.25 14 #define SI443X_MAX_PACKET_LENGTH 64 17 #define SI443X_REG_DEVICE_TYPE 0x00 18 #define SI443X_REG_DEVICE_VERSION 0x01 19 #define SI443X_REG_DEVICE_STATUS 0x02 20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03 21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04 22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05 23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06 24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07 25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08 26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09 27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A 28 #define SI443X_REG_GPIO0_CONFIG 0x0B 29 #define SI443X_REG_GPIO1_CONFIG 0x0C 30 #define SI443X_REG_GPIO2_CONFIG 0x0D 31 #define SI443X_REG_IO_PORT_CONFIG 0x0E 32 #define SI443X_REG_ADC_CONFIG 0x0F 33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10 34 #define SI443X_REG_ADC_VALUE 0x11 35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12 36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13 37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14 38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15 39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16 40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17 41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18 42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19 43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A 44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B 45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C 46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D 47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E 48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F 49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20 50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21 51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22 52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23 53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24 54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25 55 #define SI443X_REG_RSSI 0x26 56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27 57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28 58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29 59 #define SI443X_REG_AFC_LIMITER 0x2A 60 #define SI443X_REG_AFC_CORRECTION 0x2B 61 #define SI443X_REG_OOK_COUNTER_1 0x2C 62 #define SI443X_REG_OOK_COUNTER_2 0x2D 63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E 64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30 65 #define SI443X_REG_EZMAC_STATUS 0x31 66 #define SI443X_REG_HEADER_CONTROL_1 0x32 67 #define SI443X_REG_HEADER_CONTROL_2 0x33 68 #define SI443X_REG_PREAMBLE_LENGTH 0x34 69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35 70 #define SI443X_REG_SYNC_WORD_3 0x36 71 #define SI443X_REG_SYNC_WORD_2 0x37 72 #define SI443X_REG_SYNC_WORD_1 0x38 73 #define SI443X_REG_SYNC_WORD_0 0x39 74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A 75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B 76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C 77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D 78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E 79 #define SI443X_REG_CHECK_HEADER_3 0x3F 80 #define SI443X_REG_CHECK_HEADER_2 0x40 81 #define SI443X_REG_CHECK_HEADER_1 0x41 82 #define SI443X_REG_CHECK_HEADER_0 0x42 83 #define SI443X_REG_HEADER_ENABLE_3 0x43 84 #define SI443X_REG_HEADER_ENABLE_2 0x44 85 #define SI443X_REG_HEADER_ENABLE_1 0x45 86 #define SI443X_REG_HEADER_ENABLE_0 0x46 87 #define SI443X_REG_RECEIVED_HEADER_3 0x47 88 #define SI443X_REG_RECEIVED_HEADER_2 0x48 89 #define SI443X_REG_RECEIVED_HEADER_1 0x49 90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A 91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B 92 #define SI443X_REG_ADC8_CONTROL 0x4F 93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60 94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62 95 #define SI443X_REG_AGC_OVERRIDE_1 0x69 96 #define SI443X_REG_TX_POWER 0x6D 97 #define SI443X_REG_TX_DATA_RATE_1 0x6E 98 #define SI443X_REG_TX_DATA_RATE_0 0x6F 99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70 100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71 101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72 102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73 103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74 104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75 105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76 106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77 107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79 108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A 109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C 110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D 111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E 112 #define SI443X_REG_FIFO_ACCESS 0x7F 115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register 118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register 121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag 122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag 123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag 124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag 125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range) 126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx 127 #define SI443X_RX 0b00000001 // 1 0 Rx 128 #define SI443X_IDLE 0b00000000 // 1 0 idle 131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow 132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full 133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty 134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full 135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx 136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done 137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received 138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed 141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected 142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected 143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected 144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold 145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired 146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected 147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected 148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected 151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled 152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled 153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled 154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled 155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled 156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled 157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled 158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled 161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled 162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled 163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled 164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled 165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled 166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled 167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled 168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled 171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values 172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection 173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer 174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default) 175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator 176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode 177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode 178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode) 179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode) 180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode) 183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default) 184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low 185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high 186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high 187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low 188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high 189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low 190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high 191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default) 192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled 193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default) 194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled 195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default) 196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled 197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first) 198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second) 199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first) 200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second) 203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration: 204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT 207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default) 208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128 209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256 210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512 211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default) 212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled 213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz 214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz 215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz 216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz 217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz 218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz 219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default) 220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz 223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive) 224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default) 225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled 226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default) 227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default) 228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default) 229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output 230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output 231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output 232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge 233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge 234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change 235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input 236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input 237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input 238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input 239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output 240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output 241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output 242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output 243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode 244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode 245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input 246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output 247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output 248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output 249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output 250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output 251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1 252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2 253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output 254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output 255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output 256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output 257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD 258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND 261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2 262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1 263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0 264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default) 265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled 266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2 267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1 268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0 271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement 272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress 273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done 274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default) 275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0 276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1 277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2 278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-) 279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-) 280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-) 281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND 282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default) 283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3 284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2 285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain 288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset 291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default) 292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution 293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution 294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution 295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled 296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default) 297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default) 298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled 299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value 302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent 305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value: 306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms 309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms 312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V) 315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default) 316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled 317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate 318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection 321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default) 322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled 323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled 324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default) 325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting 326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default) 327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB 328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb 329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default) 330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default) 331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases 334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching 335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction 336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time 339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value 340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value 343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit 346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit 347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold 348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB 351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID 354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB 357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default) 358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled 359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default) 360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled 361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB 364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB 367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold 370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value 373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default) 374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled 375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled 376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default) 377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled 378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default) 379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB 382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB 385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time 386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time 389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled 390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default) 391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default) 392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled 393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default) 394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled 395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default) 396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled 397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled 398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default) 399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled 400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default) 401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT 402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default) 403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16 404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva 407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones 408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet 409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet 410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received 411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed 412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet 413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent 416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default) 417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0 418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1 419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2 420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3 421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none 422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0 423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1 424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default) 425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default) 428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default) 429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled 430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none 431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3 432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2 433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default) 434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0 435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default) 436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled 437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3 438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default) 439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1 440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0 441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB 444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits 447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits 448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB 451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB) 452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte 453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte 454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB) 457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles 460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power 461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready 462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune 463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx 464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx 467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default) 468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled 469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled 470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default) 471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default) 472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB 473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB 476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled 477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default) 478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max 481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or 482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps) 485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default) 486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps 487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default) 488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled 489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low 490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default) 491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled 492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default) 493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default) 494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled 495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default) 496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled 499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default) 500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin 501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin 502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin 503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default) 504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin 505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO 506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal 507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default) 508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled 509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB 510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default) 511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK 512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK 513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK 516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz 519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset: 520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz 523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default) 524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency 525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz 526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default) 527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select 530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency: 531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz] 534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number 537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size 540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold 543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold 546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold 586 int16_t
begin(
float br,
float freqDev,
float rxBw, uint8_t preambleLen);
605 int16_t
transmit(uint8_t* data,
size_t len, uint8_t addr = 0)
override;
617 int16_t
receive(uint8_t* data,
size_t len)
override;
682 int16_t
startTransmit(uint8_t* data,
size_t len, uint8_t addr = 0)
override;
700 int16_t
readData(uint8_t* data,
size_t len)
override;
738 int16_t
setSyncWord(uint8_t* syncWord,
size_t len);
802 #ifndef RADIOLIB_GODMODE 811 size_t _packetLength = 0;
812 bool _packetLengthQueried =
false;
814 int16_t setFrequencyRaw(
float newFreq);
816 #ifndef RADIOLIB_GODMODE 820 void clearIRQFlags();
822 int16_t updateClockRecovery();
823 int16_t directMode();
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:367
int16_t startReceive()
Interrupt-driven receive method. IRQ will be activated when full valid packet is received.
Definition: Si443x.cpp:254
-
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: Si443x.cpp:533
+
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: Si443x.cpp:536
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
-
int16_t getChipVersion()
Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and work...
Definition: Si443x.cpp:575
-
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: Si443x.cpp:552
-
int16_t setSyncWord(uint8_t *syncWord, size_t len)
Sets sync word. Up to 4 bytes can be set as sync word.
Definition: Si443x.cpp:471
+
int16_t getChipVersion()
Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and work...
+
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: Si443x.cpp:555
+
int16_t setSyncWord(uint8_t *syncWord, size_t len)
Sets sync word. Up to 4 bytes can be set as sync word.
Definition: Si443x.cpp:474
int16_t receiveDirect() override
Enables direct reception mode. While in direct mode, the module will not be able to transmit or recei...
Definition: Si443x.cpp:189
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets.
Definition: Si443x.cpp:202
-
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: Si443x.cpp:279
+
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: Si443x.cpp:282
Si443x(Module *mod)
Default constructor.
Definition: Si443x.cpp:4
-
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: Si443x.cpp:514
+
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: Si443x.cpp:517
void reset()
Reset method. Will reset the chip to the default state using SDN pin.
Definition: Si443x.cpp:60
-
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: Si443x.cpp:504
+
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: Si443x.cpp:507
int16_t standby() override
Sets the module to standby.
Definition: Si443x.cpp:139
int16_t receive(uint8_t *data, size_t len) override
Binary receive method. Will attempt to receive arbitrary binary data up to 64 bytes long...
Definition: Si443x.cpp:101
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Binary transmit method. Will transmit arbitrary binary data up to 64 bytes long. For overloads to tra...
Definition: Si443x.cpp:68
Base class for Si443x series. All derived classes for Si443x (e.g. Si4431 or Si4432) inherit from thi...
Definition: Si443x.h:554
int16_t begin(float br, float freqDev, float rxBw, uint8_t preambleLen)
Initialization method.
Definition: Si443x.cpp:8
void clearIrqAction()
Clears interrupt service routine to call when IRQ activates.
Definition: Si443x.cpp:210
-
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 0.123 to 256.0 kbps.
Definition: Si443x.cpp:305
+
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 0.123 to 256.0 kbps.
Definition: Si443x.cpp:308
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
void setIrqAction(void(*func)(void))
Sets interrupt service routine to call when IRQ activates.
Definition: Si443x.cpp:206
-
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: Si443x.cpp:488
+
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: Si443x.cpp:491
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
int16_t transmitDirect(uint32_t frf=0) override
Enables direct transmission mode. While in direct mode, the module will not be able to transmit or re...
Definition: Si443x.cpp:147
-
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values range from 0.625 to 320...
Definition: Si443x.cpp:336
+
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values range from 0.625 to 320...
Definition: Si443x.cpp:339
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
int16_t sleep()
Sets the module to sleep to save power. Module will not be able to transmit or receive any data while...
Definition: Si443x.cpp:123
-
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: Si443x.cpp:556
+
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: Si443x.cpp:559
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Will start transmitting arbitrary binary data up to 64 bytes...
Definition: Si443x.cpp:214
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
diff --git a/annotated.html b/annotated.html
index 1051531e..797d0590 100644
--- a/annotated.html
+++ b/annotated.html
@@ -89,53 +89,54 @@ $(document).ready(function(){initNavTree('annotated.html','');});
| CAFSKClient | Client for audio-based transmissions. Requires Arduino tone() function, and a module capable of direct mode transmission using DIO pins |
| CAX25Client | Client for AX25 communication |
| CAX25Frame | Abstraction of AX.25 frame format |
-
| CCC1101 | Control class for CC1101 module |
-
| CESP8266 | Control class for ESP8266 module. Implements TransportLayer methods |
-
| CHC05 | Control class for HC05 module. Most methods supported by this module are implemented in ISerial interface |
-
| CHellClient | Client for Hellschreiber transmissions |
-
| CHTTPClient | Client for simple HTTP communication |
-
| CISerial | Interface class for Arduino Serial. Only calls the appropriate methods for the active UART interface |
-
| CITA2String | ITA2-encoded string |
-
| CJDY08 | Control class for JDY08 module. Most methods supported by this module are implemented in ISerial interface |
-
| CModule | Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class |
-
| CMorseClient | Client for Morse Code communication. The public interface is the same as Arduino Serial |
-
| CMQTTClient | Client for simple MQTT communication |
-
| CnRF24 | Control class for nRF24 module |
-
| CPhysicalLayer | Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN. Also extracts some common module-independent methods. Using this interface class allows to use the protocols on various modules without much code duplicity. Because this class is used mainly as interface, all of its virtual members must be implemented in the module class |
-
| CRF69 | Control class for RF69 module. Also serves as base class for SX1231 |
-
| CRFM22 | Only exists as alias for Si4432, since there seems to be no difference between RFM22 and Si4432 modules |
-
| CRFM23 | Only exists as alias for Si4431, since there seems to be no difference between RFM23 and Si4431 modules |
-
| CRFM95 | Derived class for RFM95 modules. Overrides some methods from SX1278 due to different parameter ranges |
-
| CRFM96 | Derived class for RFM96 modules. Overrides some methods from SX1278 due to different parameter ranges |
-
| CRFM97 | Derived class for RFM97 modules. Overrides some methods from RFM95 due to different parameter ranges |
-
| CRFM98 | Only exists as alias for RFM96, since there seems to be no difference between RFM96 and RFM98 modules |
-
| CRTTYClient | Client for RTTY communication. The public interface is the same as Arduino Serial |
-
| CSi4430 | Derived class for Si4430 modules |
-
| CSi4431 | Derived class for Si4431 modules |
-
| CSi4432 | Derived class for Si4432 modules |
-
| CSi443x | Base class for Si443x series. All derived classes for Si443x (e.g. Si4431 or Si4432) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
-
| CSSTVClient | Client for SSTV transmissions |
-
| CSSTVMode_t | Structure to save data about supported SSTV modes |
-
| CSX1231 | Control class for SX1231 module. Overrides some methods from RF69 due to different register values |
-
| CSX1261 | Derived class for SX1261 modules |
-
| CSX1262 | Derived class for SX1262 modules |
-
| CSX1268 | Derived class for SX1268 modules |
-
| CSX126x | Base class for SX126x series. All derived classes for SX126x (e.g. SX1262 or SX1268) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
-
| CSX1272 | Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic hardware and only differ in parameter ranges |
-
| CSX1273 | Derived class for SX1273 modules. Overrides some methods from SX1272 due to different parameter ranges |
-
| CSX1276 | Derived class for SX1276 modules. Overrides some methods from SX1278 due to different parameter ranges |
-
| CSX1277 | Derived class for SX1277 modules. Overrides some methods from SX1278 due to different parameter ranges |
-
| CSX1278 | Derived class for SX1278 modules. Also used as base class for SX1276, SX1277, SX1279, RFM95 and RFM96. All of these modules use the same basic hardware and only differ in parameter ranges (and names) |
-
| CSX1279 | Derived class for SX1279 modules. Overrides some methods from SX1278 due to different parameter ranges |
-
| CSX127x | Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
-
| CSX1280 | Derived class for SX1280 modules |
-
| CSX1281 | Derived class for SX1281 modules |
-
| CSX1282 | Derived class for SX1282 modules |
-
| CSX128x | Base class for SX128x series. All derived classes for SX128x (e.g. SX1280 or SX1281) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
-
| Ctone_t | Structure to save data about tone |
-
| CTransportLayer | Provides common interface for protocols that run on modules with Internet connectivity, such as HTTP or MQTT. Because this class is used mainly as interface, all of its virtual members must be implemented in the module class |
-
| CXBee | Control class for XBee modules |
-
| CXBeeSerial | XBee Serial interface. This class is used for XBees in transparent mode, i.e. when two XBees act as a "wireless UART" |
+
| CAX5243 | Control class for AX5243 module |
+
| CCC1101 | Control class for CC1101 module |
+
| CESP8266 | Control class for ESP8266 module. Implements TransportLayer methods |
+
| CHC05 | Control class for HC05 module. Most methods supported by this module are implemented in ISerial interface |
+
| CHellClient | Client for Hellschreiber transmissions |
+
| CHTTPClient | Client for simple HTTP communication |
+
| CISerial | Interface class for Arduino Serial. Only calls the appropriate methods for the active UART interface |
+
| CITA2String | ITA2-encoded string |
+
| CJDY08 | Control class for JDY08 module. Most methods supported by this module are implemented in ISerial interface |
+
| CModule | Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class |
+
| CMorseClient | Client for Morse Code communication. The public interface is the same as Arduino Serial |
+
| CMQTTClient | Client for simple MQTT communication |
+
| CnRF24 | Control class for nRF24 module |
+
| CPhysicalLayer | Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN. Also extracts some common module-independent methods. Using this interface class allows to use the protocols on various modules without much code duplicity. Because this class is used mainly as interface, all of its virtual members must be implemented in the module class |
+
| CRF69 | Control class for RF69 module. Also serves as base class for SX1231 |
+
| CRFM22 | Only exists as alias for Si4432, since there seems to be no difference between RFM22 and Si4432 modules |
+
| CRFM23 | Only exists as alias for Si4431, since there seems to be no difference between RFM23 and Si4431 modules |
+
| CRFM95 | Derived class for RFM95 modules. Overrides some methods from SX1278 due to different parameter ranges |
+
| CRFM96 | Derived class for RFM96 modules. Overrides some methods from SX1278 due to different parameter ranges |
+
| CRFM97 | Derived class for RFM97 modules. Overrides some methods from RFM95 due to different parameter ranges |
+
| CRFM98 | Only exists as alias for RFM96, since there seems to be no difference between RFM96 and RFM98 modules |
+
| CRTTYClient | Client for RTTY communication. The public interface is the same as Arduino Serial |
+
| CSi4430 | Derived class for Si4430 modules |
+
| CSi4431 | Derived class for Si4431 modules |
+
| CSi4432 | Derived class for Si4432 modules |
+
| CSi443x | Base class for Si443x series. All derived classes for Si443x (e.g. Si4431 or Si4432) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
+
| CSSTVClient | Client for SSTV transmissions |
+
| CSSTVMode_t | Structure to save data about supported SSTV modes |
+
| CSX1231 | Control class for SX1231 module. Overrides some methods from RF69 due to different register values |
+
| CSX1261 | Derived class for SX1261 modules |
+
| CSX1262 | Derived class for SX1262 modules |
+
| CSX1268 | Derived class for SX1268 modules |
+
| CSX126x | Base class for SX126x series. All derived classes for SX126x (e.g. SX1262 or SX1268) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
+
| CSX1272 | Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic hardware and only differ in parameter ranges |
+
| CSX1273 | Derived class for SX1273 modules. Overrides some methods from SX1272 due to different parameter ranges |
+
| CSX1276 | Derived class for SX1276 modules. Overrides some methods from SX1278 due to different parameter ranges |
+
| CSX1277 | Derived class for SX1277 modules. Overrides some methods from SX1278 due to different parameter ranges |
+
| CSX1278 | Derived class for SX1278 modules. Also used as base class for SX1276, SX1277, SX1279, RFM95 and RFM96. All of these modules use the same basic hardware and only differ in parameter ranges (and names) |
+
| CSX1279 | Derived class for SX1279 modules. Overrides some methods from SX1278 due to different parameter ranges |
+
| CSX127x | Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
+
| CSX1280 | Derived class for SX1280 modules |
+
| CSX1281 | Derived class for SX1281 modules |
+
| CSX1282 | Derived class for SX1282 modules |
+
| CSX128x | Base class for SX128x series. All derived classes for SX128x (e.g. SX1280 or SX1281) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes |
+
| Ctone_t | Structure to save data about tone |
+
| CTransportLayer | Provides common interface for protocols that run on modules with Internet connectivity, such as HTTP or MQTT. Because this class is used mainly as interface, all of its virtual members must be implemented in the module class |
+
| CXBee | Control class for XBee modules |
+
| CXBeeSerial | XBee Serial interface. This class is used for XBees in transparent mode, i.e. when two XBees act as a "wireless UART" |
1.8.13
+ 
+
+ 
Public Member Functions inherited from PhysicalLayer