From e421ab4272d21af6d7b5e5d57f2dded84923b6e0 Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 6 Jul 2022 15:28:50 +0200 Subject: [PATCH 1/6] Introduce setDIOMapping on the PhysicalLayer class which, by default, returns "not implemented" --- src/TypeDef.h | 10 ++++++++++ src/protocols/PhysicalLayer/PhysicalLayer.cpp | 4 ++++ src/protocols/PhysicalLayer/PhysicalLayer.h | 11 +++++++++++ 3 files changed, 25 insertions(+) diff --git a/src/TypeDef.h b/src/TypeDef.h index a9687c13..71b738c2 100644 --- a/src/TypeDef.h +++ b/src/TypeDef.h @@ -203,6 +203,16 @@ */ #define RADIOLIB_ERR_LORA_HEADER_DAMAGED (-24) +/*! + \brief The requested functionality is not supported for this device +*/ +#define RADIOLIB_ERR_UNSUPPORTED (-25) + +/*! + \brief The specified DIO pin does not exist on this device +*/ +#define RADIOLIB_ERR_INVALID_DIO_PIN (-26) + // RF69-specific status codes /*! diff --git a/src/protocols/PhysicalLayer/PhysicalLayer.cpp b/src/protocols/PhysicalLayer/PhysicalLayer.cpp index 8b514a9c..98c8778c 100644 --- a/src/protocols/PhysicalLayer/PhysicalLayer.cpp +++ b/src/protocols/PhysicalLayer/PhysicalLayer.cpp @@ -246,3 +246,7 @@ void PhysicalLayer::updateDirectBuffer(uint8_t bit) { } } } + +int16_t PhysicalLayer::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { + return(RADIOLIB_ERR_UNSUPPORTED); +} diff --git a/src/protocols/PhysicalLayer/PhysicalLayer.h b/src/protocols/PhysicalLayer/PhysicalLayer.h index c1d236d8..e67dd1e8 100644 --- a/src/protocols/PhysicalLayer/PhysicalLayer.h +++ b/src/protocols/PhysicalLayer/PhysicalLayer.h @@ -300,6 +300,17 @@ class PhysicalLayer { */ uint8_t read(); + /*! + \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). + + \param pin Pin number onto which a signal is to be placed. + + \param value The value that indicates which function to place on that pin. See chip datasheet for details. + + \returns \ref status_codes + */ + virtual int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); + protected: void updateDirectBuffer(uint8_t bit); From e1412108c108f5c7650ae89b55a61c7223071368 Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 6 Jul 2022 15:29:07 +0200 Subject: [PATCH 2/6] Implement setDIOMapping for CC1101 --- src/modules/CC1101/CC1101.cpp | 7 +++++++ src/modules/CC1101/CC1101.h | 11 +++++++++++ 2 files changed, 18 insertions(+) diff --git a/src/modules/CC1101/CC1101.cpp b/src/modules/CC1101/CC1101.cpp index d55d222d..e0407eba 100644 --- a/src/modules/CC1101/CC1101.cpp +++ b/src/modules/CC1101/CC1101.cpp @@ -885,6 +885,13 @@ void CC1101::readBit(RADIOLIB_PIN_TYPE pin) { updateDirectBuffer((uint8_t)digitalRead(pin)); } +int16_t CC1101::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { + if (pin > 2) + return RADIOLIB_ERR_INVALID_DIO_PIN; + + return(SPIsetRegValue(RADIOLIB_CC1101_REG_IOCFG0 - pin, value)); +} + int16_t CC1101::config() { // Reset the radio. Registers may be dirty from previous usage. SPIsendCommand(RADIOLIB_CC1101_CMD_RESET); diff --git a/src/modules/CC1101/CC1101.h b/src/modules/CC1101/CC1101.h index ae440b4c..e88d48e3 100644 --- a/src/modules/CC1101/CC1101.h +++ b/src/modules/CC1101/CC1101.h @@ -932,6 +932,17 @@ class CC1101: public PhysicalLayer { */ void readBit(RADIOLIB_PIN_TYPE pin); + /*! + \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). + + \param pin Pin number onto which a signal is to be placed. + + \param value The value that indicates which function to place on that pin. See chip datasheet for details. + + \returns \ref status_codes + */ + int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); + #if !defined(RADIOLIB_GODMODE) && !defined(RADIOLIB_LOW_LEVEL) protected: #endif From 069428a9f6ac94647b3e334fd3522ccbe56f45eb Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 6 Jul 2022 15:29:27 +0200 Subject: [PATCH 3/6] Implement setDIOMapping for SX1278 family --- src/modules/SX127x/SX1278.cpp | 14 ++++++ src/modules/SX127x/SX1278.h | 81 +++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/src/modules/SX127x/SX1278.cpp b/src/modules/SX127x/SX1278.cpp index 685fe175..94518c8e 100644 --- a/src/modules/SX127x/SX1278.cpp +++ b/src/modules/SX127x/SX1278.cpp @@ -471,6 +471,20 @@ int16_t SX1278::explicitHeader() { return(setHeaderType(RADIOLIB_SX1278_HEADER_EXPL_MODE)); } +int16_t SX1278::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { + if (pin > 5) + return RADIOLIB_ERR_INVALID_DIO_PIN; + + if (pin < 4) + return(_mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_1, value, 7 - 2 * pin, 6 - 2 * pin)); + else + return(_mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_2, value, 15 - 2 * pin, 14 - 2 * pin)); +} + +int16_t SX1278::setDIOPreambleDetect(bool usePreambleDetect) { + return _mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_2, (usePreambleDetect) ? RADIOLIB_SX1278_DIO_MAP_PREAMBLE_DETECT : RADIOLIB_SX1278_DIO_MAP_RSSI, 0, 0); +} + int16_t SX1278::setBandwidthRaw(uint8_t newBandwidth) { // set mode to standby int16_t state = SX127x::standby(); diff --git a/src/modules/SX127x/SX1278.h b/src/modules/SX127x/SX1278.h index cffedc81..8ebbfe0a 100644 --- a/src/modules/SX127x/SX1278.h +++ b/src/modules/SX127x/SX1278.h @@ -10,6 +10,8 @@ // SX1278 specific register map #define RADIOLIB_SX1278_REG_MODEM_CONFIG_3 0x26 +#define RADIOLIB_SX1278_REG_DIO_MAPPING_1 0x40 +#define RADIOLIB_SX1278_REG_DIO_MAPPING_2 0x41 #define RADIOLIB_SX1278_REG_PLL_HOP 0x44 #define RADIOLIB_SX1278_REG_TCXO 0x4B #define RADIOLIB_SX1278_REG_PA_DAC 0x4D @@ -95,6 +97,65 @@ #define RADIOLIB_SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold #define RADIOLIB_SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold +// SX1278_REG_DIO_MAPPING_1 +#define RADIOLIB_SX1278_DIO0_LORA_RX_DONE 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_LORA_TX_DONE 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_LORA_CAD_DONE 0b10000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_CONT_MODE_READY 0b11000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_CONT_RSSI_PREAMBLE_DETECT 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_CONT_RX_READY 0b10000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_CONT_TX_READY 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_PACK_CRC_OK 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6 +#define RADIOLIB_SX1278_DIO1_LORA_RX_TIMEOUT 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO1_LORA_FHSS_CHANGE_CHANNEL 0b01000000 // 5 4 +#define RADIOLIB_SX1278_DIO1_LORA_CAD_DETECTED 0b10000000 // 5 4 +#define RADIOLIB_SX1278_DIO1_CONT_DCLK 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO1_CONT_RSSI_PREAMBLE_DETECT 0b00010000 // 5 4 +#define RADIOLIB_SX1278_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4 +#define RADIOLIB_SX1278_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4 +#define RADIOLIB_SX1278_DIO2_LORA_FHSS_CHANGE_CHANNEL 0b00000000 // 3 2 +#define RADIOLIB_SX1278_DIO2_CONT_DATA 0b00000000 // 3 2 +#define RADIOLIB_SX1278_DIO2_PACK_FIFO_FULL 0b00000000 // 3 2 +#define RADIOLIB_SX1278_DIO2_PACK_RX_READY 0b00000100 // 3 2 +#define RADIOLIB_SX1278_DIO2_PACK_TIMEOUT 0b00001000 // 3 2 +#define RADIOLIB_SX1278_DIO2_PACK_SYNC_ADDRESS 0b00011000 // 3 2 +#define RADIOLIB_SX1278_DIO3_LORA_CAD_DONE 0b00000000 // 0 1 +#define RADIOLIB_SX1278_DIO3_LORA_VALID_HEADER 0b00000001 // 0 1 +#define RADIOLIB_SX1278_DIO3_LORA_PAYLOAD_CRC_ERROR 0b00000010 // 0 1 +#define RADIOLIB_SX1278_DIO3_CONT_TIMEOUT 0b00000000 // 0 1 +#define RADIOLIB_SX1278_DIO3_CONT_RSSI_PREAMBLE_DETECT 0b00000001 // 0 1 +#define RADIOLIB_SX1278_DIO3_CONT_TEMP_CHANGE_LOW_BAT 0b00000011 // 0 1 +#define RADIOLIB_SX1278_DIO3_PACK_FIFO_EMPTY 0b00000000 // 0 1 +#define RADIOLIB_SX1278_DIO3_PACK_TX_READY 0b00000001 // 0 1 + +// SX1278_REG_DIO_MAPPING_2 +#define RADIOLIB_SX1278_DIO4_LORA_CAD_DETECTED 0b10000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_LORA_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_CONT_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_CONT_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_CONT_TIMEOUT 0b10000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_CONT_MODE_READY 0b11000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_PACK_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_PACK_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_PACK_TIMEOUT 0b10000000 // 7 6 +#define RADIOLIB_SX1278_DIO4_PACK_RSSI_PREAMBLE_DETECT 0b11000000 // 7 6 +#define RADIOLIB_SX1278_DIO5_LORA_MODE_READY 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO5_LORA_CLK_OUT 0b00010000 // 5 4 +#define RADIOLIB_SX1278_DIO5_CONT_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO5_CONT_PLL_LOCK 0b00010000 // 5 4 +#define RADIOLIB_SX1278_DIO5_CONT_RSSI_PREAMBLE_DETECT 0b00100000 // 5 4 +#define RADIOLIB_SX1278_DIO5_CONT_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX1278_DIO5_PACK_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX1278_DIO5_PACK_PLL_LOCK 0b00010000 // 5 4 +#define RADIOLIB_SX1278_DIO5_PACK_DATA 0b00100000 // 5 4 +#define RADIOLIB_SX1278_DIO5_PACK_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX1278_DIO_MAP_PREAMBLE_DETECT 0b00000001 // 0 0 +#define RADIOLIB_SX1278_DIO_MAP_RSSI 0b00000000 // 0 0 /*! \class SX1278 @@ -302,6 +363,26 @@ class SX1278: public SX127x { */ int16_t explicitHeader(); + /*! + \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). + + \param pin Pin number onto which a signal is to be placed. + + \param value The value that indicates which function to place on that pin. See chip datasheet for details. + + \returns \ref status_codes + */ + int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); + + /*! + \brief Configure DIO mapping to use RSSI or Preamble Detect for pins that support it. + + \param usePreambleDetect Whether to use PreambleDetect (true) or RSSI (false) on the pins that are mapped to this function. + + \returns \ref status_codes + */ + int16_t setDIOPreambleDetect(bool usePreambleDetect); + #if !defined(RADIOLIB_GODMODE) protected: #endif From bdb14b9e9d999855b1870a339129cd85f4ad4e68 Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 6 Jul 2022 15:29:40 +0200 Subject: [PATCH 4/6] Implement setDIOMapping for RF69 family --- src/modules/RF69/RF69.cpp | 10 ++++++++++ src/modules/RF69/RF69.h | 41 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/modules/RF69/RF69.cpp b/src/modules/RF69/RF69.cpp index 5a388152..f21cb0b5 100644 --- a/src/modules/RF69/RF69.cpp +++ b/src/modules/RF69/RF69.cpp @@ -806,6 +806,16 @@ void RF69::readBit(RADIOLIB_PIN_TYPE pin) { updateDirectBuffer((uint8_t)digitalRead(pin)); } +int16_t RF69::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { + if (pin > 5) + return RADIOLIB_ERR_INVALID_DIO_PIN; + + if (pin < 4) + return(_mod->SPIsetRegValue(RADIOLIB_RF69_REG_DIO_MAPPING_1, value, 7 - 2 * pin, 6 - 2 * pin)); + else + return(_mod->SPIsetRegValue(RADIOLIB_RF69_REG_DIO_MAPPING_2, value, 15 - 2 * pin, 14 - 2 * pin)); +} + int16_t RF69::getChipVersion() { return(_mod->SPIgetRegValue(RADIOLIB_RF69_REG_VERSION)); } diff --git a/src/modules/RF69/RF69.h b/src/modules/RF69/RF69.h index 7e13deb6..e3ade50e 100644 --- a/src/modules/RF69/RF69.h +++ b/src/modules/RF69/RF69.h @@ -295,8 +295,38 @@ #define RADIOLIB_RF69_DIO1_PACK_PLL_LOCK 0b00110000 // 5 4 #define RADIOLIB_RF69_DIO1_PACK_TIMEOUT 0b00110000 // 5 4 #define RADIOLIB_RF69_DIO2_CONT_DATA 0b00000000 // 3 2 +#define RADIOLIB_RF69_DIO2_PACK_FIFO_NOT_EMPTY 0b00000000 // 3 2 +#define RADIOLIB_RF69_DIO2_PACK_AUTO_MODE 0b00001100 // 3 2 +#define RADIOLIB_RF69_DIO2_PACK_DATA 0b00000100 // 3 2 +#define RADIOLIB_RF69_DIO3_CONT_AUTO_MODE 0b00000010 // 0 1 +#define RADIOLIB_RF69_DIO3_CONT_RSSI 0b00000000 // 0 1 +#define RADIOLIB_RF69_DIO3_CONT_RX_READY 0b00000001 // 0 1 +#define RADIOLIB_RF69_DIO3_CONT_TIMEOUT 0b00000011 // 0 1 +#define RADIOLIB_RF69_DIO3_CONT_TX_READY 0b00000001 // 0 1 +#define RADIOLIB_RF69_DIO3_PACK_FIFO_FULL 0b00000000 // 0 1 +#define RADIOLIB_RF69_DIO3_PACK_PLL_LOCK 0b00000011 // 0 1 +#define RADIOLIB_RF69_DIO3_PACK_RSSI 0b00000001 // 0 1 +#define RADIOLIB_RF69_DIO3_PACK_SYNC_ADDRESSS 0b00000010 // 0 1 +#define RADIOLIB_RF69_DIO3_PACK_TX_READY 0b00000001 // 0 1 // RF69_REG_DIO_MAPPING_2 +#define RADIOLIB_RF69_DIO4_CONT_PLL_LOCK 0b11000000 // 7 6 +#define RADIOLIB_RF69_DIO4_CONT_TIMEOUT 0b00000000 // 7 6 +#define RADIOLIB_RF69_DIO4_CONT_RX_READY 0b01000000 // 7 6 +#define RADIOLIB_RF69_DIO4_CONT_SYNC_ADDRESS 0b10000000 // 7 6 +#define RADIOLIB_RF69_DIO4_CONT_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_PLL_LOCK 0b11000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_TIMEOUT 0b00000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_RSSI 0b01000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_RX_READY 0b10000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_MODE_READY 0b00000000 // 7 6 +#define RADIOLIB_RF69_DIO4_PACK_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_RF69_DIO5_CONT_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_RF69_DIO5_CONT_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_RF69_DIO5_CONT_RSSI 0b00010000 // 5 4 +#define RADIOLIB_RF69_DIO5_PACK_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_RF69_DIO5_PACK_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_RF69_DIO5_PACK_DATA 0b00010000 // 5 4 #define RADIOLIB_RF69_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC) #define RADIOLIB_RF69_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2 #define RADIOLIB_RF69_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4 @@ -919,6 +949,17 @@ class RF69: public PhysicalLayer { */ void readBit(RADIOLIB_PIN_TYPE pin); + /*! + \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). + + \param pin Pin number onto which a signal is to be placed. + + \param value The value that indicates which function to place on that pin. See chip datasheet for details. + + \returns \ref status_codes + */ + int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); + #if !defined(RADIOLIB_GODMODE) && !defined(RADIOLIB_LOW_LEVEL) protected: #endif From f9ab9d80d503169ffb1e50d5cecd4ecc69421303 Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 6 Jul 2022 15:30:08 +0200 Subject: [PATCH 5/6] SX1231 has slightly different DIO mapping tables from the RF69 ones --- src/modules/SX1231/SX1231.h | 68 +++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/src/modules/SX1231/SX1231.h b/src/modules/SX1231/SX1231.h index e989fa20..21a14c68 100644 --- a/src/modules/SX1231/SX1231.h +++ b/src/modules/SX1231/SX1231.h @@ -18,6 +18,74 @@ //SX1231_REG_TEST_OOK #define RADIOLIB_SX1231_OOK_DELTA_THRESHOLD 0x0C +// SX1231_REG_DIO_MAPPING_1 +#define RADIOLIB_SX1231_DIO0_CONT_LOW_BAT 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_MODE_READY 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_PLL_LOCK 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_TIMEOUT 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_RSSI 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_MODE_READY 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_CONT_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_LOW_BAT 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_PLL_LOCK 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_CRC_OK 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_PAYLOAD_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_SYNC_ADDRESS 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_RSSI 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO0_PACK_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO1_CONT_LOW_BAT 0b00100000 // 5 4 +#define RADIOLIB_SX1231_DIO1_CONT_PLL_LOCK 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO1_CONT_DCLK 0b00000000 // 5 4 +#define RADIOLIB_SX1231_DIO1_CONT_RX_READY 0b00010000 // 5 4 +#define RADIOLIB_SX1231_DIO1_CONT_SYNC_ADDRESS 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO1_CONT_TX_READY 0b00010000 // 5 4 +#define RADIOLIB_SX1231_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4 +#define RADIOLIB_SX1231_DIO1_PACK_FIFO_FULL 0b00010000 // 5 4 +#define RADIOLIB_SX1231_DIO1_PACK_FIFO_NOT_EMPTY 0b00100000 // 5 4 +#define RADIOLIB_SX1231_DIO1_PACK_PLL_LOCK 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO1_PACK_TIMEOUT 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO2_CONT_DATA 0b00000000 // 3 2 +#define RADIOLIB_SX1231_DIO2_PACK_FIFO_NOT_EMPTY 0b00000000 // 3 2 +#define RADIOLIB_SX1231_DIO2_PACK_LOW_BAT 0b00001000 // 3 2 +#define RADIOLIB_SX1231_DIO2_PACK_AUTO_MODE 0b00001100 // 3 2 +#define RADIOLIB_SX1231_DIO2_PACK_DATA 0b00000100 // 3 2 +#define RADIOLIB_SX1231_DIO3_CONT_AUTO_MODE 0b00000010 // 0 1 +#define RADIOLIB_SX1231_DIO3_CONT_RSSI 0b00000000 // 0 1 +#define RADIOLIB_SX1231_DIO3_CONT_RX_READY 0b00000001 // 0 1 +#define RADIOLIB_SX1231_DIO3_CONT_TIMEOUT 0b00000011 // 0 1 +#define RADIOLIB_SX1231_DIO3_CONT_TX_READY 0b00000001 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_FIFO_FULL 0b00000000 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_LOW_BAT 0b00000010 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_PLL_LOCK 0b00000011 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_RSSI 0b00000001 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_SYNC_ADDRESSS 0b00000010 // 0 1 +#define RADIOLIB_SX1231_DIO3_PACK_TX_READY 0b00000001 // 0 1 + +// SX1231_REG_DIO_MAPPING_2 +#define RADIOLIB_SX1231_DIO4_CONT_LOW_BAT 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_CONT_PLL_LOCK 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_CONT_TIMEOUT 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_CONT_RX_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_CONT_SYNC_ADDRESS 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_CONT_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_LOW_BAT 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_PLL_LOCK 0b11000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_TIMEOUT 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_RSSI 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_RX_READY 0b10000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_MODE_READY 0b00000000 // 7 6 +#define RADIOLIB_SX1231_DIO4_PACK_TX_READY 0b01000000 // 7 6 +#define RADIOLIB_SX1231_DIO5_CONT_LOW_BAT 0b00100000 // 5 4 +#define RADIOLIB_SX1231_DIO5_CONT_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO5_CONT_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX1231_DIO5_CONT_RSSI 0b00010000 // 5 4 +#define RADIOLIB_SX1231_DIO5_PACK_LOW_BAT 0b00100000 // 5 4 +#define RADIOLIB_SX1231_DIO5_PACK_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX1231_DIO5_PACK_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX1231_DIO5_PACK_DATA 0b00010000 // 5 4 + /*! \class SX1231 From 0b2238a0a45eea03e97072bb2fae0016eadcbe94 Mon Sep 17 00:00:00 2001 From: obones Date: Wed, 13 Jul 2022 10:05:45 +0200 Subject: [PATCH 6/6] The SX127x family of chips shares the same DIO pin functions, so move all the support code in the base SX127x class --- src/modules/SX127x/SX1278.cpp | 14 ------ src/modules/SX127x/SX1278.h | 81 ----------------------------------- src/modules/SX127x/SX127x.cpp | 24 ++++++++--- src/modules/SX127x/SX127x.h | 78 ++++++++++++++++++++++++++++----- 4 files changed, 86 insertions(+), 111 deletions(-) diff --git a/src/modules/SX127x/SX1278.cpp b/src/modules/SX127x/SX1278.cpp index 94518c8e..685fe175 100644 --- a/src/modules/SX127x/SX1278.cpp +++ b/src/modules/SX127x/SX1278.cpp @@ -471,20 +471,6 @@ int16_t SX1278::explicitHeader() { return(setHeaderType(RADIOLIB_SX1278_HEADER_EXPL_MODE)); } -int16_t SX1278::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { - if (pin > 5) - return RADIOLIB_ERR_INVALID_DIO_PIN; - - if (pin < 4) - return(_mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_1, value, 7 - 2 * pin, 6 - 2 * pin)); - else - return(_mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_2, value, 15 - 2 * pin, 14 - 2 * pin)); -} - -int16_t SX1278::setDIOPreambleDetect(bool usePreambleDetect) { - return _mod->SPIsetRegValue(RADIOLIB_SX1278_REG_DIO_MAPPING_2, (usePreambleDetect) ? RADIOLIB_SX1278_DIO_MAP_PREAMBLE_DETECT : RADIOLIB_SX1278_DIO_MAP_RSSI, 0, 0); -} - int16_t SX1278::setBandwidthRaw(uint8_t newBandwidth) { // set mode to standby int16_t state = SX127x::standby(); diff --git a/src/modules/SX127x/SX1278.h b/src/modules/SX127x/SX1278.h index 8ebbfe0a..cffedc81 100644 --- a/src/modules/SX127x/SX1278.h +++ b/src/modules/SX127x/SX1278.h @@ -10,8 +10,6 @@ // SX1278 specific register map #define RADIOLIB_SX1278_REG_MODEM_CONFIG_3 0x26 -#define RADIOLIB_SX1278_REG_DIO_MAPPING_1 0x40 -#define RADIOLIB_SX1278_REG_DIO_MAPPING_2 0x41 #define RADIOLIB_SX1278_REG_PLL_HOP 0x44 #define RADIOLIB_SX1278_REG_TCXO 0x4B #define RADIOLIB_SX1278_REG_PA_DAC 0x4D @@ -97,65 +95,6 @@ #define RADIOLIB_SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold #define RADIOLIB_SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold -// SX1278_REG_DIO_MAPPING_1 -#define RADIOLIB_SX1278_DIO0_LORA_RX_DONE 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_LORA_TX_DONE 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_LORA_CAD_DONE 0b10000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_CONT_MODE_READY 0b11000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_CONT_RSSI_PREAMBLE_DETECT 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_CONT_RX_READY 0b10000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_CONT_TX_READY 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_PACK_CRC_OK 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6 -#define RADIOLIB_SX1278_DIO1_LORA_RX_TIMEOUT 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO1_LORA_FHSS_CHANGE_CHANNEL 0b01000000 // 5 4 -#define RADIOLIB_SX1278_DIO1_LORA_CAD_DETECTED 0b10000000 // 5 4 -#define RADIOLIB_SX1278_DIO1_CONT_DCLK 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO1_CONT_RSSI_PREAMBLE_DETECT 0b00010000 // 5 4 -#define RADIOLIB_SX1278_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4 -#define RADIOLIB_SX1278_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4 -#define RADIOLIB_SX1278_DIO2_LORA_FHSS_CHANGE_CHANNEL 0b00000000 // 3 2 -#define RADIOLIB_SX1278_DIO2_CONT_DATA 0b00000000 // 3 2 -#define RADIOLIB_SX1278_DIO2_PACK_FIFO_FULL 0b00000000 // 3 2 -#define RADIOLIB_SX1278_DIO2_PACK_RX_READY 0b00000100 // 3 2 -#define RADIOLIB_SX1278_DIO2_PACK_TIMEOUT 0b00001000 // 3 2 -#define RADIOLIB_SX1278_DIO2_PACK_SYNC_ADDRESS 0b00011000 // 3 2 -#define RADIOLIB_SX1278_DIO3_LORA_CAD_DONE 0b00000000 // 0 1 -#define RADIOLIB_SX1278_DIO3_LORA_VALID_HEADER 0b00000001 // 0 1 -#define RADIOLIB_SX1278_DIO3_LORA_PAYLOAD_CRC_ERROR 0b00000010 // 0 1 -#define RADIOLIB_SX1278_DIO3_CONT_TIMEOUT 0b00000000 // 0 1 -#define RADIOLIB_SX1278_DIO3_CONT_RSSI_PREAMBLE_DETECT 0b00000001 // 0 1 -#define RADIOLIB_SX1278_DIO3_CONT_TEMP_CHANGE_LOW_BAT 0b00000011 // 0 1 -#define RADIOLIB_SX1278_DIO3_PACK_FIFO_EMPTY 0b00000000 // 0 1 -#define RADIOLIB_SX1278_DIO3_PACK_TX_READY 0b00000001 // 0 1 - -// SX1278_REG_DIO_MAPPING_2 -#define RADIOLIB_SX1278_DIO4_LORA_CAD_DETECTED 0b10000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_LORA_PLL_LOCK 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_CONT_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_CONT_PLL_LOCK 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_CONT_TIMEOUT 0b10000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_CONT_MODE_READY 0b11000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_PACK_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_PACK_PLL_LOCK 0b01000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_PACK_TIMEOUT 0b10000000 // 7 6 -#define RADIOLIB_SX1278_DIO4_PACK_RSSI_PREAMBLE_DETECT 0b11000000 // 7 6 -#define RADIOLIB_SX1278_DIO5_LORA_MODE_READY 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO5_LORA_CLK_OUT 0b00010000 // 5 4 -#define RADIOLIB_SX1278_DIO5_CONT_CLK_OUT 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO5_CONT_PLL_LOCK 0b00010000 // 5 4 -#define RADIOLIB_SX1278_DIO5_CONT_RSSI_PREAMBLE_DETECT 0b00100000 // 5 4 -#define RADIOLIB_SX1278_DIO5_CONT_MODE_READY 0b00110000 // 5 4 -#define RADIOLIB_SX1278_DIO5_PACK_CLK_OUT 0b00000000 // 5 4 -#define RADIOLIB_SX1278_DIO5_PACK_PLL_LOCK 0b00010000 // 5 4 -#define RADIOLIB_SX1278_DIO5_PACK_DATA 0b00100000 // 5 4 -#define RADIOLIB_SX1278_DIO5_PACK_MODE_READY 0b00110000 // 5 4 -#define RADIOLIB_SX1278_DIO_MAP_PREAMBLE_DETECT 0b00000001 // 0 0 -#define RADIOLIB_SX1278_DIO_MAP_RSSI 0b00000000 // 0 0 /*! \class SX1278 @@ -363,26 +302,6 @@ class SX1278: public SX127x { */ int16_t explicitHeader(); - /*! - \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). - - \param pin Pin number onto which a signal is to be placed. - - \param value The value that indicates which function to place on that pin. See chip datasheet for details. - - \returns \ref status_codes - */ - int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); - - /*! - \brief Configure DIO mapping to use RSSI or Preamble Detect for pins that support it. - - \param usePreambleDetect Whether to use PreambleDetect (true) or RSSI (false) on the pins that are mapped to this function. - - \returns \ref status_codes - */ - int16_t setDIOPreambleDetect(bool usePreambleDetect); - #if !defined(RADIOLIB_GODMODE) protected: #endif diff --git a/src/modules/SX127x/SX127x.cpp b/src/modules/SX127x/SX127x.cpp index 5c038033..427a6e06 100644 --- a/src/modules/SX127x/SX127x.cpp +++ b/src/modules/SX127x/SX127x.cpp @@ -362,10 +362,10 @@ int16_t SX127x::startReceive(uint8_t len, uint8_t mode) { if(modem == RADIOLIB_SX127X_LORA) { // set DIO pin mapping if(_mod->SPIgetRegValue(RADIOLIB_SX127X_REG_HOP_PERIOD) > RADIOLIB_SX127X_HOP_PERIOD_OFF) { - state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_RX_DONE | RADIOLIB_SX127X_DIO1_FHSS_CHANGE_CHANNEL, 7, 4); + state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_LORA_RX_DONE | RADIOLIB_SX127X_DIO1_LORA_FHSS_CHANGE_CHANNEL, 7, 4); } else { - state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_RX_DONE | RADIOLIB_SX127X_DIO1_RX_TIMEOUT, 7, 4); + state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_LORA_RX_DONE | RADIOLIB_SX127X_DIO1_LORA_RX_TIMEOUT, 7, 4); } // set expected packet length for SF6 @@ -442,9 +442,9 @@ int16_t SX127x::startTransmit(uint8_t* data, size_t len, uint8_t addr) { // set DIO mapping if(_mod->SPIgetRegValue(RADIOLIB_SX127X_REG_HOP_PERIOD) > RADIOLIB_SX127X_HOP_PERIOD_OFF) { - _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_TX_DONE | RADIOLIB_SX127X_DIO1_FHSS_CHANGE_CHANNEL, 7, 4); + _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_LORA_TX_DONE | RADIOLIB_SX127X_DIO1_LORA_FHSS_CHANGE_CHANNEL, 7, 4); } else { - _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_TX_DONE, 7, 6); + _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_LORA_TX_DONE, 7, 6); } // apply fixes to errata @@ -564,7 +564,7 @@ int16_t SX127x::startChannelScan() { RADIOLIB_ASSERT(state); // set DIO pin mapping - state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_CAD_DONE | RADIOLIB_SX127X_DIO1_CAD_DETECTED, 7, 4); + state = _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_LORA_CAD_DONE | RADIOLIB_SX127X_DIO1_LORA_CAD_DETECTED, 7, 4); RADIOLIB_ASSERT(state); // clear interrupt flags @@ -1431,4 +1431,18 @@ void SX127x::clearFHSSInt(void) { } } +int16_t SX127x::setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value) { + if (pin > 5) + return RADIOLIB_ERR_INVALID_DIO_PIN; + + if (pin < 4) + return(_mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, value, 7 - 2 * pin, 6 - 2 * pin)); + else + return(_mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_2, value, 15 - 2 * pin, 14 - 2 * pin)); +} + +int16_t SX127x::setDIOPreambleDetect(bool usePreambleDetect) { + return _mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_2, (usePreambleDetect) ? RADIOLIB_SX127X_DIO_MAP_PREAMBLE_DETECT : RADIOLIB_SX127X_DIO_MAP_RSSI, 0, 0); +} + #endif diff --git a/src/modules/SX127x/SX127x.h b/src/modules/SX127x/SX127x.h index 15ba7154..656feae2 100644 --- a/src/modules/SX127x/SX127x.h +++ b/src/modules/SX127x/SX127x.h @@ -141,14 +141,6 @@ #define RADIOLIB_SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled #define RADIOLIB_SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0 -// SX127X_REG_DIO_MAPPING_1 -#define RADIOLIB_SX127X_DIO0_RX_DONE 0b00000000 // 7 6 -#define RADIOLIB_SX127X_DIO0_TX_DONE 0b01000000 // 7 6 -#define RADIOLIB_SX127X_DIO0_CAD_DONE 0b10000000 // 7 6 -#define RADIOLIB_SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4 -#define RADIOLIB_SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4 -#define RADIOLIB_SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4 - // SX127X_REG_IRQ_FLAGS #define RADIOLIB_SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout #define RADIOLIB_SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete @@ -509,20 +501,64 @@ #define RADIOLIB_SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold // SX127X_REG_DIO_MAPPING_1 +#define RADIOLIB_SX127X_DIO0_LORA_RX_DONE 0b00000000 // 7 6 +#define RADIOLIB_SX127X_DIO0_LORA_TX_DONE 0b01000000 // 7 6 +#define RADIOLIB_SX127X_DIO0_LORA_CAD_DONE 0b10000000 // 7 6 +#define RADIOLIB_SX127X_DIO0_CONT_MODE_READY 0b11000000 // 7 6 #define RADIOLIB_SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6 -#define RADIOLIB_SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6 -#define RADIOLIB_SX127X_DIO0_CONT_RSSI_RADIOLIB_PREAMBLE_DETECTED 0b01000000 // 7 6 +#define RADIOLIB_SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECT 0b01000000 // 7 6 #define RADIOLIB_SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6 +#define RADIOLIB_SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6 #define RADIOLIB_SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6 #define RADIOLIB_SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6 #define RADIOLIB_SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6 #define RADIOLIB_SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6 +#define RADIOLIB_SX127X_DIO1_LORA_RX_TIMEOUT 0b00000000 // 5 4 +#define RADIOLIB_SX127X_DIO1_LORA_FHSS_CHANGE_CHANNEL 0b01000000 // 5 4 +#define RADIOLIB_SX127X_DIO1_LORA_CAD_DETECTED 0b10000000 // 5 4 #define RADIOLIB_SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4 -#define RADIOLIB_SX127X_DIO1_CONT_RSSI_RADIOLIB_PREAMBLE_DETECTED 0b00010000 // 5 4 +#define RADIOLIB_SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECT 0b00010000 // 5 4 #define RADIOLIB_SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4 #define RADIOLIB_SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4 #define RADIOLIB_SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4 +#define RADIOLIB_SX127X_DIO2_LORA_FHSS_CHANGE_CHANNEL 0b00000000 // 3 2 #define RADIOLIB_SX127X_DIO2_CONT_DATA 0b00000000 // 3 2 +#define RADIOLIB_SX127X_DIO2_PACK_FIFO_FULL 0b00000000 // 3 2 +#define RADIOLIB_SX127X_DIO2_PACK_RX_READY 0b00000100 // 3 2 +#define RADIOLIB_SX127X_DIO2_PACK_TIMEOUT 0b00001000 // 3 2 +#define RADIOLIB_SX127X_DIO2_PACK_SYNC_ADDRESS 0b00011000 // 3 2 +#define RADIOLIB_SX127X_DIO3_LORA_CAD_DONE 0b00000000 // 0 1 +#define RADIOLIB_SX127X_DIO3_LORA_VALID_HEADER 0b00000001 // 0 1 +#define RADIOLIB_SX127X_DIO3_LORA_PAYLOAD_CRC_ERROR 0b00000010 // 0 1 +#define RADIOLIB_SX127X_DIO3_CONT_TIMEOUT 0b00000000 // 0 1 +#define RADIOLIB_SX127X_DIO3_CONT_RSSI_PREAMBLE_DETECT 0b00000001 // 0 1 +#define RADIOLIB_SX127X_DIO3_CONT_TEMP_CHANGE_LOW_BAT 0b00000011 // 0 1 +#define RADIOLIB_SX127X_DIO3_PACK_FIFO_EMPTY 0b00000000 // 0 1 +#define RADIOLIB_SX127X_DIO3_PACK_TX_READY 0b00000001 // 0 1 + +// SX127X_REG_DIO_MAPPING_2 +#define RADIOLIB_SX127X_DIO4_LORA_CAD_DETECTED 0b10000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_LORA_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_CONT_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_CONT_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_CONT_TIMEOUT 0b10000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_CONT_MODE_READY 0b11000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_PACK_TEMP_CHANGE_LOW_BAT 0b00000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_PACK_PLL_LOCK 0b01000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_PACK_TIMEOUT 0b10000000 // 7 6 +#define RADIOLIB_SX127X_DIO4_PACK_RSSI_PREAMBLE_DETECT 0b11000000 // 7 6 +#define RADIOLIB_SX127X_DIO5_LORA_MODE_READY 0b00000000 // 5 4 +#define RADIOLIB_SX127X_DIO5_LORA_CLK_OUT 0b00010000 // 5 4 +#define RADIOLIB_SX127X_DIO5_CONT_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX127X_DIO5_CONT_PLL_LOCK 0b00010000 // 5 4 +#define RADIOLIB_SX127X_DIO5_CONT_RSSI_PREAMBLE_DETECT 0b00100000 // 5 4 +#define RADIOLIB_SX127X_DIO5_CONT_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX127X_DIO5_PACK_CLK_OUT 0b00000000 // 5 4 +#define RADIOLIB_SX127X_DIO5_PACK_PLL_LOCK 0b00010000 // 5 4 +#define RADIOLIB_SX127X_DIO5_PACK_DATA 0b00100000 // 5 4 +#define RADIOLIB_SX127X_DIO5_PACK_MODE_READY 0b00110000 // 5 4 +#define RADIOLIB_SX127X_DIO_MAP_PREAMBLE_DETECT 0b00000001 // 0 0 +#define RADIOLIB_SX127X_DIO_MAP_RSSI 0b00000000 // 0 0 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP #define RADIOLIB_SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written @@ -1119,6 +1155,26 @@ class SX127x: public PhysicalLayer { */ void clearFHSSInt(void); + /*! + \brief Configure DIO pin mapping to get a given signal on a DIO pin (if available). + + \param pin Pin number onto which a signal is to be placed. + + \param value The value that indicates which function to place on that pin. See chip datasheet for details. + + \returns \ref status_codes + */ + int16_t setDIOMapping(RADIOLIB_PIN_TYPE pin, uint8_t value); + + /*! + \brief Configure DIO mapping to use RSSI or Preamble Detect for pins that support it. + + \param usePreambleDetect Whether to use PreambleDetect (true) or RSSI (false) on the pins that are mapped to this function. + + \returns \ref status_codes + */ + int16_t setDIOPreambleDetect(bool usePreambleDetect); + #if !defined(RADIOLIB_GODMODE) && !defined(RADIOLIB_LOW_LEVEL) protected: #endif