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[SX127x] Replace abs() with fabs()

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This commit is contained in:
jgromes 2021-05-04 09:21:23 +02:00
parent 4949827f50
commit 8ffca81521
5 changed files with 47 additions and 47 deletions

6
src/modules/SX127x/SX1272.cpp
View file

@ -92,11 +92,11 @@ int16_t SX1272::setBandwidth(float bw) {
uint8_t newBandwidth; uint8_t newBandwidth;
// check allowed bandwidth values // check allowed bandwidth values
if(abs(bw - 125.0) <= 0.001) { if(fabs(bw - 125.0) <= 0.001) {
newBandwidth = SX1272_BW_125_00_KHZ; newBandwidth = SX1272_BW_125_00_KHZ;
} else if(abs(bw - 250.0) <= 0.001) { } else if(fabs(bw - 250.0) <= 0.001) {
newBandwidth = SX1272_BW_250_00_KHZ; newBandwidth = SX1272_BW_250_00_KHZ;
} else if(abs(bw - 500.0) <= 0.001) { } else if(fabs(bw - 500.0) <= 0.001) {
newBandwidth = SX1272_BW_500_00_KHZ; newBandwidth = SX1272_BW_500_00_KHZ;
} else { } else {
return(ERR_INVALID_BANDWIDTH); return(ERR_INVALID_BANDWIDTH);

22
src/modules/SX127x/SX1276.cpp
View file

@ -57,7 +57,7 @@ int16_t SX1276::setFrequency(float freq) {
if(getActiveModem() == SX127X_LORA) { if(getActiveModem() == SX127X_LORA) {
// sensitivity optimization for 500kHz bandwidth // sensitivity optimization for 500kHz bandwidth
// see SX1276/77/78 Errata, section 2.1 for details // see SX1276/77/78 Errata, section 2.1 for details
if(abs(_bw - 500.0) <= 0.001) { if(fabs(_bw - 500.0) <= 0.001) {
if((freq >= 862.0) && (freq <= 1020.0)) { if((freq >= 862.0) && (freq <= 1020.0)) {
_mod->SPIwriteRegister(0x36, 0x02); _mod->SPIwriteRegister(0x36, 0x02);
_mod->SPIwriteRegister(0x3a, 0x64); _mod->SPIwriteRegister(0x3a, 0x64);
@ -69,49 +69,49 @@ int16_t SX1276::setFrequency(float freq) {
// mitigation of receiver spurious response // mitigation of receiver spurious response
// see SX1276/77/78 Errata, section 2.3 for details // see SX1276/77/78 Errata, section 2.3 for details
if(abs(_bw - 7.8) <= 0.001) { if(fabs(_bw - 7.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x48); _mod->SPIsetRegValue(0x2F, 0x48);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 7.8; freq += 7.8;
} else if(abs(_bw - 10.4) <= 0.001) { } else if(fabs(_bw - 10.4) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 10.4; freq += 10.4;
} else if(abs(_bw - 15.6) <= 0.001) { } else if(fabs(_bw - 15.6) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 15.6; freq += 15.6;
} else if(abs(_bw - 20.8) <= 0.001) { } else if(fabs(_bw - 20.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 20.8; freq += 20.8;
} else if(abs(_bw - 31.25) <= 0.001) { } else if(fabs(_bw - 31.25) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 31.25; freq += 31.25;
} else if(abs(_bw - 41.7) <= 0.001) { } else if(fabs(_bw - 41.7) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 41.7; freq += 41.7;
} else if(abs(_bw - 62.5) <= 0.001) { } else if(fabs(_bw - 62.5) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 125.0) <= 0.001) { } else if(fabs(_bw - 125.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 250.0) <= 0.001) { } else if(fabs(_bw - 250.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 500.0) <= 0.001) { } else if(fabs(_bw - 500.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b1000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b1000000, 7, 7);
} }
} }

22
src/modules/SX127x/SX1277.cpp
View file

@ -57,7 +57,7 @@ int16_t SX1277::setFrequency(float freq) {
if(getActiveModem() == SX127X_LORA) { if(getActiveModem() == SX127X_LORA) {
// sensitivity optimization for 500kHz bandwidth // sensitivity optimization for 500kHz bandwidth
// see SX1276/77/78 Errata, section 2.1 for details // see SX1276/77/78 Errata, section 2.1 for details
if(abs(_bw - 500.0) <= 0.001) { if(fabs(_bw - 500.0) <= 0.001) {
if((freq >= 862.0) && (freq <= 1020.0)) { if((freq >= 862.0) && (freq <= 1020.0)) {
_mod->SPIwriteRegister(0x36, 0x02); _mod->SPIwriteRegister(0x36, 0x02);
_mod->SPIwriteRegister(0x3a, 0x64); _mod->SPIwriteRegister(0x3a, 0x64);
@ -69,49 +69,49 @@ int16_t SX1277::setFrequency(float freq) {
// mitigation of receiver spurious response // mitigation of receiver spurious response
// see SX1276/77/78 Errata, section 2.3 for details // see SX1276/77/78 Errata, section 2.3 for details
if(abs(_bw - 7.8) <= 0.001) { if(fabs(_bw - 7.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x48); _mod->SPIsetRegValue(0x2F, 0x48);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 7.8; freq += 7.8;
} else if(abs(_bw - 10.4) <= 0.001) { } else if(fabs(_bw - 10.4) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 10.4; freq += 10.4;
} else if(abs(_bw - 15.6) <= 0.001) { } else if(fabs(_bw - 15.6) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 15.6; freq += 15.6;
} else if(abs(_bw - 20.8) <= 0.001) { } else if(fabs(_bw - 20.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 20.8; freq += 20.8;
} else if(abs(_bw - 31.25) <= 0.001) { } else if(fabs(_bw - 31.25) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 31.25; freq += 31.25;
} else if(abs(_bw - 41.7) <= 0.001) { } else if(fabs(_bw - 41.7) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 41.7; freq += 41.7;
} else if(abs(_bw - 62.5) <= 0.001) { } else if(fabs(_bw - 62.5) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 125.0) <= 0.001) { } else if(fabs(_bw - 125.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 250.0) <= 0.001) { } else if(fabs(_bw - 250.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 500.0) <= 0.001) { } else if(fabs(_bw - 500.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b1000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b1000000, 7, 7);
} }
} }

42
src/modules/SX127x/SX1278.cpp
View file

@ -74,7 +74,7 @@ int16_t SX1278::setFrequency(float freq) {
if(getActiveModem() == SX127X_LORA) { if(getActiveModem() == SX127X_LORA) {
// sensitivity optimization for 500kHz bandwidth // sensitivity optimization for 500kHz bandwidth
// see SX1276/77/78 Errata, section 2.1 for details // see SX1276/77/78 Errata, section 2.1 for details
if(abs(_bw - 500.0) <= 0.001) { if(fabs(_bw - 500.0) <= 0.001) {
if((freq >= 862.0) && (freq <= 1020.0)) { if((freq >= 862.0) && (freq <= 1020.0)) {
_mod->SPIwriteRegister(0x36, 0x02); _mod->SPIwriteRegister(0x36, 0x02);
_mod->SPIwriteRegister(0x3a, 0x64); _mod->SPIwriteRegister(0x3a, 0x64);
@ -86,49 +86,49 @@ int16_t SX1278::setFrequency(float freq) {
// mitigation of receiver spurious response // mitigation of receiver spurious response
// see SX1276/77/78 Errata, section 2.3 for details // see SX1276/77/78 Errata, section 2.3 for details
if(abs(_bw - 7.8) <= 0.001) { if(fabs(_bw - 7.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x48); _mod->SPIsetRegValue(0x2F, 0x48);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 7.8; freq += 7.8;
} else if(abs(_bw - 10.4) <= 0.001) { } else if(fabs(_bw - 10.4) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 10.4; freq += 10.4;
} else if(abs(_bw - 15.6) <= 0.001) { } else if(fabs(_bw - 15.6) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 15.6; freq += 15.6;
} else if(abs(_bw - 20.8) <= 0.001) { } else if(fabs(_bw - 20.8) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 20.8; freq += 20.8;
} else if(abs(_bw - 31.25) <= 0.001) { } else if(fabs(_bw - 31.25) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 31.25; freq += 31.25;
} else if(abs(_bw - 41.7) <= 0.001) { } else if(fabs(_bw - 41.7) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x44); _mod->SPIsetRegValue(0x2F, 0x44);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
freq += 41.7; freq += 41.7;
} else if(abs(_bw - 62.5) <= 0.001) { } else if(fabs(_bw - 62.5) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 125.0) <= 0.001) { } else if(fabs(_bw - 125.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 250.0) <= 0.001) { } else if(fabs(_bw - 250.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b0000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b0000000, 7, 7);
_mod->SPIsetRegValue(0x2F, 0x40); _mod->SPIsetRegValue(0x2F, 0x40);
_mod->SPIsetRegValue(0x30, 0x00); _mod->SPIsetRegValue(0x30, 0x00);
} else if(abs(_bw - 500.0) <= 0.001) { } else if(fabs(_bw - 500.0) <= 0.001) {
_mod->SPIsetRegValue(0x31, 0b1000000, 7, 7); _mod->SPIsetRegValue(0x31, 0b1000000, 7, 7);
} }
} }
@ -150,25 +150,25 @@ int16_t SX1278::setBandwidth(float bw) {
uint8_t newBandwidth; uint8_t newBandwidth;
// check allowed bandwidth values // check allowed bandwidth values
if(abs(bw - 7.8) <= 0.001) { if(fabs(bw - 7.8) <= 0.001) {
newBandwidth = SX1278_BW_7_80_KHZ; newBandwidth = SX1278_BW_7_80_KHZ;
} else if(abs(bw - 10.4) <= 0.001) { } else if(fabs(bw - 10.4) <= 0.001) {
newBandwidth = SX1278_BW_10_40_KHZ; newBandwidth = SX1278_BW_10_40_KHZ;
} else if(abs(bw - 15.6) <= 0.001) { } else if(fabs(bw - 15.6) <= 0.001) {
newBandwidth = SX1278_BW_15_60_KHZ; newBandwidth = SX1278_BW_15_60_KHZ;
} else if(abs(bw - 20.8) <= 0.001) { } else if(fabs(bw - 20.8) <= 0.001) {
newBandwidth = SX1278_BW_20_80_KHZ; newBandwidth = SX1278_BW_20_80_KHZ;
} else if(abs(bw - 31.25) <= 0.001) { } else if(fabs(bw - 31.25) <= 0.001) {
newBandwidth = SX1278_BW_31_25_KHZ; newBandwidth = SX1278_BW_31_25_KHZ;
} else if(abs(bw - 41.7) <= 0.001) { } else if(fabs(bw - 41.7) <= 0.001) {
newBandwidth = SX1278_BW_41_70_KHZ; newBandwidth = SX1278_BW_41_70_KHZ;
} else if(abs(bw - 62.5) <= 0.001) { } else if(fabs(bw - 62.5) <= 0.001) {
newBandwidth = SX1278_BW_62_50_KHZ; newBandwidth = SX1278_BW_62_50_KHZ;
} else if(abs(bw - 125.0) <= 0.001) { } else if(fabs(bw - 125.0) <= 0.001) {
newBandwidth = SX1278_BW_125_00_KHZ; newBandwidth = SX1278_BW_125_00_KHZ;
} else if(abs(bw - 250.0) <= 0.001) { } else if(fabs(bw - 250.0) <= 0.001) {
newBandwidth = SX1278_BW_250_00_KHZ; newBandwidth = SX1278_BW_250_00_KHZ;
} else if(abs(bw - 500.0) <= 0.001) { } else if(fabs(bw - 500.0) <= 0.001) {
newBandwidth = SX1278_BW_500_00_KHZ; newBandwidth = SX1278_BW_500_00_KHZ;
} else { } else {
return(ERR_INVALID_BANDWIDTH); return(ERR_INVALID_BANDWIDTH);

2
src/modules/SX127x/SX127x.cpp
View file

@ -763,7 +763,7 @@ uint8_t SX127x::calculateBWManExp(float bandwidth)
for(uint8_t e = 7; e >= 1; e--) { for(uint8_t e = 7; e >= 1; e--) {
for(int8_t m = 2; m >= 0; m--) { for(int8_t m = 2; m >= 0; m--) {
float point = (SX127X_CRYSTAL_FREQ * 1000000.0)/(((4 * m) + 16) * ((uint32_t)1 << (e + 2))); float point = (SX127X_CRYSTAL_FREQ * 1000000.0)/(((4 * m) + 16) * ((uint32_t)1 << (e + 2)));
if(abs(bandwidth - ((point / 1000.0) + 0.05)) <= 0.5) { if(fabs(bandwidth - ((point / 1000.0) + 0.05)) <= 0.5) {
return((m << 3) | e); return((m << 3) | e);
} }
} }