From e073da15da3ae9e6addc0f8681cecb1a53affb51 Mon Sep 17 00:00:00 2001 From: Mitrokhin Anton Date: Thu, 22 Dec 2022 12:21:01 +0700 Subject: [PATCH] Fix FSK Stream mode TX and RX --- .../Stream_Transmit/Stream_Transmit.ino | 16 ++++++++++++---- src/modules/SX127x/SX127x.cpp | 19 ------------------- 2 files changed, 12 insertions(+), 23 deletions(-) diff --git a/examples/Stream/Stream_Transmit/Stream_Transmit.ino b/examples/Stream/Stream_Transmit/Stream_Transmit.ino index 26eb7f3a..2d638fa4 100644 --- a/examples/Stream/Stream_Transmit/Stream_Transmit.ino +++ b/examples/Stream/Stream_Transmit/Stream_Transmit.ino @@ -86,6 +86,8 @@ volatile bool transmittedFlag = false; // disable interrupt when it's not needed volatile bool enableInterrupt = true; +bool isFifoEmpty = false; + // how many bytes are there in total volatile int totalLength = longPacket.length(); @@ -104,13 +106,19 @@ void fifoAdd(void) { if(!enableInterrupt) { return; } - - // add more bytes to the transmit buffer - uint8_t* txBuffPtr = (uint8_t*)longPacket.c_str(); - transmittedFlag = radio.fifoAdd(txBuffPtr, totalLength, &remLength); + isFifoEmpty = true; } void loop() { + if (isFifoEmpty) { + enableInterrupt = false; + // add more bytes to the transmit buffer + uint8_t* txBuffPtr = (uint8_t*)longPacket.c_str(); + transmittedFlag = radio.fifoAdd(txBuffPtr, totalLength, &remLength); + enableInterrupt = true; + isFifoEmpty = false; + } + // check if the previous transmission finished if(transmittedFlag) { // disable the interrupt service routine while diff --git a/src/modules/SX127x/SX127x.cpp b/src/modules/SX127x/SX127x.cpp index a3a94345..6cdb607f 100644 --- a/src/modules/SX127x/SX127x.cpp +++ b/src/modules/SX127x/SX127x.cpp @@ -478,16 +478,9 @@ bool SX127x::fifoAdd(uint8_t* data, int totalLen, volatile int* remLen) { len = RADIOLIB_SX127X_FIFO_THRESH - 1; } - // clear interrupt flags - clearIRQFlags(); - // copy the bytes to the FIFO _mod->SPIwriteRegisterBurst(RADIOLIB_SX127X_REG_FIFO, &data[totalLen - *remLen], len); - // this is a hack, but it seems Rx FIFO level is getting triggered 1 byte before it should - // we just add a padding byte that we can drop without consequence - _mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, '/'); - // we're not done yet return(false); } @@ -507,12 +500,6 @@ bool SX127x::fifoGet(volatile uint8_t* data, int totalLen, volatile int* rcvLen) _mod->SPIreadRegisterBurst(RADIOLIB_SX127X_REG_FIFO, len, dataPtr); (*rcvLen) += (len); - // dump the padding byte - _mod->SPIreadRegister(RADIOLIB_SX127X_REG_FIFO); - - // clear flags - clearIRQFlags(); - // check if we're done if(*rcvLen >= totalLen) { return(true); @@ -582,12 +569,6 @@ int16_t SX127x::startTransmit(uint8_t* data, size_t len, uint8_t addr) { } _mod->SPIwriteRegisterBurst(RADIOLIB_SX127X_REG_FIFO, data, packetLen); - // this is a hack, but it seems than in Stream mode, Rx FIFO level is getting triggered 1 byte before it should - // just add a padding byte that can be dropped without consequence - if((modem == RADIOLIB_SX127X_FSK_OOK) && (len > RADIOLIB_SX127X_MAX_PACKET_LENGTH_FSK)) { - _mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, '/'); - } - // set RF switch (if present) _mod->setRfSwitchState(LOW, HIGH);