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[Si443x] General reformatting

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This commit is contained in:
jgromes 2023-04-23 21:14:01 +02:00
parent f1c9423035
commit 674c37d00b
10 changed files with 552 additions and 655 deletions
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1
src/modules/RFM2x/RFM22.h
View file

@ -11,7 +11,6 @@
/*!
\class RFM22
\brief Only exists as alias for Si4432, since there seems to be no difference between %RFM22 and %Si4432 modules.
*/
RADIOLIB_TYPE_ALIAS(Si4432, RFM22);

1
src/modules/RFM2x/RFM23.h
View file

@ -11,7 +11,6 @@
/*!
\class RFM23
\brief Only exists as alias for Si4431, since there seems to be no difference between %RFM23 and %Si4431 modules.
*/
RADIOLIB_TYPE_ALIAS(Si4431, RFM23);

2
src/modules/Si443x/Si4430.cpp
View file

@ -32,7 +32,7 @@ int16_t Si4430::setOutputPower(int8_t power) {
RADIOLIB_CHECK_RANGE(power, -8, 13, RADIOLIB_ERR_INVALID_OUTPUT_POWER);
// set output power
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0));
}
#endif

14
src/modules/Si443x/Si4430.h
View file

@ -10,7 +10,6 @@
/*!
\class Si4430
\brief Derived class for %Si4430 modules.
*/
class Si4430: public Si4432 {
@ -20,7 +19,6 @@ class Si4430: public Si4432 {
/*!
\brief Default constructor.
\param mod Instance of Module that will be used to communicate with the radio chip.
*/
Si4430(Module* mod);
@ -29,19 +27,12 @@ class Si4430: public Si4432 {
/*!
\brief Initialization method. Must be called at least once from Arduino sketch to initialize the module.
\param freq Carrier frequency in MHz. Allowed values range from 900.0 MHz to 960.0 MHz.
\param br Bit rate of the FSK transmission in kbps (kilobits per second). Allowed values range from 0.123 to 256.0 kbps.
\param freqDev Frequency deviation of the FSK transmission in kHz. Allowed values range from 0.625 to 320.0 kbps.
\param rxBw Receiver bandwidth in kHz. Allowed values range from 2.6 to 620.7 kHz.
\param power Transmission output power in dBm. Allowed values range from -8 to 13 dBm in 3 dBm steps.
\param preambleLen Preamble Length in bits. Defaults to 16 bits.
\returns \ref status_codes
*/
int16_t begin(float freq = 434.0, float br = 4.8, float freqDev = 5.0, float rxBw = 181.1, int8_t power = 10, uint8_t preambleLen = 16);
@ -50,23 +41,18 @@ class Si4430: public Si4432 {
/*!
\brief Sets carrier frequency. Allowed values range from 900.0 MHz to 960.0 MHz.
\param freq Carrier frequency to be set in MHz.
\returns \ref status_codes
*/
int16_t setFrequency(float freq);
/*!
\brief Sets output power. Allowed values range from -8 to 13 dBm in 3 dBm steps.
\param power Output power to be set in dBm.
\returns \ref status_codes
*/
int16_t setOutputPower(int8_t power);
#if !defined(RADIOLIB_GODMODE)
protected:
#endif

2
src/modules/Si443x/Si4431.cpp
View file

@ -25,7 +25,7 @@ int16_t Si4431::setOutputPower(int8_t power) {
RADIOLIB_CHECK_RANGE(power, -8, 13, RADIOLIB_ERR_INVALID_OUTPUT_POWER);
// set output power
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 8) / 3), 2, 0));
}
#endif

12
src/modules/Si443x/Si4431.h
View file

@ -10,7 +10,6 @@
/*!
\class Si4431
\brief Derived class for %Si4431 modules.
*/
class Si4431: public Si4432 {
@ -20,7 +19,6 @@ class Si4431: public Si4432 {
/*!
\brief Default constructor.
\param mod Instance of Module that will be used to communicate with the radio chip.
*/
Si4431(Module* mod);
@ -29,19 +27,12 @@ class Si4431: public Si4432 {
/*!
\brief Initialization method. Must be called at least once from Arduino sketch to initialize the module.
\param freq Carrier frequency in MHz. Allowed values range from 240.0 MHz to 930.0 MHz.
\param br Bit rate of the FSK transmission in kbps (kilobits per second). Allowed values range from 0.123 to 256.0 kbps.
\param freqDev Frequency deviation of the FSK transmission in kHz. Allowed values range from 0.625 to 320.0 kbps.
\param rxBw Receiver bandwidth in kHz. Allowed values range from 2.6 to 620.7 kHz.
\param power Transmission output power in dBm. Allowed values range from -8 to 13 dBm in 3 dBm steps.
\param preambleLen Preamble Length in bits. Defaults to 16 bits.
\returns \ref status_codes
*/
int16_t begin(float freq = 434.0, float br = 4.8, float freqDev = 5.0, float rxBw = 181.1, int8_t power = 10, uint8_t preambleLen = 16);
@ -50,14 +41,11 @@ class Si4431: public Si4432 {
/*!
\brief Sets output power. Allowed values range from -8 to 13 dBm in 3 dBm steps.
\param power Output power to be set in dBm.
\returns \ref status_codes
*/
int16_t setOutputPower(int8_t power);
#if !defined(RADIOLIB_GODMODE)
protected:
#endif

2
src/modules/Si443x/Si4432.cpp
View file

@ -32,7 +32,7 @@ int16_t Si4432::setOutputPower(int8_t power) {
RADIOLIB_CHECK_RANGE(power, -1, 20, RADIOLIB_ERR_INVALID_OUTPUT_POWER);
// set output power
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 1) / 3), 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TX_POWER, (uint8_t)((power + 1) / 3), 2, 0));
}
#endif

14
src/modules/Si443x/Si4432.h
View file

@ -10,7 +10,6 @@
/*!
\class Si4432
\brief Derived class for %Si4432 modules.
*/
class Si4432: public Si443x {
@ -20,7 +19,6 @@ class Si4432: public Si443x {
/*!
\brief Default constructor.
\param mod Instance of Module that will be used to communicate with the radio chip.
*/
Si4432(Module* mod);
@ -29,19 +27,12 @@ class Si4432: public Si443x {
/*!
\brief Initialization method. Must be called at least once from Arduino sketch to initialize the module.
\param freq Carrier frequency in MHz. Allowed values range from 240.0 MHz to 930.0 MHz.
\param br Bit rate of the FSK transmission in kbps (kilobits per second). Allowed values range from 0.123 to 256.0 kbps.
\param freqDev Frequency deviation of the FSK transmission in kHz. Allowed values range from 0.625 to 320.0 kbps.
\param rxBw Receiver bandwidth in kHz. Allowed values range from 2.6 to 620.7 kHz.
\param power Transmission output power in dBm. Allowed values range from -1 to 20 dBm in 3 dBm steps.
\param preambleLen Preamble Length in bits. Defaults to 16 bits.
\returns \ref status_codes
*/
int16_t begin(float freq = 434.0, float br = 4.8, float freqDev = 5.0, float rxBw = 181.1, int8_t power = 10, uint8_t preambleLen = 16);
@ -50,23 +41,18 @@ class Si4432: public Si443x {
/*!
\brief Sets carrier frequency. Allowed values range from 240.0 MHz to 930.0 MHz.
\param freq Carrier frequency to be set in MHz.
\returns \ref status_codes
*/
int16_t setFrequency(float freq);
/*!
\brief Sets output power. Allowed values range from -1 to 20 dBm in 3 dBm steps.
\param power Output power to be set in dBm.
\returns \ref status_codes
*/
int16_t setOutputPower(int8_t power);
#if !defined(RADIOLIB_GODMODE)
protected:
#endif

246
src/modules/Si443x/Si443x.cpp
View file

@ -3,31 +3,31 @@
#if !defined(RADIOLIB_EXCLUDE_SI443X)
Si443x::Si443x(Module* mod) : PhysicalLayer(RADIOLIB_SI443X_FREQUENCY_STEP_SIZE, RADIOLIB_SI443X_MAX_PACKET_LENGTH) {
_mod = mod;
this->mod = mod;
}
Module* Si443x::getMod() {
return(_mod);
return(this->mod);
}
int16_t Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen) {
// set module properties
_mod->init();
_mod->hal->pinMode(_mod->getIrq(), _mod->hal->GpioModeInput);
_mod->hal->pinMode(_mod->getRst(), _mod->hal->GpioModeOutput);
_mod->hal->digitalWrite(_mod->getRst(), _mod->hal->GpioLevelLow);
this->mod->init();
this->mod->hal->pinMode(this->mod->getIrq(), this->mod->hal->GpioModeInput);
this->mod->hal->pinMode(this->mod->getRst(), this->mod->hal->GpioModeOutput);
this->mod->hal->digitalWrite(this->mod->getRst(), this->mod->hal->GpioLevelLow);
// try to find the Si443x chip
if(!Si443x::findChip()) {
RADIOLIB_DEBUG_PRINTLN("No Si443x found!");
_mod->term();
this->mod->term();
return(RADIOLIB_ERR_CHIP_NOT_FOUND);
} else {
RADIOLIB_DEBUG_PRINTLN("M\tSi443x");
}
// reset the device
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_SOFTWARE_RESET);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_SOFTWARE_RESET);
// clear POR interrupt
clearIRQFlags();
@ -68,26 +68,26 @@ int16_t Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen)
}
void Si443x::reset() {
_mod->hal->pinMode(_mod->getRst(), _mod->hal->GpioModeOutput);
_mod->hal->digitalWrite(_mod->getRst(), _mod->hal->GpioLevelHigh);
_mod->hal->delay(1);
_mod->hal->digitalWrite(_mod->getRst(), _mod->hal->GpioLevelLow);
_mod->hal->delay(100);
this->mod->hal->pinMode(this->mod->getRst(), this->mod->hal->GpioModeOutput);
this->mod->hal->digitalWrite(this->mod->getRst(), this->mod->hal->GpioLevelHigh);
this->mod->hal->delay(1);
this->mod->hal->digitalWrite(this->mod->getRst(), this->mod->hal->GpioLevelLow);
this->mod->hal->delay(100);
}
int16_t Si443x::transmit(uint8_t* data, size_t len, uint8_t addr) {
// calculate timeout (5ms + 500 % of expected time-on-air)
uint32_t timeout = 5000000 + (uint32_t)((((float)(len * 8)) / (_br * 1000.0)) * 5000000.0);
uint32_t timeout = 5000000 + (uint32_t)((((float)(len * 8)) / (this->bitRate * 1000.0)) * 5000000.0);
// start transmission
int16_t state = startTransmit(data, len, addr);
RADIOLIB_ASSERT(state);
// wait for transmission end or timeout
uint32_t start = _mod->hal->micros();
while(_mod->hal->digitalRead(_mod->getIrq())) {
_mod->hal->yield();
if(_mod->hal->micros() - start > timeout) {
uint32_t start = this->mod->hal->micros();
while(this->mod->hal->digitalRead(this->mod->getIrq())) {
this->mod->hal->yield();
if(this->mod->hal->micros() - start > timeout) {
finishTransmit();
return(RADIOLIB_ERR_TX_TIMEOUT);
}
@ -98,16 +98,16 @@ int16_t Si443x::transmit(uint8_t* data, size_t len, uint8_t addr) {
int16_t Si443x::receive(uint8_t* data, size_t len) {
// calculate timeout (500 ms + 400 full 64-byte packets at current bit rate)
uint32_t timeout = 500000 + (1.0/(_br*1000.0))*(RADIOLIB_SI443X_MAX_PACKET_LENGTH*400.0);
uint32_t timeout = 500000 + (1.0/(this->bitRate*1000.0))*(RADIOLIB_SI443X_MAX_PACKET_LENGTH*400.0);
// start reception
int16_t state = startReceive();
RADIOLIB_ASSERT(state);
// wait for packet reception or timeout
uint32_t start = _mod->hal->micros();
while(_mod->hal->digitalRead(_mod->getIrq())) {
if(_mod->hal->micros() - start > timeout) {
uint32_t start = this->mod->hal->micros();
while(this->mod->hal->digitalRead(this->mod->getIrq())) {
if(this->mod->hal->micros() - start > timeout) {
standby();
clearIRQFlags();
return(RADIOLIB_ERR_RX_TIMEOUT);
@ -120,16 +120,16 @@ int16_t Si443x::receive(uint8_t* data, size_t len) {
int16_t Si443x::sleep() {
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_IDLE);
this->mod->setRfSwitchState(Module::MODE_IDLE);
// disable wakeup timer interrupt
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, 0x00);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, 0x00);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
RADIOLIB_ASSERT(state);
// enable wakeup timer to set mode to sleep
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_ENABLE_WAKEUP_TIMER);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_ENABLE_WAKEUP_TIMER);
return(state);
}
@ -140,13 +140,13 @@ int16_t Si443x::standby() {
int16_t Si443x::standby(uint8_t mode) {
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_IDLE);
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, mode, 7, 0, 10));
this->mod->setRfSwitchState(Module::MODE_IDLE);
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, mode, 7, 0, 10));
}
int16_t Si443x::transmitDirect(uint32_t frf) {
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_TX);
this->mod->setRfSwitchState(Module::MODE_TX);
// user requested to start transmitting immediately (required for RTTY)
if(frf != 0) {
@ -166,13 +166,13 @@ int16_t Si443x::transmitDirect(uint32_t frf) {
uint16_t freqCarrier = ((newFreq / (10 * ((bandSelect >> 5) + 1))) - freqBand - 24) * (uint32_t)64000;
// update registers
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, RADIOLIB_SI443X_SIDE_BAND_SELECT_LOW | bandSelect | freqBand);
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8));
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF));
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, RADIOLIB_SI443X_SIDE_BAND_SELECT_LOW | bandSelect | freqBand);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8));
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF));
// start direct transmission
directMode();
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
return(RADIOLIB_ERR_NONE);
}
@ -182,36 +182,36 @@ int16_t Si443x::transmitDirect(uint32_t frf) {
RADIOLIB_ASSERT(state);
// start transmitting
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
return(state);
}
int16_t Si443x::receiveDirect() {
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_RX);
this->mod->setRfSwitchState(Module::MODE_RX);
// activate direct mode
int16_t state = directMode();
RADIOLIB_ASSERT(state);
// start receiving
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
return(state);
}
int16_t Si443x::packetMode() {
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0);
RADIOLIB_ASSERT(state);
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_FIFO, 5, 4));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_FIFO, 5, 4));
}
void Si443x::setIrqAction(void (*func)(void)) {
_mod->hal->attachInterrupt(_mod->hal->pinToInterrupt(_mod->getIrq()), func, _mod->hal->GpioInterruptFalling);
this->mod->hal->attachInterrupt(this->mod->hal->pinToInterrupt(this->mod->getIrq()), func, this->mod->hal->GpioInterruptFalling);
}
void Si443x::clearIrqAction() {
_mod->hal->detachInterrupt(_mod->hal->pinToInterrupt(_mod->getIrq()));
this->mod->hal->detachInterrupt(this->mod->hal->pinToInterrupt(this->mod->getIrq()));
}
int16_t Si443x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
@ -225,32 +225,32 @@ int16_t Si443x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
RADIOLIB_ASSERT(state);
// clear Tx FIFO
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_RESET, 0, 0);
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_CLEAR, 0, 0);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_RESET, 0, 0);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_TX_FIFO_CLEAR, 0, 0);
// clear interrupt flags
clearIRQFlags();
// set packet length
if (_packetLengthConfig == RADIOLIB_SI443X_FIXED_PACKET_LENGTH_OFF) {
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH, len);
if (this->packetLengthConfig == RADIOLIB_SI443X_FIXED_PACKET_LENGTH_OFF) {
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH, len);
}
/// \todo use header as address field?
(void)addr;
// write packet to FIFO
_mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, data, len);
this->mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, data, len);
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_TX);
this->mod->setRfSwitchState(Module::MODE_TX);
// set interrupt mapping
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_PACKET_SENT_ENABLED);
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_PACKET_SENT_ENABLED);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
// set mode to transmit
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_TX_ON | RADIOLIB_SI443X_XTAL_ON);
return(state);
}
@ -269,21 +269,21 @@ int16_t Si443x::startReceive() {
RADIOLIB_ASSERT(state);
// clear Rx FIFO
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_RESET, 1, 1);
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_CLEAR, 1, 1);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_RESET, 1, 1);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_2, RADIOLIB_SI443X_RX_FIFO_CLEAR, 1, 1);
// clear interrupt flags
clearIRQFlags();
// set RF switch (if present)
_mod->setRfSwitchState(Module::MODE_RX);
this->mod->setRfSwitchState(Module::MODE_RX);
// set interrupt mapping
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_VALID_PACKET_RECEIVED_ENABLED | RADIOLIB_SI443X_CRC_ERROR_ENABLED);
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_1, RADIOLIB_SI443X_VALID_PACKET_RECEIVED_ENABLED | RADIOLIB_SI443X_CRC_ERROR_ENABLED);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
// set mode to receive
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
return(state);
}
@ -310,7 +310,7 @@ int16_t Si443x::readData(uint8_t* data, size_t len) {
}
// read packet data
_mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, length, data);
this->mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_FIFO_ACCESS, length, data);
// dump the bytes that weren't requested
if(dumpLen != 0) {
@ -318,7 +318,7 @@ int16_t Si443x::readData(uint8_t* data, size_t len) {
}
// clear internal flag so getPacketLength can return the new packet length
_packetLengthQueried = false;
this->packetLengthQueried = false;
// set mode to standby
int16_t state = standby();
@ -346,12 +346,12 @@ int16_t Si443x::setBitRate(float br) {
uint16_t txDr = (br * ((uint32_t)1 << exp)) / 1000.0;
// update registers
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, dataRateMode, 5, 5);
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_1, (uint8_t)((txDr & 0xFF00) >> 8));
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_0, (uint8_t)(txDr & 0xFF));
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, dataRateMode, 5, 5);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_1, (uint8_t)((txDr & 0xFF00) >> 8));
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_TX_DATA_RATE_0, (uint8_t)(txDr & 0xFF));
if(state == RADIOLIB_ERR_NONE) {
_br = br;
this->bitRate = br;
}
RADIOLIB_ASSERT(state);
@ -374,11 +374,11 @@ int16_t Si443x::setFrequencyDeviation(float freqDev) {
uint16_t fdev = (uint16_t)(newFreqDev / 0.625);
// update registers
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, (uint8_t)((fdev & 0x0100) >> 6), 2, 2);
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_DEVIATION, (uint8_t)(fdev & 0xFF));
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, (uint8_t)((fdev & 0x0100) >> 6), 2, 2);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_FREQUENCY_DEVIATION, (uint8_t)(fdev & 0xFF));
if(state == RADIOLIB_ERR_NONE) {
_freqDev = newFreqDev;
this->frequencyDev = newFreqDev;
}
return(state);
@ -482,7 +482,7 @@ int16_t Si443x::setRxBandwidth(float rxBw) {
decRate <<= 4;
// update register
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, bypass | decRate | filterSet);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, bypass | decRate | filterSet);
RADIOLIB_ASSERT(state);
// update clock recovery
@ -499,11 +499,11 @@ int16_t Si443x::setSyncWord(uint8_t* syncWord, size_t len) {
RADIOLIB_ASSERT(state);
// set sync word length
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, (uint8_t)(len - 1) << 1, 2, 1);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, (uint8_t)(len - 1) << 1, 2, 1);
RADIOLIB_ASSERT(state);
// set sync word bytes
_mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_SYNC_WORD_3, syncWord, len);
this->mod->SPIwriteRegisterBurst(RADIOLIB_SI443X_REG_SYNC_WORD_3, syncWord, len);
return(state);
}
@ -516,25 +516,25 @@ int16_t Si443x::setPreambleLength(uint8_t preambleLen) {
// set default preamble length
uint8_t preLenNibbles = preambleLen / 4;
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_LENGTH, preLenNibbles);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_LENGTH, preLenNibbles);
RADIOLIB_ASSERT(state);
// set default preamble detection threshold to 5/8 of preamble length (in units of 4 bits)
uint8_t preThreshold = 5*preLenNibbles / 8;
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_DET_CONTROL, preThreshold << 3, 7, 3));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_PREAMBLE_DET_CONTROL, preThreshold << 3, 7, 3));
}
size_t Si443x::getPacketLength(bool update) {
if(!_packetLengthQueried && update) {
if (_packetLengthConfig == RADIOLIB_SI443X_FIXED_PACKET_LENGTH_ON) {
_packetLength = _mod->SPIreadRegister(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH);
if(!this->packetLengthQueried && update) {
if (this->packetLengthConfig == RADIOLIB_SI443X_FIXED_PACKET_LENGTH_ON) {
this->packetLength = this->mod->SPIreadRegister(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH);
} else {
_packetLength = _mod->SPIreadRegister(RADIOLIB_SI443X_REG_RECEIVED_PACKET_LENGTH);
this->packetLength = this->mod->SPIreadRegister(RADIOLIB_SI443X_REG_RECEIVED_PACKET_LENGTH);
}
_packetLengthQueried = true;
this->packetLengthQueried = true;
}
return(_packetLength);
return(this->packetLength);
}
int16_t Si443x::setEncoding(uint8_t encoding) {
@ -546,11 +546,11 @@ int16_t Si443x::setEncoding(uint8_t encoding) {
/// \todo - add inverted Manchester?
switch(encoding) {
case RADIOLIB_ENCODING_NRZ:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
case RADIOLIB_ENCODING_MANCHESTER:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_ON | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_ON | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
case RADIOLIB_ENCODING_WHITENING:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0));
default:
return(RADIOLIB_ERR_INVALID_ENCODING);
}
@ -564,37 +564,37 @@ int16_t Si443x::setDataShaping(uint8_t sh) {
// set data shaping
switch(sh) {
case RADIOLIB_SHAPING_NONE:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_OFF, 2, 0));
case RADIOLIB_SHAPING_0_3:
return(RADIOLIB_ERR_INVALID_ENCODING);
case RADIOLIB_SHAPING_0_5:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_GFSK, 1, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_GFSK, 1, 0));
case RADIOLIB_SHAPING_1_0:
return(_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0));
return(this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, RADIOLIB_SI443X_MANCHESTER_INVERTED_OFF | RADIOLIB_SI443X_MANCHESTER_OFF | RADIOLIB_SI443X_WHITENING_ON, 2, 0));
default:
return(RADIOLIB_ERR_INVALID_ENCODING);
}
}
void Si443x::setRfSwitchPins(uint32_t rxEn, uint32_t txEn) {
_mod->setRfSwitchPins(rxEn, txEn);
this->mod->setRfSwitchPins(rxEn, txEn);
}
void Si443x::setRfSwitchTable(const uint32_t (&pins)[Module::RFSWITCH_MAX_PINS], const Module::RfSwitchMode_t table[]) {
_mod->setRfSwitchTable(pins, table);
this->mod->setRfSwitchTable(pins, table);
}
uint8_t Si443x::randomByte() {
// set mode to Rx
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_OP_FUNC_CONTROL_1, RADIOLIB_SI443X_RX_ON | RADIOLIB_SI443X_XTAL_ON);
// wait a bit for the RSSI reading to stabilise
_mod->hal->delay(10);
this->mod->hal->delay(10);
// read RSSI value 8 times, always keep just the least significant bit
uint8_t randByte = 0x00;
for(uint8_t i = 0; i < 8; i++) {
randByte |= ((_mod->SPIreadRegister(RADIOLIB_SI443X_REG_RSSI) & 0x01) << i);
randByte |= ((this->mod->SPIreadRegister(RADIOLIB_SI443X_REG_RSSI) & 0x01) << i);
}
// set mode to standby
@ -604,7 +604,7 @@ uint8_t Si443x::randomByte() {
}
int16_t Si443x::getChipVersion() {
return(_mod->SPIgetRegValue(RADIOLIB_SI443X_REG_DEVICE_VERSION));
return(this->mod->SPIgetRegValue(RADIOLIB_SI443X_REG_DEVICE_VERSION));
}
#if !defined(RADIOLIB_EXCLUDE_DIRECT_RECEIVE)
@ -613,7 +613,7 @@ void Si443x::setDirectAction(void (*func)(void)) {
}
void Si443x::readBit(uint32_t pin) {
updateDirectBuffer((uint8_t)_mod->hal->digitalRead(pin));
updateDirectBuffer((uint8_t)this->mod->hal->digitalRead(pin));
}
#endif
@ -634,7 +634,7 @@ int16_t Si443x::setFrequencyRaw(float newFreq) {
uint8_t bandSelect = RADIOLIB_SI443X_BAND_SELECT_LOW;
uint8_t freqBand = (newFreq / 10) - 24;
uint8_t afcLimiter = 80;
_freq = newFreq;
this->frequency = newFreq;
if(newFreq >= 480.0) {
bandSelect = RADIOLIB_SI443X_BAND_SELECT_HIGH;
freqBand = (newFreq / 20) - 24;
@ -645,10 +645,10 @@ int16_t Si443x::setFrequencyRaw(float newFreq) {
uint16_t freqCarrier = ((newFreq / (10 * ((bandSelect >> 5) + 1))) - freqBand - 24) * (uint32_t)64000;
// update registers
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, bandSelect | freqBand, 5, 0);
state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8));
state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF));
state |= _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AFC_LIMITER, afcLimiter);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_FREQUENCY_BAND_SELECT, bandSelect | freqBand, 5, 0);
state |= this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8));
state |= this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF));
state |= this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AFC_LIMITER, afcLimiter);
return(state);
}
@ -660,15 +660,15 @@ int16_t Si443x::setPacketMode(uint8_t mode, uint8_t len) {
}
// set to fixed packet length
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, mode, 3, 3);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, mode, 3, 3);
RADIOLIB_ASSERT(state);
// set length to register
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH, len);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_TRANSMIT_PACKET_LENGTH, len);
RADIOLIB_ASSERT(state);
// update cached value
_packetLengthConfig = mode;
this->packetLengthConfig = mode;
return(state);
}
@ -680,12 +680,12 @@ bool Si443x::findChip() {
reset();
// check version register
uint8_t version = _mod->SPIreadRegister(RADIOLIB_SI443X_REG_DEVICE_VERSION);
uint8_t version = this->mod->SPIreadRegister(RADIOLIB_SI443X_REG_DEVICE_VERSION);
if(version == RADIOLIB_SI443X_DEVICE_VERSION) {
flagFound = true;
} else {
RADIOLIB_DEBUG_PRINTLN("Si443x not found! (%d of 10 tries) RADIOLIB_SI443X_REG_DEVICE_VERSION == 0x%02X, expected 0x0%X", i + 1, version, RADIOLIB_SI443X_DEVICE_VERSION);
_mod->hal->delay(10);
this->mod->hal->delay(10);
i++;
}
}
@ -695,12 +695,12 @@ bool Si443x::findChip() {
void Si443x::clearIRQFlags() {
uint8_t buff[2];
_mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_INTERRUPT_STATUS_1, 2, buff);
this->mod->SPIreadRegisterBurst(RADIOLIB_SI443X_REG_INTERRUPT_STATUS_1, 2, buff);
}
void Si443x::clearFIFO(size_t count) {
while(count) {
_mod->SPIreadRegister(RADIOLIB_SI443X_REG_FIFO_ACCESS);
this->mod->SPIreadRegister(RADIOLIB_SI443X_REG_FIFO_ACCESS);
count--;
}
}
@ -711,22 +711,22 @@ int16_t Si443x::config() {
RADIOLIB_ASSERT(state);
// disable POR and chip ready interrupts
_mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
this->mod->SPIwriteRegister(RADIOLIB_SI443X_REG_INTERRUPT_ENABLE_2, 0x00);
// enable AGC
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AGC_OVERRIDE_1, RADIOLIB_SI443X_AGC_GAIN_INCREASE_ON | RADIOLIB_SI443X_AGC_ON, 6, 5);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_AGC_OVERRIDE_1, RADIOLIB_SI443X_AGC_GAIN_INCREASE_ON | RADIOLIB_SI443X_AGC_ON, 6, 5);
RADIOLIB_ASSERT(state);
// disable packet header
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, RADIOLIB_SI443X_SYNC_WORD_TIMEOUT_OFF | RADIOLIB_SI443X_HEADER_LENGTH_HEADER_NONE, 7, 4);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_2, RADIOLIB_SI443X_SYNC_WORD_TIMEOUT_OFF | RADIOLIB_SI443X_HEADER_LENGTH_HEADER_NONE, 7, 4);
RADIOLIB_ASSERT(state);
// set antenna switching
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO0_CONFIG, RADIOLIB_SI443X_GPIOX_TX_STATE_OUT, 4, 0);
_mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_RX_STATE_OUT, 4, 0);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO0_CONFIG, RADIOLIB_SI443X_GPIOX_TX_STATE_OUT, 4, 0);
this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_RX_STATE_OUT, 4, 0);
// disable packet header checking
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_1, RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_NONE | RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_NONE);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_HEADER_CONTROL_1, RADIOLIB_SI443X_BROADCAST_ADDR_CHECK_NONE | RADIOLIB_SI443X_RECEIVED_HEADER_CHECK_NONE);
RADIOLIB_ASSERT(state);
return(state);
@ -734,9 +734,9 @@ int16_t Si443x::config() {
int16_t Si443x::updateClockRecovery() {
// get the parameters
uint8_t bypass = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 7, 7) >> 7;
uint8_t decRate = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 6, 4) >> 4;
uint8_t manch = _mod->SPIgetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, 1, 1) >> 1;
uint8_t bypass = this->mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 7, 7) >> 7;
uint8_t decRate = this->mod->SPIgetRegValue(RADIOLIB_SI443X_REG_IF_FILTER_BANDWIDTH, 6, 4) >> 4;
uint8_t manch = this->mod->SPIgetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_1, 1, 1) >> 1;
// calculate oversampling ratio, NCO offset and clock recovery gain
int8_t ndecExp = (int8_t)decRate - 3;
@ -747,9 +747,9 @@ int16_t Si443x::updateClockRecovery() {
ndecExp *= -1;
ndec = 1.0/(float)((uint16_t)1 << ndecExp);
}
float rxOsr = ((float)(500 * (1 + 2*bypass))) / (ndec * _br * ((float)(1 + manch)));
uint32_t ncoOff = (_br * (1 + manch) * ((uint32_t)(1) << (20 + decRate))) / (500 * (1 + 2*bypass));
uint16_t crGain = 2 + (((float)(65536.0 * (1 + manch)) * _br) / (rxOsr * (_freqDev / 0.625)));
float rxOsr = ((float)(500 * (1 + 2*bypass))) / (ndec * this->bitRate * ((float)(1 + manch)));
uint32_t ncoOff = (this->bitRate * (1 + manch) * ((uint32_t)(1) << (20 + decRate))) / (500 * (1 + 2*bypass));
uint16_t crGain = 2 + (((float)(65536.0 * (1 + manch)) * this->bitRate) / (rxOsr * (this->frequencyDev / 0.625)));
uint16_t rxOsr_fixed = (uint16_t)rxOsr;
// print that whole mess
@ -757,39 +757,39 @@ int16_t Si443x::updateClockRecovery() {
RADIOLIB_DEBUG_PRINTLN("%f\t%d\t%X\n%d\t%X\n%d\t%X", rxOsr, rxOsr_fixed, rxOsr_fixed, ncoOff, ncoOff, crGain, crGain);
// update oversampling ratio
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((rxOsr_fixed & 0x0700) >> 3), 7, 5);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((rxOsr_fixed & 0x0700) >> 3), 7, 5);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OVERSAMP_RATIO, (uint8_t)(rxOsr_fixed & 0x00FF));
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OVERSAMP_RATIO, (uint8_t)(rxOsr_fixed & 0x00FF));
RADIOLIB_ASSERT(state);
// update NCO offset
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((ncoOff & 0x0F0000) >> 16), 3, 0);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_2, (uint8_t)((ncoOff & 0x0F0000) >> 16), 3, 0);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_1, (uint8_t)((ncoOff & 0x00FF00) >> 8));
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_1, (uint8_t)((ncoOff & 0x00FF00) >> 8));
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_0, (uint8_t)(ncoOff & 0x0000FF));
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_OFFSET_0, (uint8_t)(ncoOff & 0x0000FF));
RADIOLIB_ASSERT(state);
// update clock recovery loop gain
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1, (uint8_t)((crGain & 0x0700) >> 8), 2, 0);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1, (uint8_t)((crGain & 0x0700) >> 8), 2, 0);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0, (uint8_t)(crGain & 0x00FF));
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0, (uint8_t)(crGain & 0x00FF));
RADIOLIB_ASSERT(state);
return(state);
}
int16_t Si443x::directMode() {
int16_t state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_GPIO, 5, 4);
int16_t state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_TX_DATA_SOURCE_GPIO, 5, 4);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_TX_RX_DATA_CLK_OUT, 4, 0);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO1_CONFIG, RADIOLIB_SI443X_GPIOX_TX_RX_DATA_CLK_OUT, 4, 0);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO2_CONFIG, RADIOLIB_SI443X_GPIOX_TX_DATA_IN, 4, 0);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_GPIO2_CONFIG, RADIOLIB_SI443X_GPIOX_TX_DATA_IN, 4, 0);
RADIOLIB_ASSERT(state);
state = _mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0);
state = this->mod->SPIsetRegValue(RADIOLIB_SI443X_REG_MODULATION_MODE_CONTROL_2, RADIOLIB_SI443X_MODULATION_FSK, 1, 0);
return(state);
}

913
src/modules/Si443x/Si443x.h
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