From 560ea42722905561f89935cbf2aae06027aeeed9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Grome=C5=A1?= Date: Tue, 24 Jul 2018 09:46:16 +0200 Subject: [PATCH] Increased SPI verification delay --- src/Module.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Module.cpp b/src/Module.cpp index 229ee5b7..5cc0e4c6 100644 --- a/src/Module.cpp +++ b/src/Module.cpp @@ -119,7 +119,7 @@ int16_t Module::SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb, uint8_t // some registers need a bit of time to process the change // e.g. SX127X_REG_OP_MODE - delay(5); + delay(20); // check if the write was successful uint8_t readValue = SPIreadRegister(reg);