diff --git a/_a_f_s_k_8h_source.html b/_a_f_s_k_8h_source.html index e9674452..e2a4f499 100644 --- a/_a_f_s_k_8h_source.html +++ b/_a_f_s_k_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/AFSK/AFSK.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@ - + - - + + + +
diff --git a/_a_x25_8h_source.html b/_a_x25_8h_source.html index 7d91a913..0d075fc5 100644 --- a/_a_x25_8h_source.html +++ b/_a_x25_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/AX25/AX25.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
- + - - + + + +
diff --git a/_build_opt_8h_source.html b/_build_opt_8h_source.html index 643f70d9..610022b8 100644 --- a/_build_opt_8h_source.html +++ b/_build_opt_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/BuildOpt.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
- + - - + + + +
diff --git a/_c_c1101_8h_source.html b/_c_c1101_8h_source.html index 8d6ef65a..1d59bdcc 100644 --- a/_c_c1101_8h_source.html +++ b/_c_c1101_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/CC1101/CC1101.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
- + - - + + + +
-
1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION 0x14
459 
460 // CC1101_REG_MARCSTATE
461 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
462 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
463 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
464 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
465 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
466 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
467 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
468 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
469 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
470 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
471 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
472 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
473 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
474 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
475 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
476 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
477 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
478 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
479 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
480 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
481 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
482 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
483 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
484 
485 // CC1101_REG_WORTIME1 + REG_WORTIME0
486 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
487 #define CC1101_WORTIME_LSB 0x00 // 7 0
488 
489 // CC1101_REG_PKTSTATUS
490 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
491 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
492 #define CC1101_CS 0b01000000 // 6 6 carrier sense
493 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
494 #define CC1101_CCA 0b00010000 // 4 4 channel clear
495 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
496 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
497 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
498 
504 class CC1101: public PhysicalLayer {
505  public:
506  // introduce PhysicalLayer overloads
507  using PhysicalLayer::transmit;
508  using PhysicalLayer::receive;
509  using PhysicalLayer::startTransmit;
510  using PhysicalLayer::readData;
511 
517  CC1101(Module* module);
518 
519  // basic methods
520 
538  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
539 
552  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
553 
564  int16_t receive(uint8_t* data, size_t len) override;
565 
571  int16_t standby() override;
572 
580  int16_t transmitDirect(uint32_t frf = 0) override;
581 
587  int16_t receiveDirect() override;
588 
592  int16_t packetMode();
593 
594  // interrupt methods
595 
603  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
604 
608  void clearGdo0Action();
609 
617  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
618 
622  void clearGdo2Action();
623 
636  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
637 
643  int16_t startReceive();
644 
654  int16_t readData(uint8_t* data, size_t len) override;
655 
656  // configuration methods
657 
665  int16_t setFrequency(float freq);
666 
674  int16_t setBitRate(float br);
675 
683  int16_t setRxBandwidth(float rxBw);
684 
692  int16_t setFrequencyDeviation(float freqDev) override;
693 
701  int16_t setOutputPower(int8_t power);
702 
716  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
717 
731  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
732 
740  int16_t setPreambleLength(uint8_t preambleLength);
741 
751  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
752 
758  int16_t disableAddressFiltering();
759 
767  int16_t setOOK(bool enableOOK);
768 
774  float getRSSI() const;
775 
781  uint8_t getLQI() const;
782 
790  size_t getPacketLength(bool update = true) override;
791 
799  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
800 
808  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
809 
819  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
820 
828  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
829 
837  int16_t setCrcFiltering(bool crcOn = true);
838 
846  int16_t setPromiscuousMode(bool promiscuous = true);
847 
856  int16_t setDataShaping(uint8_t sh) override;
857 
865  int16_t setEncoding(uint8_t encoding) override;
866 
875  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
876 
877 #ifndef RADIOLIB_GODMODE
878  private:
879 #endif
880  Module* _mod;
881 
882  float _freq = 0;
883  uint8_t _rawRSSI = 0;
884  uint8_t _rawLQI = 0;
885  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
886 
887  size_t _packetLength = 0;
888  bool _packetLengthQueried = false;
889  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
890 
891  bool _promiscuous = false;
892  bool _crcOn = true;
893 
894  uint8_t _syncWordLength = 2;
895  int8_t _power = 0;
896 
897  int16_t config();
898  int16_t directMode();
899  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
900  int16_t setPacketMode(uint8_t mode, uint8_t len);
901 
902  // SPI read overrides to set bit for burst write and status registers access
903  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
904  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
905  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
906  uint8_t SPIreadRegister(uint8_t reg);
907  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
908  void SPIwriteRegister(uint8_t reg, uint8_t data);
909 
910  void SPIsendCommand(uint8_t cmd);
911 };
912 
913 #endif
CC1101::packetMode
int16_t packetMode()
Stops direct mode. It is required to call this method to switch from direct transmissions to packet-b...
Definition: CC1101.cpp:185
+
1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION 0x14
459 
460 // CC1101_REG_MARCSTATE
461 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
462 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
463 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
464 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
465 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
466 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
467 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
468 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
469 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
470 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
471 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
472 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
473 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
474 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
475 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
476 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
477 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
478 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
479 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
480 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
481 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
482 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
483 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
484 
485 // CC1101_REG_WORTIME1 + REG_WORTIME0
486 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
487 #define CC1101_WORTIME_LSB 0x00 // 7 0
488 
489 // CC1101_REG_PKTSTATUS
490 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
491 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
492 #define CC1101_CS 0b01000000 // 6 6 carrier sense
493 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
494 #define CC1101_CCA 0b00010000 // 4 4 channel clear
495 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
496 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
497 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
498 
504 class CC1101: public PhysicalLayer {
505  public:
506  // introduce PhysicalLayer overloads
507  using PhysicalLayer::transmit;
508  using PhysicalLayer::receive;
509  using PhysicalLayer::startTransmit;
510  using PhysicalLayer::readData;
511 
517  CC1101(Module* module);
518 
519  // basic methods
520 
538  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
539 
552  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
553 
564  int16_t receive(uint8_t* data, size_t len) override;
565 
571  int16_t standby() override;
572 
580  int16_t transmitDirect(uint32_t frf = 0) override;
581 
587  int16_t receiveDirect() override;
588 
592  int16_t packetMode();
593 
594  // interrupt methods
595 
603  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
604 
608  void clearGdo0Action();
609 
617  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
618 
622  void clearGdo2Action();
623 
636  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
637 
643  int16_t startReceive();
644 
654  int16_t readData(uint8_t* data, size_t len) override;
655 
656  // configuration methods
657 
665  int16_t setFrequency(float freq);
666 
674  int16_t setBitRate(float br);
675 
683  int16_t setRxBandwidth(float rxBw);
684 
692  int16_t setFrequencyDeviation(float freqDev) override;
693 
701  int16_t setOutputPower(int8_t power);
702 
716  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
717 
731  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
732 
740  int16_t setPreambleLength(uint8_t preambleLength);
741 
751  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
752 
758  int16_t disableAddressFiltering();
759 
767  int16_t setOOK(bool enableOOK);
768 
774  float getRSSI() const;
775 
781  uint8_t getLQI() const;
782 
790  size_t getPacketLength(bool update = true) override;
791 
799  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
800 
808  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
809 
819  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
820 
828  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
829 
837  int16_t setCrcFiltering(bool crcOn = true);
838 
846  int16_t setPromiscuousMode(bool promiscuous = true);
847 
856  int16_t setDataShaping(uint8_t sh) override;
857 
865  int16_t setEncoding(uint8_t encoding) override;
866 
875  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
876 
877 #ifndef RADIOLIB_GODMODE
878  private:
879 #endif
880  Module* _mod;
881 
882  float _freq = 0;
883  uint8_t _rawRSSI = 0;
884  uint8_t _rawLQI = 0;
885  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
886 
887  size_t _packetLength = 0;
888  bool _packetLengthQueried = false;
889  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
890 
891  bool _promiscuous = false;
892  bool _crcOn = true;
893 
894  uint8_t _syncWordLength = 2;
895  int8_t _power = 0;
896 
897  int16_t config();
898  int16_t directMode();
899  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
900  int16_t setPacketMode(uint8_t mode, uint8_t len);
901 
902  // SPI read overrides to set bit for burst write and status registers access
903  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
904  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
905  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
906  uint8_t SPIreadRegister(uint8_t reg);
907  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
908  void SPIwriteRegister(uint8_t reg, uint8_t data);
909 
910  void SPIsendCommand(uint8_t cmd);
911 };
912 
913 #endif
CC1101::packetMode
int16_t packetMode()
Stops direct mode. It is required to call this method to switch from direct transmissions to packet-b...
Definition: CC1101.cpp:185
CC1101::begin
int16_t begin(float freq=434.0, float br=48.0, float freqDev=48.0, float rxBw=135.0, int8_t power=10, uint8_t preambleLength=16)
Initialization method.
Definition: CC1101.cpp:8
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
CC1101::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0, bool requireCarrierSense=false)
Enable sync word filtering and generation.
Definition: CC1101.cpp:632
@@ -120,9 +96,11 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
CC1101::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Allowed values are RADIOLIB_ENCODING_NRZ and RADIOLIB_ENCODING_WHITENING...
Definition: CC1101.cpp:707
CC1101::clearGdo0Action
void clearGdo0Action()
Clears interrupt service routine to call when GDO0 activates.
Definition: CC1101.cpp:196
CC1101
Control class for CC1101 module.
Definition: CC1101.h:504
+
CC1101::getLQI
uint8_t getLQI() const
Gets LQI (Link Quality Indicator) of the last received packet.
Definition: CC1101.cpp:606
CC1101::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: CC1101.cpp:555
CC1101::setGdo2Action
void setGdo2Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)
Sets interrupt service routine to call when GDO2 activates.
Definition: CC1101.cpp:200
CC1101::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 58.0 to 812.0 kHz.
Definition: CC1101.cpp:357
+
CC1101::getRSSI
float getRSSI() const
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: CC1101.cpp:596
CC1101::setOutputPower
int16_t setOutputPower(int8_t power)
Sets output power. Allowed values are -30, -20, -15, -10, 0, 5, 7 or 10 dBm.
Definition: CC1101.cpp:401
CC1101::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: CC1101.cpp:215
CC1101::standby
int16_t standby() override
Sets the module to standby mode.
Definition: CC1101.cpp:141
@@ -132,7 +110,6 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
CC1101::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data received after calling startReceive method.
Definition: CC1101.cpp:274
CC1101::clearGdo2Action
void clearGdo2Action()
Clears interrupt service routine to call when GDO0 activates.
Definition: CC1101.cpp:208
-
CC1101::getRSSI
float getRSSI() const
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: CC1101.cpp:596
CC1101::setSyncWord
int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)
Sets 16-bit sync word as a two byte value.
Definition: CC1101.cpp:502
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
CC1101::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: CC1101.cpp:98
@@ -143,7 +120,6 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
CC1101::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs=0)
Sets node and broadcast addresses. Calling this method will also enable address filtering.
Definition: CC1101.cpp:544
CC1101::CC1101
CC1101(Module *module)
Default constructor.
Definition: CC1101.cpp:4
CC1101::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Starts direct mode transmission.
Definition: CC1101.cpp:150
-
CC1101::getLQI
uint8_t getLQI() const
Gets LQI (Link Quality Indicator) of the last received packet.
Definition: CC1101.cpp:606
CC1101::setBitRate
int16_t setBitRate(float br)
Sets bit rate. Allowed values range from 0.025 to 600.0 kbps.
Definition: CC1101.cpp:340
CC1101::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: CC1101.cpp:662
CC1101::setCrcFiltering
int16_t setCrcFiltering(bool crcOn=true)
Enable CRC filtering and generation.
Definition: CC1101.cpp:652
@@ -160,7 +136,7 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
  • src
  • modules
  • CC1101
  • CC1101.h
  • Generated by - doxygen 1.8.11
    • + doxygen 1.8.13
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    1 #ifndef _RADIOLIB_MODULE_H
    2 #define _RADIOLIB_MODULE_H
    3 
    4 #include "TypeDef.h"
    5 
    6 #include <SPI.h>
    7 #ifndef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    8 #include <SoftwareSerial.h>
    9 #endif
    10 
    17 class Module {
    18  public:
    19 
    31 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    32  Module(RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, HardwareSerial* serial = &RADIOLIB_HARDWARE_SERIAL_PORT, RADIOLIB_PIN_TYPE rst = RADIOLIB_NC);
    33 #else
    34  Module(RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, HardwareSerial* serial = nullptr, RADIOLIB_PIN_TYPE rst = RADIOLIB_NC);
    35 #endif
    36 
    46  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst);
    47 
    59  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE gpio);
    60 
    74  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, SPIClass& spi, SPISettings spiSettings);
    75 
    91  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE gpio, SPIClass& spi, SPISettings spiSettings);
    92 
    112 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    113  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, SPIClass& spi = RADIOLIB_DEFAULT_SPI, SPISettings spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0), HardwareSerial* serial = &RADIOLIB_HARDWARE_SERIAL_PORT);
    114 #else
    115  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, SPIClass& spi = RADIOLIB_DEFAULT_SPI, SPISettings spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0), HardwareSerial* serial = nullptr);
    116 #endif
    117 
    123  Module(const Module& mod);
    124 
    130  Module& operator=(const Module& mod);
    131 
    132  // public member variables
    133 
    137 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    138  HardwareSerial* ModuleSerial;
    139 #else
    140  SoftwareSerial* ModuleSerial;
    141 #endif
    142 
    146  uint32_t baudrate = 9600;
    147 
    151  char AtLineFeed[3] = {'\r', '\n'};
    152 
    156  uint8_t SPIreadCommand = 0b00000000;
    157 
    161  uint8_t SPIwriteCommand = 0b10000000;
    162 
    163  // basic methods
    164 
    170  void init(uint8_t interface);
    171 
    177  void term(uint8_t interface);
    178 
    179  // AT methods
    180 
    184  void ATemptyBuffer();
    185 
    191  bool ATgetResponse();
    192 
    200  bool ATsendCommand(const char* cmd);
    201 
    211  bool ATsendData(uint8_t* data, uint32_t len);
    212 
    213  // SPI methods
    214 
    226  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
    227 
    243  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
    244 
    254  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
    255 
    263  uint8_t SPIreadRegister(uint8_t reg);
    264 
    274  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, uint8_t numBytes);
    275 
    283  void SPIwriteRegister(uint8_t reg, uint8_t data);
    284 
    298  void SPItransfer(uint8_t cmd, uint8_t reg, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes);
    299 
    300  // pin number access methods
    301 
    307  RADIOLIB_PIN_TYPE getCs() const { return(_cs); }
    308 
    314  RADIOLIB_PIN_TYPE getIrq() const { return(_irq); }
    315 
    321  RADIOLIB_PIN_TYPE getRst() const { return(_rst); }
    322 
    328  RADIOLIB_PIN_TYPE getGpio() const { return(_rx); }
    329 
    335  RADIOLIB_PIN_TYPE getRx() const { return(_rx); }
    336 
    342  RADIOLIB_PIN_TYPE getTx() const { return(_tx); }
    343 
    349  SPIClass* getSpi() const { return(_spi); }
    350 
    356  SPISettings getSpiSettings() const { return(_spiSettings); }
    357 
    366  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    367 
    375  void setRfSwitchState(RADIOLIB_PIN_STATUS rxPinState, RADIOLIB_PIN_STATUS txPinState);
    376 
    377  // Arduino core overrides
    378 
    386  static void pinMode(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_MODE mode);
    387 
    395  static void digitalWrite(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_STATUS value);
    396 
    404  static RADIOLIB_PIN_STATUS digitalRead(RADIOLIB_PIN_TYPE pin);
    405 
    413  static void tone(RADIOLIB_PIN_TYPE pin, uint16_t value);
    414 
    420  static void noTone(RADIOLIB_PIN_TYPE pin);
    421 
    431  static void attachInterrupt(RADIOLIB_PIN_TYPE interruptNum, void (*userFunc)(void), RADIOLIB_INTERRUPT_STATUS mode);
    432 
    438  static void detachInterrupt(RADIOLIB_PIN_TYPE interruptNum);
    439 
    443  static void yield();
    444 
    450  static void delay(uint32_t ms);
    451 
    457  static void delayMicroseconds(uint32_t us);
    458 
    462  static uint32_t millis();
    463 
    467  static uint32_t micros();
    468 
    469 #ifndef RADIOLIB_GODMODE
    470  private:
    471 #endif
    472  RADIOLIB_PIN_TYPE _cs = RADIOLIB_NC;
    473  RADIOLIB_PIN_TYPE _irq = RADIOLIB_NC;
    474  RADIOLIB_PIN_TYPE _rst = RADIOLIB_NC;
    475  RADIOLIB_PIN_TYPE _rx = RADIOLIB_NC;
    476  RADIOLIB_PIN_TYPE _tx = RADIOLIB_NC;
    477 
    478  SPISettings _spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0);
    479 
    480  bool _initInterface = false;
    481  SPIClass* _spi = NULL;
    482 
    483  bool _useRfSwitch = false;
    484  RADIOLIB_PIN_TYPE _rxEn = RADIOLIB_NC, _txEn = RADIOLIB_NC;
    485 
    486  uint32_t _ATtimeout = 15000;
    487 };
    488 
    489 #endif
    Module::pinMode
    static void pinMode(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_MODE mode)
    Arduino core pinMode override that checks RADIOLIB_NC as alias for unused pin.
    Definition: Module.cpp:319
    -
    Module::getTx
    RADIOLIB_PIN_TYPE getTx() const
    Access method to get the pin number of UART Rx.
    Definition: Module.h:342
    +
    1 #ifndef _RADIOLIB_MODULE_H
    2 #define _RADIOLIB_MODULE_H
    3 
    4 #include "TypeDef.h"
    5 
    6 #include <SPI.h>
    7 #ifndef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    8 #include <SoftwareSerial.h>
    9 #endif
    10 
    17 class Module {
    18  public:
    19 
    31 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    32  Module(RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, HardwareSerial* serial = &RADIOLIB_HARDWARE_SERIAL_PORT, RADIOLIB_PIN_TYPE rst = RADIOLIB_NC);
    33 #else
    34  Module(RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, HardwareSerial* serial = nullptr, RADIOLIB_PIN_TYPE rst = RADIOLIB_NC);
    35 #endif
    36 
    46  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst);
    47 
    59  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE gpio);
    60 
    74  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, SPIClass& spi, SPISettings spiSettings);
    75 
    91  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE gpio, SPIClass& spi, SPISettings spiSettings);
    92 
    112 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    113  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, SPIClass& spi = RADIOLIB_DEFAULT_SPI, SPISettings spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0), HardwareSerial* serial = &RADIOLIB_HARDWARE_SERIAL_PORT);
    114 #else
    115  Module(RADIOLIB_PIN_TYPE cs, RADIOLIB_PIN_TYPE irq, RADIOLIB_PIN_TYPE rst, RADIOLIB_PIN_TYPE rx, RADIOLIB_PIN_TYPE tx, SPIClass& spi = RADIOLIB_DEFAULT_SPI, SPISettings spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0), HardwareSerial* serial = nullptr);
    116 #endif
    117 
    123  Module(const Module& mod);
    124 
    130  Module& operator=(const Module& mod);
    131 
    132  // public member variables
    133 
    137 #ifdef RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
    138  HardwareSerial* ModuleSerial;
    139 #else
    140  SoftwareSerial* ModuleSerial;
    141 #endif
    142 
    146  uint32_t baudrate = 9600;
    147 
    151  char AtLineFeed[3] = {'\r', '\n'};
    152 
    156  uint8_t SPIreadCommand = 0b00000000;
    157 
    161  uint8_t SPIwriteCommand = 0b10000000;
    162 
    163  // basic methods
    164 
    170  void init(uint8_t interface);
    171 
    177  void term(uint8_t interface);
    178 
    179  // AT methods
    180 
    184  void ATemptyBuffer();
    185 
    191  bool ATgetResponse();
    192 
    200  bool ATsendCommand(const char* cmd);
    201 
    211  bool ATsendData(uint8_t* data, uint32_t len);
    212 
    213  // SPI methods
    214 
    226  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
    227 
    243  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
    244 
    254  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
    255 
    263  uint8_t SPIreadRegister(uint8_t reg);
    264 
    274  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, uint8_t numBytes);
    275 
    283  void SPIwriteRegister(uint8_t reg, uint8_t data);
    284 
    298  void SPItransfer(uint8_t cmd, uint8_t reg, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes);
    299 
    300  // pin number access methods
    301 
    307  RADIOLIB_PIN_TYPE getCs() const { return(_cs); }
    308 
    314  RADIOLIB_PIN_TYPE getIrq() const { return(_irq); }
    315 
    321  RADIOLIB_PIN_TYPE getRst() const { return(_rst); }
    322 
    328  RADIOLIB_PIN_TYPE getGpio() const { return(_rx); }
    329 
    335  RADIOLIB_PIN_TYPE getRx() const { return(_rx); }
    336 
    342  RADIOLIB_PIN_TYPE getTx() const { return(_tx); }
    343 
    349  SPIClass* getSpi() const { return(_spi); }
    350 
    356  SPISettings getSpiSettings() const { return(_spiSettings); }
    357 
    366  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    367 
    375  void setRfSwitchState(RADIOLIB_PIN_STATUS rxPinState, RADIOLIB_PIN_STATUS txPinState);
    376 
    377  // Arduino core overrides
    378 
    386  static void pinMode(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_MODE mode);
    387 
    395  static void digitalWrite(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_STATUS value);
    396 
    404  static RADIOLIB_PIN_STATUS digitalRead(RADIOLIB_PIN_TYPE pin);
    405 
    413  static void tone(RADIOLIB_PIN_TYPE pin, uint16_t value);
    414 
    420  static void noTone(RADIOLIB_PIN_TYPE pin);
    421 
    431  static void attachInterrupt(RADIOLIB_PIN_TYPE interruptNum, void (*userFunc)(void), RADIOLIB_INTERRUPT_STATUS mode);
    432 
    438  static void detachInterrupt(RADIOLIB_PIN_TYPE interruptNum);
    439 
    443  static void yield();
    444 
    450  static void delay(uint32_t ms);
    451 
    457  static void delayMicroseconds(uint32_t us);
    458 
    462  static uint32_t millis();
    463 
    467  static uint32_t micros();
    468 
    469 #ifndef RADIOLIB_GODMODE
    470  private:
    471 #endif
    472  RADIOLIB_PIN_TYPE _cs = RADIOLIB_NC;
    473  RADIOLIB_PIN_TYPE _irq = RADIOLIB_NC;
    474  RADIOLIB_PIN_TYPE _rst = RADIOLIB_NC;
    475  RADIOLIB_PIN_TYPE _rx = RADIOLIB_NC;
    476  RADIOLIB_PIN_TYPE _tx = RADIOLIB_NC;
    477 
    478  SPISettings _spiSettings = SPISettings(2000000, MSBFIRST, SPI_MODE0);
    479 
    480  bool _initInterface = false;
    481  SPIClass* _spi = NULL;
    482 
    483  bool _useRfSwitch = false;
    484  RADIOLIB_PIN_TYPE _rxEn = RADIOLIB_NC, _txEn = RADIOLIB_NC;
    485 
    486  uint32_t _ATtimeout = 15000;
    487 };
    488 
    489 #endif
    Module::pinMode
    static void pinMode(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_MODE mode)
    Arduino core pinMode override that checks RADIOLIB_NC as alias for unused pin.
    Definition: Module.cpp:319
    Module::AtLineFeed
    char AtLineFeed[3]
    Line feed to be used when sending AT commands. Defaults to CR+LF.
    Definition: Module.h:151
    Module::operator=
    Module & operator=(const Module &mod)
    Overload for assignment operator.
    Definition: Module.cpp:96
    +
    Module::getSpiSettings
    SPISettings getSpiSettings() const
    Access method to get the SPI interface settings.
    Definition: Module.h:356
    Module::SPIwriteRegisterBurst
    void SPIwriteRegisterBurst(uint8_t reg, uint8_t *data, uint8_t numBytes)
    SPI burst write method.
    Definition: Module.cpp:264
    Module::digitalRead
    static RADIOLIB_PIN_STATUS digitalRead(RADIOLIB_PIN_TYPE pin)
    Arduino core digitalWrite override that checks RADIOLIB_NC as alias for unused pin.
    Definition: Module.cpp:331
    +
    Module::getIrq
    RADIOLIB_PIN_TYPE getIrq() const
    Access method to get the pin number of interrupt/GPIO.
    Definition: Module.h:314
    +
    Module::getTx
    RADIOLIB_PIN_TYPE getTx() const
    Access method to get the pin number of UART Rx.
    Definition: Module.h:342
    Module::ModuleSerial
    SoftwareSerial * ModuleSerial
    Internal SoftwareSerial instance.
    Definition: Module.h:140
    Module::SPItransfer
    void SPItransfer(uint8_t cmd, uint8_t reg, uint8_t *dataOut, uint8_t *dataIn, uint8_t numBytes)
    SPI single transfer method.
    Definition: Module.cpp:272
    +
    Module::getGpio
    RADIOLIB_PIN_TYPE getGpio() const
    Access method to get the pin number of second interrupt/GPIO.
    Definition: Module.h:328
    Module::delay
    static void delay(uint32_t ms)
    Arduino core delay override.
    Definition: Module.cpp:368
    +
    Module::getRx
    RADIOLIB_PIN_TYPE getRx() const
    Access method to get the pin number of UART Rx.
    Definition: Module.h:335
    Module::yield
    static void yield()
    Arduino core yield override.
    Definition: Module.cpp:364
    Module::digitalWrite
    static void digitalWrite(RADIOLIB_PIN_TYPE pin, RADIOLIB_PIN_STATUS value)
    Arduino core digitalWrite override that checks RADIOLIB_NC as alias for unused pin.
    Definition: Module.cpp:325
    -
    Module::getRx
    RADIOLIB_PIN_TYPE getRx() const
    Access method to get the pin number of UART Rx.
    Definition: Module.h:335
    -
    Module::getIrq
    RADIOLIB_PIN_TYPE getIrq() const
    Access method to get the pin number of interrupt/GPIO.
    Definition: Module.h:314
    Module::SPIreadCommand
    uint8_t SPIreadCommand
    Basic SPI read command. Defaults to 0x00.
    Definition: Module.h:156
    Module::baudrate
    uint32_t baudrate
    Baud rate of SoftwareSerial UART communication. Defaults to 9600 baud.
    Definition: Module.h:146
    Module::term
    void term(uint8_t interface)
    Terminate low-level module control.
    Definition: Module.cpp:137
    +
    Module::getCs
    RADIOLIB_PIN_TYPE getCs() const
    Access method to get the pin number of SPI chip select.
    Definition: Module.h:307
    Module::delayMicroseconds
    static void delayMicroseconds(uint32_t us)
    Arduino core delayMicroseconds override.
    Definition: Module.cpp:372
    -
    Module::getGpio
    RADIOLIB_PIN_TYPE getGpio() const
    Access method to get the pin number of second interrupt/GPIO.
    Definition: Module.h:328
    Module::init
    void init(uint8_t interface)
    Initialize low-level module control.
    Definition: Module.cpp:113
    Module::ATemptyBuffer
    void ATemptyBuffer()
    Empty internal AT buffer.
    Definition: Module.cpp:152
    Module::tone
    static void tone(RADIOLIB_PIN_TYPE pin, uint16_t value)
    Arduino core tone override that checks RADIOLIB_NC as alias for unused pin and RADIOLIB_TONE_UNSUPPOR...
    Definition: Module.cpp:338
    Module::setRfSwitchState
    void setRfSwitchState(RADIOLIB_PIN_STATUS rxPinState, RADIOLIB_PIN_STATUS txPinState)
    Set RF switch state.
    Definition: Module.cpp:392
    Module::ATgetResponse
    bool ATgetResponse()
    Get response after sending AT command.
    Definition: Module.cpp:175
    -
    Module::getRst
    RADIOLIB_PIN_TYPE getRst() const
    Access method to get the pin number of hardware reset pin.
    Definition: Module.h:321
    Module
    Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
    Definition: Module.h:17
    -
    Module::getSpiSettings
    SPISettings getSpiSettings() const
    Access method to get the SPI interface settings.
    Definition: Module.h:356
    Module::ATsendData
    bool ATsendData(uint8_t *data, uint32_t len)
    Send raw AT data. Will also call ATgetResponse.
    Definition: Module.cpp:165
    Module::SPIgetRegValue
    int16_t SPIgetRegValue(uint8_t reg, uint8_t msb=7, uint8_t lsb=0)
    SPI read method that automatically masks unused bits. This method is the preferred SPI read mechanism...
    Definition: Module.cpp:199
    Module::millis
    static uint32_t millis()
    Arduino core millis override.
    Definition: Module.cpp:376
    -
    Module::getCs
    RADIOLIB_PIN_TYPE getCs() const
    Access method to get the pin number of SPI chip select.
    Definition: Module.h:307
    Module::SPIwriteRegister
    void SPIwriteRegister(uint8_t reg, uint8_t data)
    SPI basic write method. Use of this method is reserved for special cases, SPIsetRegValue should be us...
    Definition: Module.cpp:268
    Module::SPIreadRegister
    uint8_t SPIreadRegister(uint8_t reg)
    SPI basic read method. Use of this method is reserved for special cases, SPIgetRegValue should be use...
    Definition: Module.cpp:258
    Module::noTone
    static void noTone(RADIOLIB_PIN_TYPE pin)
    Arduino core noTone override that checks RADIOLIB_NC as alias for unused pin and RADIOLIB_TONE_UNSUPP...
    Definition: Module.cpp:347
    @@ -147,7 +122,8 @@ $(document).ready(function(){initNavTree('_module_8h_source.html','');});
    Module::attachInterrupt
    static void attachInterrupt(RADIOLIB_PIN_TYPE interruptNum, void(*userFunc)(void), RADIOLIB_INTERRUPT_STATUS mode)
    Arduino core attachInterrupt override.
    Definition: Module.cpp:356
    Module::SPIwriteCommand
    uint8_t SPIwriteCommand
    Basic SPI write command. Defaults to 0x80.
    Definition: Module.h:161
    Module::SPIreadRegisterBurst
    void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t *inBytes)
    SPI burst read method.
    Definition: Module.cpp:254
    -
    Module::getSpi
    SPIClass * getSpi() const
    Access method to get the SPI interface.
    Definition: Module.h:349
    +
    Module::getRst
    RADIOLIB_PIN_TYPE getRst() const
    Access method to get the pin number of hardware reset pin.
    Definition: Module.h:321
    +
    Module::getSpi
    SPIClass * getSpi() const
    Access method to get the SPI interface.
    Definition: Module.h:349
    Module::SPIsetRegValue
    int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb=7, uint8_t lsb=0, uint8_t checkInterval=2)
    Overwrite-safe SPI write method with verification. This method is the preferred SPI write mechanism...
    Definition: Module.cpp:209
    Module::micros
    static uint32_t micros()
    Arduino core micros override.
    Definition: Module.cpp:380
    Module::setRfSwitchPins
    void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
    Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
    Definition: Module.cpp:384
    @@ -159,7 +135,7 @@ $(document).ready(function(){initNavTree('_module_8h_source.html','');});
  • src
  • Module.h
  • Generated by - doxygen 1.8.11
    • + doxygen 1.8.13
    diff --git a/_morse_8h_source.html b/_morse_8h_source.html index d1d1c008..d032ddcf 100644 --- a/_morse_8h_source.html +++ b/_morse_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/Morse/Morse.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_physical_layer_8h_source.html b/_physical_layer_8h_source.html index adb6dc0d..83219700 100644 --- a/_physical_layer_8h_source.html +++ b/_physical_layer_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/PhysicalLayer/PhysicalLayer.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    -
    1 #ifndef _RADIOLIB_PHYSICAL_LAYER_H
    2 #define _RADIOLIB_PHYSICAL_LAYER_H
    3 
    4 #include "../../TypeDef.h"
    5 
    13 class PhysicalLayer {
    14  public:
    15 
    16  // constructor
    17 
    25  PhysicalLayer(float freqStep, size_t maxPacketLength);
    26 
    27  // basic methods
    28 
    38  int16_t transmit(__FlashStringHelper* fstr, uint8_t addr = 0);
    39 
    49  int16_t transmit(String& str, uint8_t addr = 0);
    50 
    60  int16_t transmit(const char* str, uint8_t addr = 0);
    61 
    73  virtual int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
    74 
    84  int16_t receive(String& str, size_t len = 0);
    85 
    91  virtual int16_t standby() = 0;
    92 
    102  virtual int16_t receive(uint8_t* data, size_t len) = 0;
    103 
    114  int16_t startTransmit(String& str, uint8_t addr = 0);
    115 
    126  int16_t startTransmit(const char* str, uint8_t addr = 0);
    127 
    139  virtual int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
    140 
    150  int16_t readData(String& str, size_t len = 0);
    151 
    161  virtual int16_t readData(uint8_t* data, size_t len) = 0;
    162 
    171  virtual int16_t transmitDirect(uint32_t frf = 0) = 0;
    172 
    179  virtual int16_t receiveDirect() = 0;
    180 
    181  // configuration methods
    182 
    191  virtual int16_t setFrequencyDeviation(float freqDev) = 0;
    192 
    200  virtual int16_t setDataShaping(uint8_t sh) = 0;
    201 
    209  virtual int16_t setEncoding(uint8_t encoding) = 0;
    210 
    216  float getFreqStep() const;
    217 
    225  virtual size_t getPacketLength(bool update = true) = 0;
    226 
    227 #ifndef RADIOLIB_GODMODE
    228  private:
    229 #endif
    230  float _freqStep;
    231  size_t _maxPacketLength;
    232 };
    233 
    234 #endif
    PhysicalLayer::setEncoding
    virtual int16_t setEncoding(uint8_t encoding)=0
    Sets FSK data encoding. Only available in FSK mode. Must be implemented in module class...
    -
    PhysicalLayer::getFreqStep
    float getFreqStep() const
    Gets the module frequency step size that was set in constructor.
    Definition: PhysicalLayer.cpp:143
    +
    1 #ifndef _RADIOLIB_PHYSICAL_LAYER_H
    2 #define _RADIOLIB_PHYSICAL_LAYER_H
    3 
    4 #include "../../TypeDef.h"
    5 
    13 class PhysicalLayer {
    14  public:
    15 
    16  // constructor
    17 
    25  PhysicalLayer(float freqStep, size_t maxPacketLength);
    26 
    27  // basic methods
    28 
    38  int16_t transmit(__FlashStringHelper* fstr, uint8_t addr = 0);
    39 
    49  int16_t transmit(String& str, uint8_t addr = 0);
    50 
    60  int16_t transmit(const char* str, uint8_t addr = 0);
    61 
    73  virtual int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
    74 
    84  int16_t receive(String& str, size_t len = 0);
    85 
    91  virtual int16_t standby() = 0;
    92 
    102  virtual int16_t receive(uint8_t* data, size_t len) = 0;
    103 
    114  int16_t startTransmit(String& str, uint8_t addr = 0);
    115 
    126  int16_t startTransmit(const char* str, uint8_t addr = 0);
    127 
    139  virtual int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
    140 
    150  int16_t readData(String& str, size_t len = 0);
    151 
    161  virtual int16_t readData(uint8_t* data, size_t len) = 0;
    162 
    171  virtual int16_t transmitDirect(uint32_t frf = 0) = 0;
    172 
    179  virtual int16_t receiveDirect() = 0;
    180 
    181  // configuration methods
    182 
    191  virtual int16_t setFrequencyDeviation(float freqDev) = 0;
    192 
    200  virtual int16_t setDataShaping(uint8_t sh) = 0;
    201 
    209  virtual int16_t setEncoding(uint8_t encoding) = 0;
    210 
    216  float getFreqStep() const;
    217 
    225  virtual size_t getPacketLength(bool update = true) = 0;
    226 
    227 #ifndef RADIOLIB_GODMODE
    228  private:
    229 #endif
    230  float _freqStep;
    231  size_t _maxPacketLength;
    232 };
    233 
    234 #endif
    PhysicalLayer::setEncoding
    virtual int16_t setEncoding(uint8_t encoding)=0
    Sets FSK data encoding. Only available in FSK mode. Must be implemented in module class...
    +
    PhysicalLayer::getFreqStep
    float getFreqStep() const
    Gets the module frequency step size that was set in constructor.
    Definition: PhysicalLayer.cpp:143
    PhysicalLayer::startTransmit
    int16_t startTransmit(String &str, uint8_t addr=0)
    Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
    Definition: PhysicalLayer.cpp:49
    PhysicalLayer::getPacketLength
    virtual size_t getPacketLength(bool update=true)=0
    Query modem for the packet length of received payload.
    PhysicalLayer::transmitDirect
    virtual int16_t transmitDirect(uint32_t frf=0)=0
    Enables direct transmission mode on pins DIO1 (clock) and DIO2 (data). Must be implemented in module ...
    @@ -130,7 +106,7 @@ $(document).ready(function(){initNavTree('_physical_layer_8h_source.html','');})
  • src
  • protocols
  • PhysicalLayer
  • PhysicalLayer.h
  • Generated by - doxygen 1.8.11
    • + doxygen 1.8.13
    diff --git a/_r_f69_8h_source.html b/_r_f69_8h_source.html index 93a00bcd..e9a09135 100644 --- a/_r_f69_8h_source.html +++ b/_r_f69_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RF69/RF69.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_f_m22_8h_source.html b/_r_f_m22_8h_source.html index 0af01f47..86a5199a 100644 --- a/_r_f_m22_8h_source.html +++ b/_r_f_m22_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RFM2x/RFM22.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_f_m23_8h_source.html b/_r_f_m23_8h_source.html index 2ecc1c20..40dd86bf 100644 --- a/_r_f_m23_8h_source.html +++ b/_r_f_m23_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RFM2x/RFM23.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_f_m95_8h_source.html b/_r_f_m95_8h_source.html index db93ca8e..1c3a9061 100644 --- a/_r_f_m95_8h_source.html +++ b/_r_f_m95_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RFM9x/RFM95.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_f_m96_8h_source.html b/_r_f_m96_8h_source.html index a8da4b66..b2faa4fd 100644 --- a/_r_f_m96_8h_source.html +++ b/_r_f_m96_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RFM9x/RFM96.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_f_m97_8h_source.html b/_r_f_m97_8h_source.html index 7f3ec7ef..15e557db 100644 --- a/_r_f_m97_8h_source.html +++ b/_r_f_m97_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/RFM9x/RFM97.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_r_t_t_y_8h_source.html b/_r_t_t_y_8h_source.html index c75e8b1e..b4e5f670 100644 --- a/_r_t_t_y_8h_source.html +++ b/_r_t_t_y_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/RTTY/RTTY.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_radio_lib_8h_source.html b/_radio_lib_8h_source.html index 56318ff6..80183fd7 100644 --- a/_radio_lib_8h_source.html +++ b/_radio_lib_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/RadioLib.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_s_t_v_8h_source.html b/_s_s_t_v_8h_source.html index af9e24d0..81a3f575 100644 --- a/_s_s_t_v_8h_source.html +++ b/_s_s_t_v_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/protocols/SSTV/SSTV.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x1231_8h_source.html b/_s_x1231_8h_source.html index 8cee39a1..74345cbc 100644 --- a/_s_x1231_8h_source.html +++ b/_s_x1231_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX1231/SX1231.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x1261_8h_source.html b/_s_x1261_8h_source.html index 8aa6a8b5..e714d901 100644 --- a/_s_x1261_8h_source.html +++ b/_s_x1261_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX126x/SX1261.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x1262_8h_source.html b/_s_x1262_8h_source.html index a1566dbf..af4be649 100644 --- a/_s_x1262_8h_source.html +++ b/_s_x1262_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX126x/SX1262.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x1268_8h_source.html b/_s_x1268_8h_source.html index efcd9c63..dd4ee793 100644 --- a/_s_x1268_8h_source.html +++ b/_s_x1268_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX126x/SX1268.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x126x_8h_source.html b/_s_x126x_8h_source.html index d0008908..d1e37717 100644 --- a/_s_x126x_8h_source.html +++ b/_s_x126x_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX126x/SX126x.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    -
    1 #if !defined(_RADIOLIB_SX126X_H)
    2 #define _RADIOLIB_SX126X_H
    3 
    4 #include "../../TypeDef.h"
    5 
    6 #if !defined(RADIOLIB_EXCLUDE_SX126X)
    7 
    8 #include "../../Module.h"
    9 
    10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
    11 
    12 // SX126X physical layer properties
    13 #define SX126X_FREQUENCY_STEP_SIZE 0.9536743164
    14 #define SX126X_MAX_PACKET_LENGTH 255
    15 #define SX126X_CRYSTAL_FREQ 32.0
    16 #define SX126X_DIV_EXPONENT 25
    17 
    18 // SX126X SPI commands
    19 // operational modes commands
    20 #define SX126X_CMD_NOP 0x00
    21 #define SX126X_CMD_SET_SLEEP 0x84
    22 #define SX126X_CMD_SET_STANDBY 0x80
    23 #define SX126X_CMD_SET_FS 0xC1
    24 #define SX126X_CMD_SET_TX 0x83
    25 #define SX126X_CMD_SET_RX 0x82
    26 #define SX126X_CMD_STOP_TIMER_ON_PREAMBLE 0x9F
    27 #define SX126X_CMD_SET_RX_DUTY_CYCLE 0x94
    28 #define SX126X_CMD_SET_CAD 0xC5
    29 #define SX126X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
    30 #define SX126X_CMD_SET_TX_INFINITE_PREAMBLE 0xD2
    31 #define SX126X_CMD_SET_REGULATOR_MODE 0x96
    32 #define SX126X_CMD_CALIBRATE 0x89
    33 #define SX126X_CMD_CALIBRATE_IMAGE 0x98
    34 #define SX126X_CMD_SET_PA_CONFIG 0x95
    35 #define SX126X_CMD_SET_RX_TX_FALLBACK_MODE 0x93
    36 
    37 // register and buffer access commands
    38 #define SX126X_CMD_WRITE_REGISTER 0x0D
    39 #define SX126X_CMD_READ_REGISTER 0x1D
    40 #define SX126X_CMD_WRITE_BUFFER 0x0E
    41 #define SX126X_CMD_READ_BUFFER 0x1E
    42 
    43 // DIO and IRQ control
    44 #define SX126X_CMD_SET_DIO_IRQ_PARAMS 0x08
    45 #define SX126X_CMD_GET_IRQ_STATUS 0x12
    46 #define SX126X_CMD_CLEAR_IRQ_STATUS 0x02
    47 #define SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL 0x9D
    48 #define SX126X_CMD_SET_DIO3_AS_TCXO_CTRL 0x97
    49 
    50 // RF, modulation and packet commands
    51 #define SX126X_CMD_SET_RF_FREQUENCY 0x86
    52 #define SX126X_CMD_SET_PACKET_TYPE 0x8A
    53 #define SX126X_CMD_GET_PACKET_TYPE 0x11
    54 #define SX126X_CMD_SET_TX_PARAMS 0x8E
    55 #define SX126X_CMD_SET_MODULATION_PARAMS 0x8B
    56 #define SX126X_CMD_SET_PACKET_PARAMS 0x8C
    57 #define SX126X_CMD_SET_CAD_PARAMS 0x88
    58 #define SX126X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
    59 #define SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT 0x0A
    60 
    61 // status commands
    62 #define SX126X_CMD_GET_STATUS 0xC0
    63 #define SX126X_CMD_GET_RSSI_INST 0x15
    64 #define SX126X_CMD_GET_RX_BUFFER_STATUS 0x13
    65 #define SX126X_CMD_GET_PACKET_STATUS 0x14
    66 #define SX126X_CMD_GET_DEVICE_ERRORS 0x17
    67 #define SX126X_CMD_CLEAR_DEVICE_ERRORS 0x07
    68 #define SX126X_CMD_GET_STATS 0x10
    69 #define SX126X_CMD_RESET_STATS 0x00
    70 
    71 
    72 // SX126X register map
    73 #define SX126X_REG_WHITENING_INITIAL_MSB 0x06B8
    74 #define SX126X_REG_WHITENING_INITIAL_LSB 0x06B9
    75 #define SX126X_REG_CRC_INITIAL_MSB 0x06BC
    76 #define SX126X_REG_CRC_INITIAL_LSB 0x06BD
    77 #define SX126X_REG_CRC_POLYNOMIAL_MSB 0x06BE
    78 #define SX126X_REG_CRC_POLYNOMIAL_LSB 0x06BF
    79 #define SX126X_REG_SYNC_WORD_0 0x06C0
    80 #define SX126X_REG_SYNC_WORD_1 0x06C1
    81 #define SX126X_REG_SYNC_WORD_2 0x06C2
    82 #define SX126X_REG_SYNC_WORD_3 0x06C3
    83 #define SX126X_REG_SYNC_WORD_4 0x06C4
    84 #define SX126X_REG_SYNC_WORD_5 0x06C5
    85 #define SX126X_REG_SYNC_WORD_6 0x06C6
    86 #define SX126X_REG_SYNC_WORD_7 0x06C7
    87 #define SX126X_REG_NODE_ADDRESS 0x06CD
    88 #define SX126X_REG_BROADCAST_ADDRESS 0x06CE
    89 #define SX126X_REG_LORA_SYNC_WORD_MSB 0x0740
    90 #define SX126X_REG_LORA_SYNC_WORD_LSB 0x0741
    91 #define SX126X_REG_RANDOM_NUMBER_0 0x0819
    92 #define SX126X_REG_RANDOM_NUMBER_1 0x081A
    93 #define SX126X_REG_RANDOM_NUMBER_2 0x081B
    94 #define SX126X_REG_RANDOM_NUMBER_3 0x081C
    95 #define SX126X_REG_RX_GAIN 0x08AC
    96 #define SX126X_REG_OCP_CONFIGURATION 0x08E7
    97 #define SX126X_REG_XTA_TRIM 0x0911
    98 #define SX126X_REG_XTB_TRIM 0x0912
    99 
    100 // undocumented registers
    101 #define SX126X_REG_SENSITIVITY_CONFIG 0x0889 // SX1268 datasheet v1.1, section 15.1
    102 #define SX126X_REG_TX_CLAMP_CONFIG 0x08D8 // SX1268 datasheet v1.1, section 15.2
    103 #define SX126X_REG_RTC_STOP 0x0920 // SX1268 datasheet v1.1, section 15.3
    104 #define SX126X_REG_RTC_EVENT 0x0944 // SX1268 datasheet v1.1, section 15.3
    105 #define SX126X_REG_IQ_CONFIG 0x0736 // SX1268 datasheet v1.1, section 15.4
    106 #define SX126X_REG_RX_GAIN_RETENTION_0 0x029F // SX1268 datasheet v1.1, section 9.6
    107 #define SX126X_REG_RX_GAIN_RETENTION_1 0x02A0 // SX1268 datasheet v1.1, section 9.6
    108 #define SX126X_REG_RX_GAIN_RETENTION_2 0x02A1 // SX1268 datasheet v1.1, section 9.6
    109 
    110 
    111 // SX126X SPI command variables
    112 //SX126X_CMD_SET_SLEEP MSB LSB DESCRIPTION
    113 #define SX126X_SLEEP_START_COLD 0b00000000 // 2 2 sleep mode: cold start, configuration is lost (default)
    114 #define SX126X_SLEEP_START_WARM 0b00000100 // 2 2 warm start, configuration is retained
    115 #define SX126X_SLEEP_RTC_OFF 0b00000000 // 0 0 wake on RTC timeout: disabled
    116 #define SX126X_SLEEP_RTC_ON 0b00000001 // 0 0 enabled
    117 
    118 //SX126X_CMD_SET_STANDBY
    119 #define SX126X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
    120 #define SX126X_STANDBY_XOSC 0x01 // 7 0 32 MHz crystal oscillator
    121 
    122 //SX126X_CMD_SET_RX
    123 #define SX126X_RX_TIMEOUT_NONE 0x000000 // 23 0 Rx timeout duration: no timeout (Rx single mode)
    124 #define SX126X_RX_TIMEOUT_INF 0xFFFFFF // 23 0 infinite (Rx continuous mode)
    125 
    126 //SX126X_CMD_SET_TX
    127 #define SX126X_TX_TIMEOUT_NONE 0x000000 // 23 0 Tx timeout duration: no timeout (Tx single mode)
    128 
    129 //SX126X_CMD_STOP_TIMER_ON_PREAMBLE
    130 #define SX126X_STOP_ON_PREAMBLE_OFF 0x00 // 7 0 stop timer on: sync word or header (default)
    131 #define SX126X_STOP_ON_PREAMBLE_ON 0x01 // 7 0 preamble detection
    132 
    133 //SX126X_CMD_SET_REGULATOR_MODE
    134 #define SX126X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
    135 #define SX126X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
    136 
    137 //SX126X_CMD_CALIBRATE
    138 #define SX126X_CALIBRATE_IMAGE_OFF 0b00000000 // 6 6 image calibration: disabled
    139 #define SX126X_CALIBRATE_IMAGE_ON 0b01000000 // 6 6 enabled
    140 #define SX126X_CALIBRATE_ADC_BULK_P_OFF 0b00000000 // 5 5 ADC bulk P calibration: disabled
    141 #define SX126X_CALIBRATE_ADC_BULK_P_ON 0b00100000 // 5 5 enabled
    142 #define SX126X_CALIBRATE_ADC_BULK_N_OFF 0b00000000 // 4 4 ADC bulk N calibration: disabled
    143 #define SX126X_CALIBRATE_ADC_BULK_N_ON 0b00010000 // 4 4 enabled
    144 #define SX126X_CALIBRATE_ADC_PULSE_OFF 0b00000000 // 3 3 ADC pulse calibration: disabled
    145 #define SX126X_CALIBRATE_ADC_PULSE_ON 0b00001000 // 3 3 enabled
    146 #define SX126X_CALIBRATE_PLL_OFF 0b00000000 // 2 2 PLL calibration: disabled
    147 #define SX126X_CALIBRATE_PLL_ON 0b00000100 // 2 2 enabled
    148 #define SX126X_CALIBRATE_RC13M_OFF 0b00000000 // 1 1 13 MHz RC osc. calibration: disabled
    149 #define SX126X_CALIBRATE_RC13M_ON 0b00000010 // 1 1 enabled
    150 #define SX126X_CALIBRATE_RC64K_OFF 0b00000000 // 0 0 64 kHz RC osc. calibration: disabled
    151 #define SX126X_CALIBRATE_RC64K_ON 0b00000001 // 0 0 enabled
    152 #define SX126X_CALIBRATE_ALL 0b01111111 // 6 0 calibrate all blocks
    153 
    154 //SX126X_CMD_CALIBRATE_IMAGE
    155 #define SX126X_CAL_IMG_430_MHZ_1 0x6B
    156 #define SX126X_CAL_IMG_430_MHZ_2 0x6F
    157 #define SX126X_CAL_IMG_470_MHZ_1 0x75
    158 #define SX126X_CAL_IMG_470_MHZ_2 0x81
    159 #define SX126X_CAL_IMG_779_MHZ_1 0xC1
    160 #define SX126X_CAL_IMG_779_MHZ_2 0xC5
    161 #define SX126X_CAL_IMG_863_MHZ_1 0xD7
    162 #define SX126X_CAL_IMG_863_MHZ_2 0xDB
    163 #define SX126X_CAL_IMG_902_MHZ_1 0xE1
    164 #define SX126X_CAL_IMG_902_MHZ_2 0xE9
    165 
    166 //SX126X_CMD_SET_PA_CONFIG
    167 #define SX126X_PA_CONFIG_HP_MAX 0x07
    168 #define SX126X_PA_CONFIG_PA_LUT 0x01
    169 #define SX126X_PA_CONFIG_SX1262_8 0x00
    170 
    171 //SX126X_CMD_SET_RX_TX_FALLBACK_MODE
    172 #define SX126X_RX_TX_FALLBACK_MODE_FS 0x40 // 7 0 after Rx/Tx go to: FS mode
    173 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_XOSC 0x30 // 7 0 standby with crystal oscillator
    174 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_RC 0x20 // 7 0 standby with RC oscillator (default)
    175 
    176 //SX126X_CMD_SET_DIO_IRQ_PARAMS
    177 #define SX126X_IRQ_TIMEOUT 0b1000000000 // 9 9 Rx or Tx timeout
    178 #define SX126X_IRQ_CAD_DETECTED 0b0100000000 // 8 8 channel activity detected
    179 #define SX126X_IRQ_CAD_DONE 0b0010000000 // 7 7 channel activity detection finished
    180 #define SX126X_IRQ_CRC_ERR 0b0001000000 // 6 6 wrong CRC received
    181 #define SX126X_IRQ_HEADER_ERR 0b0000100000 // 5 5 LoRa header CRC error
    182 #define SX126X_IRQ_HEADER_VALID 0b0000010000 // 4 4 valid LoRa header received
    183 #define SX126X_IRQ_SYNC_WORD_VALID 0b0000001000 // 3 3 valid sync word detected
    184 #define SX126X_IRQ_PREAMBLE_DETECTED 0b0000000100 // 2 2 preamble detected
    185 #define SX126X_IRQ_RX_DONE 0b0000000010 // 1 1 packet received
    186 #define SX126X_IRQ_TX_DONE 0b0000000001 // 0 0 packet transmission completed
    187 #define SX126X_IRQ_ALL 0b1111111111 // 9 0 all interrupts
    188 #define SX126X_IRQ_NONE 0b0000000000 // 9 0 no interrupts
    189 
    190 //SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL
    191 #define SX126X_DIO2_AS_IRQ 0x00 // 7 0 DIO2 configuration: IRQ
    192 #define SX126X_DIO2_AS_RF_SWITCH 0x01 // 7 0 RF switch control
    193 
    194 //SX126X_CMD_SET_DIO3_AS_TCXO_CTRL
    195 #define SX126X_DIO3_OUTPUT_1_6 0x00 // 7 0 DIO3 voltage output for TCXO: 1.6 V
    196 #define SX126X_DIO3_OUTPUT_1_7 0x01 // 7 0 1.7 V
    197 #define SX126X_DIO3_OUTPUT_1_8 0x02 // 7 0 1.8 V
    198 #define SX126X_DIO3_OUTPUT_2_2 0x03 // 7 0 2.2 V
    199 #define SX126X_DIO3_OUTPUT_2_4 0x04 // 7 0 2.4 V
    200 #define SX126X_DIO3_OUTPUT_2_7 0x05 // 7 0 2.7 V
    201 #define SX126X_DIO3_OUTPUT_3_0 0x06 // 7 0 3.0 V
    202 #define SX126X_DIO3_OUTPUT_3_3 0x07 // 7 0 3.3 V
    203 
    204 //SX126X_CMD_SET_PACKET_TYPE
    205 #define SX126X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: GFSK
    206 #define SX126X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
    207 
    208 //SX126X_CMD_SET_TX_PARAMS
    209 #define SX126X_PA_RAMP_10U 0x00 // 7 0 ramp time: 10 us
    210 #define SX126X_PA_RAMP_20U 0x01 // 7 0 20 us
    211 #define SX126X_PA_RAMP_40U 0x02 // 7 0 40 us
    212 #define SX126X_PA_RAMP_80U 0x03 // 7 0 80 us
    213 #define SX126X_PA_RAMP_200U 0x04 // 7 0 200 us
    214 #define SX126X_PA_RAMP_800U 0x05 // 7 0 800 us
    215 #define SX126X_PA_RAMP_1700U 0x06 // 7 0 1700 us
    216 #define SX126X_PA_RAMP_3400U 0x07 // 7 0 3400 us
    217 
    218 //SX126X_CMD_SET_MODULATION_PARAMS
    219 #define SX126X_GFSK_FILTER_NONE 0x00 // 7 0 GFSK filter: none
    220 #define SX126X_GFSK_FILTER_GAUSS_0_3 0x08 // 7 0 Gaussian, BT = 0.3
    221 #define SX126X_GFSK_FILTER_GAUSS_0_5 0x09 // 7 0 Gaussian, BT = 0.5
    222 #define SX126X_GFSK_FILTER_GAUSS_0_7 0x0A // 7 0 Gaussian, BT = 0.7
    223 #define SX126X_GFSK_FILTER_GAUSS_1 0x0B // 7 0 Gaussian, BT = 1
    224 #define SX126X_GFSK_RX_BW_4_8 0x1F // 7 0 GFSK Rx bandwidth: 4.8 kHz
    225 #define SX126X_GFSK_RX_BW_5_8 0x17 // 7 0 5.8 kHz
    226 #define SX126X_GFSK_RX_BW_7_3 0x0F // 7 0 7.3 kHz
    227 #define SX126X_GFSK_RX_BW_9_7 0x1E // 7 0 9.7 kHz
    228 #define SX126X_GFSK_RX_BW_11_7 0x16 // 7 0 11.7 kHz
    229 #define SX126X_GFSK_RX_BW_14_6 0x0E // 7 0 14.6 kHz
    230 #define SX126X_GFSK_RX_BW_19_5 0x1D // 7 0 19.5 kHz
    231 #define SX126X_GFSK_RX_BW_23_4 0x15 // 7 0 23.4 kHz
    232 #define SX126X_GFSK_RX_BW_29_3 0x0D // 7 0 29.3 kHz
    233 #define SX126X_GFSK_RX_BW_39_0 0x1C // 7 0 39.0 kHz
    234 #define SX126X_GFSK_RX_BW_46_9 0x14 // 7 0 46.9 kHz
    235 #define SX126X_GFSK_RX_BW_58_6 0x0C // 7 0 58.6 kHz
    236 #define SX126X_GFSK_RX_BW_78_2 0x1B // 7 0 78.2 kHz
    237 #define SX126X_GFSK_RX_BW_93_8 0x13 // 7 0 93.8 kHz
    238 #define SX126X_GFSK_RX_BW_117_3 0x0B // 7 0 117.3 kHz
    239 #define SX126X_GFSK_RX_BW_156_2 0x1A // 7 0 156.2 kHz
    240 #define SX126X_GFSK_RX_BW_187_2 0x12 // 7 0 187.2 kHz
    241 #define SX126X_GFSK_RX_BW_234_3 0x0A // 7 0 234.3 kHz
    242 #define SX126X_GFSK_RX_BW_312_0 0x19 // 7 0 312.0 kHz
    243 #define SX126X_GFSK_RX_BW_373_6 0x11 // 7 0 373.6 kHz
    244 #define SX126X_GFSK_RX_BW_467_0 0x09 // 7 0 467.0 kHz
    245 #define SX126X_LORA_BW_7_8 0x00 // 7 0 LoRa bandwidth: 7.8 kHz
    246 #define SX126X_LORA_BW_10_4 0x08 // 7 0 10.4 kHz
    247 #define SX126X_LORA_BW_15_6 0x01 // 7 0 15.6 kHz
    248 #define SX126X_LORA_BW_20_8 0x09 // 7 0 20.8 kHz
    249 #define SX126X_LORA_BW_31_25 0x02 // 7 0 31.25 kHz
    250 #define SX126X_LORA_BW_41_7 0x0A // 7 0 41.7 kHz
    251 #define SX126X_LORA_BW_62_5 0x03 // 7 0 62.5 kHz
    252 #define SX126X_LORA_BW_125_0 0x04 // 7 0 125.0 kHz
    253 #define SX126X_LORA_BW_250_0 0x05 // 7 0 250.0 kHz
    254 #define SX126X_LORA_BW_500_0 0x06 // 7 0 500.0 kHz
    255 #define SX126X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
    256 #define SX126X_LORA_CR_4_6 0x02 // 7 0 4/6
    257 #define SX126X_LORA_CR_4_7 0x03 // 7 0 4/7
    258 #define SX126X_LORA_CR_4_8 0x04 // 7 0 4/8
    259 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_OFF 0x00 // 7 0 LoRa low data rate optimization: disabled
    260 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_ON 0x01 // 7 0 enabled
    261 
    262 //SX126X_CMD_SET_PACKET_PARAMS
    263 #define SX126X_GFSK_PREAMBLE_DETECT_OFF 0x00 // 7 0 GFSK minimum preamble length before reception starts: detector disabled
    264 #define SX126X_GFSK_PREAMBLE_DETECT_8 0x04 // 7 0 8 bits
    265 #define SX126X_GFSK_PREAMBLE_DETECT_16 0x05 // 7 0 16 bits
    266 #define SX126X_GFSK_PREAMBLE_DETECT_24 0x06 // 7 0 24 bits
    267 #define SX126X_GFSK_PREAMBLE_DETECT_32 0x07 // 7 0 32 bits
    268 #define SX126X_GFSK_ADDRESS_FILT_OFF 0x00 // 7 0 GFSK address filtering: disabled
    269 #define SX126X_GFSK_ADDRESS_FILT_NODE 0x01 // 7 0 node only
    270 #define SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST 0x02 // 7 0 node and broadcast
    271 #define SX126X_GFSK_PACKET_FIXED 0x00 // 7 0 GFSK packet type: fixed (payload length known in advance to both sides)
    272 #define SX126X_GFSK_PACKET_VARIABLE 0x01 // 7 0 variable (payload length added to packet)
    273 #define SX126X_GFSK_CRC_OFF 0x01 // 7 0 GFSK packet CRC: disabled
    274 #define SX126X_GFSK_CRC_1_BYTE 0x00 // 7 0 1 byte
    275 #define SX126X_GFSK_CRC_2_BYTE 0x02 // 7 0 2 byte
    276 #define SX126X_GFSK_CRC_1_BYTE_INV 0x04 // 7 0 1 byte, inverted
    277 #define SX126X_GFSK_CRC_2_BYTE_INV 0x06 // 7 0 2 byte, inverted
    278 #define SX126X_GFSK_WHITENING_OFF 0x00 // 7 0 GFSK data whitening: disabled
    279 #define SX126X_GFSK_WHITENING_ON 0x01 // 7 0 enabled
    280 #define SX126X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
    281 #define SX126X_LORA_HEADER_IMPLICIT 0x01 // 7 0 implicit
    282 #define SX126X_LORA_CRC_OFF 0x00 // 7 0 LoRa CRC mode: disabled
    283 #define SX126X_LORA_CRC_ON 0x01 // 7 0 enabled
    284 #define SX126X_LORA_IQ_STANDARD 0x00 // 7 0 LoRa IQ setup: standard
    285 #define SX126X_LORA_IQ_INVERTED 0x01 // 7 0 inverted
    286 
    287 //SX126X_CMD_SET_CAD_PARAMS
    288 #define SX126X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
    289 #define SX126X_CAD_ON_2_SYMB 0x01 // 7 0 2
    290 #define SX126X_CAD_ON_4_SYMB 0x02 // 7 0 4
    291 #define SX126X_CAD_ON_8_SYMB 0x03 // 7 0 8
    292 #define SX126X_CAD_ON_16_SYMB 0x04 // 7 0 16
    293 #define SX126X_CAD_GOTO_STDBY 0x00 // 7 0 after CAD is done, always go to STDBY_RC mode
    294 #define SX126X_CAD_GOTO_RX 0x01 // 7 0 after CAD is done, go to Rx mode if activity is detected
    295 
    296 //SX126X_CMD_GET_STATUS
    297 #define SX126X_STATUS_MODE_STDBY_RC 0b00100000 // 6 4 current chip mode: STDBY_RC
    298 #define SX126X_STATUS_MODE_STDBY_XOSC 0b00110000 // 6 4 STDBY_XOSC
    299 #define SX126X_STATUS_MODE_FS 0b01000000 // 6 4 FS
    300 #define SX126X_STATUS_MODE_RX 0b01010000 // 6 4 RX
    301 #define SX126X_STATUS_MODE_TX 0b01100000 // 6 4 TX
    302 #define SX126X_STATUS_DATA_AVAILABLE 0b00000100 // 3 1 command status: packet received and data can be retrieved
    303 #define SX126X_STATUS_CMD_TIMEOUT 0b00000110 // 3 1 SPI command timed out
    304 #define SX126X_STATUS_CMD_INVALID 0b00001000 // 3 1 invalid SPI command
    305 #define SX126X_STATUS_CMD_FAILED 0b00001010 // 3 1 SPI command failed to execute
    306 #define SX126X_STATUS_TX_DONE 0b00001100 // 3 1 packet transmission done
    307 #define SX126X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
    308 
    309 //SX126X_CMD_GET_PACKET_STATUS
    310 #define SX126X_GFSK_RX_STATUS_PREAMBLE_ERR 0b10000000 // 7 7 GFSK Rx status: preamble error
    311 #define SX126X_GFSK_RX_STATUS_SYNC_ERR 0b01000000 // 6 6 sync word error
    312 #define SX126X_GFSK_RX_STATUS_ADRS_ERR 0b00100000 // 5 5 address error
    313 #define SX126X_GFSK_RX_STATUS_CRC_ERR 0b00010000 // 4 4 CRC error
    314 #define SX126X_GFSK_RX_STATUS_LENGTH_ERR 0b00001000 // 3 3 length error
    315 #define SX126X_GFSK_RX_STATUS_ABORT_ERR 0b00000100 // 2 2 abort error
    316 #define SX126X_GFSK_RX_STATUS_PACKET_RECEIVED 0b00000010 // 2 2 packet received
    317 #define SX126X_GFSK_RX_STATUS_PACKET_SENT 0b00000001 // 2 2 packet sent
    318 
    319 //SX126X_CMD_GET_DEVICE_ERRORS
    320 #define SX126X_PA_RAMP_ERR 0b100000000 // 8 8 device errors: PA ramping failed
    321 #define SX126X_PLL_LOCK_ERR 0b001000000 // 6 6 PLL failed to lock
    322 #define SX126X_XOSC_START_ERR 0b000100000 // 5 5 crystal oscillator failed to start
    323 #define SX126X_IMG_CALIB_ERR 0b000010000 // 4 4 image calibration failed
    324 #define SX126X_ADC_CALIB_ERR 0b000001000 // 3 3 ADC calibration failed
    325 #define SX126X_PLL_CALIB_ERR 0b000000100 // 2 2 PLL calibration failed
    326 #define SX126X_RC13M_CALIB_ERR 0b000000010 // 1 1 RC13M calibration failed
    327 #define SX126X_RC64K_CALIB_ERR 0b000000001 // 0 0 RC64K calibration failed
    328 
    329 
    330 // SX126X SPI register variables
    331 //SX126X_REG_LORA_SYNC_WORD_MSB + LSB
    332 #define SX126X_SYNC_WORD_PUBLIC 0x34 // actually 0x3444 NOTE: The low nibbles in each byte (0x_4_4) are masked out since apparently, they're reserved.
    333 #define SX126X_SYNC_WORD_PRIVATE 0x12 // actually 0x1424 You couldn't make this up if you tried.
    334 
    335 
    342 class SX126x: public PhysicalLayer {
    343  public:
    344  // introduce PhysicalLayer overloads
    345  using PhysicalLayer::transmit;
    346  using PhysicalLayer::receive;
    347  using PhysicalLayer::startTransmit;
    348  using PhysicalLayer::readData;
    349 
    355  SX126x(Module* mod);
    356 
    357  // basic methods
    358 
    378  int16_t begin(float bw, uint8_t sf, uint8_t cr, uint8_t syncWord, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
    379 
    397  int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
    398 
    407  int16_t reset(bool verify = true);
    408 
    421  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    422 
    433  int16_t receive(uint8_t* data, size_t len) override;
    434 
    442  int16_t transmitDirect(uint32_t frf = 0) override;
    443 
    450  int16_t receiveDirect() override;
    451 
    457  int16_t scanChannel();
    458 
    466  int16_t sleep(bool retainConfig = true);
    467 
    473  int16_t standby() override;
    474 
    482  int16_t standby(uint8_t mode);
    483 
    484  // interrupt methods
    485 
    491  void setDio1Action(void (*func)(void));
    492 
    496  void clearDio1Action();
    497 
    510  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    511 
    519  int16_t startReceive(uint32_t timeout = SX126X_RX_TIMEOUT_INF);
    520 
    531  int16_t startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod);
    532 
    544  int16_t startReceiveDutyCycleAuto(uint16_t senderPreambleLength = 0, uint16_t minSymbols = 8);
    545 
    555  int16_t readData(uint8_t* data, size_t len) override;
    556 
    557  // configuration methods
    558 
    566  int16_t setBandwidth(float bw);
    567 
    575  int16_t setSpreadingFactor(uint8_t sf);
    576 
    584  int16_t setCodingRate(uint8_t cr);
    585 
    595  int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits = 0x44);
    596 
    604  int16_t setCurrentLimit(float currentLimit);
    605 
    611  float getCurrentLimit();
    612 
    620  int16_t setPreambleLength(uint16_t preambleLength);
    621 
    629  int16_t setFrequencyDeviation(float freqDev) override;
    630 
    638  int16_t setBitRate(float br);
    639 
    647  int16_t setRxBandwidth(float rxBw);
    648 
    658  int16_t setDataShaping(uint8_t sh) override;
    659 
    669  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
    670 
    680  int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen);
    681 
    689  int16_t setNodeAddress(uint8_t nodeAddr);
    690 
    698  int16_t setBroadcastAddress(uint8_t broadAddr);
    699 
    705  int16_t disableAddressFiltering();
    706 
    720  int16_t setCRC(uint8_t len, uint16_t initial = 0x1D0F, uint16_t polynomial = 0x1021, bool inverted = true);
    721 
    731  int16_t setWhitening(bool enabled, uint16_t initial = 0x0100);
    732 
    740  int16_t setTCXO(float voltage, uint32_t delay = 5000);
    741 
    747  int16_t setDio2AsRfSwitch(bool enable = true);
    748 
    754  float getDataRate() const;
    755 
    761  float getRSSI();
    762 
    768  float getSNR();
    769 
    777  size_t getPacketLength(bool update = true) override;
    778 
    786  int16_t fixedPacketLengthMode(uint8_t len = SX126X_MAX_PACKET_LENGTH);
    787 
    795  int16_t variablePacketLengthMode(uint8_t maxLen = SX126X_MAX_PACKET_LENGTH);
    796 
    804  uint32_t getTimeOnAir(size_t len);
    805 
    811  int16_t implicitHeader(size_t len);
    812 
    820  int16_t explicitHeader();
    821 
    827  int16_t setRegulatorLDO();
    828 
    834  int16_t setRegulatorDCDC();
    835 
    843  int16_t setEncoding(uint8_t encoding) override;
    844 
    853  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    854 
    863  int16_t forceLDRO(bool enable);
    864 
    871  int16_t autoLDRO();
    872 
    873 #ifndef RADIOLIB_GODMODE
    874  protected:
    875 #endif
    876  // SX126x SPI command implementations
    877  int16_t setTx(uint32_t timeout = 0);
    878  int16_t setRx(uint32_t timeout);
    879  int16_t setCad();
    880  int16_t setPaConfig(uint8_t paDutyCycle, uint8_t deviceSel, uint8_t hpMax = SX126X_PA_CONFIG_HP_MAX, uint8_t paLut = SX126X_PA_CONFIG_PA_LUT);
    881  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
    882  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
    883  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
    884  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
    885  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX126X_IRQ_NONE, uint16_t dio3Mask = SX126X_IRQ_NONE);
    886  uint16_t getIrqStatus();
    887  int16_t clearIrqStatus(uint16_t clearIrqParams = SX126X_IRQ_ALL);
    888  int16_t setRfFrequency(uint32_t frf);
    889  int16_t calibrateImage(uint8_t* data);
    890  uint8_t getPacketType();
    891  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX126X_PA_RAMP_200U);
    892  int16_t setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, uint8_t ldro);
    893  int16_t setModulationParamsFSK(uint32_t br, uint8_t pulseShape, uint8_t rxBw, uint32_t freqDev);
    894  int16_t setPacketParams(uint16_t preambleLength, uint8_t crcType, uint8_t payloadLength, uint8_t headerType, uint8_t invertIQ = SX126X_LORA_IQ_STANDARD);
    895  int16_t setPacketParamsFSK(uint16_t preambleLength, uint8_t crcType, uint8_t syncWordLength, uint8_t addrComp, uint8_t whitening, uint8_t packetType = SX126X_GFSK_PACKET_VARIABLE, uint8_t payloadLength = 0xFF, uint8_t preambleDetectorLength = SX126X_GFSK_PREAMBLE_DETECT_16);
    896  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
    897  int16_t setRegulatorMode(uint8_t mode);
    898  uint8_t getStatus();
    899  uint32_t getPacketStatus();
    900  uint16_t getDeviceErrors();
    901  int16_t clearDeviceErrors();
    902 
    903  int16_t startReceiveCommon();
    904  int16_t setFrequencyRaw(float freq);
    905  int16_t setPacketMode(uint8_t mode, uint8_t len);
    906  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
    907 
    908  // fixes to errata
    909  int16_t fixSensitivity();
    910  int16_t fixPaClamping();
    911  int16_t fixImplicitTimeout();
    912  int16_t fixInvertedIQ(uint8_t iqConfig);
    913 
    914 #ifndef RADIOLIB_GODMODE
    915  private:
    916 #endif
    917  Module* _mod;
    918 
    919  uint8_t _bw = 0, _sf = 0, _cr = 0, _ldro = 0, _crcType = 0, _headerType = 0;
    920  uint16_t _preambleLength = 0;
    921  float _bwKhz = 0;
    922  bool _ldroAuto = true;
    923 
    924  uint32_t _br = 0, _freqDev = 0;
    925  uint8_t _rxBw = 0, _pulseShape = 0, _crcTypeFSK = 0, _syncWordLength = 0, _addrComp = 0, _whitening = 0, _packetType = 0;
    926  uint16_t _preambleLengthFSK = 0;
    927  float _rxBwKhz = 0;
    928 
    929  float _dataRate = 0;
    930 
    931  uint32_t _tcxoDelay = 0;
    932 
    933  size_t _implicitLen = 0;
    934 
    935  int16_t config(uint8_t modem);
    936 
    937  // common low-level SPI interface
    938  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    939  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    940  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    941  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    942  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
    943 };
    944 
    945 #endif
    946 
    947 #endif
    SX126x::setRfSwitchPins
    void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
    Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
    Definition: SX126x.cpp:1151
    +
    1 #if !defined(_RADIOLIB_SX126X_H)
    2 #define _RADIOLIB_SX126X_H
    3 
    4 #include "../../TypeDef.h"
    5 
    6 #if !defined(RADIOLIB_EXCLUDE_SX126X)
    7 
    8 #include "../../Module.h"
    9 
    10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
    11 
    12 // SX126X physical layer properties
    13 #define SX126X_FREQUENCY_STEP_SIZE 0.9536743164
    14 #define SX126X_MAX_PACKET_LENGTH 255
    15 #define SX126X_CRYSTAL_FREQ 32.0
    16 #define SX126X_DIV_EXPONENT 25
    17 
    18 // SX126X SPI commands
    19 // operational modes commands
    20 #define SX126X_CMD_NOP 0x00
    21 #define SX126X_CMD_SET_SLEEP 0x84
    22 #define SX126X_CMD_SET_STANDBY 0x80
    23 #define SX126X_CMD_SET_FS 0xC1
    24 #define SX126X_CMD_SET_TX 0x83
    25 #define SX126X_CMD_SET_RX 0x82
    26 #define SX126X_CMD_STOP_TIMER_ON_PREAMBLE 0x9F
    27 #define SX126X_CMD_SET_RX_DUTY_CYCLE 0x94
    28 #define SX126X_CMD_SET_CAD 0xC5
    29 #define SX126X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
    30 #define SX126X_CMD_SET_TX_INFINITE_PREAMBLE 0xD2
    31 #define SX126X_CMD_SET_REGULATOR_MODE 0x96
    32 #define SX126X_CMD_CALIBRATE 0x89
    33 #define SX126X_CMD_CALIBRATE_IMAGE 0x98
    34 #define SX126X_CMD_SET_PA_CONFIG 0x95
    35 #define SX126X_CMD_SET_RX_TX_FALLBACK_MODE 0x93
    36 
    37 // register and buffer access commands
    38 #define SX126X_CMD_WRITE_REGISTER 0x0D
    39 #define SX126X_CMD_READ_REGISTER 0x1D
    40 #define SX126X_CMD_WRITE_BUFFER 0x0E
    41 #define SX126X_CMD_READ_BUFFER 0x1E
    42 
    43 // DIO and IRQ control
    44 #define SX126X_CMD_SET_DIO_IRQ_PARAMS 0x08
    45 #define SX126X_CMD_GET_IRQ_STATUS 0x12
    46 #define SX126X_CMD_CLEAR_IRQ_STATUS 0x02
    47 #define SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL 0x9D
    48 #define SX126X_CMD_SET_DIO3_AS_TCXO_CTRL 0x97
    49 
    50 // RF, modulation and packet commands
    51 #define SX126X_CMD_SET_RF_FREQUENCY 0x86
    52 #define SX126X_CMD_SET_PACKET_TYPE 0x8A
    53 #define SX126X_CMD_GET_PACKET_TYPE 0x11
    54 #define SX126X_CMD_SET_TX_PARAMS 0x8E
    55 #define SX126X_CMD_SET_MODULATION_PARAMS 0x8B
    56 #define SX126X_CMD_SET_PACKET_PARAMS 0x8C
    57 #define SX126X_CMD_SET_CAD_PARAMS 0x88
    58 #define SX126X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
    59 #define SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT 0x0A
    60 
    61 // status commands
    62 #define SX126X_CMD_GET_STATUS 0xC0
    63 #define SX126X_CMD_GET_RSSI_INST 0x15
    64 #define SX126X_CMD_GET_RX_BUFFER_STATUS 0x13
    65 #define SX126X_CMD_GET_PACKET_STATUS 0x14
    66 #define SX126X_CMD_GET_DEVICE_ERRORS 0x17
    67 #define SX126X_CMD_CLEAR_DEVICE_ERRORS 0x07
    68 #define SX126X_CMD_GET_STATS 0x10
    69 #define SX126X_CMD_RESET_STATS 0x00
    70 
    71 
    72 // SX126X register map
    73 #define SX126X_REG_WHITENING_INITIAL_MSB 0x06B8
    74 #define SX126X_REG_WHITENING_INITIAL_LSB 0x06B9
    75 #define SX126X_REG_CRC_INITIAL_MSB 0x06BC
    76 #define SX126X_REG_CRC_INITIAL_LSB 0x06BD
    77 #define SX126X_REG_CRC_POLYNOMIAL_MSB 0x06BE
    78 #define SX126X_REG_CRC_POLYNOMIAL_LSB 0x06BF
    79 #define SX126X_REG_SYNC_WORD_0 0x06C0
    80 #define SX126X_REG_SYNC_WORD_1 0x06C1
    81 #define SX126X_REG_SYNC_WORD_2 0x06C2
    82 #define SX126X_REG_SYNC_WORD_3 0x06C3
    83 #define SX126X_REG_SYNC_WORD_4 0x06C4
    84 #define SX126X_REG_SYNC_WORD_5 0x06C5
    85 #define SX126X_REG_SYNC_WORD_6 0x06C6
    86 #define SX126X_REG_SYNC_WORD_7 0x06C7
    87 #define SX126X_REG_NODE_ADDRESS 0x06CD
    88 #define SX126X_REG_BROADCAST_ADDRESS 0x06CE
    89 #define SX126X_REG_LORA_SYNC_WORD_MSB 0x0740
    90 #define SX126X_REG_LORA_SYNC_WORD_LSB 0x0741
    91 #define SX126X_REG_RANDOM_NUMBER_0 0x0819
    92 #define SX126X_REG_RANDOM_NUMBER_1 0x081A
    93 #define SX126X_REG_RANDOM_NUMBER_2 0x081B
    94 #define SX126X_REG_RANDOM_NUMBER_3 0x081C
    95 #define SX126X_REG_RX_GAIN 0x08AC
    96 #define SX126X_REG_OCP_CONFIGURATION 0x08E7
    97 #define SX126X_REG_XTA_TRIM 0x0911
    98 #define SX126X_REG_XTB_TRIM 0x0912
    99 
    100 // undocumented registers
    101 #define SX126X_REG_SENSITIVITY_CONFIG 0x0889 // SX1268 datasheet v1.1, section 15.1
    102 #define SX126X_REG_TX_CLAMP_CONFIG 0x08D8 // SX1268 datasheet v1.1, section 15.2
    103 #define SX126X_REG_RTC_STOP 0x0920 // SX1268 datasheet v1.1, section 15.3
    104 #define SX126X_REG_RTC_EVENT 0x0944 // SX1268 datasheet v1.1, section 15.3
    105 #define SX126X_REG_IQ_CONFIG 0x0736 // SX1268 datasheet v1.1, section 15.4
    106 #define SX126X_REG_RX_GAIN_RETENTION_0 0x029F // SX1268 datasheet v1.1, section 9.6
    107 #define SX126X_REG_RX_GAIN_RETENTION_1 0x02A0 // SX1268 datasheet v1.1, section 9.6
    108 #define SX126X_REG_RX_GAIN_RETENTION_2 0x02A1 // SX1268 datasheet v1.1, section 9.6
    109 
    110 
    111 // SX126X SPI command variables
    112 //SX126X_CMD_SET_SLEEP MSB LSB DESCRIPTION
    113 #define SX126X_SLEEP_START_COLD 0b00000000 // 2 2 sleep mode: cold start, configuration is lost (default)
    114 #define SX126X_SLEEP_START_WARM 0b00000100 // 2 2 warm start, configuration is retained
    115 #define SX126X_SLEEP_RTC_OFF 0b00000000 // 0 0 wake on RTC timeout: disabled
    116 #define SX126X_SLEEP_RTC_ON 0b00000001 // 0 0 enabled
    117 
    118 //SX126X_CMD_SET_STANDBY
    119 #define SX126X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
    120 #define SX126X_STANDBY_XOSC 0x01 // 7 0 32 MHz crystal oscillator
    121 
    122 //SX126X_CMD_SET_RX
    123 #define SX126X_RX_TIMEOUT_NONE 0x000000 // 23 0 Rx timeout duration: no timeout (Rx single mode)
    124 #define SX126X_RX_TIMEOUT_INF 0xFFFFFF // 23 0 infinite (Rx continuous mode)
    125 
    126 //SX126X_CMD_SET_TX
    127 #define SX126X_TX_TIMEOUT_NONE 0x000000 // 23 0 Tx timeout duration: no timeout (Tx single mode)
    128 
    129 //SX126X_CMD_STOP_TIMER_ON_PREAMBLE
    130 #define SX126X_STOP_ON_PREAMBLE_OFF 0x00 // 7 0 stop timer on: sync word or header (default)
    131 #define SX126X_STOP_ON_PREAMBLE_ON 0x01 // 7 0 preamble detection
    132 
    133 //SX126X_CMD_SET_REGULATOR_MODE
    134 #define SX126X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
    135 #define SX126X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
    136 
    137 //SX126X_CMD_CALIBRATE
    138 #define SX126X_CALIBRATE_IMAGE_OFF 0b00000000 // 6 6 image calibration: disabled
    139 #define SX126X_CALIBRATE_IMAGE_ON 0b01000000 // 6 6 enabled
    140 #define SX126X_CALIBRATE_ADC_BULK_P_OFF 0b00000000 // 5 5 ADC bulk P calibration: disabled
    141 #define SX126X_CALIBRATE_ADC_BULK_P_ON 0b00100000 // 5 5 enabled
    142 #define SX126X_CALIBRATE_ADC_BULK_N_OFF 0b00000000 // 4 4 ADC bulk N calibration: disabled
    143 #define SX126X_CALIBRATE_ADC_BULK_N_ON 0b00010000 // 4 4 enabled
    144 #define SX126X_CALIBRATE_ADC_PULSE_OFF 0b00000000 // 3 3 ADC pulse calibration: disabled
    145 #define SX126X_CALIBRATE_ADC_PULSE_ON 0b00001000 // 3 3 enabled
    146 #define SX126X_CALIBRATE_PLL_OFF 0b00000000 // 2 2 PLL calibration: disabled
    147 #define SX126X_CALIBRATE_PLL_ON 0b00000100 // 2 2 enabled
    148 #define SX126X_CALIBRATE_RC13M_OFF 0b00000000 // 1 1 13 MHz RC osc. calibration: disabled
    149 #define SX126X_CALIBRATE_RC13M_ON 0b00000010 // 1 1 enabled
    150 #define SX126X_CALIBRATE_RC64K_OFF 0b00000000 // 0 0 64 kHz RC osc. calibration: disabled
    151 #define SX126X_CALIBRATE_RC64K_ON 0b00000001 // 0 0 enabled
    152 #define SX126X_CALIBRATE_ALL 0b01111111 // 6 0 calibrate all blocks
    153 
    154 //SX126X_CMD_CALIBRATE_IMAGE
    155 #define SX126X_CAL_IMG_430_MHZ_1 0x6B
    156 #define SX126X_CAL_IMG_430_MHZ_2 0x6F
    157 #define SX126X_CAL_IMG_470_MHZ_1 0x75
    158 #define SX126X_CAL_IMG_470_MHZ_2 0x81
    159 #define SX126X_CAL_IMG_779_MHZ_1 0xC1
    160 #define SX126X_CAL_IMG_779_MHZ_2 0xC5
    161 #define SX126X_CAL_IMG_863_MHZ_1 0xD7
    162 #define SX126X_CAL_IMG_863_MHZ_2 0xDB
    163 #define SX126X_CAL_IMG_902_MHZ_1 0xE1
    164 #define SX126X_CAL_IMG_902_MHZ_2 0xE9
    165 
    166 //SX126X_CMD_SET_PA_CONFIG
    167 #define SX126X_PA_CONFIG_HP_MAX 0x07
    168 #define SX126X_PA_CONFIG_PA_LUT 0x01
    169 #define SX126X_PA_CONFIG_SX1262_8 0x00
    170 
    171 //SX126X_CMD_SET_RX_TX_FALLBACK_MODE
    172 #define SX126X_RX_TX_FALLBACK_MODE_FS 0x40 // 7 0 after Rx/Tx go to: FS mode
    173 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_XOSC 0x30 // 7 0 standby with crystal oscillator
    174 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_RC 0x20 // 7 0 standby with RC oscillator (default)
    175 
    176 //SX126X_CMD_SET_DIO_IRQ_PARAMS
    177 #define SX126X_IRQ_TIMEOUT 0b1000000000 // 9 9 Rx or Tx timeout
    178 #define SX126X_IRQ_CAD_DETECTED 0b0100000000 // 8 8 channel activity detected
    179 #define SX126X_IRQ_CAD_DONE 0b0010000000 // 7 7 channel activity detection finished
    180 #define SX126X_IRQ_CRC_ERR 0b0001000000 // 6 6 wrong CRC received
    181 #define SX126X_IRQ_HEADER_ERR 0b0000100000 // 5 5 LoRa header CRC error
    182 #define SX126X_IRQ_HEADER_VALID 0b0000010000 // 4 4 valid LoRa header received
    183 #define SX126X_IRQ_SYNC_WORD_VALID 0b0000001000 // 3 3 valid sync word detected
    184 #define SX126X_IRQ_PREAMBLE_DETECTED 0b0000000100 // 2 2 preamble detected
    185 #define SX126X_IRQ_RX_DONE 0b0000000010 // 1 1 packet received
    186 #define SX126X_IRQ_TX_DONE 0b0000000001 // 0 0 packet transmission completed
    187 #define SX126X_IRQ_ALL 0b1111111111 // 9 0 all interrupts
    188 #define SX126X_IRQ_NONE 0b0000000000 // 9 0 no interrupts
    189 
    190 //SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL
    191 #define SX126X_DIO2_AS_IRQ 0x00 // 7 0 DIO2 configuration: IRQ
    192 #define SX126X_DIO2_AS_RF_SWITCH 0x01 // 7 0 RF switch control
    193 
    194 //SX126X_CMD_SET_DIO3_AS_TCXO_CTRL
    195 #define SX126X_DIO3_OUTPUT_1_6 0x00 // 7 0 DIO3 voltage output for TCXO: 1.6 V
    196 #define SX126X_DIO3_OUTPUT_1_7 0x01 // 7 0 1.7 V
    197 #define SX126X_DIO3_OUTPUT_1_8 0x02 // 7 0 1.8 V
    198 #define SX126X_DIO3_OUTPUT_2_2 0x03 // 7 0 2.2 V
    199 #define SX126X_DIO3_OUTPUT_2_4 0x04 // 7 0 2.4 V
    200 #define SX126X_DIO3_OUTPUT_2_7 0x05 // 7 0 2.7 V
    201 #define SX126X_DIO3_OUTPUT_3_0 0x06 // 7 0 3.0 V
    202 #define SX126X_DIO3_OUTPUT_3_3 0x07 // 7 0 3.3 V
    203 
    204 //SX126X_CMD_SET_PACKET_TYPE
    205 #define SX126X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: GFSK
    206 #define SX126X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
    207 
    208 //SX126X_CMD_SET_TX_PARAMS
    209 #define SX126X_PA_RAMP_10U 0x00 // 7 0 ramp time: 10 us
    210 #define SX126X_PA_RAMP_20U 0x01 // 7 0 20 us
    211 #define SX126X_PA_RAMP_40U 0x02 // 7 0 40 us
    212 #define SX126X_PA_RAMP_80U 0x03 // 7 0 80 us
    213 #define SX126X_PA_RAMP_200U 0x04 // 7 0 200 us
    214 #define SX126X_PA_RAMP_800U 0x05 // 7 0 800 us
    215 #define SX126X_PA_RAMP_1700U 0x06 // 7 0 1700 us
    216 #define SX126X_PA_RAMP_3400U 0x07 // 7 0 3400 us
    217 
    218 //SX126X_CMD_SET_MODULATION_PARAMS
    219 #define SX126X_GFSK_FILTER_NONE 0x00 // 7 0 GFSK filter: none
    220 #define SX126X_GFSK_FILTER_GAUSS_0_3 0x08 // 7 0 Gaussian, BT = 0.3
    221 #define SX126X_GFSK_FILTER_GAUSS_0_5 0x09 // 7 0 Gaussian, BT = 0.5
    222 #define SX126X_GFSK_FILTER_GAUSS_0_7 0x0A // 7 0 Gaussian, BT = 0.7
    223 #define SX126X_GFSK_FILTER_GAUSS_1 0x0B // 7 0 Gaussian, BT = 1
    224 #define SX126X_GFSK_RX_BW_4_8 0x1F // 7 0 GFSK Rx bandwidth: 4.8 kHz
    225 #define SX126X_GFSK_RX_BW_5_8 0x17 // 7 0 5.8 kHz
    226 #define SX126X_GFSK_RX_BW_7_3 0x0F // 7 0 7.3 kHz
    227 #define SX126X_GFSK_RX_BW_9_7 0x1E // 7 0 9.7 kHz
    228 #define SX126X_GFSK_RX_BW_11_7 0x16 // 7 0 11.7 kHz
    229 #define SX126X_GFSK_RX_BW_14_6 0x0E // 7 0 14.6 kHz
    230 #define SX126X_GFSK_RX_BW_19_5 0x1D // 7 0 19.5 kHz
    231 #define SX126X_GFSK_RX_BW_23_4 0x15 // 7 0 23.4 kHz
    232 #define SX126X_GFSK_RX_BW_29_3 0x0D // 7 0 29.3 kHz
    233 #define SX126X_GFSK_RX_BW_39_0 0x1C // 7 0 39.0 kHz
    234 #define SX126X_GFSK_RX_BW_46_9 0x14 // 7 0 46.9 kHz
    235 #define SX126X_GFSK_RX_BW_58_6 0x0C // 7 0 58.6 kHz
    236 #define SX126X_GFSK_RX_BW_78_2 0x1B // 7 0 78.2 kHz
    237 #define SX126X_GFSK_RX_BW_93_8 0x13 // 7 0 93.8 kHz
    238 #define SX126X_GFSK_RX_BW_117_3 0x0B // 7 0 117.3 kHz
    239 #define SX126X_GFSK_RX_BW_156_2 0x1A // 7 0 156.2 kHz
    240 #define SX126X_GFSK_RX_BW_187_2 0x12 // 7 0 187.2 kHz
    241 #define SX126X_GFSK_RX_BW_234_3 0x0A // 7 0 234.3 kHz
    242 #define SX126X_GFSK_RX_BW_312_0 0x19 // 7 0 312.0 kHz
    243 #define SX126X_GFSK_RX_BW_373_6 0x11 // 7 0 373.6 kHz
    244 #define SX126X_GFSK_RX_BW_467_0 0x09 // 7 0 467.0 kHz
    245 #define SX126X_LORA_BW_7_8 0x00 // 7 0 LoRa bandwidth: 7.8 kHz
    246 #define SX126X_LORA_BW_10_4 0x08 // 7 0 10.4 kHz
    247 #define SX126X_LORA_BW_15_6 0x01 // 7 0 15.6 kHz
    248 #define SX126X_LORA_BW_20_8 0x09 // 7 0 20.8 kHz
    249 #define SX126X_LORA_BW_31_25 0x02 // 7 0 31.25 kHz
    250 #define SX126X_LORA_BW_41_7 0x0A // 7 0 41.7 kHz
    251 #define SX126X_LORA_BW_62_5 0x03 // 7 0 62.5 kHz
    252 #define SX126X_LORA_BW_125_0 0x04 // 7 0 125.0 kHz
    253 #define SX126X_LORA_BW_250_0 0x05 // 7 0 250.0 kHz
    254 #define SX126X_LORA_BW_500_0 0x06 // 7 0 500.0 kHz
    255 #define SX126X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
    256 #define SX126X_LORA_CR_4_6 0x02 // 7 0 4/6
    257 #define SX126X_LORA_CR_4_7 0x03 // 7 0 4/7
    258 #define SX126X_LORA_CR_4_8 0x04 // 7 0 4/8
    259 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_OFF 0x00 // 7 0 LoRa low data rate optimization: disabled
    260 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_ON 0x01 // 7 0 enabled
    261 
    262 //SX126X_CMD_SET_PACKET_PARAMS
    263 #define SX126X_GFSK_PREAMBLE_DETECT_OFF 0x00 // 7 0 GFSK minimum preamble length before reception starts: detector disabled
    264 #define SX126X_GFSK_PREAMBLE_DETECT_8 0x04 // 7 0 8 bits
    265 #define SX126X_GFSK_PREAMBLE_DETECT_16 0x05 // 7 0 16 bits
    266 #define SX126X_GFSK_PREAMBLE_DETECT_24 0x06 // 7 0 24 bits
    267 #define SX126X_GFSK_PREAMBLE_DETECT_32 0x07 // 7 0 32 bits
    268 #define SX126X_GFSK_ADDRESS_FILT_OFF 0x00 // 7 0 GFSK address filtering: disabled
    269 #define SX126X_GFSK_ADDRESS_FILT_NODE 0x01 // 7 0 node only
    270 #define SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST 0x02 // 7 0 node and broadcast
    271 #define SX126X_GFSK_PACKET_FIXED 0x00 // 7 0 GFSK packet type: fixed (payload length known in advance to both sides)
    272 #define SX126X_GFSK_PACKET_VARIABLE 0x01 // 7 0 variable (payload length added to packet)
    273 #define SX126X_GFSK_CRC_OFF 0x01 // 7 0 GFSK packet CRC: disabled
    274 #define SX126X_GFSK_CRC_1_BYTE 0x00 // 7 0 1 byte
    275 #define SX126X_GFSK_CRC_2_BYTE 0x02 // 7 0 2 byte
    276 #define SX126X_GFSK_CRC_1_BYTE_INV 0x04 // 7 0 1 byte, inverted
    277 #define SX126X_GFSK_CRC_2_BYTE_INV 0x06 // 7 0 2 byte, inverted
    278 #define SX126X_GFSK_WHITENING_OFF 0x00 // 7 0 GFSK data whitening: disabled
    279 #define SX126X_GFSK_WHITENING_ON 0x01 // 7 0 enabled
    280 #define SX126X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
    281 #define SX126X_LORA_HEADER_IMPLICIT 0x01 // 7 0 implicit
    282 #define SX126X_LORA_CRC_OFF 0x00 // 7 0 LoRa CRC mode: disabled
    283 #define SX126X_LORA_CRC_ON 0x01 // 7 0 enabled
    284 #define SX126X_LORA_IQ_STANDARD 0x00 // 7 0 LoRa IQ setup: standard
    285 #define SX126X_LORA_IQ_INVERTED 0x01 // 7 0 inverted
    286 
    287 //SX126X_CMD_SET_CAD_PARAMS
    288 #define SX126X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
    289 #define SX126X_CAD_ON_2_SYMB 0x01 // 7 0 2
    290 #define SX126X_CAD_ON_4_SYMB 0x02 // 7 0 4
    291 #define SX126X_CAD_ON_8_SYMB 0x03 // 7 0 8
    292 #define SX126X_CAD_ON_16_SYMB 0x04 // 7 0 16
    293 #define SX126X_CAD_GOTO_STDBY 0x00 // 7 0 after CAD is done, always go to STDBY_RC mode
    294 #define SX126X_CAD_GOTO_RX 0x01 // 7 0 after CAD is done, go to Rx mode if activity is detected
    295 
    296 //SX126X_CMD_GET_STATUS
    297 #define SX126X_STATUS_MODE_STDBY_RC 0b00100000 // 6 4 current chip mode: STDBY_RC
    298 #define SX126X_STATUS_MODE_STDBY_XOSC 0b00110000 // 6 4 STDBY_XOSC
    299 #define SX126X_STATUS_MODE_FS 0b01000000 // 6 4 FS
    300 #define SX126X_STATUS_MODE_RX 0b01010000 // 6 4 RX
    301 #define SX126X_STATUS_MODE_TX 0b01100000 // 6 4 TX
    302 #define SX126X_STATUS_DATA_AVAILABLE 0b00000100 // 3 1 command status: packet received and data can be retrieved
    303 #define SX126X_STATUS_CMD_TIMEOUT 0b00000110 // 3 1 SPI command timed out
    304 #define SX126X_STATUS_CMD_INVALID 0b00001000 // 3 1 invalid SPI command
    305 #define SX126X_STATUS_CMD_FAILED 0b00001010 // 3 1 SPI command failed to execute
    306 #define SX126X_STATUS_TX_DONE 0b00001100 // 3 1 packet transmission done
    307 #define SX126X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
    308 
    309 //SX126X_CMD_GET_PACKET_STATUS
    310 #define SX126X_GFSK_RX_STATUS_PREAMBLE_ERR 0b10000000 // 7 7 GFSK Rx status: preamble error
    311 #define SX126X_GFSK_RX_STATUS_SYNC_ERR 0b01000000 // 6 6 sync word error
    312 #define SX126X_GFSK_RX_STATUS_ADRS_ERR 0b00100000 // 5 5 address error
    313 #define SX126X_GFSK_RX_STATUS_CRC_ERR 0b00010000 // 4 4 CRC error
    314 #define SX126X_GFSK_RX_STATUS_LENGTH_ERR 0b00001000 // 3 3 length error
    315 #define SX126X_GFSK_RX_STATUS_ABORT_ERR 0b00000100 // 2 2 abort error
    316 #define SX126X_GFSK_RX_STATUS_PACKET_RECEIVED 0b00000010 // 2 2 packet received
    317 #define SX126X_GFSK_RX_STATUS_PACKET_SENT 0b00000001 // 2 2 packet sent
    318 
    319 //SX126X_CMD_GET_DEVICE_ERRORS
    320 #define SX126X_PA_RAMP_ERR 0b100000000 // 8 8 device errors: PA ramping failed
    321 #define SX126X_PLL_LOCK_ERR 0b001000000 // 6 6 PLL failed to lock
    322 #define SX126X_XOSC_START_ERR 0b000100000 // 5 5 crystal oscillator failed to start
    323 #define SX126X_IMG_CALIB_ERR 0b000010000 // 4 4 image calibration failed
    324 #define SX126X_ADC_CALIB_ERR 0b000001000 // 3 3 ADC calibration failed
    325 #define SX126X_PLL_CALIB_ERR 0b000000100 // 2 2 PLL calibration failed
    326 #define SX126X_RC13M_CALIB_ERR 0b000000010 // 1 1 RC13M calibration failed
    327 #define SX126X_RC64K_CALIB_ERR 0b000000001 // 0 0 RC64K calibration failed
    328 
    329 
    330 // SX126X SPI register variables
    331 //SX126X_REG_LORA_SYNC_WORD_MSB + LSB
    332 #define SX126X_SYNC_WORD_PUBLIC 0x34 // actually 0x3444 NOTE: The low nibbles in each byte (0x_4_4) are masked out since apparently, they're reserved.
    333 #define SX126X_SYNC_WORD_PRIVATE 0x12 // actually 0x1424 You couldn't make this up if you tried.
    334 
    335 
    342 class SX126x: public PhysicalLayer {
    343  public:
    344  // introduce PhysicalLayer overloads
    345  using PhysicalLayer::transmit;
    346  using PhysicalLayer::receive;
    347  using PhysicalLayer::startTransmit;
    348  using PhysicalLayer::readData;
    349 
    355  SX126x(Module* mod);
    356 
    357  // basic methods
    358 
    378  int16_t begin(float bw, uint8_t sf, uint8_t cr, uint8_t syncWord, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
    379 
    397  int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
    398 
    407  int16_t reset(bool verify = true);
    408 
    421  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    422 
    433  int16_t receive(uint8_t* data, size_t len) override;
    434 
    442  int16_t transmitDirect(uint32_t frf = 0) override;
    443 
    450  int16_t receiveDirect() override;
    451 
    457  int16_t scanChannel();
    458 
    466  int16_t sleep(bool retainConfig = true);
    467 
    473  int16_t standby() override;
    474 
    482  int16_t standby(uint8_t mode);
    483 
    484  // interrupt methods
    485 
    491  void setDio1Action(void (*func)(void));
    492 
    496  void clearDio1Action();
    497 
    510  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    511 
    519  int16_t startReceive(uint32_t timeout = SX126X_RX_TIMEOUT_INF);
    520 
    531  int16_t startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod);
    532 
    544  int16_t startReceiveDutyCycleAuto(uint16_t senderPreambleLength = 0, uint16_t minSymbols = 8);
    545 
    555  int16_t readData(uint8_t* data, size_t len) override;
    556 
    557  // configuration methods
    558 
    566  int16_t setBandwidth(float bw);
    567 
    575  int16_t setSpreadingFactor(uint8_t sf);
    576 
    584  int16_t setCodingRate(uint8_t cr);
    585 
    595  int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits = 0x44);
    596 
    604  int16_t setCurrentLimit(float currentLimit);
    605 
    611  float getCurrentLimit();
    612 
    620  int16_t setPreambleLength(uint16_t preambleLength);
    621 
    629  int16_t setFrequencyDeviation(float freqDev) override;
    630 
    638  int16_t setBitRate(float br);
    639 
    647  int16_t setRxBandwidth(float rxBw);
    648 
    658  int16_t setDataShaping(uint8_t sh) override;
    659 
    669  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
    670 
    680  int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen);
    681 
    689  int16_t setNodeAddress(uint8_t nodeAddr);
    690 
    698  int16_t setBroadcastAddress(uint8_t broadAddr);
    699 
    705  int16_t disableAddressFiltering();
    706 
    720  int16_t setCRC(uint8_t len, uint16_t initial = 0x1D0F, uint16_t polynomial = 0x1021, bool inverted = true);
    721 
    731  int16_t setWhitening(bool enabled, uint16_t initial = 0x0100);
    732 
    740  int16_t setTCXO(float voltage, uint32_t delay = 5000);
    741 
    747  int16_t setDio2AsRfSwitch(bool enable = true);
    748 
    754  float getDataRate() const;
    755 
    761  float getRSSI();
    762 
    768  float getSNR();
    769 
    777  size_t getPacketLength(bool update = true) override;
    778 
    786  int16_t fixedPacketLengthMode(uint8_t len = SX126X_MAX_PACKET_LENGTH);
    787 
    795  int16_t variablePacketLengthMode(uint8_t maxLen = SX126X_MAX_PACKET_LENGTH);
    796 
    804  uint32_t getTimeOnAir(size_t len);
    805 
    811  int16_t implicitHeader(size_t len);
    812 
    820  int16_t explicitHeader();
    821 
    827  int16_t setRegulatorLDO();
    828 
    834  int16_t setRegulatorDCDC();
    835 
    843  int16_t setEncoding(uint8_t encoding) override;
    844 
    853  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    854 
    863  int16_t forceLDRO(bool enable);
    864 
    871  int16_t autoLDRO();
    872 
    873 #ifndef RADIOLIB_GODMODE
    874  protected:
    875 #endif
    876  // SX126x SPI command implementations
    877  int16_t setTx(uint32_t timeout = 0);
    878  int16_t setRx(uint32_t timeout);
    879  int16_t setCad();
    880  int16_t setPaConfig(uint8_t paDutyCycle, uint8_t deviceSel, uint8_t hpMax = SX126X_PA_CONFIG_HP_MAX, uint8_t paLut = SX126X_PA_CONFIG_PA_LUT);
    881  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
    882  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
    883  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
    884  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
    885  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX126X_IRQ_NONE, uint16_t dio3Mask = SX126X_IRQ_NONE);
    886  uint16_t getIrqStatus();
    887  int16_t clearIrqStatus(uint16_t clearIrqParams = SX126X_IRQ_ALL);
    888  int16_t setRfFrequency(uint32_t frf);
    889  int16_t calibrateImage(uint8_t* data);
    890  uint8_t getPacketType();
    891  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX126X_PA_RAMP_200U);
    892  int16_t setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, uint8_t ldro);
    893  int16_t setModulationParamsFSK(uint32_t br, uint8_t pulseShape, uint8_t rxBw, uint32_t freqDev);
    894  int16_t setPacketParams(uint16_t preambleLength, uint8_t crcType, uint8_t payloadLength, uint8_t headerType, uint8_t invertIQ = SX126X_LORA_IQ_STANDARD);
    895  int16_t setPacketParamsFSK(uint16_t preambleLength, uint8_t crcType, uint8_t syncWordLength, uint8_t addrComp, uint8_t whitening, uint8_t packetType = SX126X_GFSK_PACKET_VARIABLE, uint8_t payloadLength = 0xFF, uint8_t preambleDetectorLength = SX126X_GFSK_PREAMBLE_DETECT_16);
    896  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
    897  int16_t setRegulatorMode(uint8_t mode);
    898  uint8_t getStatus();
    899  uint32_t getPacketStatus();
    900  uint16_t getDeviceErrors();
    901  int16_t clearDeviceErrors();
    902 
    903  int16_t startReceiveCommon();
    904  int16_t setFrequencyRaw(float freq);
    905  int16_t setPacketMode(uint8_t mode, uint8_t len);
    906  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
    907 
    908  // fixes to errata
    909  int16_t fixSensitivity();
    910  int16_t fixPaClamping();
    911  int16_t fixImplicitTimeout();
    912  int16_t fixInvertedIQ(uint8_t iqConfig);
    913 
    914 #ifndef RADIOLIB_GODMODE
    915  private:
    916 #endif
    917  Module* _mod;
    918 
    919  uint8_t _bw = 0, _sf = 0, _cr = 0, _ldro = 0, _crcType = 0, _headerType = 0;
    920  uint16_t _preambleLength = 0;
    921  float _bwKhz = 0;
    922  bool _ldroAuto = true;
    923 
    924  uint32_t _br = 0, _freqDev = 0;
    925  uint8_t _rxBw = 0, _pulseShape = 0, _crcTypeFSK = 0, _syncWordLength = 0, _addrComp = 0, _whitening = 0, _packetType = 0;
    926  uint16_t _preambleLengthFSK = 0;
    927  float _rxBwKhz = 0;
    928 
    929  float _dataRate = 0;
    930 
    931  uint32_t _tcxoDelay = 0;
    932 
    933  size_t _implicitLen = 0;
    934 
    935  int16_t config(uint8_t modem);
    936 
    937  // common low-level SPI interface
    938  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    939  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    940  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    941  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
    942  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
    943 };
    944 
    945 #endif
    946 
    947 #endif
    SX126x::setRfSwitchPins
    void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
    Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
    Definition: SX126x.cpp:1151
    SX126x::setBroadcastAddress
    int16_t setBroadcastAddress(uint8_t broadAddr)
    Sets broadcast address. Calling this method will also enable address filtering for node and broadcast...
    Definition: SX126x.cpp:930
    SX126x::setSyncWord
    int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits=0x44)
    Sets LoRa sync word.
    Definition: SX126x.cpp:682
    SX126x::getCurrentLimit
    float getCurrentLimit()
    Reads current protection limit.
    Definition: SX126x.cpp:706
    @@ -125,6 +101,7 @@ $(document).ready(function(){initNavTree('_s_x126x_8h_source.html','');});
    SX126x::standby
    int16_t standby() override
    Sets the module to standby mode (overload for PhysicalLayer compatibility, uses 13 MHz RC oscillator)...
    Definition: SX126x.cpp:392
    SX126x::scanChannel
    int16_t scanChannel()
    Performs scan for LoRa transmission in the current channel. Detects both preamble and payload...
    Definition: SX126x.cpp:331
    SX126x::variablePacketLengthMode
    int16_t variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)
    Set modem in variable packet length mode. Available in FSK mode only.
    Definition: SX126x.cpp:1092
    +
    SX126x::getDataRate
    float getDataRate() const
    Gets effective data rate for the last transmitted packet. The value is calculated only for payload by...
    Definition: SX126x.cpp:1054
    SX126x::clearDio1Action
    void clearDio1Action()
    Clears interrupt service routine to call when DIO1 activates.
    Definition: SX126x.cpp:408
    SX126x::startTransmit
    int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
    Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
    Definition: SX126x.cpp:412
    SX126x::reset
    int16_t reset(bool verify=true)
    Reset method. Will reset the chip to the default state using RST pin.
    Definition: SX126x.cpp:158
    @@ -146,7 +123,6 @@ $(document).ready(function(){initNavTree('_s_x126x_8h_source.html','');});
    SX126x::autoLDRO
    int16_t autoLDRO()
    Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
    Definition: SX126x.cpp:1167
    SX126x::setCodingRate
    int16_t setCodingRate(uint8_t cr)
    Sets LoRa coding rate denominator. Allowed values range from 5 to 8.
    Definition: SX126x.cpp:669
    SX126x::setEncoding
    int16_t setEncoding(uint8_t encoding) override
    Sets transmission encoding. Available in FSK mode only. Serves only as alias for PhysicalLayer compat...
    Definition: SX126x.cpp:1147
    -
    SX126x::getDataRate
    float getDataRate() const
    Gets effective data rate for the last transmitted packet. The value is calculated only for payload by...
    Definition: SX126x.cpp:1054
    SX126x::transmitDirect
    int16_t transmitDirect(uint32_t frf=0) override
    Starts direct mode transmission.
    Definition: SX126x.cpp:307
    PhysicalLayer
    Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
    Definition: PhysicalLayer.h:13
    SX126x::getTimeOnAir
    uint32_t getTimeOnAir(size_t len)
    Get expected time-on-air for a given size of payload.
    Definition: SX126x.cpp:1096
    @@ -175,7 +151,7 @@ $(document).ready(function(){initNavTree('_s_x126x_8h_source.html','');});
  • src
  • modules
  • SX126x
  • SX126x.h
  • Generated by - doxygen 1.8.11
    • + doxygen 1.8.13
    diff --git a/_s_x1272_8h_source.html b/_s_x1272_8h_source.html index c3b69d62..56b5d033 100644 --- a/_s_x1272_8h_source.html +++ b/_s_x1272_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1272.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
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    diff --git a/_s_x1273_8h_source.html b/_s_x1273_8h_source.html index 2180ae1d..7ac9d940 100644 --- a/_s_x1273_8h_source.html +++ b/_s_x1273_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1273.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
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    diff --git a/_s_x1276_8h_source.html b/_s_x1276_8h_source.html index e598a3f3..97da2bd2 100644 --- a/_s_x1276_8h_source.html +++ b/_s_x1276_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1276.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
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    diff --git a/_s_x1277_8h_source.html b/_s_x1277_8h_source.html index f9b6acb4..4016a4bf 100644 --- a/_s_x1277_8h_source.html +++ b/_s_x1277_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1277.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
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    diff --git a/_s_x1278_8h_source.html b/_s_x1278_8h_source.html index 418a9977..7f5e94c1 100644 --- a/_s_x1278_8h_source.html +++ b/_s_x1278_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1278.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
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    diff --git a/_s_x1279_8h_source.html b/_s_x1279_8h_source.html index fcfe2831..7d7e63f1 100644 --- a/_s_x1279_8h_source.html +++ b/_s_x1279_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX1279.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    diff --git a/_s_x127x_8h_source.html b/_s_x127x_8h_source.html index d5ea7796..f9b022f0 100644 --- a/_s_x127x_8h_source.html +++ b/_s_x127x_8h_source.html @@ -3,7 +3,8 @@ - + + RadioLib: src/modules/SX127x/SX127x.h Source File @@ -14,14 +15,10 @@ - @@ -40,40 +37,19 @@
    - + - - + + + +
    -
    1 #if !defined(_RADIOLIB_SX127X_H)
    2 #define _RADIOLIB_SX127X_H
    3 
    4 #include "../../TypeDef.h"
    5 
    6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
    7 
    8 #include "../../Module.h"
    9 
    10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
    11 
    12 // SX127x physical layer properties
    13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
    14 #define SX127X_MAX_PACKET_LENGTH 255
    15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
    16 #define SX127X_CRYSTAL_FREQ 32.0
    17 #define SX127X_DIV_EXPONENT 19
    18 
    19 // SX127x series common LoRa registers
    20 #define SX127X_REG_FIFO 0x00
    21 #define SX127X_REG_OP_MODE 0x01
    22 #define SX127X_REG_FRF_MSB 0x06
    23 #define SX127X_REG_FRF_MID 0x07
    24 #define SX127X_REG_FRF_LSB 0x08
    25 #define SX127X_REG_PA_CONFIG 0x09
    26 #define SX127X_REG_PA_RAMP 0x0A
    27 #define SX127X_REG_OCP 0x0B
    28 #define SX127X_REG_LNA 0x0C
    29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
    30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
    31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
    32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
    33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
    34 #define SX127X_REG_IRQ_FLAGS 0x12
    35 #define SX127X_REG_RX_NB_BYTES 0x13
    36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
    37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
    38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
    39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
    40 #define SX127X_REG_MODEM_STAT 0x18
    41 #define SX127X_REG_PKT_SNR_VALUE 0x19
    42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
    43 #define SX127X_REG_RSSI_VALUE 0x1B
    44 #define SX127X_REG_HOP_CHANNEL 0x1C
    45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
    46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
    47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
    48 #define SX127X_REG_PREAMBLE_MSB 0x20
    49 #define SX127X_REG_PREAMBLE_LSB 0x21
    50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
    51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
    52 #define SX127X_REG_HOP_PERIOD 0x24
    53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
    54 #define SX127X_REG_FEI_MSB 0x28
    55 #define SX127X_REG_FEI_MID 0x29
    56 #define SX127X_REG_FEI_LSB 0x2A
    57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
    58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
    59 #define SX127X_REG_INVERT_IQ 0x33
    60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
    61 #define SX127X_REG_SYNC_WORD 0x39
    62 #define SX127X_REG_DIO_MAPPING_1 0x40
    63 #define SX127X_REG_DIO_MAPPING_2 0x41
    64 #define SX127X_REG_VERSION 0x42
    65 
    66 // SX127x common LoRa modem settings
    67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
    68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
    69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
    70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
    71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
    72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
    73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
    74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
    75 #define SX127X_TX 0b00000011 // 2 0 transmit
    76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
    77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
    78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
    79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
    80 
    81 // SX127X_REG_PA_CONFIG
    82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
    83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
    84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
    85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
    86 
    87 // SX127X_REG_OCP
    88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
    89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
    90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
    91 
    92 // SX127X_REG_LNA
    93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
    94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
    95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
    96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
    97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
    98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
    99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
    100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
    101 
    102 // SX127X_REG_MODEM_CONFIG_2
    103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
    104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
    105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
    106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
    107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
    108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
    109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
    110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
    111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
    112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
    113 
    114 // SX127X_REG_SYMB_TIMEOUT_LSB
    115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
    116 
    117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
    118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
    119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
    120 
    121 // SX127X_REG_DETECT_OPTIMIZE
    122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
    123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
    124 
    125 // SX127X_REG_DETECTION_THRESHOLD
    126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
    127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
    128 
    129 // SX127X_REG_PA_DAC
    130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
    131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
    132 
    133 // SX127X_REG_HOP_PERIOD
    134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
    135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
    136 
    137 // SX127X_REG_DIO_MAPPING_1
    138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
    139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
    140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
    141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
    142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
    143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
    144 
    145 // SX127X_REG_IRQ_FLAGS
    146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
    147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
    148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
    149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
    150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
    151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
    152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
    153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
    154 
    155 // SX127X_REG_IRQ_FLAGS_MASK
    156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
    157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
    158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
    159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
    160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
    161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
    162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
    163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
    164 
    165 // SX127X_REG_FIFO_TX_BASE_ADDR
    166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
    167 
    168 // SX127X_REG_FIFO_RX_BASE_ADDR
    169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
    170 
    171 // SX127X_REG_SYNC_WORD
    172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
    173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
    174 
    175 // SX127x series common FSK registers
    176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
    177 #define SX127X_REG_BITRATE_MSB 0x02
    178 #define SX127X_REG_BITRATE_LSB 0x03
    179 #define SX127X_REG_FDEV_MSB 0x04
    180 #define SX127X_REG_FDEV_LSB 0x05
    181 #define SX127X_REG_RX_CONFIG 0x0D
    182 #define SX127X_REG_RSSI_CONFIG 0x0E
    183 #define SX127X_REG_RSSI_COLLISION 0x0F
    184 #define SX127X_REG_RSSI_THRESH 0x10
    185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
    186 #define SX127X_REG_RX_BW 0x12
    187 #define SX127X_REG_AFC_BW 0x13
    188 #define SX127X_REG_OOK_PEAK 0x14
    189 #define SX127X_REG_OOK_FIX 0x15
    190 #define SX127X_REG_OOK_AVG 0x16
    191 #define SX127X_REG_AFC_FEI 0x1A
    192 #define SX127X_REG_AFC_MSB 0x1B
    193 #define SX127X_REG_AFC_LSB 0x1C
    194 #define SX127X_REG_FEI_MSB_FSK 0x1D
    195 #define SX127X_REG_FEI_LSB_FSK 0x1E
    196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
    197 #define SX127X_REG_RX_TIMEOUT_1 0x20
    198 #define SX127X_REG_RX_TIMEOUT_2 0x21
    199 #define SX127X_REG_RX_TIMEOUT_3 0x22
    200 #define SX127X_REG_RX_DELAY 0x23
    201 #define SX127X_REG_OSC 0x24
    202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
    203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
    204 #define SX127X_REG_SYNC_CONFIG 0x27
    205 #define SX127X_REG_SYNC_VALUE_1 0x28
    206 #define SX127X_REG_SYNC_VALUE_2 0x29
    207 #define SX127X_REG_SYNC_VALUE_3 0x2A
    208 #define SX127X_REG_SYNC_VALUE_4 0x2B
    209 #define SX127X_REG_SYNC_VALUE_5 0x2C
    210 #define SX127X_REG_SYNC_VALUE_6 0x2D
    211 #define SX127X_REG_SYNC_VALUE_7 0x2E
    212 #define SX127X_REG_SYNC_VALUE_8 0x2F
    213 #define SX127X_REG_PACKET_CONFIG_1 0x30
    214 #define SX127X_REG_PACKET_CONFIG_2 0x31
    215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
    216 #define SX127X_REG_NODE_ADRS 0x33
    217 #define SX127X_REG_BROADCAST_ADRS 0x34
    218 #define SX127X_REG_FIFO_THRESH 0x35
    219 #define SX127X_REG_SEQ_CONFIG_1 0x36
    220 #define SX127X_REG_SEQ_CONFIG_2 0x37
    221 #define SX127X_REG_TIMER_RESOL 0x38
    222 #define SX127X_REG_TIMER1_COEF 0x39
    223 #define SX127X_REG_TIMER2_COEF 0x3A
    224 #define SX127X_REG_IMAGE_CAL 0x3B
    225 #define SX127X_REG_TEMP 0x3C
    226 #define SX127X_REG_LOW_BAT 0x3D
    227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
    228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
    229 
    230 // SX127x common FSK modem settings
    231 // SX127X_REG_OP_MODE
    232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
    233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
    234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
    235 
    236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
    237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
    238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
    239 
    240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
    241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
    242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
    243 
    244 // SX127X_REG_RX_CONFIG
    245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
    246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
    247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
    248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
    249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
    250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
    251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
    252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
    253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
    254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
    255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
    256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
    257 
    258 // SX127X_REG_RSSI_CONFIG
    259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
    260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
    261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
    262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
    263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
    264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
    265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
    266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
    267 
    268 // SX127X_REG_RSSI_COLLISION
    269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
    270 
    271 // SX127X_REG_RSSI_THRESH
    272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
    273 
    274 // SX127X_REG_RX_BW
    275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
    276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
    277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
    278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
    279 
    280 // SX127X_REG_AFC_BW
    281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
    282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
    283 
    284 // SX127X_REG_OOK_PEAK
    285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
    286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
    287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
    288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
    289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
    290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
    291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
    292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
    293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
    294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
    295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
    296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
    297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
    298 
    299 // SX127X_REG_OOK_FIX
    300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
    301 
    302 // SX127X_REG_OOK_AVG
    303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
    304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
    305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
    306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
    307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
    308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
    309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
    310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
    311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
    312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
    313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
    314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
    315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
    316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
    317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
    318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
    319 
    320 // SX127X_REG_AFC_FEI
    321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
    322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
    323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
    324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
    325 
    326 // SX127X_REG_PREAMBLE_DETECT
    327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
    328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
    329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
    330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
    331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
    332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
    333 
    334 // SX127X_REG_RX_TIMEOUT_1
    335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
    336 
    337 // SX127X_REG_RX_TIMEOUT_2
    338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
    339 
    340 // SX127X_REG_RX_TIMEOUT_3
    341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
    342 
    343 // SX127X_REG_OSC
    344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
    345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
    346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
    347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
    348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
    349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
    350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
    351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
    352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
    353 
    354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
    355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
    356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
    357 
    358 // SX127X_REG_SYNC_CONFIG
    359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
    360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
    361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
    362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
    363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
    364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
    365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
    366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
    367 
    368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
    369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
    370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
    371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
    372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
    373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
    374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
    375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
    376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
    377 
    378 // SX127X_REG_PACKET_CONFIG_1
    379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
    380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
    381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
    382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
    383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
    384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
    385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
    386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
    387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
    388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
    389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
    390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
    391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
    392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
    393 
    394 // SX127X_REG_PACKET_CONFIG_2
    395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
    396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
    397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
    398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
    399 
    400 // SX127X_REG_FIFO_THRESH
    401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
    402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
    403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
    404 
    405 // SX127X_REG_SEQ_CONFIG_1
    406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
    407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
    408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
    409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
    410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
    411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
    412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
    413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
    414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
    415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
    416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
    417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
    418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
    419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
    420 
    421 // SX127X_REG_SEQ_CONFIG_2
    422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
    423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
    424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
    425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
    426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
    427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
    428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
    429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
    430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
    431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
    432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
    433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
    434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
    435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
    436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
    437 
    438 // SX127X_REG_TIMER_RESOL
    439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
    440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
    441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
    442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
    443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
    444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
    445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
    446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
    447 
    448 // SX127X_REG_TIMER1_COEF
    449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
    450 
    451 // SX127X_REG_TIMER2_COEF
    452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
    453 
    454 // SX127X_REG_IMAGE_CAL
    455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
    456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
    457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
    458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
    459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
    460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
    461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
    462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
    463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
    464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
    465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
    466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
    467 
    468 // SX127X_REG_LOW_BAT
    469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
    470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
    471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
    472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
    473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
    474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
    475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
    476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
    477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
    478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
    479 
    480 // SX127X_REG_IRQ_FLAGS_1
    481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
    482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
    483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
    484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
    485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
    486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
    487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
    488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
    489 
    490 // SX127X_REG_IRQ_FLAGS_2
    491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
    492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
    493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
    494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
    495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
    496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
    497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
    498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
    499 
    500 // SX127X_REG_DIO_MAPPING_1
    501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
    502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
    503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
    504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
    505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
    506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
    507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
    508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
    509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
    510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
    511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
    512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
    513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
    514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
    515 
    516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
    517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
    518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
    519 
    520 // SX1272_REG_TCXO + SX1278_REG_TCXO
    521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
    522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
    523 
    524 // SX1272_REG_PLL + SX1278_REG_PLL
    525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
    526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
    527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
    528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
    529 
    536 class SX127x: public PhysicalLayer {
    537  public:
    538  // introduce PhysicalLayer overloads
    539  using PhysicalLayer::transmit;
    540  using PhysicalLayer::receive;
    541  using PhysicalLayer::startTransmit;
    542  using PhysicalLayer::readData;
    543 
    544  // constructor
    545 
    551  SX127x(Module* mod);
    552 
    553  // basic methods
    554 
    566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
    567 
    571  virtual void reset() = 0;
    572 
    590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
    591 
    604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    605 
    616  int16_t receive(uint8_t* data, size_t len) override;
    617 
    623  int16_t scanChannel();
    624 
    631  int16_t sleep();
    632 
    638  int16_t standby() override;
    639 
    648  int16_t transmitDirect(uint32_t frf = 0) override;
    649 
    656  int16_t receiveDirect() override;
    657 
    663  int16_t packetMode();
    664 
    665  // interrupt methods
    666 
    672  void setDio0Action(void (*func)(void));
    673 
    677  void clearDio0Action();
    678 
    684  void setDio1Action(void (*func)(void));
    685 
    689  void clearDio1Action();
    690 
    702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    703 
    713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
    714 
    724  int16_t readData(uint8_t* data, size_t len) override;
    725 
    726 
    727  // configuration methods
    728 
    736  int16_t setSyncWord(uint8_t syncWord);
    737 
    745  int16_t setCurrentLimit(uint8_t currentLimit);
    746 
    754  int16_t setPreambleLength(uint16_t preambleLength);
    755 
    763  float getFrequencyError(bool autoCorrect = false);
    764 
    770  float getSNR();
    771 
    777  float getDataRate() const;
    778 
    786  int16_t setBitRate(float br);
    787 
    795  int16_t setFrequencyDeviation(float freqDev) override;
    796 
    804  int16_t setRxBandwidth(float rxBw);
    805 
    815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
    816 
    824  int16_t setNodeAddress(uint8_t nodeAddr);
    825 
    833  int16_t setBroadcastAddress(uint8_t broadAddr);
    834 
    840  int16_t disableAddressFiltering();
    841 
    849  int16_t setOOK(bool enableOOK);
    850 
    858  size_t getPacketLength(bool update = true) override;
    859 
    867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
    868 
    876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
    877 
    888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
    889 
    898  int16_t setEncoding(uint8_t encoding) override;
    899 
    907  uint16_t getIRQFlags();
    908 
    914  uint8_t getModemStatus();
    915 
    922  int8_t getTempRaw();
    923 
    932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    933 
    934 #ifndef RADIOLIB_GODMODE
    935  protected:
    936 #endif
    937  Module* _mod;
    938 
    939  float _freq = 0;
    940  float _bw = 0;
    941  uint8_t _sf = 0;
    942  uint8_t _cr = 0;
    943  float _br = 0;
    944  float _rxBw = 0;
    945  bool _ook = false;
    946 
    947  int16_t setFrequencyRaw(float newFreq);
    948  int16_t config();
    949  int16_t configFSK();
    950  int16_t getActiveModem();
    951  int16_t directMode();
    952  int16_t setPacketMode(uint8_t mode, uint8_t len);
    953 
    954 #ifndef RADIOLIB_GODMODE
    955  private:
    956 #endif
    957  float _dataRate = 0;
    958  size_t _packetLength = 0;
    959  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
    960  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
    961 
    962  bool findChip(uint8_t ver);
    963  int16_t setMode(uint8_t mode);
    964  int16_t setActiveModem(uint8_t modem);
    965  void clearIRQFlags();
    966  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
    967 };
    968 
    969 #endif
    970 
    971 #endif
    SX127x::getDataRate
    float getDataRate() const
    Get data rate of the latest transmitted packet.
    Definition: SX127x.cpp:659
    -
    SX127x::setRSSIConfig
    int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
    Sets RSSI measurement configuration in FSK mode.
    Definition: SX127x.cpp:890
    +
    1 #if !defined(_RADIOLIB_SX127X_H)
    2 #define _RADIOLIB_SX127X_H
    3 
    4 #include "../../TypeDef.h"
    5 
    6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
    7 
    8 #include "../../Module.h"
    9 
    10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
    11 
    12 // SX127x physical layer properties
    13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
    14 #define SX127X_MAX_PACKET_LENGTH 255
    15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
    16 #define SX127X_CRYSTAL_FREQ 32.0
    17 #define SX127X_DIV_EXPONENT 19
    18 
    19 // SX127x series common LoRa registers
    20 #define SX127X_REG_FIFO 0x00
    21 #define SX127X_REG_OP_MODE 0x01
    22 #define SX127X_REG_FRF_MSB 0x06
    23 #define SX127X_REG_FRF_MID 0x07
    24 #define SX127X_REG_FRF_LSB 0x08
    25 #define SX127X_REG_PA_CONFIG 0x09
    26 #define SX127X_REG_PA_RAMP 0x0A
    27 #define SX127X_REG_OCP 0x0B
    28 #define SX127X_REG_LNA 0x0C
    29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
    30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
    31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
    32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
    33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
    34 #define SX127X_REG_IRQ_FLAGS 0x12
    35 #define SX127X_REG_RX_NB_BYTES 0x13
    36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
    37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
    38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
    39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
    40 #define SX127X_REG_MODEM_STAT 0x18
    41 #define SX127X_REG_PKT_SNR_VALUE 0x19
    42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
    43 #define SX127X_REG_RSSI_VALUE 0x1B
    44 #define SX127X_REG_HOP_CHANNEL 0x1C
    45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
    46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
    47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
    48 #define SX127X_REG_PREAMBLE_MSB 0x20
    49 #define SX127X_REG_PREAMBLE_LSB 0x21
    50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
    51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
    52 #define SX127X_REG_HOP_PERIOD 0x24
    53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
    54 #define SX127X_REG_FEI_MSB 0x28
    55 #define SX127X_REG_FEI_MID 0x29
    56 #define SX127X_REG_FEI_LSB 0x2A
    57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
    58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
    59 #define SX127X_REG_INVERT_IQ 0x33
    60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
    61 #define SX127X_REG_SYNC_WORD 0x39
    62 #define SX127X_REG_DIO_MAPPING_1 0x40
    63 #define SX127X_REG_DIO_MAPPING_2 0x41
    64 #define SX127X_REG_VERSION 0x42
    65 
    66 // SX127x common LoRa modem settings
    67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
    68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
    69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
    70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
    71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
    72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
    73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
    74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
    75 #define SX127X_TX 0b00000011 // 2 0 transmit
    76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
    77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
    78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
    79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
    80 
    81 // SX127X_REG_PA_CONFIG
    82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
    83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
    84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
    85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
    86 
    87 // SX127X_REG_OCP
    88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
    89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
    90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
    91 
    92 // SX127X_REG_LNA
    93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
    94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
    95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
    96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
    97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
    98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
    99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
    100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
    101 
    102 // SX127X_REG_MODEM_CONFIG_2
    103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
    104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
    105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
    106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
    107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
    108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
    109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
    110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
    111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
    112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
    113 
    114 // SX127X_REG_SYMB_TIMEOUT_LSB
    115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
    116 
    117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
    118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
    119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
    120 
    121 // SX127X_REG_DETECT_OPTIMIZE
    122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
    123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
    124 
    125 // SX127X_REG_DETECTION_THRESHOLD
    126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
    127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
    128 
    129 // SX127X_REG_PA_DAC
    130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
    131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
    132 
    133 // SX127X_REG_HOP_PERIOD
    134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
    135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
    136 
    137 // SX127X_REG_DIO_MAPPING_1
    138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
    139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
    140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
    141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
    142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
    143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
    144 
    145 // SX127X_REG_IRQ_FLAGS
    146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
    147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
    148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
    149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
    150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
    151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
    152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
    153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
    154 
    155 // SX127X_REG_IRQ_FLAGS_MASK
    156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
    157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
    158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
    159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
    160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
    161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
    162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
    163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
    164 
    165 // SX127X_REG_FIFO_TX_BASE_ADDR
    166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
    167 
    168 // SX127X_REG_FIFO_RX_BASE_ADDR
    169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
    170 
    171 // SX127X_REG_SYNC_WORD
    172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
    173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
    174 
    175 // SX127x series common FSK registers
    176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
    177 #define SX127X_REG_BITRATE_MSB 0x02
    178 #define SX127X_REG_BITRATE_LSB 0x03
    179 #define SX127X_REG_FDEV_MSB 0x04
    180 #define SX127X_REG_FDEV_LSB 0x05
    181 #define SX127X_REG_RX_CONFIG 0x0D
    182 #define SX127X_REG_RSSI_CONFIG 0x0E
    183 #define SX127X_REG_RSSI_COLLISION 0x0F
    184 #define SX127X_REG_RSSI_THRESH 0x10
    185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
    186 #define SX127X_REG_RX_BW 0x12
    187 #define SX127X_REG_AFC_BW 0x13
    188 #define SX127X_REG_OOK_PEAK 0x14
    189 #define SX127X_REG_OOK_FIX 0x15
    190 #define SX127X_REG_OOK_AVG 0x16
    191 #define SX127X_REG_AFC_FEI 0x1A
    192 #define SX127X_REG_AFC_MSB 0x1B
    193 #define SX127X_REG_AFC_LSB 0x1C
    194 #define SX127X_REG_FEI_MSB_FSK 0x1D
    195 #define SX127X_REG_FEI_LSB_FSK 0x1E
    196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
    197 #define SX127X_REG_RX_TIMEOUT_1 0x20
    198 #define SX127X_REG_RX_TIMEOUT_2 0x21
    199 #define SX127X_REG_RX_TIMEOUT_3 0x22
    200 #define SX127X_REG_RX_DELAY 0x23
    201 #define SX127X_REG_OSC 0x24
    202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
    203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
    204 #define SX127X_REG_SYNC_CONFIG 0x27
    205 #define SX127X_REG_SYNC_VALUE_1 0x28
    206 #define SX127X_REG_SYNC_VALUE_2 0x29
    207 #define SX127X_REG_SYNC_VALUE_3 0x2A
    208 #define SX127X_REG_SYNC_VALUE_4 0x2B
    209 #define SX127X_REG_SYNC_VALUE_5 0x2C
    210 #define SX127X_REG_SYNC_VALUE_6 0x2D
    211 #define SX127X_REG_SYNC_VALUE_7 0x2E
    212 #define SX127X_REG_SYNC_VALUE_8 0x2F
    213 #define SX127X_REG_PACKET_CONFIG_1 0x30
    214 #define SX127X_REG_PACKET_CONFIG_2 0x31
    215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
    216 #define SX127X_REG_NODE_ADRS 0x33
    217 #define SX127X_REG_BROADCAST_ADRS 0x34
    218 #define SX127X_REG_FIFO_THRESH 0x35
    219 #define SX127X_REG_SEQ_CONFIG_1 0x36
    220 #define SX127X_REG_SEQ_CONFIG_2 0x37
    221 #define SX127X_REG_TIMER_RESOL 0x38
    222 #define SX127X_REG_TIMER1_COEF 0x39
    223 #define SX127X_REG_TIMER2_COEF 0x3A
    224 #define SX127X_REG_IMAGE_CAL 0x3B
    225 #define SX127X_REG_TEMP 0x3C
    226 #define SX127X_REG_LOW_BAT 0x3D
    227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
    228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
    229 
    230 // SX127x common FSK modem settings
    231 // SX127X_REG_OP_MODE
    232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
    233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
    234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
    235 
    236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
    237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
    238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
    239 
    240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
    241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
    242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
    243 
    244 // SX127X_REG_RX_CONFIG
    245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
    246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
    247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
    248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
    249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
    250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
    251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
    252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
    253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
    254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
    255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
    256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
    257 
    258 // SX127X_REG_RSSI_CONFIG
    259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
    260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
    261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
    262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
    263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
    264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
    265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
    266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
    267 
    268 // SX127X_REG_RSSI_COLLISION
    269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
    270 
    271 // SX127X_REG_RSSI_THRESH
    272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
    273 
    274 // SX127X_REG_RX_BW
    275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
    276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
    277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
    278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
    279 
    280 // SX127X_REG_AFC_BW
    281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
    282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
    283 
    284 // SX127X_REG_OOK_PEAK
    285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
    286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
    287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
    288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
    289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
    290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
    291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
    292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
    293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
    294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
    295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
    296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
    297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
    298 
    299 // SX127X_REG_OOK_FIX
    300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
    301 
    302 // SX127X_REG_OOK_AVG
    303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
    304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
    305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
    306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
    307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
    308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
    309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
    310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
    311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
    312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
    313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
    314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
    315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
    316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
    317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
    318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
    319 
    320 // SX127X_REG_AFC_FEI
    321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
    322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
    323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
    324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
    325 
    326 // SX127X_REG_PREAMBLE_DETECT
    327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
    328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
    329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
    330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
    331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
    332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
    333 
    334 // SX127X_REG_RX_TIMEOUT_1
    335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
    336 
    337 // SX127X_REG_RX_TIMEOUT_2
    338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
    339 
    340 // SX127X_REG_RX_TIMEOUT_3
    341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
    342 
    343 // SX127X_REG_OSC
    344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
    345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
    346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
    347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
    348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
    349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
    350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
    351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
    352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
    353 
    354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
    355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
    356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
    357 
    358 // SX127X_REG_SYNC_CONFIG
    359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
    360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
    361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
    362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
    363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
    364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
    365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
    366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
    367 
    368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
    369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
    370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
    371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
    372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
    373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
    374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
    375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
    376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
    377 
    378 // SX127X_REG_PACKET_CONFIG_1
    379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
    380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
    381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
    382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
    383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
    384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
    385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
    386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
    387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
    388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
    389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
    390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
    391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
    392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
    393 
    394 // SX127X_REG_PACKET_CONFIG_2
    395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
    396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
    397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
    398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
    399 
    400 // SX127X_REG_FIFO_THRESH
    401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
    402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
    403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
    404 
    405 // SX127X_REG_SEQ_CONFIG_1
    406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
    407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
    408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
    409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
    410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
    411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
    412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
    413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
    414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
    415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
    416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
    417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
    418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
    419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
    420 
    421 // SX127X_REG_SEQ_CONFIG_2
    422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
    423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
    424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
    425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
    426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
    427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
    428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
    429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
    430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
    431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
    432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
    433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
    434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
    435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
    436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
    437 
    438 // SX127X_REG_TIMER_RESOL
    439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
    440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
    441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
    442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
    443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
    444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
    445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
    446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
    447 
    448 // SX127X_REG_TIMER1_COEF
    449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
    450 
    451 // SX127X_REG_TIMER2_COEF
    452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
    453 
    454 // SX127X_REG_IMAGE_CAL
    455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
    456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
    457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
    458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
    459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
    460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
    461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
    462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
    463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
    464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
    465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
    466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
    467 
    468 // SX127X_REG_LOW_BAT
    469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
    470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
    471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
    472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
    473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
    474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
    475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
    476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
    477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
    478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
    479 
    480 // SX127X_REG_IRQ_FLAGS_1
    481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
    482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
    483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
    484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
    485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
    486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
    487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
    488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
    489 
    490 // SX127X_REG_IRQ_FLAGS_2
    491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
    492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
    493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
    494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
    495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
    496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
    497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
    498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
    499 
    500 // SX127X_REG_DIO_MAPPING_1
    501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
    502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
    503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
    504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
    505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
    506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
    507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
    508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
    509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
    510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
    511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
    512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
    513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
    514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
    515 
    516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
    517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
    518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
    519 
    520 // SX1272_REG_TCXO + SX1278_REG_TCXO
    521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
    522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
    523 
    524 // SX1272_REG_PLL + SX1278_REG_PLL
    525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
    526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
    527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
    528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
    529 
    536 class SX127x: public PhysicalLayer {
    537  public:
    538  // introduce PhysicalLayer overloads
    539  using PhysicalLayer::transmit;
    540  using PhysicalLayer::receive;
    541  using PhysicalLayer::startTransmit;
    542  using PhysicalLayer::readData;
    543 
    544  // constructor
    545 
    551  SX127x(Module* mod);
    552 
    553  // basic methods
    554 
    566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
    567 
    571  virtual void reset() = 0;
    572 
    590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
    591 
    604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    605 
    616  int16_t receive(uint8_t* data, size_t len) override;
    617 
    623  int16_t scanChannel();
    624 
    631  int16_t sleep();
    632 
    638  int16_t standby() override;
    639 
    648  int16_t transmitDirect(uint32_t frf = 0) override;
    649 
    656  int16_t receiveDirect() override;
    657 
    663  int16_t packetMode();
    664 
    665  // interrupt methods
    666 
    672  void setDio0Action(void (*func)(void));
    673 
    677  void clearDio0Action();
    678 
    684  void setDio1Action(void (*func)(void));
    685 
    689  void clearDio1Action();
    690 
    702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
    703 
    713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
    714 
    724  int16_t readData(uint8_t* data, size_t len) override;
    725 
    726 
    727  // configuration methods
    728 
    736  int16_t setSyncWord(uint8_t syncWord);
    737 
    745  int16_t setCurrentLimit(uint8_t currentLimit);
    746 
    754  int16_t setPreambleLength(uint16_t preambleLength);
    755 
    763  float getFrequencyError(bool autoCorrect = false);
    764 
    770  float getSNR();
    771 
    777  float getDataRate() const;
    778 
    786  int16_t setBitRate(float br);
    787 
    795  int16_t setFrequencyDeviation(float freqDev) override;
    796 
    804  int16_t setRxBandwidth(float rxBw);
    805 
    815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
    816 
    824  int16_t setNodeAddress(uint8_t nodeAddr);
    825 
    833  int16_t setBroadcastAddress(uint8_t broadAddr);
    834 
    840  int16_t disableAddressFiltering();
    841 
    849  int16_t setOOK(bool enableOOK);
    850 
    858  size_t getPacketLength(bool update = true) override;
    859 
    867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
    868 
    876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
    877 
    888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
    889 
    898  int16_t setEncoding(uint8_t encoding) override;
    899 
    907  uint16_t getIRQFlags();
    908 
    914  uint8_t getModemStatus();
    915 
    922  int8_t getTempRaw();
    923 
    932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
    933 
    934 #ifndef RADIOLIB_GODMODE
    935  protected:
    936 #endif
    937  Module* _mod;
    938 
    939  float _freq = 0;
    940  float _bw = 0;
    941  uint8_t _sf = 0;
    942  uint8_t _cr = 0;
    943  float _br = 0;
    944  float _rxBw = 0;
    945  bool _ook = false;
    946 
    947  int16_t setFrequencyRaw(float newFreq);
    948  int16_t config();
    949  int16_t configFSK();
    950  int16_t getActiveModem();
    951  int16_t directMode();
    952  int16_t setPacketMode(uint8_t mode, uint8_t len);
    953 
    954 #ifndef RADIOLIB_GODMODE
    955  private:
    956 #endif
    957  float _dataRate = 0;
    958  size_t _packetLength = 0;
    959  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
    960  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
    961 
    962  bool findChip(uint8_t ver);
    963  int16_t setMode(uint8_t mode);
    964  int16_t setActiveModem(uint8_t modem);
    965  void clearIRQFlags();
    966  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
    967 };
    968 
    969 #endif
    970 
    971 #endif
    SX127x::setRSSIConfig
    int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
    Sets RSSI measurement configuration in FSK mode.
    Definition: SX127x.cpp:890
    SX127x
    Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
    Definition: SX127x.h:536
    SX127x::getPacketLength
    size_t getPacketLength(bool update=true) override
    Query modem for the packet length of received payload.
    Definition: SX127x.cpp:854
    SX127x::readData
    int16_t readData(uint8_t *data, size_t len) override
    Reads data that was received after calling startReceive method. This method reads len characters...
    Definition: SX127x.cpp:480
    @@ -151,6 +126,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
    SX127x::disableAddressFiltering
    int16_t disableAddressFiltering()
    Disables FSK address filtering.
    Definition: SX127x.cpp:802
    SX127x::setBroadcastAddress
    int16_t setBroadcastAddress(uint8_t broadAddr)
    Sets FSK broadcast address. Calling this method will enable address filtering. Only available in FSK ...
    Definition: SX127x.cpp:788
    SX127x::setDio1Action
    void setDio1Action(void(*func)(void))
    Set interrupt service routine function to call when DIO1 activates.
    Definition: SX127x.cpp:405
    +
    SX127x::getDataRate
    float getDataRate() const
    Get data rate of the latest transmitted packet.
    Definition: SX127x.cpp:659
    SX127x::SX127x
    SX127x(Module *mod)
    Default constructor. Called internally when creating new LoRa instance.
    Definition: SX127x.cpp:4
    SX127x::fixedPacketLengthMode
    int16_t fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)
    Set modem in fixed packet length mode. Available in FSK mode only.
    Definition: SX127x.cpp:882
    SX127x::begin
    int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength)
    Initialization method. Will be called with appropriate parameters when calling initialization method ...
    Definition: SX127x.cpp:8
    @@ -164,7 +140,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
  • src
  • modules
  • SX127x
  • SX127x.h
  • Generated by - doxygen 1.8.11
    • + doxygen 1.8.13
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