From 4bbd9f8d3ef12c99a9f06aa91dcd9ebb22a7f0f6 Mon Sep 17 00:00:00 2001 From: jgromes Date: Thu, 19 Nov 2020 16:09:34 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=20c1277?= =?UTF-8?q?12c5e4c90ad17ffe721ccbe025fb2d0cb21=20=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- _s_x1272_8h_source.html | 4 +-- _s_x1278_8h_source.html | 4 +-- _s_x127x_8h_source.html | 46 ++++++++++++++--------------- _type_def_8h_source.html | 2 +- group__status__codes.html | 4 +++ group__status__codes.js | 1 + navtreeindex3.js | 61 ++++++++++++++++++++------------------- search/all_4.js | 1 + 8 files changed, 65 insertions(+), 58 deletions(-) diff --git a/_s_x1272_8h_source.html b/_s_x1272_8h_source.html index 56b5d033..3e951384 100644 --- a/_s_x1272_8h_source.html +++ b/_s_x1272_8h_source.html @@ -87,7 +87,7 @@ $(document).ready(function(){initNavTree('_s_x1272_8h_source.html','');});
1 #if !defined(_RADIOLIB_SX1272_H)
2 #define _RADIOLIB_SX1272_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1272 specific register map
12 #define SX1272_REG_AGC_REF 0x43
13 #define SX1272_REG_AGC_THRESH_1 0x44
14 #define SX1272_REG_AGC_THRESH_2 0x45
15 #define SX1272_REG_AGC_THRESH_3 0x46
16 #define SX1272_REG_PLL_HOP 0x4B
17 #define SX1272_REG_TCXO 0x58
18 #define SX1272_REG_PA_DAC 0x5A
19 #define SX1272_REG_PLL 0x5C
20 #define SX1272_REG_PLL_LOW_PN 0x5E
21 #define SX1272_REG_FORMER_TEMP 0x6C
22 #define SX1272_REG_BIT_RATE_FRAC 0x70
23 
24 // SX1272 LoRa modem settings
25 // SX1272_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
26 #define SX1272_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
27 #define SX1272_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
28 #define SX1272_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
29 
30 // SX1272_REG_MODEM_CONFIG_1
31 #define SX1272_BW_125_00_KHZ 0b00000000 // 7 6 bandwidth: 125 kHz
32 #define SX1272_BW_250_00_KHZ 0b01000000 // 7 6 250 kHz
33 #define SX1272_BW_500_00_KHZ 0b10000000 // 7 6 500 kHz
34 #define SX1272_CR_4_5 0b00001000 // 5 3 error coding rate: 4/5
35 #define SX1272_CR_4_6 0b00010000 // 5 3 4/6
36 #define SX1272_CR_4_7 0b00011000 // 5 3 4/7
37 #define SX1272_CR_4_8 0b00100000 // 5 3 4/8
38 #define SX1272_HEADER_EXPL_MODE 0b00000000 // 2 2 explicit header mode
39 #define SX1272_HEADER_IMPL_MODE 0b00000100 // 2 2 implicit header mode
40 #define SX1272_RX_CRC_MODE_OFF 0b00000000 // 1 1 CRC disabled
41 #define SX1272_RX_CRC_MODE_ON 0b00000010 // 1 1 CRC enabled
42 #define SX1272_LOW_DATA_RATE_OPT_OFF 0b00000000 // 0 0 low data rate optimization disabled
43 #define SX1272_LOW_DATA_RATE_OPT_ON 0b00000001 // 0 0 low data rate optimization enabled, mandatory for SF 11 and 12 with BW 125 kHz
44 
45 // SX1272_REG_MODEM_CONFIG_2
46 #define SX1272_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
47 #define SX1272_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
48 
49 // SX127X_REG_VERSION
50 #define SX1272_CHIP_VERSION 0x22
51 
52 // SX1272 FSK modem settings
53 // SX127X_REG_OP_MODE
54 #define SX1272_NO_SHAPING 0b00000000 // 4 3 data shaping: no shaping (default)
55 #define SX1272_FSK_GAUSSIAN_1_0 0b00001000 // 4 3 FSK modulation Gaussian filter, BT = 1.0
56 #define SX1272_FSK_GAUSSIAN_0_5 0b00010000 // 4 3 FSK modulation Gaussian filter, BT = 0.5
57 #define SX1272_FSK_GAUSSIAN_0_3 0b00011000 // 4 3 FSK modulation Gaussian filter, BT = 0.3
58 #define SX1272_OOK_FILTER_BR 0b00001000 // 4 3 OOK modulation filter, f_cutoff = BR
59 #define SX1272_OOK_FILTER_2BR 0b00010000 // 4 3 OOK modulation filter, f_cutoff = 2*BR
60 
61 // SX127X_REG_PA_RAMP
62 #define SX1272_LOW_PN_TX_PLL_OFF 0b00010000 // 4 4 use standard PLL in transmit mode (default)
63 #define SX1272_LOW_PN_TX_PLL_ON 0b00000000 // 4 4 use lower phase noise PLL in transmit mode
64 
65 // SX127X_REG_SYNC_CONFIG
66 #define SX1272_FIFO_FILL_CONDITION_SYNC_ADDRESS 0b00000000 // 3 3 FIFO will be filled when sync address interrupt occurs (default)
67 #define SX1272_FIFO_FILL_CONDITION_ALWAYS 0b00001000 // 3 3 FIFO will be filled as long as this bit is set
68 
69 // SX1272_REG_AGC_REF
70 #define SX1272_AGC_REFERENCE_LEVEL 0x13 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]
71 
72 // SX1272_REG_AGC_THRESH_1
73 #define SX1272_AGC_STEP_1 0x0E // 4 0 1st AGC threshold
74 
75 // SX1272_REG_AGC_THRESH_2
76 #define SX1272_AGC_STEP_2 0x50 // 7 4 2nd AGC threshold
77 #define SX1272_AGC_STEP_3 0x0B // 4 0 3rd AGC threshold
78 
79 // SX1272_REG_AGC_THRESH_3
80 #define SX1272_AGC_STEP_4 0xD0 // 7 4 4th AGC threshold
81 #define SX1272_AGC_STEP_5 0x0B // 4 0 5th AGC threshold
82 
83 // SX1272_REG_PLL_LOW_PN
84 #define SX1272_PLL_LOW_PN_BANDWIDTH_75_KHZ 0b00000000 // 7 6 low phase noise PLL bandwidth: 75 kHz
85 #define SX1272_PLL_LOW_PN_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
86 #define SX1272_PLL_LOW_PN_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
87 #define SX1272_PLL_LOW_PN_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
88 
95 class SX1272: public SX127x {
96  public:
97 
98  // constructor
99 
105  SX1272(Module* mod);
106 
107  // basic methods
108 
133  int16_t begin(float freq = 915.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
134 
155  int16_t beginFSK(float freq = 915.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
156 
160  void reset() override;
161 
162  // configuration methods
163 
171  int16_t setFrequency(float freq);
172 
180  int16_t setBandwidth(float bw);
181 
189  int16_t setSpreadingFactor(uint8_t sf);
190 
198  int16_t setCodingRate(uint8_t cr);
199 
207  int16_t setOutputPower(int8_t power);
208 
217  int16_t setGain(uint8_t gain);
218 
227  int16_t setDataShaping(uint8_t sh) override;
228 
238  int16_t setDataShapingOOK(uint8_t sh);
239 
245  float getRSSI();
246 
254  int16_t setCRC(bool enableCRC);
255 
264  int16_t forceLDRO(bool enable);
265 
272  int16_t autoLDRO();
273 
274 #ifndef RADIOLIB_GODMODE
275  protected:
276 #endif
277  int16_t setBandwidthRaw(uint8_t newBandwidth);
278  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
279  int16_t setCodingRateRaw(uint8_t newCodingRate);
280 
281  int16_t configFSK();
282 
283 #ifndef RADIOLIB_GODMODE
284  private:
285 #endif
286  bool _ldroAuto = true;
287  bool _ldroEnabled = false;
288 
289 };
290 
291 #endif
292 
293 #endif
SX1272
Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic...
Definition: SX1272.h:95
SX1272::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 860.0 MHz to 1020.0 MHz.
Definition: SX1272.cpp:74
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
-
SX1272::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:392
+
SX1272::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:393
SX1272::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1272.cpp:244
SX1272::begin
int16_t begin(float freq=915.0, float bw=125.0, uint8_t sf=9, uint8_t cr=7, uint8_t syncWord=SX127X_SYNC_WORD, int8_t power=10, uint16_t preambleLength=8, uint8_t gain=0)
LoRa modem initialization method. Must be called at least once from Arduino sketch to initialize the ...
Definition: SX1272.cpp:8
SX1272::setDataShapingOOK
int16_t setDataShapingOOK(uint8_t sh)
Sets filter cutoff frequency that will be used for data shaping. Allowed values are 1 for frequency e...
Definition: SX1272.cpp:299
@@ -101,7 +101,7 @@ $(document).ready(function(){initNavTree('_s_x1272_8h_source.html','');});
SX1272::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1272.cpp:181
SX1272::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1272.cpp:125
SX1272::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1272.cpp:269
-
SX1272::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:379
+
SX1272::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:380
SX1272::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1272.cpp:66
diff --git a/_s_x1278_8h_source.html b/_s_x1278_8h_source.html index 7f5e94c1..7972b619 100644 --- a/_s_x1278_8h_source.html +++ b/_s_x1278_8h_source.html @@ -87,9 +87,9 @@ $(document).ready(function(){initNavTree('_s_x1278_8h_source.html','');});
1 #if !defined(_RADIOLIB_SX1278_H)
2 #define _RADIOLIB_SX1278_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1278 specific register map
12 #define SX1278_REG_MODEM_CONFIG_3 0x26
13 #define SX1278_REG_PLL_HOP 0x44
14 #define SX1278_REG_TCXO 0x4B
15 #define SX1278_REG_PA_DAC 0x4D
16 #define SX1278_REG_FORMER_TEMP 0x5B
17 #define SX1278_REG_REG_BIT_RATE_FRAC 0x5D
18 #define SX1278_REG_AGC_REF 0x61
19 #define SX1278_REG_AGC_THRESH_1 0x62
20 #define SX1278_REG_AGC_THRESH_2 0x63
21 #define SX1278_REG_AGC_THRESH_3 0x64
22 #define SX1278_REG_PLL 0x70
23 
24 // SX1278 LoRa modem settings
25 // SX1278_REG_OP_MODE MSB LSB DESCRIPTION
26 #define SX1278_HIGH_FREQ 0b00000000 // 3 3 access HF test registers
27 #define SX1278_LOW_FREQ 0b00001000 // 3 3 access LF test registers
28 
29 // SX1278_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
30 #define SX1278_FRF_MSB 0x6C // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
31 #define SX1278_FRF_MID 0x80 // 7 0 where F(XOSC) = 32 MHz
32 #define SX1278_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
33 
34 // SX1278_REG_PA_CONFIG
35 #define SX1278_MAX_POWER 0b01110000 // 6 4 max power: P_max = 10.8 + 0.6*MAX_POWER [dBm]; P_max(MAX_POWER = 0b111) = 15 dBm
36 #define SX1278_LOW_POWER 0b00100000 // 6 4
37 
38 // SX1278_REG_LNA
39 #define SX1278_LNA_BOOST_LF_OFF 0b00000000 // 4 3 default LNA current
40 
41 // SX1278_REG_MODEM_CONFIG_1
42 #define SX1278_BW_7_80_KHZ 0b00000000 // 7 4 bandwidth: 7.80 kHz
43 #define SX1278_BW_10_40_KHZ 0b00010000 // 7 4 10.40 kHz
44 #define SX1278_BW_15_60_KHZ 0b00100000 // 7 4 15.60 kHz
45 #define SX1278_BW_20_80_KHZ 0b00110000 // 7 4 20.80 kHz
46 #define SX1278_BW_31_25_KHZ 0b01000000 // 7 4 31.25 kHz
47 #define SX1278_BW_41_70_KHZ 0b01010000 // 7 4 41.70 kHz
48 #define SX1278_BW_62_50_KHZ 0b01100000 // 7 4 62.50 kHz
49 #define SX1278_BW_125_00_KHZ 0b01110000 // 7 4 125.00 kHz
50 #define SX1278_BW_250_00_KHZ 0b10000000 // 7 4 250.00 kHz
51 #define SX1278_BW_500_00_KHZ 0b10010000 // 7 4 500.00 kHz
52 #define SX1278_CR_4_5 0b00000010 // 3 1 error coding rate: 4/5
53 #define SX1278_CR_4_6 0b00000100 // 3 1 4/6
54 #define SX1278_CR_4_7 0b00000110 // 3 1 4/7
55 #define SX1278_CR_4_8 0b00001000 // 3 1 4/8
56 #define SX1278_HEADER_EXPL_MODE 0b00000000 // 0 0 explicit header mode
57 #define SX1278_HEADER_IMPL_MODE 0b00000001 // 0 0 implicit header mode
58 
59 // SX1278_REG_MODEM_CONFIG_2
60 #define SX1278_RX_CRC_MODE_OFF 0b00000000 // 2 2 CRC disabled
61 #define SX1278_RX_CRC_MODE_ON 0b00000100 // 2 2 CRC enabled
62 
63 // SX1278_REG_MODEM_CONFIG_3
64 #define SX1278_LOW_DATA_RATE_OPT_OFF 0b00000000 // 3 3 low data rate optimization disabled
65 #define SX1278_LOW_DATA_RATE_OPT_ON 0b00001000 // 3 3 low data rate optimization enabled
66 #define SX1278_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
67 #define SX1278_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
68 
69 // SX127X_REG_VERSION
70 #define SX1278_CHIP_VERSION 0x12
71 
72 // SX1278 FSK modem settings
73 // SX127X_REG_PA_RAMP
74 #define SX1278_NO_SHAPING 0b00000000 // 6 5 data shaping: no shaping (default)
75 #define SX1278_FSK_GAUSSIAN_1_0 0b00100000 // 6 5 FSK modulation Gaussian filter, BT = 1.0
76 #define SX1278_FSK_GAUSSIAN_0_5 0b01000000 // 6 5 FSK modulation Gaussian filter, BT = 0.5
77 #define SX1278_FSK_GAUSSIAN_0_3 0b01100000 // 6 5 FSK modulation Gaussian filter, BT = 0.3
78 #define SX1278_OOK_FILTER_BR 0b00100000 // 6 5 OOK modulation filter, f_cutoff = BR
79 #define SX1278_OOK_FILTER_2BR 0b01000000 // 6 5 OOK modulation filter, f_cutoff = 2*BR
80 
81 // SX1278_REG_AGC_REF
82 #define SX1278_AGC_REFERENCE_LEVEL_LF 0x19 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]: below 525 MHz
83 #define SX1278_AGC_REFERENCE_LEVEL_HF 0x1C // 5 0 above 779 MHz
84 
85 // SX1278_REG_AGC_THRESH_1
86 #define SX1278_AGC_STEP_1_LF 0x0C // 4 0 1st AGC threshold: below 525 MHz
87 #define SX1278_AGC_STEP_1_HF 0x0E // 4 0 above 779 MHz
88 
89 // SX1278_REG_AGC_THRESH_2
90 #define SX1278_AGC_STEP_2_LF 0x40 // 7 4 2nd AGC threshold: below 525 MHz
91 #define SX1278_AGC_STEP_2_HF 0x50 // 7 4 above 779 MHz
92 #define SX1278_AGC_STEP_3 0x0B // 3 0 3rd AGC threshold
93 
94 // SX1278_REG_AGC_THRESH_3
95 #define SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold
96 #define SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold
97 
104 class SX1278: public SX127x {
105  public:
106 
107  // constructor
108 
114  SX1278(Module* mod);
115 
116  // basic methods
117 
141  int16_t begin(float freq = 434.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
142 
163  int16_t beginFSK(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
164 
168  void reset() override;
169 
170  // configuration methods
171 
179  int16_t setFrequency(float freq);
180 
188  int16_t setBandwidth(float bw);
189 
197  int16_t setSpreadingFactor(uint8_t sf);
198 
206  int16_t setCodingRate(uint8_t cr);
207 
215  int16_t setOutputPower(int8_t power);
216 
225  int16_t setGain(uint8_t gain);
226 
235  int16_t setDataShaping(uint8_t sh) override;
236 
246  int16_t setDataShapingOOK(uint8_t sh);
247 
253  float getRSSI();
254 
262  int16_t setCRC(bool enableCRC);
263 
272  int16_t forceLDRO(bool enable);
273 
280  int16_t autoLDRO();
281 
282 #ifndef RADIOLIB_GODMODE
283  protected:
284 #endif
285  int16_t setBandwidthRaw(uint8_t newBandwidth);
286  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
287  int16_t setCodingRateRaw(uint8_t newCodingRate);
288 
289  int16_t configFSK();
290 
291 #ifndef RADIOLIB_GODMODE
292  private:
293 #endif
294  bool _ldroAuto = true;
295  bool _ldroEnabled = false;
296 
297 };
298 
299 #endif
300 
301 #endif
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
SX1278::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1278.cpp:341
SX1278::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1278.cpp:403
-
SX1278::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:457
+
SX1278::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:458
SX1278::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1278.cpp:316
-
SX1278::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:470
+
SX1278::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:471
SX1278::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 137.0 MHz to 525.0 MHz.
Definition: SX1278.cpp:69
SX1278::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1278.cpp:439
SX1278::beginFSK
int16_t beginFSK(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=125.0, int8_t power=10, uint16_t preambleLength=16, bool enableOOK=false)
FSK modem initialization method. Must be called at least once from Arduino sketch to initialize the m...
Definition: SX1278.cpp:39
diff --git a/_s_x127x_8h_source.html b/_s_x127x_8h_source.html index 831f9343..93cf8178 100644 --- a/_s_x127x_8h_source.html +++ b/_s_x127x_8h_source.html @@ -84,26 +84,26 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x.h
-
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
941 #ifndef RADIOLIB_GODMODE
942  protected:
943 #endif
944  Module* _mod;
945 
946  float _freq = 0;
947  float _bw = 0;
948  uint8_t _sf = 0;
949  uint8_t _cr = 0;
950  float _br = 0;
951  float _rxBw = 0;
952  bool _ook = false;
953 
954  int16_t setFrequencyRaw(float newFreq);
955  int16_t config();
956  int16_t configFSK();
957  int16_t getActiveModem();
958  int16_t directMode();
959  int16_t setPacketMode(uint8_t mode, uint8_t len);
960 
961 #ifndef RADIOLIB_GODMODE
962  private:
963 #endif
964  float _dataRate = 0;
965  size_t _packetLength = 0;
966  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
967  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
968 
969  bool findChip(uint8_t ver);
970  int16_t setMode(uint8_t mode);
971  int16_t setActiveModem(uint8_t modem);
972  void clearIRQFlags();
973  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
974 };
975 
976 #endif
977 
978 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:890
+
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
941 #ifndef RADIOLIB_GODMODE
942  protected:
943 #endif
944  Module* _mod;
945 
946  float _freq = 0;
947  float _bw = 0;
948  uint8_t _sf = 0;
949  uint8_t _cr = 0;
950  float _br = 0;
951  float _rxBw = 0;
952  bool _ook = false;
953  bool _crcEnabled = false;
954 
955  int16_t setFrequencyRaw(float newFreq);
956  int16_t config();
957  int16_t configFSK();
958  int16_t getActiveModem();
959  int16_t directMode();
960  int16_t setPacketMode(uint8_t mode, uint8_t len);
961 
962 #ifndef RADIOLIB_GODMODE
963  private:
964 #endif
965  float _dataRate = 0;
966  size_t _packetLength = 0;
967  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
968  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
969 
970  bool findChip(uint8_t ver);
971  int16_t setMode(uint8_t mode);
972  int16_t setActiveModem(uint8_t modem);
973  void clearIRQFlags();
974  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
975 };
976 
977 #endif
978 
979 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:897
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
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SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:854
+
SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:861
SX127x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: SX127x.cpp:480
SX127x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Enables direct transmission mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:288
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SX127x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX127x.cpp:961
+
SX127x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX127x.cpp:968
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
SX127x::clearDio0Action
void clearDio0Action()
Clears interrupt service routine to call when DIO0 activates.
Definition: SX127x.cpp:401
SX127x::reset
virtual void reset()=0
Reset method. Will reset the chip to the default state using RST pin. Declared pure virtual since SX1...
-
SX127x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets FSK node address. Calling this method will enable address filtering. Only available in FSK mode...
Definition: SX127x.cpp:774
+
SX127x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets FSK node address. Calling this method will enable address filtering. Only available in FSK mode...
Definition: SX127x.cpp:781
SX127x::receive
int16_t receive(uint8_t *data, size_t len) override
Binary receive method. Will attempt to receive arbitrary binary data up to 255 bytes long using LoRa ...
Definition: SX127x.cpp:188
SX127x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Binary transmit method. Will transmit arbitrary binary data up to 255 bytes long using LoRa or up to ...
Definition: SX127x.cpp:121
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SX127x::getSNR
float getSNR()
Gets signal-to-noise ratio of the latest received packet.
Definition: SX127x.cpp:648
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SX127x::setSyncWord
int16_t setSyncWord(uint8_t syncWord)
Sets LoRa sync word. Only available in LoRa mode.
Definition: SX127x.cpp:530
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SX127x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 1.2 to 300 kbps. Only available in FSK mode...
Definition: SX127x.cpp:663
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SX127x::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: SX127x.cpp:820
-
SX127x::getFrequencyError
float getFrequencyError(bool autoCorrect=false)
Gets frequency error of the latest received packet.
Definition: SX127x.cpp:595
+
SX127x::getSNR
float getSNR()
Gets signal-to-noise ratio of the latest received packet.
Definition: SX127x.cpp:655
+
SX127x::setSyncWord
int16_t setSyncWord(uint8_t syncWord)
Sets LoRa sync word. Only available in LoRa mode.
Definition: SX127x.cpp:537
+
SX127x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 1.2 to 300 kbps. Only available in FSK mode...
Definition: SX127x.cpp:670
+
SX127x::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: SX127x.cpp:827
+
SX127x::getFrequencyError
float getFrequencyError(bool autoCorrect=false)
Gets frequency error of the latest received packet.
Definition: SX127x.cpp:602
SX127x::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Will start transmitting arbitrary binary data up to 255 byte...
Definition: SX127x.cpp:419
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SX127x::getModemStatus
uint8_t getModemStatus()
Reads modem status. Only available in LoRa mode.
Definition: SX127x.cpp:947
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SX127x::setCurrentLimit
int16_t setCurrentLimit(uint8_t currentLimit)
Sets current limit for over current protection at transmitter amplifier. Allowed values range from 45...
Definition: SX127x.cpp:543
+
SX127x::getModemStatus
uint8_t getModemStatus()
Reads modem status. Only available in LoRa mode.
Definition: SX127x.cpp:954
+
SX127x::setCurrentLimit
int16_t setCurrentLimit(uint8_t currentLimit)
Sets current limit for over current protection at transmitter amplifier. Allowed values range from 45...
Definition: SX127x.cpp:550
SX127x::sleep
int16_t sleep()
Sets the LoRa module to sleep to save power. Module will not be able to transmit or receive any data ...
Definition: SX127x.cpp:272
SX127x::startReceive
int16_t startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)
Interrupt-driven receive method. DIO0 will be activated when full valid packet is received...
Definition: SX127x.cpp:353
SX127x::setDio0Action
void setDio0Action(void(*func)(void))
Set interrupt service routine function to call when DIO0 activates.
Definition: SX127x.cpp:397
@@ -111,28 +111,28 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
SX127x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:314
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SX127x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: SX127x.cpp:913
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SX127x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:886
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SX127x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values depend on bit rate setting and mu...
Definition: SX127x.cpp:692
+
SX127x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: SX127x.cpp:920
+
SX127x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:893
+
SX127x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values depend on bit rate setting and mu...
Definition: SX127x.cpp:699
SX127x::standby
int16_t standby() override
Sets the LoRa module to standby.
Definition: SX127x.cpp:280
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
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SX127x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values range from 2.6 to 250 kHz. Only available in FSK mode...
Definition: SX127x.cpp:715
+
SX127x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values range from 2.6 to 250 kHz. Only available in FSK mode...
Definition: SX127x.cpp:722
SX127x::beginFSK
int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK)
Initialization method for FSK modem. Will be called with appropriate parameters when calling FSK init...
Definition: SX127x.cpp:52
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SX127x::getIRQFlags
uint16_t getIRQFlags()
Reads currently active IRQ flags, can be used to check which event caused an interrupt. In LoRa mode, this is the content of SX127X_REG_IRQ_FLAGS register. In FSK mode, this is the contents of SX127X_REG_IRQ_FLAGS_2 (MSB) and SX127X_REG_IRQ_FLAGS_1 (LSB) registers.
Definition: SX127x.cpp:932
+
SX127x::getIRQFlags
uint16_t getIRQFlags()
Reads currently active IRQ flags, can be used to check which event caused an interrupt. In LoRa mode, this is the content of SX127X_REG_IRQ_FLAGS register. In FSK mode, this is the contents of SX127X_REG_IRQ_FLAGS_2 (MSB) and SX127X_REG_IRQ_FLAGS_1 (LSB) registers.
Definition: SX127x.cpp:939
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
-
SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:986
+
SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:993
SX127x::scanChannel
int16_t scanChannel()
Performs scan for valid LoRa preamble in the current channel.
Definition: SX127x.cpp:233
-
SX127x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX127x.cpp:957
+
SX127x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX127x.cpp:964
SX127x::packetMode
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets. Can only be activated in FSK mode.
Definition: SX127x.cpp:344
-
SX127x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables FSK address filtering.
Definition: SX127x.cpp:802
-
SX127x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets FSK broadcast address. Calling this method will enable address filtering. Only available in FSK ...
Definition: SX127x.cpp:788
+
SX127x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables FSK address filtering.
Definition: SX127x.cpp:809
+
SX127x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets FSK broadcast address. Calling this method will enable address filtering. Only available in FSK ...
Definition: SX127x.cpp:795
SX127x::setDio1Action
void setDio1Action(void(*func)(void))
Set interrupt service routine function to call when DIO1 activates.
Definition: SX127x.cpp:405
-
SX127x::getDataRate
float getDataRate() const
Get data rate of the latest transmitted packet.
Definition: SX127x.cpp:659
+
SX127x::getDataRate
float getDataRate() const
Get data rate of the latest transmitted packet.
Definition: SX127x.cpp:666
SX127x::SX127x
SX127x(Module *mod)
Default constructor. Called internally when creating new LoRa instance.
Definition: SX127x.cpp:4
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SX127x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:882
+
SX127x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:889
SX127x::begin
int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength)
Initialization method. Will be called with appropriate parameters when calling initialization method ...
Definition: SX127x.cpp:8
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
-
SX127x::setPreambleLength
int16_t setPreambleLength(uint16_t preambleLength)
Sets LoRa preamble length. Allowed values range from 6 to 65535. Only available in LoRa mode...
Definition: SX127x.cpp:567
+
SX127x::setPreambleLength
int16_t setPreambleLength(uint16_t preambleLength)
Sets LoRa preamble length. Allowed values range from 6 to 65535. Only available in LoRa mode...
Definition: SX127x.cpp:574
diff --git a/_type_def_8h_source.html b/_type_def_8h_source.html index e85438b5..4ba08560 100644 --- a/_type_def_8h_source.html +++ b/_type_def_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_type_def_8h_source.html','');});
TypeDef.h
-
1 #ifndef _RADIOLIB_TYPES_H
2 #define _RADIOLIB_TYPES_H
3 
4 #include "BuildOpt.h"
5 
15 #define RADIOLIB_USE_SPI 0x00
16 
20 #define RADIOLIB_USE_UART 0x01
21 
25 #define RADIOLIB_USE_I2C 0x02
26 
40 #define RADIOLIB_UART_STOPBIT_1 0x01
41 
45 #define RADIOLIB_UART_STOPBIT_1_5 0x02
46 
50 #define RADIOLIB_UART_STOPBIT_2 0x03
51 
55 #define RADIOLIB_UART_PARITY_NONE 0x00
56 
60 #define RADIOLIB_UART_PARITY_ODD 0x01
61 
65 #define RADIOLIB_UART_PARITY_EVEN 0x02
66 
70 #define RADIOLIB_UART_FLOW_NONE 0x00
71 
75 #define RADIOLIB_UART_FLOW_RTS 0x01
76 
80 #define RADIOLIB_UART_FLOW_CTS 0x02
81 
85 #define RADIOLIB_UART_FLOW_BOTH 0x03
86 
100 #define RADIOLIB_SHAPING_NONE 0x00
101 
105 #define RADIOLIB_SHAPING_0_3 0x01
106 
110 #define RADIOLIB_SHAPING_0_5 0x02
111 
115 #define RADIOLIB_SHAPING_0_7 0x03
116 
120 #define RADIOLIB_SHAPING_1_0 0x04
121 
135 #define RADIOLIB_ENCODING_NRZ 0x00
136 
140 #define RADIOLIB_ENCODING_MANCHESTER 0x01
141 
145 #define RADIOLIB_ENCODING_WHITENING 0x02
146 
157 // common status codes
158 
162 #define ERR_NONE 0
163 
168 #define ERR_UNKNOWN -1
169 
170 // SX127x/RFM9x status codes
171 
176 #define ERR_CHIP_NOT_FOUND -2
177 
181 #define ERR_MEMORY_ALLOCATION_FAILED -3
182 
186 #define ERR_PACKET_TOO_LONG -4
187 
191 #define ERR_TX_TIMEOUT -5
192 
196 #define ERR_RX_TIMEOUT -6
197 
202 #define ERR_CRC_MISMATCH -7
203 
207 #define ERR_INVALID_BANDWIDTH -8
208 
212 #define ERR_INVALID_SPREADING_FACTOR -9
213 
217 #define ERR_INVALID_CODING_RATE -10
218 
222 #define ERR_INVALID_BIT_RANGE -11
223 
227 #define ERR_INVALID_FREQUENCY -12
228 
232 #define ERR_INVALID_OUTPUT_POWER -13
233 
238 #define PREAMBLE_DETECTED -14
239 
243 #define CHANNEL_FREE -15
244 
248 #define ERR_SPI_WRITE_FAILED -16
249 
253 #define ERR_INVALID_CURRENT_LIMIT -17
254 
258 #define ERR_INVALID_PREAMBLE_LENGTH -18
259 
263 #define ERR_INVALID_GAIN -19
264 
269 #define ERR_WRONG_MODEM -20
270 
274 #define ERR_INVALID_NUM_SAMPLES -21
275 
279 #define ERR_INVALID_RSSI_OFFSET -22
280 
284 #define ERR_INVALID_ENCODING -23
285 
286 // RF69-specific status codes
287 
291 #define ERR_INVALID_BIT_RATE -101
292 
296 #define ERR_INVALID_FREQUENCY_DEVIATION -102
297 
301 #define ERR_INVALID_BIT_RATE_BW_RATIO -103
302 
306 #define ERR_INVALID_RX_BANDWIDTH -104
307 
311 #define ERR_INVALID_SYNC_WORD -105
312 
316 #define ERR_INVALID_DATA_SHAPING -106
317 
321 #define ERR_INVALID_MODULATION -107
322 
323 // ESP8266 status codes
324 
328 #define ERR_AT_FAILED -201
329 
333 #define ERR_URL_MALFORMED -202
334 
338 #define ERR_RESPONSE_MALFORMED_AT -203
339 
343 #define ERR_RESPONSE_MALFORMED -204
344 
348 #define ERR_MQTT_CONN_VERSION_REJECTED -205
349 
353 #define ERR_MQTT_CONN_ID_REJECTED -206
354 
358 #define ERR_MQTT_CONN_SERVER_UNAVAILABLE -207
359 
363 #define ERR_MQTT_CONN_BAD_USERNAME_PASSWORD -208
364 
368 #define ERR_MQTT_CONN_NOT_AUTHORIZED -208
369 
373 #define ERR_MQTT_UNEXPECTED_PACKET_ID -209
374 
378 #define ERR_MQTT_NO_NEW_PACKET_AVAILABLE -210
379 
383 #define MQTT_SUBS_SUCCESS_QOS_0 0x00
384 
388 #define MQTT_SUBS_SUCCESS_QOS_1 0x01
389 
393 #define MQTT_SUBS_SUCCESS_QOS_2 0x02
394 
398 #define ERR_MQTT_SUBS_FAILED 0x80
399 
400 // XBee status codes
401 
405 #define ERR_CMD_MODE_FAILED -301
406 
410 #define ERR_FRAME_MALFORMED -302
411 
415 #define ERR_FRAME_INCORRECT_CHECKSUM -303
416 
420 #define ERR_FRAME_UNEXPECTED_ID -304
421 
425 #define ERR_FRAME_NO_RESPONSE -305
426 
427 // RTTY status codes
428 
432 #define ERR_INVALID_RTTY_SHIFT -401
433 
437 #define ERR_UNSUPPORTED_ENCODING -402
438 
439 // nRF24-specific status codes
440 
444 #define ERR_INVALID_DATA_RATE -501
445 
449 #define ERR_INVALID_ADDRESS_WIDTH -502
450 
454 #define ERR_INVALID_PIPE_NUMBER -503
455 
459 #define ERR_ACK_NOT_RECEIVED -504
460 
461 // CC1101-specific status codes
462 
466 #define ERR_INVALID_NUM_BROAD_ADDRS -601
467 
468 // SX126x-specific status codes
469 
473 #define ERR_INVALID_CRC_CONFIGURATION -701
474 
478 #define LORA_DETECTED -702
479 
483 #define ERR_INVALID_TCXO_VOLTAGE -703
484 
488 #define ERR_INVALID_MODULATION_PARAMETERS -704
489 
493 #define ERR_SPI_CMD_TIMEOUT -705
494 
498 #define ERR_SPI_CMD_INVALID -706
499 
503 #define ERR_SPI_CMD_FAILED -707
504 
511 #define ERR_INVALID_SLEEP_PERIOD -708
512 
518 #define ERR_INVALID_RX_PERIOD -709
519 
520 // AX.25-specific status codes
521 
527 #define ERR_INVALID_CALLSIGN -801
528 
534 #define ERR_INVALID_NUM_REPEATERS -802
535 
541 #define ERR_INVALID_REPEATER_CALLSIGN -803
542 
543 // SX128x-specific status codes
544 
548 #define ERR_RANGING_TIMEOUT -901
549 
554 #endif
+
1 #ifndef _RADIOLIB_TYPES_H
2 #define _RADIOLIB_TYPES_H
3 
4 #include "BuildOpt.h"
5 
15 #define RADIOLIB_USE_SPI 0x00
16 
20 #define RADIOLIB_USE_UART 0x01
21 
25 #define RADIOLIB_USE_I2C 0x02
26 
40 #define RADIOLIB_UART_STOPBIT_1 0x01
41 
45 #define RADIOLIB_UART_STOPBIT_1_5 0x02
46 
50 #define RADIOLIB_UART_STOPBIT_2 0x03
51 
55 #define RADIOLIB_UART_PARITY_NONE 0x00
56 
60 #define RADIOLIB_UART_PARITY_ODD 0x01
61 
65 #define RADIOLIB_UART_PARITY_EVEN 0x02
66 
70 #define RADIOLIB_UART_FLOW_NONE 0x00
71 
75 #define RADIOLIB_UART_FLOW_RTS 0x01
76 
80 #define RADIOLIB_UART_FLOW_CTS 0x02
81 
85 #define RADIOLIB_UART_FLOW_BOTH 0x03
86 
100 #define RADIOLIB_SHAPING_NONE 0x00
101 
105 #define RADIOLIB_SHAPING_0_3 0x01
106 
110 #define RADIOLIB_SHAPING_0_5 0x02
111 
115 #define RADIOLIB_SHAPING_0_7 0x03
116 
120 #define RADIOLIB_SHAPING_1_0 0x04
121 
135 #define RADIOLIB_ENCODING_NRZ 0x00
136 
140 #define RADIOLIB_ENCODING_MANCHESTER 0x01
141 
145 #define RADIOLIB_ENCODING_WHITENING 0x02
146 
157 // common status codes
158 
162 #define ERR_NONE 0
163 
168 #define ERR_UNKNOWN -1
169 
170 // SX127x/RFM9x status codes
171 
176 #define ERR_CHIP_NOT_FOUND -2
177 
181 #define ERR_MEMORY_ALLOCATION_FAILED -3
182 
186 #define ERR_PACKET_TOO_LONG -4
187 
191 #define ERR_TX_TIMEOUT -5
192 
196 #define ERR_RX_TIMEOUT -6
197 
202 #define ERR_CRC_MISMATCH -7
203 
207 #define ERR_INVALID_BANDWIDTH -8
208 
212 #define ERR_INVALID_SPREADING_FACTOR -9
213 
217 #define ERR_INVALID_CODING_RATE -10
218 
222 #define ERR_INVALID_BIT_RANGE -11
223 
227 #define ERR_INVALID_FREQUENCY -12
228 
232 #define ERR_INVALID_OUTPUT_POWER -13
233 
238 #define PREAMBLE_DETECTED -14
239 
243 #define CHANNEL_FREE -15
244 
248 #define ERR_SPI_WRITE_FAILED -16
249 
253 #define ERR_INVALID_CURRENT_LIMIT -17
254 
258 #define ERR_INVALID_PREAMBLE_LENGTH -18
259 
263 #define ERR_INVALID_GAIN -19
264 
269 #define ERR_WRONG_MODEM -20
270 
274 #define ERR_INVALID_NUM_SAMPLES -21
275 
279 #define ERR_INVALID_RSSI_OFFSET -22
280 
284 #define ERR_INVALID_ENCODING -23
285 
289 #define ERR_LORA_HEADER_DAMAGED -24
290 
291 // RF69-specific status codes
292 
296 #define ERR_INVALID_BIT_RATE -101
297 
301 #define ERR_INVALID_FREQUENCY_DEVIATION -102
302 
306 #define ERR_INVALID_BIT_RATE_BW_RATIO -103
307 
311 #define ERR_INVALID_RX_BANDWIDTH -104
312 
316 #define ERR_INVALID_SYNC_WORD -105
317 
321 #define ERR_INVALID_DATA_SHAPING -106
322 
326 #define ERR_INVALID_MODULATION -107
327 
328 // ESP8266 status codes
329 
333 #define ERR_AT_FAILED -201
334 
338 #define ERR_URL_MALFORMED -202
339 
343 #define ERR_RESPONSE_MALFORMED_AT -203
344 
348 #define ERR_RESPONSE_MALFORMED -204
349 
353 #define ERR_MQTT_CONN_VERSION_REJECTED -205
354 
358 #define ERR_MQTT_CONN_ID_REJECTED -206
359 
363 #define ERR_MQTT_CONN_SERVER_UNAVAILABLE -207
364 
368 #define ERR_MQTT_CONN_BAD_USERNAME_PASSWORD -208
369 
373 #define ERR_MQTT_CONN_NOT_AUTHORIZED -208
374 
378 #define ERR_MQTT_UNEXPECTED_PACKET_ID -209
379 
383 #define ERR_MQTT_NO_NEW_PACKET_AVAILABLE -210
384 
388 #define MQTT_SUBS_SUCCESS_QOS_0 0x00
389 
393 #define MQTT_SUBS_SUCCESS_QOS_1 0x01
394 
398 #define MQTT_SUBS_SUCCESS_QOS_2 0x02
399 
403 #define ERR_MQTT_SUBS_FAILED 0x80
404 
405 // XBee status codes
406 
410 #define ERR_CMD_MODE_FAILED -301
411 
415 #define ERR_FRAME_MALFORMED -302
416 
420 #define ERR_FRAME_INCORRECT_CHECKSUM -303
421 
425 #define ERR_FRAME_UNEXPECTED_ID -304
426 
430 #define ERR_FRAME_NO_RESPONSE -305
431 
432 // RTTY status codes
433 
437 #define ERR_INVALID_RTTY_SHIFT -401
438 
442 #define ERR_UNSUPPORTED_ENCODING -402
443 
444 // nRF24-specific status codes
445 
449 #define ERR_INVALID_DATA_RATE -501
450 
454 #define ERR_INVALID_ADDRESS_WIDTH -502
455 
459 #define ERR_INVALID_PIPE_NUMBER -503
460 
464 #define ERR_ACK_NOT_RECEIVED -504
465 
466 // CC1101-specific status codes
467 
471 #define ERR_INVALID_NUM_BROAD_ADDRS -601
472 
473 // SX126x-specific status codes
474 
478 #define ERR_INVALID_CRC_CONFIGURATION -701
479 
483 #define LORA_DETECTED -702
484 
488 #define ERR_INVALID_TCXO_VOLTAGE -703
489 
493 #define ERR_INVALID_MODULATION_PARAMETERS -704
494 
498 #define ERR_SPI_CMD_TIMEOUT -705
499 
503 #define ERR_SPI_CMD_INVALID -706
504 
508 #define ERR_SPI_CMD_FAILED -707
509 
516 #define ERR_INVALID_SLEEP_PERIOD -708
517 
523 #define ERR_INVALID_RX_PERIOD -709
524 
525 // AX.25-specific status codes
526 
532 #define ERR_INVALID_CALLSIGN -801
533 
539 #define ERR_INVALID_NUM_REPEATERS -802
540 
546 #define ERR_INVALID_REPEATER_CALLSIGN -803
547 
548 // SX128x-specific status codes
549 
553 #define ERR_RANGING_TIMEOUT -901
554 
559 #endif