From 3fe5c6d0a09fd33244e3355f828f27c3aaab0e94 Mon Sep 17 00:00:00 2001 From: jgromes Date: Sat, 13 Feb 2021 16:44:20 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=207ecd5?= =?UTF-8?q?6d2caef3a8d7c4009f0ecc55dbc8b16829d=20=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- _a_f_s_k_8h_source.html | 7 +-- _c_c1101_8h_source.html | 40 ++++++++-------- _hellschreiber_8h_source.html | 2 +- _morse_8h_source.html | 2 +- _physical_layer_8h_source.html | 3 +- _r_f69_8h_source.html | 42 ++++++++--------- _s_x126x_8h_source.html | 56 +++++++++++----------- _s_x1272_8h_source.html | 26 +++++------ _s_x1278_8h_source.html | 26 +++++------ _s_x127x_8h_source.html | 78 +++++++++++++++---------------- _s_x128x_8h_source.html | 28 +++++------ _si443x_8h_source.html | 18 +++---- class_a_f_s_k_client-members.html | 13 +++--- class_a_f_s_k_client.html | 23 +++++++++ class_a_f_s_k_client.js | 1 + class_c_c1101-members.html | 21 +++++---- class_c_c1101.html | 3 ++ class_physical_layer-members.html | 17 +++---- class_physical_layer.html | 23 +++++++++ class_physical_layer.js | 1 + class_r_f69-members.html | 21 +++++---- class_r_f69.html | 3 ++ class_r_f_m95-members.html | 25 +++++----- class_r_f_m95.html | 3 ++ class_r_f_m96-members.html | 25 +++++----- class_r_f_m96.html | 3 ++ class_r_f_m97-members.html | 25 +++++----- class_r_f_m97.html | 3 ++ class_s_x1231-members.html | 23 ++++----- class_s_x1231.html | 3 ++ class_s_x1261-members.html | 31 ++++++------ class_s_x1261.html | 3 ++ class_s_x1262-members.html | 29 ++++++------ class_s_x1262.html | 3 ++ class_s_x1268-members.html | 29 ++++++------ class_s_x1268.html | 3 ++ class_s_x126x-members.html | 27 +++++------ class_s_x126x.html | 3 ++ class_s_x1272-members.html | 25 +++++----- class_s_x1272.html | 3 ++ class_s_x1273-members.html | 27 +++++------ class_s_x1273.html | 3 ++ class_s_x1276-members.html | 27 +++++------ class_s_x1276.html | 3 ++ class_s_x1277-members.html | 27 +++++------ class_s_x1277.html | 3 ++ class_s_x1278-members.html | 25 +++++----- class_s_x1278.html | 3 ++ class_s_x1279-members.html | 27 +++++------ class_s_x1279.html | 3 ++ class_s_x127x-members.html | 23 ++++----- class_s_x127x.html | 3 ++ class_s_x1280-members.html | 27 +++++------ class_s_x1280.html | 3 ++ class_s_x1281-members.html | 23 ++++----- class_s_x1281.html | 3 ++ class_s_x1282-members.html | 29 ++++++------ class_s_x1282.html | 3 ++ class_s_x128x-members.html | 21 +++++---- class_s_x128x.html | 3 ++ class_si4430-members.html | 19 ++++---- class_si4430.html | 3 ++ class_si4431-members.html | 19 ++++---- class_si4431.html | 3 ++ class_si4432-members.html | 19 ++++---- class_si4432.html | 3 ++ class_si443x-members.html | 19 ++++---- class_si443x.html | 3 ++ classn_r_f24-members.html | 19 ++++---- classn_r_f24.html | 3 ++ functions_b.html | 3 +- functions_func_b.html | 5 +- functions_func_s.html | 9 ++-- functions_s.html | 11 +++-- navtreedata.js | 6 +-- navtreeindex0.js | 18 +++---- navtreeindex1.js | 22 ++++----- navtreeindex2.js | 6 +-- navtreeindex3.js | 6 ++- search/all_1.js | 2 +- search/all_10.js | 1 + search/functions_1.js | 2 +- search/functions_10.js | 1 + 83 files changed, 688 insertions(+), 520 deletions(-) diff --git a/_a_f_s_k_8h_source.html b/_a_f_s_k_8h_source.html index e2a4f499..d13b32a1 100644 --- a/_a_f_s_k_8h_source.html +++ b/_a_f_s_k_8h_source.html @@ -84,16 +84,17 @@ $(document).ready(function(){initNavTree('_a_f_s_k_8h_source.html','');});
AFSK.h
-
1 #if !defined(_RADIOLIB_AFSK_H)
2 #define _RADIOLIB_AFSK_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_AFSK)
7 
8 #include "../../Module.h"
9 
10 #include "../PhysicalLayer/PhysicalLayer.h"
11 
17 class AFSKClient {
18  public:
26  AFSKClient(PhysicalLayer* phy, RADIOLIB_PIN_TYPE pin);
27 
37  int16_t tone(uint16_t freq, bool autoStart = true);
38 
44  int16_t noTone();
45 
46 #ifndef RADIOLIB_GODMODE
47  private:
48 #endif
49  PhysicalLayer* _phy;
50  RADIOLIB_PIN_TYPE _pin;
51 
52  // allow specific classes access the private PhysicalLayer pointer
53  friend class RTTYClient;
54  friend class MorseClient;
55  friend class HellClient;
56  friend class SSTVClient;
57  friend class AX25Client;
58 };
59 
60 #endif
61 
62 #endif
AFSKClient
Client for audio-based transmissions. Requires Arduino tone() function, and a module capable of direc...
Definition: AFSK.h:17
-
AFSKClient::noTone
int16_t noTone()
Stops transmitting audio tone.
Definition: AFSK.cpp:22
+
1 #if !defined(_RADIOLIB_AFSK_H)
2 #define _RADIOLIB_AFSK_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_AFSK)
7 
8 #include "../../Module.h"
9 
10 #include "../PhysicalLayer/PhysicalLayer.h"
11 
17 class AFSKClient {
18  public:
26  AFSKClient(PhysicalLayer* phy, RADIOLIB_PIN_TYPE pin);
27 
33  int16_t begin();
34 
44  int16_t tone(uint16_t freq, bool autoStart = true);
45 
51  int16_t noTone();
52 
53 #ifndef RADIOLIB_GODMODE
54  private:
55 #endif
56  PhysicalLayer* _phy;
57  RADIOLIB_PIN_TYPE _pin;
58 
59  // allow specific classes access the private PhysicalLayer pointer
60  friend class RTTYClient;
61  friend class MorseClient;
62  friend class HellClient;
63  friend class SSTVClient;
64  friend class AX25Client;
65 };
66 
67 #endif
68 
69 #endif
AFSKClient
Client for audio-based transmissions. Requires Arduino tone() function, and a module capable of direc...
Definition: AFSK.h:17
+
AFSKClient::noTone
int16_t noTone()
Stops transmitting audio tone.
Definition: AFSK.cpp:26
HellClient
Client for Hellschreiber transmissions.
Definition: Hellschreiber.h:89
AFSKClient::AFSKClient
AFSKClient(PhysicalLayer *phy, RADIOLIB_PIN_TYPE pin)
Default contructor.
Definition: AFSK.cpp:4
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
RTTYClient
Client for RTTY communication. The public interface is the same as Arduino Serial.
Definition: RTTY.h:88
SSTVClient
Client for SSTV transmissions.
Definition: SSTV.h:120
AX25Client
Client for AX25 communication.
Definition: AX25.h:279
+
AFSKClient::begin
int16_t begin()
Initialization method.
Definition: AFSK.cpp:8
MorseClient
Client for Morse Code communication. The public interface is the same as Arduino Serial.
Definition: Morse.h:89
-
AFSKClient::tone
int16_t tone(uint16_t freq, bool autoStart=true)
Start transmitting audio tone.
Definition: AFSK.cpp:8
+
AFSKClient::tone
int16_t tone(uint16_t freq, bool autoStart=true)
Start transmitting audio tone.
Definition: AFSK.cpp:12
diff --git a/_c_c1101_8h_source.html b/_c_c1101_8h_source.html index ac9f6900..19d81c53 100644 --- a/_c_c1101_8h_source.html +++ b/_c_c1101_8h_source.html @@ -84,51 +84,51 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
CC1101.h
-
1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION_CURRENT 0x14
459 #define CC1101_VERSION_LEGACY 0x04
460 
461 // CC1101_REG_MARCSTATE
462 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
463 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
464 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
465 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
466 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
467 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
468 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
469 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
470 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
471 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
472 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
473 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
474 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
475 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
476 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
477 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
478 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
479 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
480 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
481 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
482 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
483 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
484 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
485 
486 // CC1101_REG_WORTIME1 + REG_WORTIME0
487 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
488 #define CC1101_WORTIME_LSB 0x00 // 7 0
489 
490 // CC1101_REG_PKTSTATUS
491 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
492 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
493 #define CC1101_CS 0b01000000 // 6 6 carrier sense
494 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
495 #define CC1101_CCA 0b00010000 // 4 4 channel clear
496 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
497 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
498 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
499 
505 class CC1101: public PhysicalLayer {
506  public:
507  // introduce PhysicalLayer overloads
508  using PhysicalLayer::transmit;
509  using PhysicalLayer::receive;
510  using PhysicalLayer::startTransmit;
511  using PhysicalLayer::readData;
512 
518  CC1101(Module* module);
519 
520  // basic methods
521 
539  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
540 
553  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
554 
565  int16_t receive(uint8_t* data, size_t len) override;
566 
572  int16_t standby() override;
573 
581  int16_t transmitDirect(uint32_t frf = 0) override;
582 
588  int16_t receiveDirect() override;
589 
593  int16_t packetMode();
594 
595  // interrupt methods
596 
604  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
605 
609  void clearGdo0Action();
610 
618  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
619 
623  void clearGdo2Action();
624 
637  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
638 
644  int16_t startReceive();
645 
655  int16_t readData(uint8_t* data, size_t len) override;
656 
657  // configuration methods
658 
666  int16_t setFrequency(float freq);
667 
675  int16_t setBitRate(float br);
676 
684  int16_t setRxBandwidth(float rxBw);
685 
693  int16_t setFrequencyDeviation(float freqDev) override;
694 
702  int16_t setOutputPower(int8_t power);
703 
717  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
718 
732  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
733 
741  int16_t setPreambleLength(uint8_t preambleLength);
742 
752  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
753 
759  int16_t disableAddressFiltering();
760 
768  int16_t setOOK(bool enableOOK);
769 
775  float getRSSI() const;
776 
782  uint8_t getLQI() const;
783 
791  size_t getPacketLength(bool update = true) override;
792 
800  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
801 
809  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
810 
820  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
821 
829  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
830 
838  int16_t setCrcFiltering(bool crcOn = true);
839 
847  int16_t setPromiscuousMode(bool promiscuous = true);
848 
857  int16_t setDataShaping(uint8_t sh) override;
858 
866  int16_t setEncoding(uint8_t encoding) override;
867 
876  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
877 
883  uint8_t random();
884 
890  int16_t getChipVersion();
891 
892 #ifndef RADIOLIB_GODMODE
893  private:
894 #endif
895  Module* _mod;
896 
897  float _freq = 0;
898  float _br = 0;
899  uint8_t _rawRSSI = 0;
900  uint8_t _rawLQI = 0;
901  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
902 
903  size_t _packetLength = 0;
904  bool _packetLengthQueried = false;
905  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
906 
907  bool _promiscuous = false;
908  bool _crcOn = true;
909 
910  uint8_t _syncWordLength = 2;
911  int8_t _power = 0;
912 
913  int16_t config();
914  int16_t directMode();
915  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
916  int16_t setPacketMode(uint8_t mode, uint8_t len);
917 
918  // SPI read overrides to set bit for burst write and status registers access
919  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
920  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
921  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
922  uint8_t SPIreadRegister(uint8_t reg);
923  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
924  void SPIwriteRegister(uint8_t reg, uint8_t data);
925 
926  void SPIsendCommand(uint8_t cmd);
927 };
928 
929 #endif
CC1101::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: CC1101.cpp:769
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1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION_CURRENT 0x14
459 #define CC1101_VERSION_LEGACY 0x04
460 
461 // CC1101_REG_MARCSTATE
462 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
463 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
464 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
465 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
466 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
467 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
468 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
469 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
470 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
471 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
472 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
473 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
474 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
475 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
476 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
477 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
478 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
479 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
480 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
481 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
482 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
483 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
484 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
485 
486 // CC1101_REG_WORTIME1 + REG_WORTIME0
487 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
488 #define CC1101_WORTIME_LSB 0x00 // 7 0
489 
490 // CC1101_REG_PKTSTATUS
491 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
492 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
493 #define CC1101_CS 0b01000000 // 6 6 carrier sense
494 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
495 #define CC1101_CCA 0b00010000 // 4 4 channel clear
496 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
497 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
498 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
499 
505 class CC1101: public PhysicalLayer {
506  public:
507  // introduce PhysicalLayer overloads
508  using PhysicalLayer::transmit;
509  using PhysicalLayer::receive;
510  using PhysicalLayer::startTransmit;
511  using PhysicalLayer::readData;
512 
518  CC1101(Module* module);
519 
520  // basic methods
521 
539  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
540 
553  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
554 
565  int16_t receive(uint8_t* data, size_t len) override;
566 
572  int16_t standby() override;
573 
581  int16_t transmitDirect(uint32_t frf = 0) override;
582 
588  int16_t receiveDirect() override;
589 
593  int16_t packetMode();
594 
595  // interrupt methods
596 
604  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
605 
609  void clearGdo0Action();
610 
618  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
619 
623  void clearGdo2Action();
624 
637  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
638 
644  int16_t startReceive();
645 
655  int16_t readData(uint8_t* data, size_t len) override;
656 
657  // configuration methods
658 
666  int16_t setFrequency(float freq);
667 
675  int16_t setBitRate(float br);
676 
684  int16_t setRxBandwidth(float rxBw);
685 
693  int16_t setFrequencyDeviation(float freqDev) override;
694 
702  int16_t setOutputPower(int8_t power);
703 
717  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
718 
732  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
733 
741  int16_t setPreambleLength(uint8_t preambleLength);
742 
752  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
753 
759  int16_t disableAddressFiltering();
760 
768  int16_t setOOK(bool enableOOK);
769 
775  float getRSSI() const;
776 
782  uint8_t getLQI() const;
783 
791  size_t getPacketLength(bool update = true) override;
792 
800  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
801 
809  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
810 
820  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
821 
829  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
830 
838  int16_t setCrcFiltering(bool crcOn = true);
839 
847  int16_t setPromiscuousMode(bool promiscuous = true);
848 
857  int16_t setDataShaping(uint8_t sh) override;
858 
866  int16_t setEncoding(uint8_t encoding) override;
867 
876  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
877 
883  uint8_t random();
884 
890  int16_t getChipVersion();
891 
892 #ifndef RADIOLIB_GODMODE
893  private:
894 #endif
895  Module* _mod;
896 
897  float _freq = 0;
898  float _br = 0;
899  uint8_t _rawRSSI = 0;
900  uint8_t _rawLQI = 0;
901  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
902 
903  size_t _packetLength = 0;
904  bool _packetLengthQueried = false;
905  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
906 
907  bool _promiscuous = false;
908  bool _crcOn = true;
909 
910  uint8_t _syncWordLength = 2;
911  int8_t _power = 0;
912 
913  int16_t config();
914  int16_t directMode();
915  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
916  int16_t setPacketMode(uint8_t mode, uint8_t len);
917 
918  // SPI read overrides to set bit for burst write and status registers access
919  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
920  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
921  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
922  uint8_t SPIreadRegister(uint8_t reg);
923  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
924  void SPIwriteRegister(uint8_t reg, uint8_t data);
925 
926  void SPIsendCommand(uint8_t cmd);
927 };
928 
929 #endif
CC1101::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: CC1101.cpp:768
CC1101::packetMode
int16_t packetMode()
Stops direct mode. It is required to call this method to switch from direct transmissions to packet-b...
Definition: CC1101.cpp:219
CC1101::begin
int16_t begin(float freq=434.0, float br=48.0, float freqDev=48.0, float rxBw=135.0, int8_t power=10, uint8_t preambleLength=16)
Initialization method.
Definition: CC1101.cpp:8
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
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CC1101::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0, bool requireCarrierSense=false)
Enable sync word filtering and generation.
Definition: CC1101.cpp:669
+
CC1101::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0, bool requireCarrierSense=false)
Enable sync word filtering and generation.
Definition: CC1101.cpp:668
CC1101::startReceive
int16_t startReceive()
Interrupt-driven receive method. GDO0 will be activated when full packet is received.
Definition: CC1101.cpp:288
-
CC1101::disableSyncWordFiltering
int16_t disableSyncWordFiltering(bool requireCarrierSense=false)
Disable preamble and sync word filtering and generation.
Definition: CC1101.cpp:682
+
CC1101::disableSyncWordFiltering
int16_t disableSyncWordFiltering(bool requireCarrierSense=false)
Disable preamble and sync word filtering and generation.
Definition: CC1101.cpp:681
CC1101::setGdo0Action
void setGdo0Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)
Sets interrupt service routine to call when GDO0 activates.
Definition: CC1101.cpp:226
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CC1101::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)
Set modem in variable packet length mode.
Definition: CC1101.cpp:665
-
CC1101::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: CC1101.cpp:647
-
CC1101::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Allowed values are RADIOLIB_ENCODING_NRZ and RADIOLIB_ENCODING_WHITENING...
Definition: CC1101.cpp:741
+
CC1101::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)
Set modem in variable packet length mode.
Definition: CC1101.cpp:664
+
CC1101::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: CC1101.cpp:646
+
CC1101::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Allowed values are RADIOLIB_ENCODING_NRZ and RADIOLIB_ENCODING_WHITENING...
Definition: CC1101.cpp:740
CC1101::clearGdo0Action
void clearGdo0Action()
Clears interrupt service routine to call when GDO0 activates.
Definition: CC1101.cpp:230
CC1101
Control class for CC1101 module.
Definition: CC1101.h:505
-
CC1101::getLQI
uint8_t getLQI() const
Gets LQI (Link Quality Indicator) of the last received packet.
Definition: CC1101.cpp:643
-
CC1101::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: CC1101.cpp:592
+
CC1101::getLQI
uint8_t getLQI() const
Gets LQI (Link Quality Indicator) of the last received packet.
Definition: CC1101.cpp:642
+
CC1101::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: CC1101.cpp:591
CC1101::setGdo2Action
void setGdo2Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)
Sets interrupt service routine to call when GDO2 activates.
Definition: CC1101.cpp:234
CC1101::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 58.0 to 812.0 kHz.
Definition: CC1101.cpp:394
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CC1101::getRSSI
float getRSSI() const
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: CC1101.cpp:633
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CC1101::setOutputPower
int16_t setOutputPower(int8_t power)
Sets output power. Allowed values are -30, -20, -15, -10, 0, 5, 7 or 10 dBm.
Definition: CC1101.cpp:438
+
CC1101::getRSSI
float getRSSI() const
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: CC1101.cpp:632
+
CC1101::setOutputPower
int16_t setOutputPower(int8_t power)
Sets output power. Allowed values are -30, -20, -15, -10, 0, 5, 7 or 10 dBm.
Definition: CC1101.cpp:437
CC1101::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: CC1101.cpp:249
CC1101::standby
int16_t standby() override
Sets the module to standby mode.
Definition: CC1101.cpp:175
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CC1101::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: CC1101.cpp:765
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CC1101::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return CC1101_VERSION_LEGACY (0x04) or CC1101_VERSION_CURRENT (0x14...
Definition: CC1101.cpp:789
-
CC1101::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=CC1101_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode.
Definition: CC1101.cpp:661
+
CC1101::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: CC1101.cpp:764
+
CC1101::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return CC1101_VERSION_LEGACY (0x04) or CC1101_VERSION_CURRENT (0x14...
Definition: CC1101.cpp:788
+
CC1101::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=CC1101_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode.
Definition: CC1101.cpp:660
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
CC1101::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data received after calling startReceive method.
Definition: CC1101.cpp:308
CC1101::clearGdo2Action
void clearGdo2Action()
Clears interrupt service routine to call when GDO0 activates.
Definition: CC1101.cpp:242
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CC1101::setSyncWord
int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)
Sets 16-bit sync word as a two byte value.
Definition: CC1101.cpp:539
+
CC1101::setSyncWord
int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)
Sets 16-bit sync word as a two byte value.
Definition: CC1101.cpp:538
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
CC1101::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: CC1101.cpp:98
CC1101::receive
int16_t receive(uint8_t *data, size_t len) override
Blocking binary receive method. Overloads for string-based transmissions are implemented in PhysicalL...
Definition: CC1101.cpp:139
CC1101::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values are in bands 300.0 to 348.0 MHz, 387.0 to 464.0 MHz and 779.0 to 928.0 MHz.
Definition: CC1101.cpp:348
CC1101::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets frequency deviation. Allowed values range from 1.587 to 380.8 kHz.
Definition: CC1101.cpp:414
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
-
CC1101::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs=0)
Sets node and broadcast addresses. Calling this method will also enable address filtering.
Definition: CC1101.cpp:581
+
CC1101::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs=0)
Sets node and broadcast addresses. Calling this method will also enable address filtering.
Definition: CC1101.cpp:580
CC1101::CC1101
CC1101(Module *module)
Default constructor.
Definition: CC1101.cpp:4
CC1101::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Starts direct mode transmission.
Definition: CC1101.cpp:184
CC1101::setBitRate
int16_t setBitRate(float br)
Sets bit rate. Allowed values range from 0.025 to 600.0 kbps.
Definition: CC1101.cpp:374
-
CC1101::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: CC1101.cpp:696
-
CC1101::setCrcFiltering
int16_t setCrcFiltering(bool crcOn=true)
Enable CRC filtering and generation.
Definition: CC1101.cpp:686
-
CC1101::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: CC1101.cpp:602
-
CC1101::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLength)
Sets preamble length.
Definition: CC1101.cpp:544
+
CC1101::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: CC1101.cpp:695
+
CC1101::setCrcFiltering
int16_t setCrcFiltering(bool crcOn=true)
Enable CRC filtering and generation.
Definition: CC1101.cpp:685
+
CC1101::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: CC1101.cpp:601
+
CC1101::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLength)
Sets preamble length.
Definition: CC1101.cpp:543
CC1101::receiveDirect
int16_t receiveDirect() override
Starts direct mode reception.
Definition: CC1101.cpp:206
-
CC1101::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Allowed value is RADI...
Definition: CC1101.cpp:722
+
CC1101::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Allowed value is RADI...
Definition: CC1101.cpp:721
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
diff --git a/_hellschreiber_8h_source.html b/_hellschreiber_8h_source.html index 6abdcf6f..d921968d 100644 --- a/_hellschreiber_8h_source.html +++ b/_hellschreiber_8h_source.html @@ -89,7 +89,7 @@ $(document).ready(function(){initNavTree('_hellschreiber_8h_source.html','');});
HellClient
Client for Hellschreiber transmissions.
Definition: Hellschreiber.h:89
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
HellClient::begin
int16_t begin(float base, float rate=122.5)
Initialization method.
Definition: Hellschreiber.cpp:19
-
HellClient::printGlyph
size_t printGlyph(uint8_t *buff)
Method to "print" a buffer of pixels, this is exposed to allow users to send custom characters...
Definition: Hellschreiber.cpp:38
+
HellClient::printGlyph
size_t printGlyph(uint8_t *buff)
Method to "print" a buffer of pixels, this is exposed to allow users to send custom characters...
Definition: Hellschreiber.cpp:31
diff --git a/_morse_8h_source.html b/_morse_8h_source.html index d032ddcf..9f5146ed 100644 --- a/_morse_8h_source.html +++ b/_morse_8h_source.html @@ -88,7 +88,7 @@ $(document).ready(function(){initNavTree('_morse_8h_source.html','');});
MorseClient::begin
int16_t begin(float base, uint8_t speed=20)
Initialization method.
Definition: Morse.cpp:18
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
MorseClient::MorseClient
MorseClient(PhysicalLayer *phy)
Constructor for 2-FSK mode.
Definition: Morse.cpp:4
-
MorseClient::startSignal
size_t startSignal()
Send start signal.
Definition: Morse.cpp:37
+
MorseClient::startSignal
size_t startSignal()
Send start signal.
Definition: Morse.cpp:30
MorseClient
Client for Morse Code communication. The public interface is the same as Arduino Serial.
Definition: Morse.h:89
diff --git a/_physical_layer_8h_source.html b/_physical_layer_8h_source.html index 5040d336..ffb0f00c 100644 --- a/_physical_layer_8h_source.html +++ b/_physical_layer_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_physical_layer_8h_source.html','');})
PhysicalLayer.h
-
1 #ifndef _RADIOLIB_PHYSICAL_LAYER_H
2 #define _RADIOLIB_PHYSICAL_LAYER_H
3 
4 #include "../../TypeDef.h"
5 
13 class PhysicalLayer {
14  public:
15 
16  // constructor
17 
25  PhysicalLayer(float freqStep, size_t maxPacketLength);
26 
27  // basic methods
28 
38  int16_t transmit(__FlashStringHelper* fstr, uint8_t addr = 0);
39 
49  int16_t transmit(String& str, uint8_t addr = 0);
50 
60  int16_t transmit(const char* str, uint8_t addr = 0);
61 
73  virtual int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
74 
84  int16_t receive(String& str, size_t len = 0);
85 
91  virtual int16_t standby() = 0;
92 
102  virtual int16_t receive(uint8_t* data, size_t len) = 0;
103 
114  int16_t startTransmit(String& str, uint8_t addr = 0);
115 
126  int16_t startTransmit(const char* str, uint8_t addr = 0);
127 
139  virtual int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
140 
150  int16_t readData(String& str, size_t len = 0);
151 
161  virtual int16_t readData(uint8_t* data, size_t len) = 0;
162 
171  virtual int16_t transmitDirect(uint32_t frf = 0) = 0;
172 
179  virtual int16_t receiveDirect() = 0;
180 
181  // configuration methods
182 
191  virtual int16_t setFrequencyDeviation(float freqDev) = 0;
192 
200  virtual int16_t setDataShaping(uint8_t sh) = 0;
201 
209  virtual int16_t setEncoding(uint8_t encoding) = 0;
210 
216  float getFreqStep() const;
217 
225  virtual size_t getPacketLength(bool update = true) = 0;
226 
234  int32_t random(int32_t max);
235 
245  int32_t random(int32_t min, int32_t max);
246 
252  virtual uint8_t random() = 0;
253 
254 #ifndef RADIOLIB_GODMODE
255  private:
256 #endif
257  float _freqStep;
258  size_t _maxPacketLength;
259 };
260 
261 #endif
PhysicalLayer::setEncoding
virtual int16_t setEncoding(uint8_t encoding)=0
Sets FSK data encoding. Only available in FSK mode. Must be implemented in module class...
+
1 #ifndef _RADIOLIB_PHYSICAL_LAYER_H
2 #define _RADIOLIB_PHYSICAL_LAYER_H
3 
4 #include "../../TypeDef.h"
5 
13 class PhysicalLayer {
14  public:
15 
16  // constructor
17 
25  PhysicalLayer(float freqStep, size_t maxPacketLength);
26 
27  // basic methods
28 
38  int16_t transmit(__FlashStringHelper* fstr, uint8_t addr = 0);
39 
49  int16_t transmit(String& str, uint8_t addr = 0);
50 
60  int16_t transmit(const char* str, uint8_t addr = 0);
61 
73  virtual int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
74 
84  int16_t receive(String& str, size_t len = 0);
85 
91  virtual int16_t standby() = 0;
92 
102  virtual int16_t receive(uint8_t* data, size_t len) = 0;
103 
114  int16_t startTransmit(String& str, uint8_t addr = 0);
115 
126  int16_t startTransmit(const char* str, uint8_t addr = 0);
127 
139  virtual int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) = 0;
140 
150  int16_t readData(String& str, size_t len = 0);
151 
161  virtual int16_t readData(uint8_t* data, size_t len) = 0;
162 
171  virtual int16_t transmitDirect(uint32_t frf = 0) = 0;
172 
179  virtual int16_t receiveDirect() = 0;
180 
181  // configuration methods
182 
191  virtual int16_t setFrequencyDeviation(float freqDev) = 0;
192 
200  virtual int16_t setDataShaping(uint8_t sh) = 0;
201 
209  virtual int16_t setEncoding(uint8_t encoding) = 0;
210 
216  float getFreqStep() const;
217 
225  virtual size_t getPacketLength(bool update = true) = 0;
226 
234  int32_t random(int32_t max);
235 
245  int32_t random(int32_t min, int32_t max);
246 
252  virtual uint8_t random() = 0;
253 
259  int16_t startDirect();
260 
261 #ifndef RADIOLIB_GODMODE
262  private:
263 #endif
264  float _freqStep;
265  size_t _maxPacketLength;
266 };
267 
268 #endif
PhysicalLayer::setEncoding
virtual int16_t setEncoding(uint8_t encoding)=0
Sets FSK data encoding. Only available in FSK mode. Must be implemented in module class...
PhysicalLayer::getFreqStep
float getFreqStep() const
Gets the module frequency step size that was set in constructor.
Definition: PhysicalLayer.cpp:143
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
PhysicalLayer::random
virtual uint8_t random()=0
Get one truly random byte from RSSI noise. Must be implemented in module class.
@@ -94,6 +94,7 @@ $(document).ready(function(){initNavTree('_physical_layer_8h_source.html','');})
PhysicalLayer::PhysicalLayer
PhysicalLayer(float freqStep, size_t maxPacketLength)
Default constructor.
Definition: PhysicalLayer.cpp:3
PhysicalLayer::setDataShaping
virtual int16_t setDataShaping(uint8_t sh)=0
Sets GFSK data shaping. Only available in FSK mode. Must be implemented in module class...
PhysicalLayer::standby
virtual int16_t standby()=0
Sets module to standby.
+
PhysicalLayer::startDirect
int16_t startDirect()
Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX...
Definition: PhysicalLayer.cpp:171
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
diff --git a/_r_f69_8h_source.html b/_r_f69_8h_source.html index bbf26598..fb2419bb 100644 --- a/_r_f69_8h_source.html +++ b/_r_f69_8h_source.html @@ -85,57 +85,57 @@ $(document).ready(function(){initNavTree('_r_f69_8h_source.html','');});
1 #if !defined(_RADIOLIB_RF69_H)
2 #define _RADIOLIB_RF69_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_RF69)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // RF69 physical layer properties
13 #define RF69_FREQUENCY_STEP_SIZE 61.03515625
14 #define RF69_MAX_PACKET_LENGTH 64
15 #define RF69_CRYSTAL_FREQ 32.0
16 #define RF69_DIV_EXPONENT 19
17 
18 // RF69 register map
19 #define RF69_REG_FIFO 0x00
20 #define RF69_REG_OP_MODE 0x01
21 #define RF69_REG_DATA_MODUL 0x02
22 #define RF69_REG_BITRATE_MSB 0x03
23 #define RF69_REG_BITRATE_LSB 0x04
24 #define RF69_REG_FDEV_MSB 0x05
25 #define RF69_REG_FDEV_LSB 0x06
26 #define RF69_REG_FRF_MSB 0x07
27 #define RF69_REG_FRF_MID 0x08
28 #define RF69_REG_FRF_LSB 0x09
29 #define RF69_REG_OSC_1 0x0A
30 #define RF69_REG_AFC_CTRL 0x0B
31 #define RF69_REG_LISTEN_1 0x0D
32 #define RF69_REG_LISTEN_2 0x0E
33 #define RF69_REG_LISTEN_3 0x0F
34 #define RF69_REG_VERSION 0x10
35 #define RF69_REG_PA_LEVEL 0x11
36 #define RF69_REG_PA_RAMP 0x12
37 #define RF69_REG_OCP 0x13
38 #define RF69_REG_LNA 0x18
39 #define RF69_REG_RX_BW 0x19
40 #define RF69_REG_AFC_BW 0x1A
41 #define RF69_REG_OOK_PEAK 0x1B
42 #define RF69_REG_OOK_AVG 0x1C
43 #define RF69_REG_OOK_FIX 0x1D
44 #define RF69_REG_AFC_FEI 0x1E
45 #define RF69_REG_AFC_MSB 0x1F
46 #define RF69_REG_AFC_LSB 0x20
47 #define RF69_REG_FEI_MSB 0x21
48 #define RF69_REG_FEI_LSB 0x22
49 #define RF69_REG_RSSI_CONFIG 0x23
50 #define RF69_REG_RSSI_VALUE 0x24
51 #define RF69_REG_DIO_MAPPING_1 0x25
52 #define RF69_REG_DIO_MAPPING_2 0x26
53 #define RF69_REG_IRQ_FLAGS_1 0x27
54 #define RF69_REG_IRQ_FLAGS_2 0x28
55 #define RF69_REG_RSSI_THRESH 0x29
56 #define RF69_REG_RX_TIMEOUT_1 0x2A
57 #define RF69_REG_RX_TIMEOUT_2 0x2B
58 #define RF69_REG_PREAMBLE_MSB 0x2C
59 #define RF69_REG_PREAMBLE_LSB 0x2D
60 #define RF69_REG_SYNC_CONFIG 0x2E
61 #define RF69_REG_SYNC_VALUE_1 0x2F
62 #define RF69_REG_SYNC_VALUE_2 0x30
63 #define RF69_REG_SYNC_VALUE_3 0x31
64 #define RF69_REG_SYNC_VALUE_4 0x32
65 #define RF69_REG_SYNC_VALUE_5 0x33
66 #define RF69_REG_SYNC_VALUE_6 0x34
67 #define RF69_REG_SYNC_VALUE_7 0x35
68 #define RF69_REG_SYNC_VALUE_8 0x36
69 #define RF69_REG_PACKET_CONFIG_1 0x37
70 #define RF69_REG_PAYLOAD_LENGTH 0x38
71 #define RF69_REG_NODE_ADRS 0x39
72 #define RF69_REG_BROADCAST_ADRS 0x3A
73 #define RF69_REG_AUTO_MODES 0x3B
74 #define RF69_REG_FIFO_THRESH 0x3C
75 #define RF69_REG_PACKET_CONFIG_2 0x3D
76 #define RF69_REG_AES_KEY_1 0x3E
77 #define RF69_REG_AES_KEY_2 0x3F
78 #define RF69_REG_AES_KEY_3 0x40
79 #define RF69_REG_AES_KEY_4 0x41
80 #define RF69_REG_AES_KEY_5 0x42
81 #define RF69_REG_AES_KEY_6 0x43
82 #define RF69_REG_AES_KEY_7 0x44
83 #define RF69_REG_AES_KEY_8 0x45
84 #define RF69_REG_AES_KEY_9 0x46
85 #define RF69_REG_AES_KEY_10 0x47
86 #define RF69_REG_AES_KEY_11 0x48
87 #define RF69_REG_AES_KEY_12 0x49
88 #define RF69_REG_AES_KEY_13 0x4A
89 #define RF69_REG_AES_KEY_14 0x4B
90 #define RF69_REG_AES_KEY_15 0x4C
91 #define RF69_REG_AES_KEY_16 0x4D
92 #define RF69_REG_TEMP_1 0x4E
93 #define RF69_REG_TEMP_2 0x4F
94 #define RF69_REG_TEST_PA1 0x5A
95 #define RF69_REG_TEST_PA2 0x5C
96 #define RF69_REG_TEST_DAGC 0x6F
97 
98 // RF69 modem settings
99 // RF69_REG_OP_MODE MSB LSB DESCRIPTION
100 #define RF69_SEQUENCER_OFF 0b00000000 // 7 7 disable automatic sequencer
101 #define RF69_SEQUENCER_ON 0b10000000 // 7 7 enable automatic sequencer
102 #define RF69_LISTEN_OFF 0b00000000 // 6 6 disable Listen mode
103 #define RF69_LISTEN_ON 0b01000000 // 6 6 enable Listen mode
104 #define RF69_LISTEN_ABORT 0b00100000 // 5 5 abort Listen mode (has to be set together with RF69_LISTEN_OFF)
105 #define RF69_SLEEP 0b00000000 // 4 2 sleep
106 #define RF69_STANDBY 0b00000100 // 4 2 standby
107 #define RF69_FS 0b00001000 // 4 2 frequency synthesis
108 #define RF69_TX 0b00001100 // 4 2 transmit
109 #define RF69_RX 0b00010000 // 4 2 receive
110 
111 // RF69_REG_DATA_MODUL
112 #define RF69_PACKET_MODE 0b00000000 // 6 5 packet mode (default)
113 #define RF69_CONTINUOUS_MODE_WITH_SYNC 0b01000000 // 6 5 continuous mode with bit synchronizer
114 #define RF69_CONTINUOUS_MODE 0b01100000 // 6 5 continuous mode without bit synchronizer
115 #define RF69_FSK 0b00000000 // 4 3 modulation: FSK (default)
116 #define RF69_OOK 0b00001000 // 4 3 OOK
117 #define RF69_NO_SHAPING 0b00000000 // 1 0 modulation shaping: no shaping (default)
118 #define RF69_FSK_GAUSSIAN_1_0 0b00000001 // 1 0 FSK modulation Gaussian filter, BT = 1.0
119 #define RF69_FSK_GAUSSIAN_0_5 0b00000010 // 1 0 FSK modulation Gaussian filter, BT = 0.5
120 #define RF69_FSK_GAUSSIAN_0_3 0b00000011 // 1 0 FSK modulation Gaussian filter, BT = 0.3
121 #define RF69_OOK_FILTER_BR 0b00000001 // 1 0 OOK modulation filter, f_cutoff = BR
122 #define RF69_OOK_FILTER_2BR 0b00000010 // 1 0 OOK modulation filter, f_cutoff = 2*BR
123 
124 // RF69_REG_BITRATE_MSB + REG_BITRATE_LSB
125 #define RF69_BITRATE_MSB 0x1A // 7 0 bit rate setting: rate = F(XOSC) / BITRATE
126 #define RF69_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps 0x40 // 7 0
127 
128 // RF69_REG_FDEV_MSB + REG_FDEV_LSB
129 #define RF69_FDEV_MSB 0x00 // 5 0 frequency deviation: f_dev = f_step * FDEV
130 #define RF69_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
131 
132 // RF69_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
133 #define RF69_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
134 #define RF69_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
135 #define RF69_FRF_LSB 0x00 // 7 0 default value: 915 MHz
136 
137 // RF69_REG_OSC_1
138 #define RF69_RC_CAL_START 0b10000000 // 7 7 force RC oscillator calibration
139 #define RF69_RC_CAL_RUNNING 0b00000000 // 6 6 RC oscillator calibration is still running
140 #define RF69_RC_CAL_DONE 0b00000000 // 5 5 RC oscillator calibration has finished
141 
142 // RF69_REG_AFC_CTRL
143 #define RF69_AFC_LOW_BETA_OFF 0b00000000 // 5 5 standard AFC routine
144 #define RF69_AFC_LOW_BETA_ON 0b00100000 // 5 5 improved AFC routine for signals with modulation index less than 2
145 
146 // RF69_REG_LISTEN_1
147 #define RF69_LISTEN_RES_IDLE_64_US 0b01000000 // 7 6 resolution of Listen mode idle time: 64 us
148 #define RF69_LISTEN_RES_IDLE_4_1_MS 0b10000000 // 7 6 4.1 ms (default)
149 #define RF69_LISTEN_RES_IDLE_262_MS 0b11000000 // 7 6 262 ms
150 #define RF69_LISTEN_RES_RX_64_US 0b00010000 // 5 4 resolution of Listen mode rx time: 64 us (default)
151 #define RF69_LISTEN_RES_RX_4_1_MS 0b00100000 // 5 4 4.1 ms
152 #define RF69_LISTEN_RES_RX_262_MS 0b00110000 // 5 4 262 ms
153 #define RF69_LISTEN_ACCEPT_ABOVE_RSSI_THRESH 0b00000000 // 3 3 packet acceptance criteria: RSSI above threshold
154 #define RF69_LISTEN_ACCEPT_MATCH_SYNC_ADDRESS 0b00001000 // 3 3 RSSI above threshold AND sync address matched
155 #define RF69_LISTEN_END_KEEP_RX 0b00000000 // 2 1 action after packet acceptance: stay in Rx mode
156 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT 0b00000010 // 2 1 stay in Rx mode until timeout (default)
157 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT_RESUME 0b00000100 // 2 1 stay in Rx mode until timeout, Listen mode will resume
158 
159 // RF69_REG_LISTEN_2
160 #define RF69_LISTEN_COEF_IDLE 0xF5 // 7 0 duration of idle phase in Listen mode
161 
162 // RF69_REG_LISTEN_3
163 #define RF69_LISTEN_COEF_RX 0x20 // 7 0 duration of Rx phase in Listen mode
164 
165 // RF69_REG_VERSION
166 #define RF69_CHIP_VERSION 0x24 // 7 0
167 
168 // RF69_REG_PA_LEVEL
169 #define RF69_PA0_OFF 0b00000000 // 7 7 PA0 disabled
170 #define RF69_PA0_ON 0b10000000 // 7 7 PA0 enabled (default)
171 #define RF69_PA1_OFF 0b00000000 // 6 6 PA1 disabled (default)
172 #define RF69_PA1_ON 0b01000000 // 6 6 PA1 enabled
173 #define RF69_PA2_OFF 0b00000000 // 5 5 PA2 disabled (default)
174 #define RF69_PA2_ON 0b00100000 // 5 5 PA2 enabled
175 #define RF69_OUTPUT_POWER 0b00011111 // 4 0 output power: P_out = -18 + OUTPUT_POWER
176 
177 // RF69_REG_PA_RAMP
178 #define RF69_PA_RAMP_3_4_MS 0b00000000 // 3 0 PA ramp rise/fall time: 3.4 ms
179 #define RF69_PA_RAMP_2_MS 0b00000001 // 3 0 2 ms
180 #define RF69_PA_RAMP_1_MS 0b00000010 // 3 0 1 ms
181 #define RF69_PA_RAMP_500_US 0b00000011 // 3 0 500 us
182 #define RF69_PA_RAMP_250_US 0b00000100 // 3 0 250 us
183 #define RF69_PA_RAMP_125_US 0b00000101 // 3 0 125 us
184 #define RF69_PA_RAMP_100_US 0b00000110 // 3 0 100 us
185 #define RF69_PA_RAMP_62_US 0b00000111 // 3 0 62 us
186 #define RF69_PA_RAMP_50_US 0b00001000 // 3 0 50 us
187 #define RF69_PA_RAMP_40_US 0b00001001 // 3 0 40 us (default)
188 #define RF69_PA_RAMP_31_US 0b00001010 // 3 0 31 us
189 #define RF69_PA_RAMP_25_US 0b00001011 // 3 0 25 us
190 #define RF69_PA_RAMP_20_US 0b00001100 // 3 0 20 us
191 #define RF69_PA_RAMP_15_US 0b00001101 // 3 0 15 us
192 #define RF69_PA_RAMP_12_US 0b00001110 // 3 0 12 us
193 #define RF69_PA_RAMP_10_US 0b00001111 // 3 0 10 us
194 
195 // RF69_REG_OCP
196 #define RF69_OCP_OFF 0b00000000 // 4 4 PA overload current protection disabled
197 #define RF69_OCP_ON 0b00010000 // 4 4 PA overload current protection enabled
198 #define RF69_OCP_TRIM 0b00001010 // 3 0 OCP current: I_max(OCP_TRIM = 0b1010) = 95 mA
199 
200 // RF69_REG_LNA
201 #define RF69_LNA_Z_IN_50_OHM 0b00000000 // 7 7 LNA input impedance: 50 ohm
202 #define RF69_LNA_Z_IN_200_OHM 0b10000000 // 7 7 200 ohm
203 #define RF69_LNA_CURRENT_GAIN 0b00001000 // 5 3 manually set LNA current gain
204 #define RF69_LNA_GAIN_AUTO 0b00000000 // 2 0 LNA gain setting: set automatically by AGC
205 #define RF69_LNA_GAIN_MAX 0b00000001 // 2 0 max gain
206 #define RF69_LNA_GAIN_MAX_6_DB 0b00000010 // 2 0 max gain - 6 dB
207 #define RF69_LNA_GAIN_MAX_12_DB 0b00000011 // 2 0 max gain - 12 dB
208 #define RF69_LNA_GAIN_MAX_24_DB 0b00000100 // 2 0 max gain - 24 dB
209 #define RF69_LNA_GAIN_MAX_36_DB 0b00000101 // 2 0 max gain - 36 dB
210 #define RF69_LNA_GAIN_MAX_48_DB 0b00000110 // 2 0 max gain - 48 dB
211 
212 // RF69_REG_RX_BW
213 #define RF69_DCC_FREQ 0b01000000 // 7 5 DC offset canceller cutoff frequency (4% Rx BW by default)
214 #define RF69_RX_BW_MANT_16 0b00000000 // 4 3 Channel filter bandwidth FSK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 2))
215 #define RF69_RX_BW_MANT_20 0b00001000 // 4 3 OOK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 3))
216 #define RF69_RX_BW_MANT_24 0b00010000 // 4 3
217 #define RF69_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp value = 5
218 
219 // RF69_REG_AFC_BW
220 #define RF69_DCC_FREQ_AFC 0b10000000 // 7 5 default DccFreq parameter for AFC
221 #define RF69_DCC_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter for AFC
222 #define RF69_DCC_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter for AFC
223 
224 // RF69_REG_OOK_PEAK
225 #define RF69_OOK_THRESH_FIXED 0b00000000 // 7 6 OOK threshold type: fixed
226 #define RF69_OOK_THRESH_PEAK 0b01000000 // 7 6 peak (default)
227 #define RF69_OOK_THRESH_AVERAGE 0b10000000 // 7 6 average
228 #define RF69_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 5 3 OOK demodulator step size: 0.5 dB (default)
229 #define RF69_OOK_PEAK_THRESH_STEP_1_0_DB 0b00001000 // 5 3 1.0 dB
230 #define RF69_OOK_PEAK_THRESH_STEP_1_5_DB 0b00010000 // 5 3 1.5 dB
231 #define RF69_OOK_PEAK_THRESH_STEP_2_0_DB 0b00011000 // 5 3 2.0 dB
232 #define RF69_OOK_PEAK_THRESH_STEP_3_0_DB 0b00100000 // 5 3 3.0 dB
233 #define RF69_OOK_PEAK_THRESH_STEP_4_0_DB 0b00101000 // 5 3 4.0 dB
234 #define RF69_OOK_PEAK_THRESH_STEP_5_0_DB 0b00110000 // 5 3 5.0 dB
235 #define RF69_OOK_PEAK_THRESH_STEP_6_0_DB 0b00111000 // 5 3 6.0 dB
236 #define RF69_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 2 0 OOK demodulator step period: once per chip (default)
237 #define RF69_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00000001 // 2 0 once every 2 chips
238 #define RF69_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b00000010 // 2 0 once every 4 chips
239 #define RF69_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b00000011 // 2 0 once every 8 chips
240 #define RF69_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b00000100 // 2 0 2 times per chip
241 #define RF69_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b00000101 // 2 0 4 times per chip
242 #define RF69_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b00000110 // 2 0 8 times per chip
243 #define RF69_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b00000111 // 2 0 16 times per chip
244 
245 // RF69_REG_OOK_AVG
246 #define RF69_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 7 6 OOK average filter coefficient: chip rate / 32*pi
247 #define RF69_OOK_AVG_THRESH_FILT_8_PI 0b01000000 // 7 6 chip rate / 8*pi
248 #define RF69_OOK_AVG_THRESH_FILT_4_PI 0b10000000 // 7 6 chip rate / 4*pi (default)
249 #define RF69_OOK_AVG_THRESH_FILT_2_PI 0b11000000 // 7 6 chip rate / 2*pi
250 
251 // RF69_REG_OOK_FIX
252 #define RF69_OOK_FIXED_THRESH 0b00000110 // 7 0 default OOK fixed threshold (6 dB)
253 
254 // RF69_REG_AFC_FEI
255 #define RF69_FEI_RUNNING 0b00000000 // 6 6 FEI status: on-going
256 #define RF69_FEI_DONE 0b01000000 // 6 6 done
257 #define RF69_FEI_START 0b00100000 // 5 5 force new FEI measurement
258 #define RF69_AFC_RUNNING 0b00000000 // 4 4 AFC status: on-going
259 #define RF69_AFC_DONE 0b00010000 // 4 4 done
260 #define RF69_AFC_AUTOCLEAR_OFF 0b00000000 // 3 3 AFC register autoclear disabled
261 #define RF69_AFC_AUTOCLEAR_ON 0b00001000 // 3 3 AFC register autoclear enabled
262 #define RF69_AFC_AUTO_OFF 0b00000000 // 2 2 perform AFC only manually
263 #define RF69_AFC_AUTO_ON 0b00000100 // 2 2 perform AFC each time Rx mode is started
264 #define RF69_AFC_CLEAR 0b00000010 // 1 1 clear AFC register
265 #define RF69_AFC_START 0b00000001 // 0 0 start AFC
266 
267 // RF69_REG_RSSI_CONFIG
268 #define RF69_RSSI_RUNNING 0b00000000 // 1 1 RSSI status: on-going
269 #define RF69_RSSI_DONE 0b00000010 // 1 1 done
270 #define RF69_RSSI_START 0b00000001 // 0 0 start RSSI measurement
271 
272 // RF69_REG_DIO_MAPPING_1
273 #define RF69_DIO0_CONT_MODE_READY 0b11000000 // 7 6
274 #define RF69_DIO0_CONT_PLL_LOCK 0b00000000 // 7 6
275 #define RF69_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
276 #define RF69_DIO0_CONT_TIMEOUT 0b01000000 // 7 6
277 #define RF69_DIO0_CONT_RSSI 0b10000000 // 7 6
278 #define RF69_DIO0_CONT_TX_READY 0b01000000 // 7 6
279 #define RF69_DIO0_PACK_PLL_LOCK 0b11000000 // 7 6
280 #define RF69_DIO0_PACK_CRC_OK 0b00000000 // 7 6
281 #define RF69_DIO0_PACK_PAYLOAD_READY 0b01000000 // 7 6
282 #define RF69_DIO0_PACK_SYNC_ADDRESS 0b10000000 // 7 6
283 #define RF69_DIO0_PACK_RSSI 0b11000000 // 7 6
284 #define RF69_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
285 #define RF69_DIO0_PACK_TX_READY 0b01000000 // 7 6
286 #define RF69_DIO1_CONT_PLL_LOCK 0b00110000 // 5 4
287 #define RF69_DIO1_CONT_DCLK 0b00000000 // 5 4
288 #define RF69_DIO1_CONT_RX_READY 0b00010000 // 5 4
289 #define RF69_DIO1_CONT_SYNC_ADDRESS 0b00110000 // 5 4
290 #define RF69_DIO1_CONT_TX_READY 0b00010000 // 5 4
291 #define RF69_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
292 #define RF69_DIO1_PACK_FIFO_FULL 0b00010000 // 5 4
293 #define RF69_DIO1_PACK_FIFO_NOT_EMPTY 0b00100000 // 5 4
294 #define RF69_DIO1_PACK_PLL_LOCK 0b00110000 // 5 4
295 #define RF69_DIO1_PACK_TIMEOUT 0b00110000 // 5 4
296 #define RF69_DIO2_CONT_DATA 0b00000000 // 3 2
297 
298 // RF69_REG_DIO_MAPPING_2
299 #define RF69_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
300 #define RF69_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
301 #define RF69_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
302 #define RF69_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
303 #define RF69_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
304 #define RF69_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 31
305 #define RF69_CLK_OUT_RC 0b00000110 // 2 0 RC
306 #define RF69_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
307 
308 // RF69_REG_IRQ_FLAGS_1
309 #define RF69_IRQ_MODE_READY 0b10000000 // 7 7 requested mode was set
310 #define RF69_IRQ_RX_READY 0b01000000 // 6 6 Rx mode ready
311 #define RF69_IRQ_TX_READY 0b00100000 // 5 5 Tx mode ready
312 #define RF69_IRQ_PLL_LOCK 0b00010000 // 4 4 PLL is locked
313 #define RF69_IRQ_RSSI 0b00001000 // 3 3 RSSI value exceeded RssiThreshold
314 #define RF69_IRQ_TIMEOUT 0b00000100 // 2 2 timeout occurred
315 #define RF69_IRQ_AUTO_MODE 0b00000010 // 1 1 entered intermediate mode
316 #define RF69_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address detected
317 
318 // RF69_REG_IRQ_FLAGS_2
319 #define RF69_IRQ_FIFO_FULL 0b10000000 // 7 7 FIFO is full
320 #define RF69_IRQ_FIFO_NOT_EMPTY 0b01000000 // 6 6 FIFO contains at least 1 byte
321 #define RF69_IRQ_FIFO_LEVEL 0b00100000 // 5 5 FIFO contains more than FifoThreshold bytes
322 #define RF69_IRQ_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
323 #define RF69_IRQ_PACKET_SENT 0b00001000 // 3 3 packet was sent
324 #define RF69_IRQ_PAYLOAD_READY 0b00000100 // 2 2 last payload byte received and CRC check passed
325 #define RF69_IRQ_CRC_OK 0b00000010 // 1 1 CRC check passed
326 
327 // RF69_REG_RSSI_THRESH
328 #define RF69_RSSI_THRESHOLD 0xE4 // 7 0 RSSI threshold level (2 dB by default)
329 
330 // RF69_REG_RX_TIMEOUT_1
331 #define RF69_TIMEOUT_RX_START_OFF 0x00 // 7 0 RSSI interrupt timeout disabled (default)
332 #define RF69_TIMEOUT_RX_START 0xFF // 7 0 timeout will occur if RSSI interrupt is not received
333 
334 // RF69_REG_RX_TIMEOUT_2
335 #define RF69_TIMEOUT_RSSI_THRESH_OFF 0x00 // 7 0 PayloadReady interrupt timeout disabled (default)
336 #define RF69_TIMEOUT_RSSI_THRESH 0xFF // 7 0 timeout will occur if PayloadReady interrupt is not received
337 
338 // RF69_REG_PREAMBLE_MSB + REG_PREAMBLE_MSB
339 #define RF69_PREAMBLE_MSB 0x00 // 7 0 2-byte preamble size value
340 #define RF69_PREAMBLE_LSB 0x03 // 7 0
341 
342 // RF69_REG_SYNC_CONFIG
343 #define RF69_SYNC_OFF 0b00000000 // 7 7 sync word detection off
344 #define RF69_SYNC_ON 0b10000000 // 7 7 sync word detection on (default)
345 #define RF69_FIFO_FILL_CONDITION_SYNC 0b00000000 // 6 6 FIFO fill condition: on SyncAddress interrupt (default)
346 #define RF69_FIFO_FILL_CONDITION 0b01000000 // 6 6 as long as the bit is set
347 #define RF69_SYNC_SIZE 0b00001000 // 5 3 size of sync word: SyncSize + 1 bytes
348 #define RF69_SYNC_TOL 0b00000000 // 2 0 number of tolerated errors in sync word
349 
350 // RF69_REG_SYNC_VALUE_1 - SYNC_VALUE_8
351 #define RF69_SYNC_BYTE_1 0x01 // 7 0 sync word: 1st byte (MSB)
352 #define RF69_SYNC_BYTE_2 0x01 // 7 0 2nd byte
353 #define RF69_SYNC_BYTE_3 0x01 // 7 0 3rd byte
354 #define RF69_SYNC_BYTE_4 0x01 // 7 0 4th byte
355 #define RF69_SYNC_BYTE_5 0x01 // 7 0 5th byte
356 #define RF69_SYNC_BYTE_6 0x01 // 7 0 6th byte
357 #define RF69_SYNC_BYTE_7 0x01 // 7 0 7th byte
358 #define RF69_SYNC_BYTE_8 0x01 // 7 0 8th byte (LSB)
359 
360 // RF69_REG_PACKET_CONFIG_1
361 #define RF69_PACKET_FORMAT_FIXED 0b00000000 // 7 7 fixed packet length (default)
362 #define RF69_PACKET_FORMAT_VARIABLE 0b10000000 // 7 7 variable packet length
363 #define RF69_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: none (default)
364 #define RF69_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
365 #define RF69_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
366 #define RF69_CRC_OFF 0b00000000 // 4 4 CRC disabled
367 #define RF69_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
368 #define RF69_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 discard packet when CRC check fails (default)
369 #define RF69_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep packet when CRC check fails
370 #define RF69_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
371 #define RF69_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
372 #define RF69_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
373 
374 // RF69_REG_PAYLOAD_LENGTH
375 #define RF69_PAYLOAD_LENGTH 0xFF // 7 0 payload length
376 
377 // RF69_REG_AUTO_MODES
378 #define RF69_ENTER_COND_NONE 0b00000000 // 7 5 condition for entering intermediate mode: none, AutoModes disabled (default)
379 #define RF69_ENTER_COND_FIFO_NOT_EMPTY 0b00100000 // 7 5 FifoNotEmpty rising edge
380 #define RF69_ENTER_COND_FIFO_LEVEL 0b01000000 // 7 5 FifoLevel rising edge
381 #define RF69_ENTER_COND_CRC_OK 0b01100000 // 7 5 CrcOk rising edge
382 #define RF69_ENTER_COND_PAYLOAD_READY 0b10000000 // 7 5 PayloadReady rising edge
383 #define RF69_ENTER_COND_SYNC_ADDRESS 0b10100000 // 7 5 SyncAddress rising edge
384 #define RF69_ENTER_COND_PACKET_SENT 0b11000000 // 7 5 PacketSent rising edge
385 #define RF69_ENTER_COND_FIFO_EMPTY 0b11100000 // 7 5 FifoNotEmpty falling edge
386 #define RF69_EXIT_COND_NONE 0b00000000 // 4 2 condition for exiting intermediate mode: none, AutoModes disabled (default)
387 #define RF69_EXIT_COND_FIFO_EMPTY 0b00100000 // 4 2 FifoNotEmpty falling edge
388 #define RF69_EXIT_COND_FIFO_LEVEL 0b01000000 // 4 2 FifoLevel rising edge
389 #define RF69_EXIT_COND_CRC_OK 0b01100000 // 4 2 CrcOk rising edge
390 #define RF69_EXIT_COND_PAYLOAD_READY 0b10000000 // 4 2 PayloadReady rising edge
391 #define RF69_EXIT_COND_SYNC_ADDRESS 0b10100000 // 4 2 SyncAddress rising edge
392 #define RF69_EXIT_COND_PACKET_SENT 0b11000000 // 4 2 PacketSent rising edge
393 #define RF69_EXIT_COND_TIMEOUT 0b11100000 // 4 2 timeout rising edge
394 #define RF69_INTER_MODE_SLEEP 0b00000000 // 1 0 intermediate mode: sleep (default)
395 #define RF69_INTER_MODE_STANDBY 0b00000001 // 1 0 standby
396 #define RF69_INTER_MODE_RX 0b00000010 // 1 0 Rx
397 #define RF69_INTER_MODE_TX 0b00000011 // 1 0 Tx
398 
399 // RF69_REG_FIFO_THRESH
400 #define RF69_TX_START_CONDITION_FIFO_LEVEL 0b00000000 // 7 7 packet transmission start condition: FifoLevel
401 #define RF69_TX_START_CONDITION_FIFO_NOT_EMPTY 0b10000000 // 7 7 FifoNotEmpty (default)
402 #define RF69_FIFO_THRESHOLD 0b00001111 // 6 0 default threshold to trigger FifoLevel interrupt
403 
404 // RF69_REG_PACKET_CONFIG_2
405 #define RF69_INTER_PACKET_RX_DELAY 0b00000000 // 7 4 delay between FIFO empty and start of new RSSI phase
406 #define RF69_RESTART_RX 0b00000100 // 2 2 force receiver into wait mode
407 #define RF69_AUTO_RX_RESTART_OFF 0b00000000 // 1 1 auto Rx restart disabled
408 #define RF69_AUTO_RX_RESTART_ON 0b00000010 // 1 1 auto Rx restart enabled (default)
409 #define RF69_AES_OFF 0b00000000 // 0 0 AES encryption disabled (default)
410 #define RF69_AES_ON 0b00000001 // 0 0 AES encryption enabled, payload size limited to 66 bytes
411 
412 // RF69_REG_TEMP_1
413 #define RF69_TEMP_MEAS_START 0b00001000 // 3 3 trigger temperature measurement
414 #define RF69_TEMP_MEAS_RUNNING 0b00000100 // 2 2 temperature measurement status: on-going
415 #define RF69_TEMP_MEAS_DONE 0b00000000 // 2 2 done
416 
417 // RF69_REG_TEST_DAGC
418 #define RF69_CONTINUOUS_DAGC_NORMAL 0x00 // 7 0 fading margin improvement: normal mode
419 #define RF69_CONTINUOUS_DAGC_LOW_BETA_ON 0x20 // 7 0 improved mode for AfcLowBetaOn
420 #define RF69_CONTINUOUS_DAGC_LOW_BETA_OFF 0x30 // 7 0 improved mode for AfcLowBetaOff (default)
421 
422 // RF69_REG_TEST_PA1
423 #define RF69_PA1_NORMAL 0x55 // 7 0 PA_BOOST: none
424 #define RF69_PA1_20_DBM 0x5D // 7 0 +20 dBm
425 
426 // RF69_REG_TEST_PA2
427 #define RF69_PA2_NORMAL 0x70 // 7 0 PA_BOOST: none
428 #define RF69_PA2_20_DBM 0x7C // 7 0 +20 dBm
429 
435 class RF69: public PhysicalLayer {
436  public:
437  // introduce PhysicalLayer overloads
438  using PhysicalLayer::transmit;
439  using PhysicalLayer::receive;
440  using PhysicalLayer::startTransmit;
441  using PhysicalLayer::readData;
442 
448  RF69(Module* module);
449 
450  // basic methods
451 
469  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint8_t preambleLen = 16);
470 
474  void reset();
475 
488  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
489 
500  int16_t receive(uint8_t* data, size_t len) override;
501 
507  int16_t sleep();
508 
514  int16_t standby() override;
515 
523  int16_t transmitDirect(uint32_t frf = 0) override;
524 
530  int16_t receiveDirect() override;
531 
535  int16_t packetMode();
536 
537  // hardware AES support
538 
544  void setAESKey(uint8_t* key);
545 
551  int16_t enableAES();
552 
558  int16_t disableAES();
559 
560  // interrupt methods
561 
567  void setDio0Action(void (*func)(void));
568 
572  void clearDio0Action();
573 
579  void setDio1Action(void (*func)(void));
580 
584  void clearDio1Action();
585 
598  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
599 
605  int16_t startReceive();
606 
616  int16_t readData(uint8_t* data, size_t len) override;
617 
618  // configuration methods
619 
627  int16_t setFrequency(float freq);
628 
636  int16_t setBitRate(float br);
637 
645  int16_t setRxBandwidth(float rxBw);
646 
654  int16_t setFrequencyDeviation(float freqDev) override;
655 
665  int16_t setOutputPower(int8_t power, bool highPower = false);
666 
676  int16_t setSyncWord(uint8_t* syncWord, size_t len, uint8_t maxErrBits = 0);
677 
685  int16_t setPreambleLength(uint8_t preambleLen);
686 
694  int16_t setNodeAddress(uint8_t nodeAddr);
695 
703  int16_t setBroadcastAddress(uint8_t broadAddr);
704 
710  int16_t disableAddressFiltering();
711 
712  // measurement methods
713 
719  void setAmbientTemperature(int16_t tempAmbient);
720 
726  int16_t getTemperature();
727 
735  size_t getPacketLength(bool update = true) override;
736 
744  int16_t fixedPacketLengthMode(uint8_t len = RF69_MAX_PACKET_LENGTH);
745 
753  int16_t variablePacketLengthMode(uint8_t maxLen = RF69_MAX_PACKET_LENGTH);
754 
762  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0);
763 
769  int16_t disableSyncWordFiltering();
770 
778  int16_t setCrcFiltering(bool crcOn = true);
779 
787  int16_t setPromiscuousMode(bool promiscuous = true);
788 
797  int16_t setDataShaping(uint8_t sh) override;
798 
807  int16_t setEncoding(uint8_t encoding) override;
808 
814  float getRSSI();
815 
824  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
825 
831  uint8_t random();
832 
838  int16_t getChipVersion();
839 
840 #ifndef RADIOLIB_GODMODE
841  protected:
842 #endif
843  Module* _mod;
844 
845  float _br = 0;
846  float _rxBw = 0;
847  int16_t _tempOffset = 0;
848  int8_t _power = 0;
849 
850  size_t _packetLength = 0;
851  bool _packetLengthQueried = false;
852  uint8_t _packetLengthConfig = RF69_PACKET_FORMAT_VARIABLE;
853 
854  bool _promiscuous = false;
855 
856  uint8_t _syncWordLength = 2;
857 
858  int16_t config();
859  int16_t directMode();
860  int16_t setPacketMode(uint8_t mode, uint8_t len);
861 
862 #ifndef RADIOLIB_GODMODE
863  private:
864 #endif
865  int16_t setMode(uint8_t mode);
866  void clearIRQFlags();
867 };
868 
869 #endif
870 
871 #endif
RF69::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets frequency deviation.
Definition: RF69.cpp:507
-
RF69::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: RF69.cpp:615
-
RF69::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)
Sets sync word. Up to 8 bytes can be set as sync word.
Definition: RF69.cpp:563
-
RF69::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: RF69.cpp:695
+
RF69::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: RF69.cpp:621
+
RF69::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)
Sets sync word. Up to 8 bytes can be set as sync word.
Definition: RF69.cpp:569
+
RF69::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: RF69.cpp:701
RF69::standby
int16_t standby() override
Sets the module to standby mode.
Definition: RF69.cpp:171
-
RF69::disableSyncWordFiltering
int16_t disableSyncWordFiltering()
Disable preamble and sync word filtering and generation.
Definition: RF69.cpp:675
-
RF69::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: RF69.cpp:649
+
RF69::disableSyncWordFiltering
int16_t disableSyncWordFiltering()
Disable preamble and sync word filtering and generation.
Definition: RF69.cpp:681
+
RF69::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: RF69.cpp:655
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
RF69::startReceive
int16_t startReceive()
Interrupt-driven receive method. GDO0 will be activated when full packet is received.
Definition: RF69.cpp:241
-
RF69::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets node address. Calling this method will also enable address filtering for node address only...
Definition: RF69.cpp:597
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RF69::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: RF69.cpp:763
+
RF69::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets node address. Calling this method will also enable address filtering for node address only...
Definition: RF69.cpp:603
+
RF69::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: RF69.cpp:769
RF69::setBitRate
int16_t setBitRate(float br)
Sets bit rate. Allowed values range from 1.2 to 300.0 kbps.
Definition: RF69.cpp:391
RF69::receive
int16_t receive(uint8_t *data, size_t len) override
Blocking binary receive method. Overloads for string-based transmissions are implemented in PhysicalL...
Definition: RF69.cpp:139
RF69::clearDio0Action
void clearDio0Action()
Clears interrupt service routine to call when DIO0 activates.
Definition: RF69.cpp:273
-
RF69::setAmbientTemperature
void setAmbientTemperature(int16_t tempAmbient)
Sets ambient temperature. Required to correct values from on-board temperature sensor.
Definition: RF69.cpp:628
+
RF69::setAmbientTemperature
void setAmbientTemperature(int16_t tempAmbient)
Sets ambient temperature. Required to correct values from on-board temperature sensor.
Definition: RF69.cpp:634
RF69::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Starts direct mode transmission.
Definition: RF69.cpp:179
-
RF69::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: RF69.cpp:586
+
RF69::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: RF69.cpp:592
RF69::sleep
int16_t sleep()
Sets the module to sleep mode.
Definition: RF69.cpp:163
RF69::disableAES
int16_t disableAES()
Disables AES encryption.
Definition: RF69.cpp:237
-
RF69::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)
Set modem in variable packet length mode.
Definition: RF69.cpp:666
+
RF69::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)
Set modem in variable packet length mode.
Definition: RF69.cpp:672
RF69
Control class for RF69 module. Also serves as base class for SX1231.
Definition: RF69.h:435
RF69::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: RF69.cpp:110
RF69::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: RF69.cpp:285
-
RF69::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Allowed values are RA...
Definition: RF69.cpp:721
-
RF69::setCrcFiltering
int16_t setCrcFiltering(bool crcOn=true)
Enable CRC filtering and generation.
Definition: RF69.cpp:687
+
RF69::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Allowed values are RA...
Definition: RF69.cpp:727
+
RF69::setCrcFiltering
int16_t setCrcFiltering(bool crcOn=true)
Enable CRC filtering and generation.
Definition: RF69.cpp:693
RF69::begin
int16_t begin(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=125.0, int8_t power=10, uint8_t preambleLen=16)
Initialization method.
Definition: RF69.cpp:8
RF69::setDio0Action
void setDio0Action(void(*func)(void))
Sets interrupt service routine to call when DIO0 activates.
Definition: RF69.cpp:269
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
-
RF69::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER an...
Definition: RF69.cpp:741
-
RF69::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets broadcast address. Calling this method will also enable address filtering for node and broadcast...
Definition: RF69.cpp:606
+
RF69::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER an...
Definition: RF69.cpp:747
+
RF69::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets broadcast address. Calling this method will also enable address filtering for node and broadcast...
Definition: RF69.cpp:612
RF69::setDio1Action
void setDio1Action(void(*func)(void))
Sets interrupt service routine to call when DIO1 activates.
Definition: RF69.cpp:277
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
RF69::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data received after calling startReceive method.
Definition: RF69.cpp:343
-
RF69::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: RF69.cpp:759
+
RF69::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: RF69.cpp:765
RF69::enableAES
int16_t enableAES()
Enables AES encryption.
Definition: RF69.cpp:233
RF69::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values are in bands 290.0 to 340.0 MHz, 431.0 to 510.0 MHz and 862.0 to 1020.0 MHz.
Definition: RF69.cpp:372
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
-
RF69::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=RF69_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode.
Definition: RF69.cpp:662
+
RF69::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=RF69_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode.
Definition: RF69.cpp:668
RF69::setAESKey
void setAESKey(uint8_t *key)
Sets AES key.
Definition: RF69.cpp:229
RF69::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values are 2.6, 3.1, 3.9, 5.2, 6.3, 7.8, 10.4, 12.5, 15.6, 20.8, 25.0, 31.3, 41.7, 50.0, 62.5, 83.3, 100.0, 125.0, 166.7, 200.0, 250.0, 333.3, 400.0 and 500.0 kHz.
Definition: RF69.cpp:412
RF69::reset
void reset()
Reset method. Will reset the chip to the default state using RST pin.
Definition: RF69.cpp:102
-
RF69::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: RF69.cpp:767
-
RF69::setOutputPower
int16_t setOutputPower(int8_t power, bool highPower=false)
Sets output power. Allowed values range from -18 to 13 dBm for low power modules (RF69C/CW) or -2 to ...
Definition: RF69.cpp:525
+
RF69::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: RF69.cpp:773
+
RF69::setOutputPower
int16_t setOutputPower(int8_t power, bool highPower=false)
Sets output power. Allowed values range from -18 to 13 dBm for low power modules (RF69C/CW) or -2 to ...
Definition: RF69.cpp:531
RF69::packetMode
int16_t packetMode()
Stops direct mode. It is required to call this method to switch from direct transmissions to packet-b...
Definition: RF69.cpp:225
RF69::RF69
RF69(Module *module)
Default constructor.
Definition: RF69.cpp:4
RF69::receiveDirect
int16_t receiveDirect() override
Starts direct mode reception.
Definition: RF69.cpp:200
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
-
RF69::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working...
Definition: RF69.cpp:786
-
RF69::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0)
Enable sync word filtering and generation.
Definition: RF69.cpp:670
+
RF69::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working...
Definition: RF69.cpp:792
+
RF69::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0)
Enable sync word filtering and generation.
Definition: RF69.cpp:676
RF69::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: RF69.cpp:292
-
RF69::getTemperature
int16_t getTemperature()
Measures temperature.
Definition: RF69.cpp:632
+
RF69::getTemperature
int16_t getTemperature()
Measures temperature.
Definition: RF69.cpp:638
diff --git a/_s_x126x_8h_source.html b/_s_x126x_8h_source.html index 824faf1a..6b8f3c4c 100644 --- a/_s_x126x_8h_source.html +++ b/_s_x126x_8h_source.html @@ -84,67 +84,67 @@ $(document).ready(function(){initNavTree('_s_x126x_8h_source.html','');});
SX126x.h
-
1 #if !defined(_RADIOLIB_SX126X_H)
2 #define _RADIOLIB_SX126X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX126X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX126X physical layer properties
13 #define SX126X_FREQUENCY_STEP_SIZE 0.9536743164
14 #define SX126X_MAX_PACKET_LENGTH 255
15 #define SX126X_CRYSTAL_FREQ 32.0
16 #define SX126X_DIV_EXPONENT 25
17 
18 // SX126X SPI commands
19 // operational modes commands
20 #define SX126X_CMD_NOP 0x00
21 #define SX126X_CMD_SET_SLEEP 0x84
22 #define SX126X_CMD_SET_STANDBY 0x80
23 #define SX126X_CMD_SET_FS 0xC1
24 #define SX126X_CMD_SET_TX 0x83
25 #define SX126X_CMD_SET_RX 0x82
26 #define SX126X_CMD_STOP_TIMER_ON_PREAMBLE 0x9F
27 #define SX126X_CMD_SET_RX_DUTY_CYCLE 0x94
28 #define SX126X_CMD_SET_CAD 0xC5
29 #define SX126X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
30 #define SX126X_CMD_SET_TX_INFINITE_PREAMBLE 0xD2
31 #define SX126X_CMD_SET_REGULATOR_MODE 0x96
32 #define SX126X_CMD_CALIBRATE 0x89
33 #define SX126X_CMD_CALIBRATE_IMAGE 0x98
34 #define SX126X_CMD_SET_PA_CONFIG 0x95
35 #define SX126X_CMD_SET_RX_TX_FALLBACK_MODE 0x93
36 
37 // register and buffer access commands
38 #define SX126X_CMD_WRITE_REGISTER 0x0D
39 #define SX126X_CMD_READ_REGISTER 0x1D
40 #define SX126X_CMD_WRITE_BUFFER 0x0E
41 #define SX126X_CMD_READ_BUFFER 0x1E
42 
43 // DIO and IRQ control
44 #define SX126X_CMD_SET_DIO_IRQ_PARAMS 0x08
45 #define SX126X_CMD_GET_IRQ_STATUS 0x12
46 #define SX126X_CMD_CLEAR_IRQ_STATUS 0x02
47 #define SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL 0x9D
48 #define SX126X_CMD_SET_DIO3_AS_TCXO_CTRL 0x97
49 
50 // RF, modulation and packet commands
51 #define SX126X_CMD_SET_RF_FREQUENCY 0x86
52 #define SX126X_CMD_SET_PACKET_TYPE 0x8A
53 #define SX126X_CMD_GET_PACKET_TYPE 0x11
54 #define SX126X_CMD_SET_TX_PARAMS 0x8E
55 #define SX126X_CMD_SET_MODULATION_PARAMS 0x8B
56 #define SX126X_CMD_SET_PACKET_PARAMS 0x8C
57 #define SX126X_CMD_SET_CAD_PARAMS 0x88
58 #define SX126X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
59 #define SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT 0x0A
60 
61 // status commands
62 #define SX126X_CMD_GET_STATUS 0xC0
63 #define SX126X_CMD_GET_RSSI_INST 0x15
64 #define SX126X_CMD_GET_RX_BUFFER_STATUS 0x13
65 #define SX126X_CMD_GET_PACKET_STATUS 0x14
66 #define SX126X_CMD_GET_DEVICE_ERRORS 0x17
67 #define SX126X_CMD_CLEAR_DEVICE_ERRORS 0x07
68 #define SX126X_CMD_GET_STATS 0x10
69 #define SX126X_CMD_RESET_STATS 0x00
70 
71 
72 // SX126X register map
73 #define SX126X_REG_WHITENING_INITIAL_MSB 0x06B8
74 #define SX126X_REG_WHITENING_INITIAL_LSB 0x06B9
75 #define SX126X_REG_CRC_INITIAL_MSB 0x06BC
76 #define SX126X_REG_CRC_INITIAL_LSB 0x06BD
77 #define SX126X_REG_CRC_POLYNOMIAL_MSB 0x06BE
78 #define SX126X_REG_CRC_POLYNOMIAL_LSB 0x06BF
79 #define SX126X_REG_SYNC_WORD_0 0x06C0
80 #define SX126X_REG_SYNC_WORD_1 0x06C1
81 #define SX126X_REG_SYNC_WORD_2 0x06C2
82 #define SX126X_REG_SYNC_WORD_3 0x06C3
83 #define SX126X_REG_SYNC_WORD_4 0x06C4
84 #define SX126X_REG_SYNC_WORD_5 0x06C5
85 #define SX126X_REG_SYNC_WORD_6 0x06C6
86 #define SX126X_REG_SYNC_WORD_7 0x06C7
87 #define SX126X_REG_NODE_ADDRESS 0x06CD
88 #define SX126X_REG_BROADCAST_ADDRESS 0x06CE
89 #define SX126X_REG_LORA_SYNC_WORD_MSB 0x0740
90 #define SX126X_REG_LORA_SYNC_WORD_LSB 0x0741
91 #define SX126X_REG_RANDOM_NUMBER_0 0x0819
92 #define SX126X_REG_RANDOM_NUMBER_1 0x081A
93 #define SX126X_REG_RANDOM_NUMBER_2 0x081B
94 #define SX126X_REG_RANDOM_NUMBER_3 0x081C
95 #define SX126X_REG_RX_GAIN 0x08AC
96 #define SX126X_REG_OCP_CONFIGURATION 0x08E7
97 #define SX126X_REG_XTA_TRIM 0x0911
98 #define SX126X_REG_XTB_TRIM 0x0912
99 
100 // undocumented registers
101 #define SX126X_REG_SENSITIVITY_CONFIG 0x0889 // SX1268 datasheet v1.1, section 15.1
102 #define SX126X_REG_TX_CLAMP_CONFIG 0x08D8 // SX1268 datasheet v1.1, section 15.2
103 #define SX126X_REG_RTC_STOP 0x0920 // SX1268 datasheet v1.1, section 15.3
104 #define SX126X_REG_RTC_EVENT 0x0944 // SX1268 datasheet v1.1, section 15.3
105 #define SX126X_REG_IQ_CONFIG 0x0736 // SX1268 datasheet v1.1, section 15.4
106 #define SX126X_REG_RX_GAIN_RETENTION_0 0x029F // SX1268 datasheet v1.1, section 9.6
107 #define SX126X_REG_RX_GAIN_RETENTION_1 0x02A0 // SX1268 datasheet v1.1, section 9.6
108 #define SX126X_REG_RX_GAIN_RETENTION_2 0x02A1 // SX1268 datasheet v1.1, section 9.6
109 
110 
111 // SX126X SPI command variables
112 //SX126X_CMD_SET_SLEEP MSB LSB DESCRIPTION
113 #define SX126X_SLEEP_START_COLD 0b00000000 // 2 2 sleep mode: cold start, configuration is lost (default)
114 #define SX126X_SLEEP_START_WARM 0b00000100 // 2 2 warm start, configuration is retained
115 #define SX126X_SLEEP_RTC_OFF 0b00000000 // 0 0 wake on RTC timeout: disabled
116 #define SX126X_SLEEP_RTC_ON 0b00000001 // 0 0 enabled
117 
118 //SX126X_CMD_SET_STANDBY
119 #define SX126X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
120 #define SX126X_STANDBY_XOSC 0x01 // 7 0 32 MHz crystal oscillator
121 
122 //SX126X_CMD_SET_RX
123 #define SX126X_RX_TIMEOUT_NONE 0x000000 // 23 0 Rx timeout duration: no timeout (Rx single mode)
124 #define SX126X_RX_TIMEOUT_INF 0xFFFFFF // 23 0 infinite (Rx continuous mode)
125 
126 //SX126X_CMD_SET_TX
127 #define SX126X_TX_TIMEOUT_NONE 0x000000 // 23 0 Tx timeout duration: no timeout (Tx single mode)
128 
129 //SX126X_CMD_STOP_TIMER_ON_PREAMBLE
130 #define SX126X_STOP_ON_PREAMBLE_OFF 0x00 // 7 0 stop timer on: sync word or header (default)
131 #define SX126X_STOP_ON_PREAMBLE_ON 0x01 // 7 0 preamble detection
132 
133 //SX126X_CMD_SET_REGULATOR_MODE
134 #define SX126X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
135 #define SX126X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
136 
137 //SX126X_CMD_CALIBRATE
138 #define SX126X_CALIBRATE_IMAGE_OFF 0b00000000 // 6 6 image calibration: disabled
139 #define SX126X_CALIBRATE_IMAGE_ON 0b01000000 // 6 6 enabled
140 #define SX126X_CALIBRATE_ADC_BULK_P_OFF 0b00000000 // 5 5 ADC bulk P calibration: disabled
141 #define SX126X_CALIBRATE_ADC_BULK_P_ON 0b00100000 // 5 5 enabled
142 #define SX126X_CALIBRATE_ADC_BULK_N_OFF 0b00000000 // 4 4 ADC bulk N calibration: disabled
143 #define SX126X_CALIBRATE_ADC_BULK_N_ON 0b00010000 // 4 4 enabled
144 #define SX126X_CALIBRATE_ADC_PULSE_OFF 0b00000000 // 3 3 ADC pulse calibration: disabled
145 #define SX126X_CALIBRATE_ADC_PULSE_ON 0b00001000 // 3 3 enabled
146 #define SX126X_CALIBRATE_PLL_OFF 0b00000000 // 2 2 PLL calibration: disabled
147 #define SX126X_CALIBRATE_PLL_ON 0b00000100 // 2 2 enabled
148 #define SX126X_CALIBRATE_RC13M_OFF 0b00000000 // 1 1 13 MHz RC osc. calibration: disabled
149 #define SX126X_CALIBRATE_RC13M_ON 0b00000010 // 1 1 enabled
150 #define SX126X_CALIBRATE_RC64K_OFF 0b00000000 // 0 0 64 kHz RC osc. calibration: disabled
151 #define SX126X_CALIBRATE_RC64K_ON 0b00000001 // 0 0 enabled
152 #define SX126X_CALIBRATE_ALL 0b01111111 // 6 0 calibrate all blocks
153 
154 //SX126X_CMD_CALIBRATE_IMAGE
155 #define SX126X_CAL_IMG_430_MHZ_1 0x6B
156 #define SX126X_CAL_IMG_430_MHZ_2 0x6F
157 #define SX126X_CAL_IMG_470_MHZ_1 0x75
158 #define SX126X_CAL_IMG_470_MHZ_2 0x81
159 #define SX126X_CAL_IMG_779_MHZ_1 0xC1
160 #define SX126X_CAL_IMG_779_MHZ_2 0xC5
161 #define SX126X_CAL_IMG_863_MHZ_1 0xD7
162 #define SX126X_CAL_IMG_863_MHZ_2 0xDB
163 #define SX126X_CAL_IMG_902_MHZ_1 0xE1
164 #define SX126X_CAL_IMG_902_MHZ_2 0xE9
165 
166 //SX126X_CMD_SET_PA_CONFIG
167 #define SX126X_PA_CONFIG_HP_MAX 0x07
168 #define SX126X_PA_CONFIG_PA_LUT 0x01
169 #define SX126X_PA_CONFIG_SX1262_8 0x00
170 
171 //SX126X_CMD_SET_RX_TX_FALLBACK_MODE
172 #define SX126X_RX_TX_FALLBACK_MODE_FS 0x40 // 7 0 after Rx/Tx go to: FS mode
173 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_XOSC 0x30 // 7 0 standby with crystal oscillator
174 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_RC 0x20 // 7 0 standby with RC oscillator (default)
175 
176 //SX126X_CMD_SET_DIO_IRQ_PARAMS
177 #define SX126X_IRQ_TIMEOUT 0b1000000000 // 9 9 Rx or Tx timeout
178 #define SX126X_IRQ_CAD_DETECTED 0b0100000000 // 8 8 channel activity detected
179 #define SX126X_IRQ_CAD_DONE 0b0010000000 // 7 7 channel activity detection finished
180 #define SX126X_IRQ_CRC_ERR 0b0001000000 // 6 6 wrong CRC received
181 #define SX126X_IRQ_HEADER_ERR 0b0000100000 // 5 5 LoRa header CRC error
182 #define SX126X_IRQ_HEADER_VALID 0b0000010000 // 4 4 valid LoRa header received
183 #define SX126X_IRQ_SYNC_WORD_VALID 0b0000001000 // 3 3 valid sync word detected
184 #define SX126X_IRQ_PREAMBLE_DETECTED 0b0000000100 // 2 2 preamble detected
185 #define SX126X_IRQ_RX_DONE 0b0000000010 // 1 1 packet received
186 #define SX126X_IRQ_TX_DONE 0b0000000001 // 0 0 packet transmission completed
187 #define SX126X_IRQ_ALL 0b1111111111 // 9 0 all interrupts
188 #define SX126X_IRQ_NONE 0b0000000000 // 9 0 no interrupts
189 
190 //SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL
191 #define SX126X_DIO2_AS_IRQ 0x00 // 7 0 DIO2 configuration: IRQ
192 #define SX126X_DIO2_AS_RF_SWITCH 0x01 // 7 0 RF switch control
193 
194 //SX126X_CMD_SET_DIO3_AS_TCXO_CTRL
195 #define SX126X_DIO3_OUTPUT_1_6 0x00 // 7 0 DIO3 voltage output for TCXO: 1.6 V
196 #define SX126X_DIO3_OUTPUT_1_7 0x01 // 7 0 1.7 V
197 #define SX126X_DIO3_OUTPUT_1_8 0x02 // 7 0 1.8 V
198 #define SX126X_DIO3_OUTPUT_2_2 0x03 // 7 0 2.2 V
199 #define SX126X_DIO3_OUTPUT_2_4 0x04 // 7 0 2.4 V
200 #define SX126X_DIO3_OUTPUT_2_7 0x05 // 7 0 2.7 V
201 #define SX126X_DIO3_OUTPUT_3_0 0x06 // 7 0 3.0 V
202 #define SX126X_DIO3_OUTPUT_3_3 0x07 // 7 0 3.3 V
203 
204 //SX126X_CMD_SET_PACKET_TYPE
205 #define SX126X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: GFSK
206 #define SX126X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
207 
208 //SX126X_CMD_SET_TX_PARAMS
209 #define SX126X_PA_RAMP_10U 0x00 // 7 0 ramp time: 10 us
210 #define SX126X_PA_RAMP_20U 0x01 // 7 0 20 us
211 #define SX126X_PA_RAMP_40U 0x02 // 7 0 40 us
212 #define SX126X_PA_RAMP_80U 0x03 // 7 0 80 us
213 #define SX126X_PA_RAMP_200U 0x04 // 7 0 200 us
214 #define SX126X_PA_RAMP_800U 0x05 // 7 0 800 us
215 #define SX126X_PA_RAMP_1700U 0x06 // 7 0 1700 us
216 #define SX126X_PA_RAMP_3400U 0x07 // 7 0 3400 us
217 
218 //SX126X_CMD_SET_MODULATION_PARAMS
219 #define SX126X_GFSK_FILTER_NONE 0x00 // 7 0 GFSK filter: none
220 #define SX126X_GFSK_FILTER_GAUSS_0_3 0x08 // 7 0 Gaussian, BT = 0.3
221 #define SX126X_GFSK_FILTER_GAUSS_0_5 0x09 // 7 0 Gaussian, BT = 0.5
222 #define SX126X_GFSK_FILTER_GAUSS_0_7 0x0A // 7 0 Gaussian, BT = 0.7
223 #define SX126X_GFSK_FILTER_GAUSS_1 0x0B // 7 0 Gaussian, BT = 1
224 #define SX126X_GFSK_RX_BW_4_8 0x1F // 7 0 GFSK Rx bandwidth: 4.8 kHz
225 #define SX126X_GFSK_RX_BW_5_8 0x17 // 7 0 5.8 kHz
226 #define SX126X_GFSK_RX_BW_7_3 0x0F // 7 0 7.3 kHz
227 #define SX126X_GFSK_RX_BW_9_7 0x1E // 7 0 9.7 kHz
228 #define SX126X_GFSK_RX_BW_11_7 0x16 // 7 0 11.7 kHz
229 #define SX126X_GFSK_RX_BW_14_6 0x0E // 7 0 14.6 kHz
230 #define SX126X_GFSK_RX_BW_19_5 0x1D // 7 0 19.5 kHz
231 #define SX126X_GFSK_RX_BW_23_4 0x15 // 7 0 23.4 kHz
232 #define SX126X_GFSK_RX_BW_29_3 0x0D // 7 0 29.3 kHz
233 #define SX126X_GFSK_RX_BW_39_0 0x1C // 7 0 39.0 kHz
234 #define SX126X_GFSK_RX_BW_46_9 0x14 // 7 0 46.9 kHz
235 #define SX126X_GFSK_RX_BW_58_6 0x0C // 7 0 58.6 kHz
236 #define SX126X_GFSK_RX_BW_78_2 0x1B // 7 0 78.2 kHz
237 #define SX126X_GFSK_RX_BW_93_8 0x13 // 7 0 93.8 kHz
238 #define SX126X_GFSK_RX_BW_117_3 0x0B // 7 0 117.3 kHz
239 #define SX126X_GFSK_RX_BW_156_2 0x1A // 7 0 156.2 kHz
240 #define SX126X_GFSK_RX_BW_187_2 0x12 // 7 0 187.2 kHz
241 #define SX126X_GFSK_RX_BW_234_3 0x0A // 7 0 234.3 kHz
242 #define SX126X_GFSK_RX_BW_312_0 0x19 // 7 0 312.0 kHz
243 #define SX126X_GFSK_RX_BW_373_6 0x11 // 7 0 373.6 kHz
244 #define SX126X_GFSK_RX_BW_467_0 0x09 // 7 0 467.0 kHz
245 #define SX126X_LORA_BW_7_8 0x00 // 7 0 LoRa bandwidth: 7.8 kHz
246 #define SX126X_LORA_BW_10_4 0x08 // 7 0 10.4 kHz
247 #define SX126X_LORA_BW_15_6 0x01 // 7 0 15.6 kHz
248 #define SX126X_LORA_BW_20_8 0x09 // 7 0 20.8 kHz
249 #define SX126X_LORA_BW_31_25 0x02 // 7 0 31.25 kHz
250 #define SX126X_LORA_BW_41_7 0x0A // 7 0 41.7 kHz
251 #define SX126X_LORA_BW_62_5 0x03 // 7 0 62.5 kHz
252 #define SX126X_LORA_BW_125_0 0x04 // 7 0 125.0 kHz
253 #define SX126X_LORA_BW_250_0 0x05 // 7 0 250.0 kHz
254 #define SX126X_LORA_BW_500_0 0x06 // 7 0 500.0 kHz
255 #define SX126X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
256 #define SX126X_LORA_CR_4_6 0x02 // 7 0 4/6
257 #define SX126X_LORA_CR_4_7 0x03 // 7 0 4/7
258 #define SX126X_LORA_CR_4_8 0x04 // 7 0 4/8
259 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_OFF 0x00 // 7 0 LoRa low data rate optimization: disabled
260 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_ON 0x01 // 7 0 enabled
261 
262 //SX126X_CMD_SET_PACKET_PARAMS
263 #define SX126X_GFSK_PREAMBLE_DETECT_OFF 0x00 // 7 0 GFSK minimum preamble length before reception starts: detector disabled
264 #define SX126X_GFSK_PREAMBLE_DETECT_8 0x04 // 7 0 8 bits
265 #define SX126X_GFSK_PREAMBLE_DETECT_16 0x05 // 7 0 16 bits
266 #define SX126X_GFSK_PREAMBLE_DETECT_24 0x06 // 7 0 24 bits
267 #define SX126X_GFSK_PREAMBLE_DETECT_32 0x07 // 7 0 32 bits
268 #define SX126X_GFSK_ADDRESS_FILT_OFF 0x00 // 7 0 GFSK address filtering: disabled
269 #define SX126X_GFSK_ADDRESS_FILT_NODE 0x01 // 7 0 node only
270 #define SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST 0x02 // 7 0 node and broadcast
271 #define SX126X_GFSK_PACKET_FIXED 0x00 // 7 0 GFSK packet type: fixed (payload length known in advance to both sides)
272 #define SX126X_GFSK_PACKET_VARIABLE 0x01 // 7 0 variable (payload length added to packet)
273 #define SX126X_GFSK_CRC_OFF 0x01 // 7 0 GFSK packet CRC: disabled
274 #define SX126X_GFSK_CRC_1_BYTE 0x00 // 7 0 1 byte
275 #define SX126X_GFSK_CRC_2_BYTE 0x02 // 7 0 2 byte
276 #define SX126X_GFSK_CRC_1_BYTE_INV 0x04 // 7 0 1 byte, inverted
277 #define SX126X_GFSK_CRC_2_BYTE_INV 0x06 // 7 0 2 byte, inverted
278 #define SX126X_GFSK_WHITENING_OFF 0x00 // 7 0 GFSK data whitening: disabled
279 #define SX126X_GFSK_WHITENING_ON 0x01 // 7 0 enabled
280 #define SX126X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
281 #define SX126X_LORA_HEADER_IMPLICIT 0x01 // 7 0 implicit
282 #define SX126X_LORA_CRC_OFF 0x00 // 7 0 LoRa CRC mode: disabled
283 #define SX126X_LORA_CRC_ON 0x01 // 7 0 enabled
284 #define SX126X_LORA_IQ_STANDARD 0x00 // 7 0 LoRa IQ setup: standard
285 #define SX126X_LORA_IQ_INVERTED 0x01 // 7 0 inverted
286 
287 //SX126X_CMD_SET_CAD_PARAMS
288 #define SX126X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
289 #define SX126X_CAD_ON_2_SYMB 0x01 // 7 0 2
290 #define SX126X_CAD_ON_4_SYMB 0x02 // 7 0 4
291 #define SX126X_CAD_ON_8_SYMB 0x03 // 7 0 8
292 #define SX126X_CAD_ON_16_SYMB 0x04 // 7 0 16
293 #define SX126X_CAD_GOTO_STDBY 0x00 // 7 0 after CAD is done, always go to STDBY_RC mode
294 #define SX126X_CAD_GOTO_RX 0x01 // 7 0 after CAD is done, go to Rx mode if activity is detected
295 
296 //SX126X_CMD_GET_STATUS
297 #define SX126X_STATUS_MODE_STDBY_RC 0b00100000 // 6 4 current chip mode: STDBY_RC
298 #define SX126X_STATUS_MODE_STDBY_XOSC 0b00110000 // 6 4 STDBY_XOSC
299 #define SX126X_STATUS_MODE_FS 0b01000000 // 6 4 FS
300 #define SX126X_STATUS_MODE_RX 0b01010000 // 6 4 RX
301 #define SX126X_STATUS_MODE_TX 0b01100000 // 6 4 TX
302 #define SX126X_STATUS_DATA_AVAILABLE 0b00000100 // 3 1 command status: packet received and data can be retrieved
303 #define SX126X_STATUS_CMD_TIMEOUT 0b00000110 // 3 1 SPI command timed out
304 #define SX126X_STATUS_CMD_INVALID 0b00001000 // 3 1 invalid SPI command
305 #define SX126X_STATUS_CMD_FAILED 0b00001010 // 3 1 SPI command failed to execute
306 #define SX126X_STATUS_TX_DONE 0b00001100 // 3 1 packet transmission done
307 #define SX126X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
308 
309 //SX126X_CMD_GET_PACKET_STATUS
310 #define SX126X_GFSK_RX_STATUS_PREAMBLE_ERR 0b10000000 // 7 7 GFSK Rx status: preamble error
311 #define SX126X_GFSK_RX_STATUS_SYNC_ERR 0b01000000 // 6 6 sync word error
312 #define SX126X_GFSK_RX_STATUS_ADRS_ERR 0b00100000 // 5 5 address error
313 #define SX126X_GFSK_RX_STATUS_CRC_ERR 0b00010000 // 4 4 CRC error
314 #define SX126X_GFSK_RX_STATUS_LENGTH_ERR 0b00001000 // 3 3 length error
315 #define SX126X_GFSK_RX_STATUS_ABORT_ERR 0b00000100 // 2 2 abort error
316 #define SX126X_GFSK_RX_STATUS_PACKET_RECEIVED 0b00000010 // 2 2 packet received
317 #define SX126X_GFSK_RX_STATUS_PACKET_SENT 0b00000001 // 2 2 packet sent
318 
319 //SX126X_CMD_GET_DEVICE_ERRORS
320 #define SX126X_PA_RAMP_ERR 0b100000000 // 8 8 device errors: PA ramping failed
321 #define SX126X_PLL_LOCK_ERR 0b001000000 // 6 6 PLL failed to lock
322 #define SX126X_XOSC_START_ERR 0b000100000 // 5 5 crystal oscillator failed to start
323 #define SX126X_IMG_CALIB_ERR 0b000010000 // 4 4 image calibration failed
324 #define SX126X_ADC_CALIB_ERR 0b000001000 // 3 3 ADC calibration failed
325 #define SX126X_PLL_CALIB_ERR 0b000000100 // 2 2 PLL calibration failed
326 #define SX126X_RC13M_CALIB_ERR 0b000000010 // 1 1 RC13M calibration failed
327 #define SX126X_RC64K_CALIB_ERR 0b000000001 // 0 0 RC64K calibration failed
328 
329 
330 // SX126X SPI register variables
331 //SX126X_REG_LORA_SYNC_WORD_MSB + LSB
332 #define SX126X_SYNC_WORD_PUBLIC 0x34 // actually 0x3444 NOTE: The low nibbles in each byte (0x_4_4) are masked out since apparently, they're reserved.
333 #define SX126X_SYNC_WORD_PRIVATE 0x12 // actually 0x1424 You couldn't make this up if you tried.
334 
335 
342 class SX126x: public PhysicalLayer {
343  public:
344  // introduce PhysicalLayer overloads
345  using PhysicalLayer::transmit;
346  using PhysicalLayer::receive;
347  using PhysicalLayer::startTransmit;
348  using PhysicalLayer::readData;
349 
355  SX126x(Module* mod);
356 
357  // basic methods
358 
378  int16_t begin(float bw, uint8_t sf, uint8_t cr, uint8_t syncWord, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
379 
397  int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
398 
407  int16_t reset(bool verify = true);
408 
421  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
422 
433  int16_t receive(uint8_t* data, size_t len) override;
434 
442  int16_t transmitDirect(uint32_t frf = 0) override;
443 
450  int16_t receiveDirect() override;
451 
457  int16_t scanChannel();
458 
466  int16_t sleep(bool retainConfig = true);
467 
473  int16_t standby() override;
474 
482  int16_t standby(uint8_t mode);
483 
484  // interrupt methods
485 
491  void setDio1Action(void (*func)(void));
492 
496  void clearDio1Action();
497 
510  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
511 
519  int16_t startReceive(uint32_t timeout = SX126X_RX_TIMEOUT_INF);
520 
531  int16_t startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod);
532 
544  int16_t startReceiveDutyCycleAuto(uint16_t senderPreambleLength = 0, uint16_t minSymbols = 8);
545 
555  int16_t readData(uint8_t* data, size_t len) override;
556 
557  // configuration methods
558 
566  int16_t setBandwidth(float bw);
567 
575  int16_t setSpreadingFactor(uint8_t sf);
576 
584  int16_t setCodingRate(uint8_t cr);
585 
595  int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits = 0x44);
596 
604  int16_t setCurrentLimit(float currentLimit);
605 
611  float getCurrentLimit();
612 
620  int16_t setPreambleLength(uint16_t preambleLength);
621 
629  int16_t setFrequencyDeviation(float freqDev) override;
630 
638  int16_t setBitRate(float br);
639 
647  int16_t setRxBandwidth(float rxBw);
648 
658  int16_t setDataShaping(uint8_t sh) override;
659 
669  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
670 
680  int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen);
681 
689  int16_t setNodeAddress(uint8_t nodeAddr);
690 
698  int16_t setBroadcastAddress(uint8_t broadAddr);
699 
705  int16_t disableAddressFiltering();
706 
720  int16_t setCRC(uint8_t len, uint16_t initial = 0x1D0F, uint16_t polynomial = 0x1021, bool inverted = true);
721 
731  int16_t setWhitening(bool enabled, uint16_t initial = 0x0100);
732 
743  int16_t setTCXO(float voltage, uint32_t delay = 5000);
744 
750  int16_t setDio2AsRfSwitch(bool enable = true);
751 
757  float getDataRate() const;
758 
764  float getRSSI();
765 
771  float getSNR();
772 
780  size_t getPacketLength(bool update = true) override;
781 
789  int16_t fixedPacketLengthMode(uint8_t len = SX126X_MAX_PACKET_LENGTH);
790 
798  int16_t variablePacketLengthMode(uint8_t maxLen = SX126X_MAX_PACKET_LENGTH);
799 
807  uint32_t getTimeOnAir(size_t len);
808 
814  float getRSSIInst();
815 
821  int16_t implicitHeader(size_t len);
822 
830  int16_t explicitHeader();
831 
837  int16_t setRegulatorLDO();
838 
844  int16_t setRegulatorDCDC();
845 
853  int16_t setEncoding(uint8_t encoding) override;
854 
863  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
864 
873  int16_t forceLDRO(bool enable);
874 
881  int16_t autoLDRO();
882 
888  uint8_t random();
889 
890 #ifndef RADIOLIB_GODMODE
891  protected:
892 #endif
893  // SX126x SPI command implementations
894  int16_t setTx(uint32_t timeout = 0);
895  int16_t setRx(uint32_t timeout);
896  int16_t setCad();
897  int16_t setPaConfig(uint8_t paDutyCycle, uint8_t deviceSel, uint8_t hpMax = SX126X_PA_CONFIG_HP_MAX, uint8_t paLut = SX126X_PA_CONFIG_PA_LUT);
898  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
899  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
900  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
901  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
902  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX126X_IRQ_NONE, uint16_t dio3Mask = SX126X_IRQ_NONE);
903  uint16_t getIrqStatus();
904  int16_t clearIrqStatus(uint16_t clearIrqParams = SX126X_IRQ_ALL);
905  int16_t setRfFrequency(uint32_t frf);
906  int16_t calibrateImage(uint8_t* data);
907  uint8_t getPacketType();
908  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX126X_PA_RAMP_200U);
909  int16_t setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, uint8_t ldro);
910  int16_t setModulationParamsFSK(uint32_t br, uint8_t pulseShape, uint8_t rxBw, uint32_t freqDev);
911  int16_t setPacketParams(uint16_t preambleLength, uint8_t crcType, uint8_t payloadLength, uint8_t headerType, uint8_t invertIQ = SX126X_LORA_IQ_STANDARD);
912  int16_t setPacketParamsFSK(uint16_t preambleLength, uint8_t crcType, uint8_t syncWordLength, uint8_t addrComp, uint8_t whitening, uint8_t packetType = SX126X_GFSK_PACKET_VARIABLE, uint8_t payloadLength = 0xFF, uint8_t preambleDetectorLength = SX126X_GFSK_PREAMBLE_DETECT_16);
913  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
914  int16_t setRegulatorMode(uint8_t mode);
915  uint8_t getStatus();
916  uint32_t getPacketStatus();
917  uint16_t getDeviceErrors();
918  int16_t clearDeviceErrors();
919 
920  int16_t startReceiveCommon();
921  int16_t setFrequencyRaw(float freq);
922  int16_t setPacketMode(uint8_t mode, uint8_t len);
923  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
924 
925  // fixes to errata
926  int16_t fixSensitivity();
927  int16_t fixPaClamping();
928  int16_t fixImplicitTimeout();
929  int16_t fixInvertedIQ(uint8_t iqConfig);
930 
931 #ifndef RADIOLIB_GODMODE
932  private:
933 #endif
934  Module* _mod;
935 
936  uint8_t _bw = 0, _sf = 0, _cr = 0, _ldro = 0, _crcType = 0, _headerType = 0;
937  uint16_t _preambleLength = 0;
938  float _bwKhz = 0;
939  bool _ldroAuto = true;
940 
941  uint32_t _br = 0, _freqDev = 0;
942  uint8_t _rxBw = 0, _pulseShape = 0, _crcTypeFSK = 0, _syncWordLength = 0, _addrComp = 0, _whitening = 0, _packetType = 0;
943  uint16_t _preambleLengthFSK = 0;
944  float _rxBwKhz = 0;
945 
946  float _dataRate = 0;
947 
948  uint32_t _tcxoDelay = 0;
949 
950  size_t _implicitLen = 0;
951 
952  int16_t config(uint8_t modem);
953 
954  // common low-level SPI interface
955  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
956  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
957  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
958  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
959  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
960 };
961 
962 #endif
963 
964 #endif
SX126x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX126x.cpp:1160
-
SX126x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets broadcast address. Calling this method will also enable address filtering for node and broadcast...
Definition: SX126x.cpp:932
+
1 #if !defined(_RADIOLIB_SX126X_H)
2 #define _RADIOLIB_SX126X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX126X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX126X physical layer properties
13 #define SX126X_FREQUENCY_STEP_SIZE 0.9536743164
14 #define SX126X_MAX_PACKET_LENGTH 255
15 #define SX126X_CRYSTAL_FREQ 32.0
16 #define SX126X_DIV_EXPONENT 25
17 
18 // SX126X SPI commands
19 // operational modes commands
20 #define SX126X_CMD_NOP 0x00
21 #define SX126X_CMD_SET_SLEEP 0x84
22 #define SX126X_CMD_SET_STANDBY 0x80
23 #define SX126X_CMD_SET_FS 0xC1
24 #define SX126X_CMD_SET_TX 0x83
25 #define SX126X_CMD_SET_RX 0x82
26 #define SX126X_CMD_STOP_TIMER_ON_PREAMBLE 0x9F
27 #define SX126X_CMD_SET_RX_DUTY_CYCLE 0x94
28 #define SX126X_CMD_SET_CAD 0xC5
29 #define SX126X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
30 #define SX126X_CMD_SET_TX_INFINITE_PREAMBLE 0xD2
31 #define SX126X_CMD_SET_REGULATOR_MODE 0x96
32 #define SX126X_CMD_CALIBRATE 0x89
33 #define SX126X_CMD_CALIBRATE_IMAGE 0x98
34 #define SX126X_CMD_SET_PA_CONFIG 0x95
35 #define SX126X_CMD_SET_RX_TX_FALLBACK_MODE 0x93
36 
37 // register and buffer access commands
38 #define SX126X_CMD_WRITE_REGISTER 0x0D
39 #define SX126X_CMD_READ_REGISTER 0x1D
40 #define SX126X_CMD_WRITE_BUFFER 0x0E
41 #define SX126X_CMD_READ_BUFFER 0x1E
42 
43 // DIO and IRQ control
44 #define SX126X_CMD_SET_DIO_IRQ_PARAMS 0x08
45 #define SX126X_CMD_GET_IRQ_STATUS 0x12
46 #define SX126X_CMD_CLEAR_IRQ_STATUS 0x02
47 #define SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL 0x9D
48 #define SX126X_CMD_SET_DIO3_AS_TCXO_CTRL 0x97
49 
50 // RF, modulation and packet commands
51 #define SX126X_CMD_SET_RF_FREQUENCY 0x86
52 #define SX126X_CMD_SET_PACKET_TYPE 0x8A
53 #define SX126X_CMD_GET_PACKET_TYPE 0x11
54 #define SX126X_CMD_SET_TX_PARAMS 0x8E
55 #define SX126X_CMD_SET_MODULATION_PARAMS 0x8B
56 #define SX126X_CMD_SET_PACKET_PARAMS 0x8C
57 #define SX126X_CMD_SET_CAD_PARAMS 0x88
58 #define SX126X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
59 #define SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT 0x0A
60 
61 // status commands
62 #define SX126X_CMD_GET_STATUS 0xC0
63 #define SX126X_CMD_GET_RSSI_INST 0x15
64 #define SX126X_CMD_GET_RX_BUFFER_STATUS 0x13
65 #define SX126X_CMD_GET_PACKET_STATUS 0x14
66 #define SX126X_CMD_GET_DEVICE_ERRORS 0x17
67 #define SX126X_CMD_CLEAR_DEVICE_ERRORS 0x07
68 #define SX126X_CMD_GET_STATS 0x10
69 #define SX126X_CMD_RESET_STATS 0x00
70 
71 
72 // SX126X register map
73 #define SX126X_REG_WHITENING_INITIAL_MSB 0x06B8
74 #define SX126X_REG_WHITENING_INITIAL_LSB 0x06B9
75 #define SX126X_REG_CRC_INITIAL_MSB 0x06BC
76 #define SX126X_REG_CRC_INITIAL_LSB 0x06BD
77 #define SX126X_REG_CRC_POLYNOMIAL_MSB 0x06BE
78 #define SX126X_REG_CRC_POLYNOMIAL_LSB 0x06BF
79 #define SX126X_REG_SYNC_WORD_0 0x06C0
80 #define SX126X_REG_SYNC_WORD_1 0x06C1
81 #define SX126X_REG_SYNC_WORD_2 0x06C2
82 #define SX126X_REG_SYNC_WORD_3 0x06C3
83 #define SX126X_REG_SYNC_WORD_4 0x06C4
84 #define SX126X_REG_SYNC_WORD_5 0x06C5
85 #define SX126X_REG_SYNC_WORD_6 0x06C6
86 #define SX126X_REG_SYNC_WORD_7 0x06C7
87 #define SX126X_REG_NODE_ADDRESS 0x06CD
88 #define SX126X_REG_BROADCAST_ADDRESS 0x06CE
89 #define SX126X_REG_LORA_SYNC_WORD_MSB 0x0740
90 #define SX126X_REG_LORA_SYNC_WORD_LSB 0x0741
91 #define SX126X_REG_RANDOM_NUMBER_0 0x0819
92 #define SX126X_REG_RANDOM_NUMBER_1 0x081A
93 #define SX126X_REG_RANDOM_NUMBER_2 0x081B
94 #define SX126X_REG_RANDOM_NUMBER_3 0x081C
95 #define SX126X_REG_RX_GAIN 0x08AC
96 #define SX126X_REG_OCP_CONFIGURATION 0x08E7
97 #define SX126X_REG_XTA_TRIM 0x0911
98 #define SX126X_REG_XTB_TRIM 0x0912
99 
100 // undocumented registers
101 #define SX126X_REG_SENSITIVITY_CONFIG 0x0889 // SX1268 datasheet v1.1, section 15.1
102 #define SX126X_REG_TX_CLAMP_CONFIG 0x08D8 // SX1268 datasheet v1.1, section 15.2
103 #define SX126X_REG_RTC_STOP 0x0920 // SX1268 datasheet v1.1, section 15.3
104 #define SX126X_REG_RTC_EVENT 0x0944 // SX1268 datasheet v1.1, section 15.3
105 #define SX126X_REG_IQ_CONFIG 0x0736 // SX1268 datasheet v1.1, section 15.4
106 #define SX126X_REG_RX_GAIN_RETENTION_0 0x029F // SX1268 datasheet v1.1, section 9.6
107 #define SX126X_REG_RX_GAIN_RETENTION_1 0x02A0 // SX1268 datasheet v1.1, section 9.6
108 #define SX126X_REG_RX_GAIN_RETENTION_2 0x02A1 // SX1268 datasheet v1.1, section 9.6
109 
110 
111 // SX126X SPI command variables
112 //SX126X_CMD_SET_SLEEP MSB LSB DESCRIPTION
113 #define SX126X_SLEEP_START_COLD 0b00000000 // 2 2 sleep mode: cold start, configuration is lost (default)
114 #define SX126X_SLEEP_START_WARM 0b00000100 // 2 2 warm start, configuration is retained
115 #define SX126X_SLEEP_RTC_OFF 0b00000000 // 0 0 wake on RTC timeout: disabled
116 #define SX126X_SLEEP_RTC_ON 0b00000001 // 0 0 enabled
117 
118 //SX126X_CMD_SET_STANDBY
119 #define SX126X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
120 #define SX126X_STANDBY_XOSC 0x01 // 7 0 32 MHz crystal oscillator
121 
122 //SX126X_CMD_SET_RX
123 #define SX126X_RX_TIMEOUT_NONE 0x000000 // 23 0 Rx timeout duration: no timeout (Rx single mode)
124 #define SX126X_RX_TIMEOUT_INF 0xFFFFFF // 23 0 infinite (Rx continuous mode)
125 
126 //SX126X_CMD_SET_TX
127 #define SX126X_TX_TIMEOUT_NONE 0x000000 // 23 0 Tx timeout duration: no timeout (Tx single mode)
128 
129 //SX126X_CMD_STOP_TIMER_ON_PREAMBLE
130 #define SX126X_STOP_ON_PREAMBLE_OFF 0x00 // 7 0 stop timer on: sync word or header (default)
131 #define SX126X_STOP_ON_PREAMBLE_ON 0x01 // 7 0 preamble detection
132 
133 //SX126X_CMD_SET_REGULATOR_MODE
134 #define SX126X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
135 #define SX126X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
136 
137 //SX126X_CMD_CALIBRATE
138 #define SX126X_CALIBRATE_IMAGE_OFF 0b00000000 // 6 6 image calibration: disabled
139 #define SX126X_CALIBRATE_IMAGE_ON 0b01000000 // 6 6 enabled
140 #define SX126X_CALIBRATE_ADC_BULK_P_OFF 0b00000000 // 5 5 ADC bulk P calibration: disabled
141 #define SX126X_CALIBRATE_ADC_BULK_P_ON 0b00100000 // 5 5 enabled
142 #define SX126X_CALIBRATE_ADC_BULK_N_OFF 0b00000000 // 4 4 ADC bulk N calibration: disabled
143 #define SX126X_CALIBRATE_ADC_BULK_N_ON 0b00010000 // 4 4 enabled
144 #define SX126X_CALIBRATE_ADC_PULSE_OFF 0b00000000 // 3 3 ADC pulse calibration: disabled
145 #define SX126X_CALIBRATE_ADC_PULSE_ON 0b00001000 // 3 3 enabled
146 #define SX126X_CALIBRATE_PLL_OFF 0b00000000 // 2 2 PLL calibration: disabled
147 #define SX126X_CALIBRATE_PLL_ON 0b00000100 // 2 2 enabled
148 #define SX126X_CALIBRATE_RC13M_OFF 0b00000000 // 1 1 13 MHz RC osc. calibration: disabled
149 #define SX126X_CALIBRATE_RC13M_ON 0b00000010 // 1 1 enabled
150 #define SX126X_CALIBRATE_RC64K_OFF 0b00000000 // 0 0 64 kHz RC osc. calibration: disabled
151 #define SX126X_CALIBRATE_RC64K_ON 0b00000001 // 0 0 enabled
152 #define SX126X_CALIBRATE_ALL 0b01111111 // 6 0 calibrate all blocks
153 
154 //SX126X_CMD_CALIBRATE_IMAGE
155 #define SX126X_CAL_IMG_430_MHZ_1 0x6B
156 #define SX126X_CAL_IMG_430_MHZ_2 0x6F
157 #define SX126X_CAL_IMG_470_MHZ_1 0x75
158 #define SX126X_CAL_IMG_470_MHZ_2 0x81
159 #define SX126X_CAL_IMG_779_MHZ_1 0xC1
160 #define SX126X_CAL_IMG_779_MHZ_2 0xC5
161 #define SX126X_CAL_IMG_863_MHZ_1 0xD7
162 #define SX126X_CAL_IMG_863_MHZ_2 0xDB
163 #define SX126X_CAL_IMG_902_MHZ_1 0xE1
164 #define SX126X_CAL_IMG_902_MHZ_2 0xE9
165 
166 //SX126X_CMD_SET_PA_CONFIG
167 #define SX126X_PA_CONFIG_HP_MAX 0x07
168 #define SX126X_PA_CONFIG_PA_LUT 0x01
169 #define SX126X_PA_CONFIG_SX1262_8 0x00
170 
171 //SX126X_CMD_SET_RX_TX_FALLBACK_MODE
172 #define SX126X_RX_TX_FALLBACK_MODE_FS 0x40 // 7 0 after Rx/Tx go to: FS mode
173 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_XOSC 0x30 // 7 0 standby with crystal oscillator
174 #define SX126X_RX_TX_FALLBACK_MODE_STDBY_RC 0x20 // 7 0 standby with RC oscillator (default)
175 
176 //SX126X_CMD_SET_DIO_IRQ_PARAMS
177 #define SX126X_IRQ_TIMEOUT 0b1000000000 // 9 9 Rx or Tx timeout
178 #define SX126X_IRQ_CAD_DETECTED 0b0100000000 // 8 8 channel activity detected
179 #define SX126X_IRQ_CAD_DONE 0b0010000000 // 7 7 channel activity detection finished
180 #define SX126X_IRQ_CRC_ERR 0b0001000000 // 6 6 wrong CRC received
181 #define SX126X_IRQ_HEADER_ERR 0b0000100000 // 5 5 LoRa header CRC error
182 #define SX126X_IRQ_HEADER_VALID 0b0000010000 // 4 4 valid LoRa header received
183 #define SX126X_IRQ_SYNC_WORD_VALID 0b0000001000 // 3 3 valid sync word detected
184 #define SX126X_IRQ_PREAMBLE_DETECTED 0b0000000100 // 2 2 preamble detected
185 #define SX126X_IRQ_RX_DONE 0b0000000010 // 1 1 packet received
186 #define SX126X_IRQ_TX_DONE 0b0000000001 // 0 0 packet transmission completed
187 #define SX126X_IRQ_ALL 0b1111111111 // 9 0 all interrupts
188 #define SX126X_IRQ_NONE 0b0000000000 // 9 0 no interrupts
189 
190 //SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL
191 #define SX126X_DIO2_AS_IRQ 0x00 // 7 0 DIO2 configuration: IRQ
192 #define SX126X_DIO2_AS_RF_SWITCH 0x01 // 7 0 RF switch control
193 
194 //SX126X_CMD_SET_DIO3_AS_TCXO_CTRL
195 #define SX126X_DIO3_OUTPUT_1_6 0x00 // 7 0 DIO3 voltage output for TCXO: 1.6 V
196 #define SX126X_DIO3_OUTPUT_1_7 0x01 // 7 0 1.7 V
197 #define SX126X_DIO3_OUTPUT_1_8 0x02 // 7 0 1.8 V
198 #define SX126X_DIO3_OUTPUT_2_2 0x03 // 7 0 2.2 V
199 #define SX126X_DIO3_OUTPUT_2_4 0x04 // 7 0 2.4 V
200 #define SX126X_DIO3_OUTPUT_2_7 0x05 // 7 0 2.7 V
201 #define SX126X_DIO3_OUTPUT_3_0 0x06 // 7 0 3.0 V
202 #define SX126X_DIO3_OUTPUT_3_3 0x07 // 7 0 3.3 V
203 
204 //SX126X_CMD_SET_PACKET_TYPE
205 #define SX126X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: GFSK
206 #define SX126X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
207 
208 //SX126X_CMD_SET_TX_PARAMS
209 #define SX126X_PA_RAMP_10U 0x00 // 7 0 ramp time: 10 us
210 #define SX126X_PA_RAMP_20U 0x01 // 7 0 20 us
211 #define SX126X_PA_RAMP_40U 0x02 // 7 0 40 us
212 #define SX126X_PA_RAMP_80U 0x03 // 7 0 80 us
213 #define SX126X_PA_RAMP_200U 0x04 // 7 0 200 us
214 #define SX126X_PA_RAMP_800U 0x05 // 7 0 800 us
215 #define SX126X_PA_RAMP_1700U 0x06 // 7 0 1700 us
216 #define SX126X_PA_RAMP_3400U 0x07 // 7 0 3400 us
217 
218 //SX126X_CMD_SET_MODULATION_PARAMS
219 #define SX126X_GFSK_FILTER_NONE 0x00 // 7 0 GFSK filter: none
220 #define SX126X_GFSK_FILTER_GAUSS_0_3 0x08 // 7 0 Gaussian, BT = 0.3
221 #define SX126X_GFSK_FILTER_GAUSS_0_5 0x09 // 7 0 Gaussian, BT = 0.5
222 #define SX126X_GFSK_FILTER_GAUSS_0_7 0x0A // 7 0 Gaussian, BT = 0.7
223 #define SX126X_GFSK_FILTER_GAUSS_1 0x0B // 7 0 Gaussian, BT = 1
224 #define SX126X_GFSK_RX_BW_4_8 0x1F // 7 0 GFSK Rx bandwidth: 4.8 kHz
225 #define SX126X_GFSK_RX_BW_5_8 0x17 // 7 0 5.8 kHz
226 #define SX126X_GFSK_RX_BW_7_3 0x0F // 7 0 7.3 kHz
227 #define SX126X_GFSK_RX_BW_9_7 0x1E // 7 0 9.7 kHz
228 #define SX126X_GFSK_RX_BW_11_7 0x16 // 7 0 11.7 kHz
229 #define SX126X_GFSK_RX_BW_14_6 0x0E // 7 0 14.6 kHz
230 #define SX126X_GFSK_RX_BW_19_5 0x1D // 7 0 19.5 kHz
231 #define SX126X_GFSK_RX_BW_23_4 0x15 // 7 0 23.4 kHz
232 #define SX126X_GFSK_RX_BW_29_3 0x0D // 7 0 29.3 kHz
233 #define SX126X_GFSK_RX_BW_39_0 0x1C // 7 0 39.0 kHz
234 #define SX126X_GFSK_RX_BW_46_9 0x14 // 7 0 46.9 kHz
235 #define SX126X_GFSK_RX_BW_58_6 0x0C // 7 0 58.6 kHz
236 #define SX126X_GFSK_RX_BW_78_2 0x1B // 7 0 78.2 kHz
237 #define SX126X_GFSK_RX_BW_93_8 0x13 // 7 0 93.8 kHz
238 #define SX126X_GFSK_RX_BW_117_3 0x0B // 7 0 117.3 kHz
239 #define SX126X_GFSK_RX_BW_156_2 0x1A // 7 0 156.2 kHz
240 #define SX126X_GFSK_RX_BW_187_2 0x12 // 7 0 187.2 kHz
241 #define SX126X_GFSK_RX_BW_234_3 0x0A // 7 0 234.3 kHz
242 #define SX126X_GFSK_RX_BW_312_0 0x19 // 7 0 312.0 kHz
243 #define SX126X_GFSK_RX_BW_373_6 0x11 // 7 0 373.6 kHz
244 #define SX126X_GFSK_RX_BW_467_0 0x09 // 7 0 467.0 kHz
245 #define SX126X_LORA_BW_7_8 0x00 // 7 0 LoRa bandwidth: 7.8 kHz
246 #define SX126X_LORA_BW_10_4 0x08 // 7 0 10.4 kHz
247 #define SX126X_LORA_BW_15_6 0x01 // 7 0 15.6 kHz
248 #define SX126X_LORA_BW_20_8 0x09 // 7 0 20.8 kHz
249 #define SX126X_LORA_BW_31_25 0x02 // 7 0 31.25 kHz
250 #define SX126X_LORA_BW_41_7 0x0A // 7 0 41.7 kHz
251 #define SX126X_LORA_BW_62_5 0x03 // 7 0 62.5 kHz
252 #define SX126X_LORA_BW_125_0 0x04 // 7 0 125.0 kHz
253 #define SX126X_LORA_BW_250_0 0x05 // 7 0 250.0 kHz
254 #define SX126X_LORA_BW_500_0 0x06 // 7 0 500.0 kHz
255 #define SX126X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
256 #define SX126X_LORA_CR_4_6 0x02 // 7 0 4/6
257 #define SX126X_LORA_CR_4_7 0x03 // 7 0 4/7
258 #define SX126X_LORA_CR_4_8 0x04 // 7 0 4/8
259 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_OFF 0x00 // 7 0 LoRa low data rate optimization: disabled
260 #define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_ON 0x01 // 7 0 enabled
261 
262 //SX126X_CMD_SET_PACKET_PARAMS
263 #define SX126X_GFSK_PREAMBLE_DETECT_OFF 0x00 // 7 0 GFSK minimum preamble length before reception starts: detector disabled
264 #define SX126X_GFSK_PREAMBLE_DETECT_8 0x04 // 7 0 8 bits
265 #define SX126X_GFSK_PREAMBLE_DETECT_16 0x05 // 7 0 16 bits
266 #define SX126X_GFSK_PREAMBLE_DETECT_24 0x06 // 7 0 24 bits
267 #define SX126X_GFSK_PREAMBLE_DETECT_32 0x07 // 7 0 32 bits
268 #define SX126X_GFSK_ADDRESS_FILT_OFF 0x00 // 7 0 GFSK address filtering: disabled
269 #define SX126X_GFSK_ADDRESS_FILT_NODE 0x01 // 7 0 node only
270 #define SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST 0x02 // 7 0 node and broadcast
271 #define SX126X_GFSK_PACKET_FIXED 0x00 // 7 0 GFSK packet type: fixed (payload length known in advance to both sides)
272 #define SX126X_GFSK_PACKET_VARIABLE 0x01 // 7 0 variable (payload length added to packet)
273 #define SX126X_GFSK_CRC_OFF 0x01 // 7 0 GFSK packet CRC: disabled
274 #define SX126X_GFSK_CRC_1_BYTE 0x00 // 7 0 1 byte
275 #define SX126X_GFSK_CRC_2_BYTE 0x02 // 7 0 2 byte
276 #define SX126X_GFSK_CRC_1_BYTE_INV 0x04 // 7 0 1 byte, inverted
277 #define SX126X_GFSK_CRC_2_BYTE_INV 0x06 // 7 0 2 byte, inverted
278 #define SX126X_GFSK_WHITENING_OFF 0x00 // 7 0 GFSK data whitening: disabled
279 #define SX126X_GFSK_WHITENING_ON 0x01 // 7 0 enabled
280 #define SX126X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
281 #define SX126X_LORA_HEADER_IMPLICIT 0x01 // 7 0 implicit
282 #define SX126X_LORA_CRC_OFF 0x00 // 7 0 LoRa CRC mode: disabled
283 #define SX126X_LORA_CRC_ON 0x01 // 7 0 enabled
284 #define SX126X_LORA_IQ_STANDARD 0x00 // 7 0 LoRa IQ setup: standard
285 #define SX126X_LORA_IQ_INVERTED 0x01 // 7 0 inverted
286 
287 //SX126X_CMD_SET_CAD_PARAMS
288 #define SX126X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
289 #define SX126X_CAD_ON_2_SYMB 0x01 // 7 0 2
290 #define SX126X_CAD_ON_4_SYMB 0x02 // 7 0 4
291 #define SX126X_CAD_ON_8_SYMB 0x03 // 7 0 8
292 #define SX126X_CAD_ON_16_SYMB 0x04 // 7 0 16
293 #define SX126X_CAD_GOTO_STDBY 0x00 // 7 0 after CAD is done, always go to STDBY_RC mode
294 #define SX126X_CAD_GOTO_RX 0x01 // 7 0 after CAD is done, go to Rx mode if activity is detected
295 
296 //SX126X_CMD_GET_STATUS
297 #define SX126X_STATUS_MODE_STDBY_RC 0b00100000 // 6 4 current chip mode: STDBY_RC
298 #define SX126X_STATUS_MODE_STDBY_XOSC 0b00110000 // 6 4 STDBY_XOSC
299 #define SX126X_STATUS_MODE_FS 0b01000000 // 6 4 FS
300 #define SX126X_STATUS_MODE_RX 0b01010000 // 6 4 RX
301 #define SX126X_STATUS_MODE_TX 0b01100000 // 6 4 TX
302 #define SX126X_STATUS_DATA_AVAILABLE 0b00000100 // 3 1 command status: packet received and data can be retrieved
303 #define SX126X_STATUS_CMD_TIMEOUT 0b00000110 // 3 1 SPI command timed out
304 #define SX126X_STATUS_CMD_INVALID 0b00001000 // 3 1 invalid SPI command
305 #define SX126X_STATUS_CMD_FAILED 0b00001010 // 3 1 SPI command failed to execute
306 #define SX126X_STATUS_TX_DONE 0b00001100 // 3 1 packet transmission done
307 #define SX126X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
308 
309 //SX126X_CMD_GET_PACKET_STATUS
310 #define SX126X_GFSK_RX_STATUS_PREAMBLE_ERR 0b10000000 // 7 7 GFSK Rx status: preamble error
311 #define SX126X_GFSK_RX_STATUS_SYNC_ERR 0b01000000 // 6 6 sync word error
312 #define SX126X_GFSK_RX_STATUS_ADRS_ERR 0b00100000 // 5 5 address error
313 #define SX126X_GFSK_RX_STATUS_CRC_ERR 0b00010000 // 4 4 CRC error
314 #define SX126X_GFSK_RX_STATUS_LENGTH_ERR 0b00001000 // 3 3 length error
315 #define SX126X_GFSK_RX_STATUS_ABORT_ERR 0b00000100 // 2 2 abort error
316 #define SX126X_GFSK_RX_STATUS_PACKET_RECEIVED 0b00000010 // 2 2 packet received
317 #define SX126X_GFSK_RX_STATUS_PACKET_SENT 0b00000001 // 2 2 packet sent
318 
319 //SX126X_CMD_GET_DEVICE_ERRORS
320 #define SX126X_PA_RAMP_ERR 0b100000000 // 8 8 device errors: PA ramping failed
321 #define SX126X_PLL_LOCK_ERR 0b001000000 // 6 6 PLL failed to lock
322 #define SX126X_XOSC_START_ERR 0b000100000 // 5 5 crystal oscillator failed to start
323 #define SX126X_IMG_CALIB_ERR 0b000010000 // 4 4 image calibration failed
324 #define SX126X_ADC_CALIB_ERR 0b000001000 // 3 3 ADC calibration failed
325 #define SX126X_PLL_CALIB_ERR 0b000000100 // 2 2 PLL calibration failed
326 #define SX126X_RC13M_CALIB_ERR 0b000000010 // 1 1 RC13M calibration failed
327 #define SX126X_RC64K_CALIB_ERR 0b000000001 // 0 0 RC64K calibration failed
328 
329 
330 // SX126X SPI register variables
331 //SX126X_REG_LORA_SYNC_WORD_MSB + LSB
332 #define SX126X_SYNC_WORD_PUBLIC 0x34 // actually 0x3444 NOTE: The low nibbles in each byte (0x_4_4) are masked out since apparently, they're reserved.
333 #define SX126X_SYNC_WORD_PRIVATE 0x12 // actually 0x1424 You couldn't make this up if you tried.
334 
335 
342 class SX126x: public PhysicalLayer {
343  public:
344  // introduce PhysicalLayer overloads
345  using PhysicalLayer::transmit;
346  using PhysicalLayer::receive;
347  using PhysicalLayer::startTransmit;
348  using PhysicalLayer::readData;
349 
355  SX126x(Module* mod);
356 
357  // basic methods
358 
378  int16_t begin(float bw, uint8_t sf, uint8_t cr, uint8_t syncWord, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
379 
397  int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO = false);
398 
407  int16_t reset(bool verify = true);
408 
421  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
422 
433  int16_t receive(uint8_t* data, size_t len) override;
434 
442  int16_t transmitDirect(uint32_t frf = 0) override;
443 
450  int16_t receiveDirect() override;
451 
457  int16_t scanChannel();
458 
466  int16_t sleep(bool retainConfig = true);
467 
473  int16_t standby() override;
474 
482  int16_t standby(uint8_t mode);
483 
484  // interrupt methods
485 
491  void setDio1Action(void (*func)(void));
492 
496  void clearDio1Action();
497 
510  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
511 
519  int16_t startReceive(uint32_t timeout = SX126X_RX_TIMEOUT_INF);
520 
531  int16_t startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod);
532 
544  int16_t startReceiveDutyCycleAuto(uint16_t senderPreambleLength = 0, uint16_t minSymbols = 8);
545 
555  int16_t readData(uint8_t* data, size_t len) override;
556 
557  // configuration methods
558 
566  int16_t setBandwidth(float bw);
567 
575  int16_t setSpreadingFactor(uint8_t sf);
576 
584  int16_t setCodingRate(uint8_t cr);
585 
595  int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits = 0x44);
596 
604  int16_t setCurrentLimit(float currentLimit);
605 
611  float getCurrentLimit();
612 
620  int16_t setPreambleLength(uint16_t preambleLength);
621 
629  int16_t setFrequencyDeviation(float freqDev) override;
630 
638  int16_t setBitRate(float br);
639 
647  int16_t setRxBandwidth(float rxBw);
648 
658  int16_t setDataShaping(uint8_t sh) override;
659 
669  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
670 
680  int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen);
681 
689  int16_t setNodeAddress(uint8_t nodeAddr);
690 
698  int16_t setBroadcastAddress(uint8_t broadAddr);
699 
705  int16_t disableAddressFiltering();
706 
720  int16_t setCRC(uint8_t len, uint16_t initial = 0x1D0F, uint16_t polynomial = 0x1021, bool inverted = true);
721 
731  int16_t setWhitening(bool enabled, uint16_t initial = 0x0100);
732 
743  int16_t setTCXO(float voltage, uint32_t delay = 5000);
744 
750  int16_t setDio2AsRfSwitch(bool enable = true);
751 
757  float getDataRate() const;
758 
764  float getRSSI();
765 
771  float getSNR();
772 
780  size_t getPacketLength(bool update = true) override;
781 
789  int16_t fixedPacketLengthMode(uint8_t len = SX126X_MAX_PACKET_LENGTH);
790 
798  int16_t variablePacketLengthMode(uint8_t maxLen = SX126X_MAX_PACKET_LENGTH);
799 
807  uint32_t getTimeOnAir(size_t len);
808 
814  float getRSSIInst();
815 
821  int16_t implicitHeader(size_t len);
822 
830  int16_t explicitHeader();
831 
837  int16_t setRegulatorLDO();
838 
844  int16_t setRegulatorDCDC();
845 
853  int16_t setEncoding(uint8_t encoding) override;
854 
863  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
864 
873  int16_t forceLDRO(bool enable);
874 
881  int16_t autoLDRO();
882 
888  uint8_t random();
889 
890 #ifndef RADIOLIB_GODMODE
891  protected:
892 #endif
893  // SX126x SPI command implementations
894  int16_t setTx(uint32_t timeout = 0);
895  int16_t setRx(uint32_t timeout);
896  int16_t setCad();
897  int16_t setPaConfig(uint8_t paDutyCycle, uint8_t deviceSel, uint8_t hpMax = SX126X_PA_CONFIG_HP_MAX, uint8_t paLut = SX126X_PA_CONFIG_PA_LUT);
898  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
899  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
900  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
901  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
902  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX126X_IRQ_NONE, uint16_t dio3Mask = SX126X_IRQ_NONE);
903  uint16_t getIrqStatus();
904  int16_t clearIrqStatus(uint16_t clearIrqParams = SX126X_IRQ_ALL);
905  int16_t setRfFrequency(uint32_t frf);
906  int16_t calibrateImage(uint8_t* data);
907  uint8_t getPacketType();
908  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX126X_PA_RAMP_200U);
909  int16_t setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, uint8_t ldro);
910  int16_t setModulationParamsFSK(uint32_t br, uint8_t pulseShape, uint8_t rxBw, uint32_t freqDev);
911  int16_t setPacketParams(uint16_t preambleLength, uint8_t crcType, uint8_t payloadLength, uint8_t headerType, uint8_t invertIQ = SX126X_LORA_IQ_STANDARD);
912  int16_t setPacketParamsFSK(uint16_t preambleLength, uint8_t crcType, uint8_t syncWordLength, uint8_t addrComp, uint8_t whitening, uint8_t packetType = SX126X_GFSK_PACKET_VARIABLE, uint8_t payloadLength = 0xFF, uint8_t preambleDetectorLength = SX126X_GFSK_PREAMBLE_DETECT_16);
913  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
914  int16_t setRegulatorMode(uint8_t mode);
915  uint8_t getStatus();
916  uint32_t getPacketStatus();
917  uint16_t getDeviceErrors();
918  int16_t clearDeviceErrors();
919 
920  int16_t startReceiveCommon();
921  int16_t setFrequencyRaw(float freq);
922  int16_t setPacketMode(uint8_t mode, uint8_t len);
923  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
924 
925  // fixes to errata
926  int16_t fixSensitivity();
927  int16_t fixPaClamping();
928  int16_t fixImplicitTimeout();
929  int16_t fixInvertedIQ(uint8_t iqConfig);
930 
931 #ifndef RADIOLIB_GODMODE
932  private:
933 #endif
934  Module* _mod;
935 
936  uint8_t _bw = 0, _sf = 0, _cr = 0, _ldro = 0, _crcType = 0, _headerType = 0;
937  uint16_t _preambleLength = 0;
938  float _bwKhz = 0;
939  bool _ldroAuto = true;
940 
941  uint32_t _br = 0, _freqDev = 0;
942  uint8_t _rxBw = 0, _pulseShape = 0, _crcTypeFSK = 0, _syncWordLength = 0, _addrComp = 0, _whitening = 0, _packetType = 0;
943  uint16_t _preambleLengthFSK = 0;
944  float _rxBwKhz = 0;
945 
946  float _dataRate = 0;
947 
948  uint32_t _tcxoDelay = 0;
949 
950  size_t _implicitLen = 0;
951 
952  int16_t config(uint8_t modem);
953 
954  // common low-level SPI interface
955  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
956  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
957  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
958  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
959  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
960 };
961 
962 #endif
963 
964 #endif
SX126x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX126x.cpp:1166
+
SX126x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets broadcast address. Calling this method will also enable address filtering for node and broadcast...
Definition: SX126x.cpp:938
SX126x::setSyncWord
int16_t setSyncWord(uint8_t syncWord, uint8_t controlBits=0x44)
Sets LoRa sync word.
Definition: SX126x.cpp:684
SX126x::getCurrentLimit
float getCurrentLimit()
Reads current protection limit.
Definition: SX126x.cpp:708
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
SX126x::startReceiveDutyCycle
int16_t startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)
Interrupt-driven receive method where the device mostly sleeps and periodically wakes to listen...
Definition: SX126x.cpp:488
SX126x::SX126x
SX126x(Module *mod)
Default constructor.
Definition: SX126x.cpp:4
-
SX126x::setSyncBits
int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen)
Sets FSK sync word in the form of array of up to 8 bytes.
Definition: SX126x.cpp:888
-
SX126x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX126x.cpp:1185
+
SX126x::setSyncBits
int16_t setSyncBits(uint8_t *syncWord, uint8_t bitsLen)
Sets FSK sync word in the form of array of up to 8 bytes.
Definition: SX126x.cpp:894
+
SX126x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX126x.cpp:1191
SX126x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data received after calling startReceive method.
Definition: SX126x.cpp:576
-
SX126x::setDio2AsRfSwitch
int16_t setDio2AsRfSwitch(bool enable=true)
Set DIO2 to function as RF switch (default in Semtech example designs).
Definition: SX126x.cpp:1254
-
SX126x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets time-bandwidth product of Gaussian filter applied for shaping. Allowed values are RADIOLIB_SHAPI...
Definition: SX126x.cpp:835
-
SX126x::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX126x.cpp:1144
-
SX126x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 0.6 to 300.0 kbps.
Definition: SX126x.cpp:751
+
SX126x::setDio2AsRfSwitch
int16_t setDio2AsRfSwitch(bool enable=true)
Set DIO2 to function as RF switch (default in Semtech example designs).
Definition: SX126x.cpp:1260
+
SX126x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets time-bandwidth product of Gaussian filter applied for shaping. Allowed values are RADIOLIB_SHAPI...
Definition: SX126x.cpp:841
+
SX126x::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX126x.cpp:1150
+
SX126x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 0.6 to 300.0 kbps.
Definition: SX126x.cpp:757
SX126x::startReceiveDutyCycleAuto
int16_t startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)
Calls startReceiveDutyCycle with rxPeriod and sleepPeriod set so the unit shouldn't miss any messages...
Definition: SX126x.cpp:515
SX126x::standby
int16_t standby() override
Sets the module to standby mode (overload for PhysicalLayer compatibility, uses 13 MHz RC oscillator)...
Definition: SX126x.cpp:394
SX126x::scanChannel
int16_t scanChannel()
Performs scan for LoRa transmission in the current channel. Detects both preamble and payload...
Definition: SX126x.cpp:333
-
SX126x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX126x.cpp:1094
-
SX126x::getDataRate
float getDataRate() const
Gets effective data rate for the last transmitted packet. The value is calculated only for payload by...
Definition: SX126x.cpp:1056
+
SX126x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX126x.cpp:1100
+
SX126x::getDataRate
float getDataRate() const
Gets effective data rate for the last transmitted packet. The value is calculated only for payload by...
Definition: SX126x.cpp:1062
SX126x::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: SX126x.cpp:410
SX126x::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: SX126x.cpp:414
SX126x::reset
int16_t reset(bool verify=true)
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX126x.cpp:160
SX126x::beginFSK
int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO=false)
Initialization method for FSK modem.
Definition: SX126x.cpp:79
SX126x::begin
int16_t begin(float bw, uint8_t sf, uint8_t cr, uint8_t syncWord, uint16_t preambleLength, float tcxoVoltage, bool useRegulatorLDO=false)
Initialization method for LoRa modem.
Definition: SX126x.cpp:8
SX126x
Base class for SX126x series. All derived classes for SX126x (e.g. SX1262 or SX1268) inherit from thi...
Definition: SX126x.h:342
-
SX126x::setWhitening
int16_t setWhitening(bool enabled, uint16_t initial=0x0100)
Sets FSK whitening parameters.
Definition: SX126x.cpp:1019
+
SX126x::setWhitening
int16_t setWhitening(bool enabled, uint16_t initial=0x0100)
Sets FSK whitening parameters.
Definition: SX126x.cpp:1025
SX126x::startReceive
int16_t startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)
Interrupt-driven receive method. DIO1 will be activated when full packet is received.
Definition: SX126x.cpp:475
SX126x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: SX126x.cpp:193
-
SX126x::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: SX126x.cpp:1060
-
SX126x::getRSSIInst
float getRSSIInst()
Get instantaneous RSSI value during recption of the packet. Should switch to FSK receive mode for LBT...
Definition: SX126x.cpp:1133
+
SX126x::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: SX126x.cpp:1066
+
SX126x::getRSSIInst
float getRSSIInst()
Get instantaneous RSSI value during recption of the packet. Should switch to FSK receive mode for LBT...
Definition: SX126x.cpp:1139
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
-
SX126x::getSNR
float getSNR()
Gets SNR (Signal to Noise Ratio) of the last received packet. Only available for LoRa modem...
Definition: SX126x.cpp:1067
+
SX126x::getSNR
float getSNR()
Gets SNR (Signal to Noise Ratio) of the last received packet. Only available for LoRa modem...
Definition: SX126x.cpp:1073
SX126x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation. Allowed values range from 0.0 to 200.0 kHz.
Definition: SX126x.cpp:730
SX126x::setCurrentLimit
int16_t setCurrentLimit(float currentLimit)
Sets current protection limit. Can be set in 0.25 mA steps.
Definition: SX126x.cpp:695
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
-
SX126x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values are 4.8, 5.8, 7.3, 9.7, 11.7, 14.6, 19.5, 23.4, 29.3, 39.0, 46.9, 58.6, 78.2, 93.8, 117.3, 156.2, 187.2, 234.3, 312.0, 373.6 and 467.0 kHz.
Definition: SX126x.cpp:772
+
SX126x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values are 4.8, 5.8, 7.3, 9.7, 11.7, 14.6, 19.5, 23.4, 29.3, 39.0, 46.9, 58.6, 78.2, 93.8, 117.3, 156.2, 187.2, 234.3, 312.0, 373.6 and 467.0 kHz.
Definition: SX126x.cpp:778
SX126x::setDio1Action
void setDio1Action(void(*func)(void))
Sets interrupt service routine to call when DIO1 activates.
Definition: SX126x.cpp:406
-
SX126x::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX126x.cpp:1176
+
SX126x::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX126x.cpp:1182
SX126x::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa coding rate denominator. Allowed values range from 5 to 8.
Definition: SX126x.cpp:671
-
SX126x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Available in FSK mode only. Serves only as alias for PhysicalLayer compat...
Definition: SX126x.cpp:1156
+
SX126x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Available in FSK mode only. Serves only as alias for PhysicalLayer compat...
Definition: SX126x.cpp:1162
SX126x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Starts direct mode transmission.
Definition: SX126x.cpp:309
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
-
SX126x::getTimeOnAir
uint32_t getTimeOnAir(size_t len)
Get expected time-on-air for a given size of payload.
Definition: SX126x.cpp:1098
+
SX126x::getTimeOnAir
uint32_t getTimeOnAir(size_t len)
Get expected time-on-air for a given size of payload.
Definition: SX126x.cpp:1104
SX126x::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa bandwidth. Allowed values are 7.8, 10.4, 15.6, 20.8, 31.25, 41.7, 62.5, 125...
Definition: SX126x.cpp:607
-
SX126x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX126X_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX126x.cpp:1090
-
SX126x::setRegulatorDCDC
int16_t setRegulatorDCDC()
Set regulator mode to DC-DC.
Definition: SX126x.cpp:1152
-
SX126x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets node address. Calling this method will also enable address filtering for node address only...
Definition: SX126x.cpp:915
+
SX126x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX126X_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX126x.cpp:1096
+
SX126x::setRegulatorDCDC
int16_t setRegulatorDCDC()
Set regulator mode to DC-DC.
Definition: SX126x.cpp:1158
+
SX126x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets node address. Calling this method will also enable address filtering for node address only...
Definition: SX126x.cpp:921
SX126x::receiveDirect
int16_t receiveDirect() override
Starts direct mode reception. Only implemented for PhysicalLayer compatibility, as SX126x series does...
Definition: SX126x.cpp:325
-
SX126x::setRegulatorLDO
int16_t setRegulatorLDO()
Set regulator mode to LDO.
Definition: SX126x.cpp:1148
-
SX126x::setCRC
int16_t setCRC(uint8_t len, uint16_t initial=0x1D0F, uint16_t polynomial=0x1021, bool inverted=true)
Sets CRC configuration.
Definition: SX126x.cpp:960
+
SX126x::setRegulatorLDO
int16_t setRegulatorLDO()
Set regulator mode to LDO.
Definition: SX126x.cpp:1154
+
SX126x::setCRC
int16_t setCRC(uint8_t len, uint16_t initial=0x1D0F, uint16_t polynomial=0x1021, bool inverted=true)
Sets CRC configuration.
Definition: SX126x.cpp:966
SX126x::setPreambleLength
int16_t setPreambleLength(uint16_t preambleLength)
Sets preamble length for LoRa or FSK modem. Allowed values range from 1 to 65535. ...
Definition: SX126x.cpp:717
-
SX126x::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX126x.cpp:1140
+
SX126x::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX126x.cpp:1146
SX126x::sleep
int16_t sleep(bool retainConfig=true)
Sets the module to sleep mode.
Definition: SX126x.cpp:378
-
SX126x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: SX126x.cpp:949
+
SX126x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: SX126x.cpp:955
SX126x::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa spreading factor. Allowed values range from 5 to 12.
Definition: SX126x.cpp:658
-
SX126x::setTCXO
int16_t setTCXO(float voltage, uint32_t delay=5000)
Sets TCXO (Temperature Compensated Crystal Oscillator) configuration.
Definition: SX126x.cpp:1206
+
SX126x::setTCXO
int16_t setTCXO(float voltage, uint32_t delay=5000)
Sets TCXO (Temperature Compensated Crystal Oscillator) configuration.
Definition: SX126x.cpp:1212
SX126x::receive
int16_t receive(uint8_t *data, size_t len) override
Blocking binary receive method. Overloads for string-based transmissions are implemented in PhysicalL...
Definition: SX126x.cpp:252
-
SX126x::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX126x.cpp:1164
+
SX126x::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX126x.cpp:1170
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
-
SX126x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX126x.cpp:1083
+
SX126x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX126x.cpp:1089
diff --git a/_s_x1272_8h_source.html b/_s_x1272_8h_source.html index 01fb1e02..dfc16912 100644 --- a/_s_x1272_8h_source.html +++ b/_s_x1272_8h_source.html @@ -85,24 +85,24 @@ $(document).ready(function(){initNavTree('_s_x1272_8h_source.html','');});
1 #if !defined(_RADIOLIB_SX1272_H)
2 #define _RADIOLIB_SX1272_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1272 specific register map
12 #define SX1272_REG_AGC_REF 0x43
13 #define SX1272_REG_AGC_THRESH_1 0x44
14 #define SX1272_REG_AGC_THRESH_2 0x45
15 #define SX1272_REG_AGC_THRESH_3 0x46
16 #define SX1272_REG_PLL_HOP 0x4B
17 #define SX1272_REG_TCXO 0x58
18 #define SX1272_REG_PA_DAC 0x5A
19 #define SX1272_REG_PLL 0x5C
20 #define SX1272_REG_PLL_LOW_PN 0x5E
21 #define SX1272_REG_FORMER_TEMP 0x6C
22 #define SX1272_REG_BIT_RATE_FRAC 0x70
23 
24 // SX1272 LoRa modem settings
25 // SX1272_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
26 #define SX1272_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
27 #define SX1272_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
28 #define SX1272_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
29 
30 // SX1272_REG_MODEM_CONFIG_1
31 #define SX1272_BW_125_00_KHZ 0b00000000 // 7 6 bandwidth: 125 kHz
32 #define SX1272_BW_250_00_KHZ 0b01000000 // 7 6 250 kHz
33 #define SX1272_BW_500_00_KHZ 0b10000000 // 7 6 500 kHz
34 #define SX1272_CR_4_5 0b00001000 // 5 3 error coding rate: 4/5
35 #define SX1272_CR_4_6 0b00010000 // 5 3 4/6
36 #define SX1272_CR_4_7 0b00011000 // 5 3 4/7
37 #define SX1272_CR_4_8 0b00100000 // 5 3 4/8
38 #define SX1272_HEADER_EXPL_MODE 0b00000000 // 2 2 explicit header mode
39 #define SX1272_HEADER_IMPL_MODE 0b00000100 // 2 2 implicit header mode
40 #define SX1272_RX_CRC_MODE_OFF 0b00000000 // 1 1 CRC disabled
41 #define SX1272_RX_CRC_MODE_ON 0b00000010 // 1 1 CRC enabled
42 #define SX1272_LOW_DATA_RATE_OPT_OFF 0b00000000 // 0 0 low data rate optimization disabled
43 #define SX1272_LOW_DATA_RATE_OPT_ON 0b00000001 // 0 0 low data rate optimization enabled, mandatory for SF 11 and 12 with BW 125 kHz
44 
45 // SX1272_REG_MODEM_CONFIG_2
46 #define SX1272_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
47 #define SX1272_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
48 
49 // SX127X_REG_VERSION
50 #define SX1272_CHIP_VERSION 0x22
51 
52 // SX1272 FSK modem settings
53 // SX127X_REG_OP_MODE
54 #define SX1272_NO_SHAPING 0b00000000 // 4 3 data shaping: no shaping (default)
55 #define SX1272_FSK_GAUSSIAN_1_0 0b00001000 // 4 3 FSK modulation Gaussian filter, BT = 1.0
56 #define SX1272_FSK_GAUSSIAN_0_5 0b00010000 // 4 3 FSK modulation Gaussian filter, BT = 0.5
57 #define SX1272_FSK_GAUSSIAN_0_3 0b00011000 // 4 3 FSK modulation Gaussian filter, BT = 0.3
58 #define SX1272_OOK_FILTER_BR 0b00001000 // 4 3 OOK modulation filter, f_cutoff = BR
59 #define SX1272_OOK_FILTER_2BR 0b00010000 // 4 3 OOK modulation filter, f_cutoff = 2*BR
60 
61 // SX127X_REG_PA_RAMP
62 #define SX1272_LOW_PN_TX_PLL_OFF 0b00010000 // 4 4 use standard PLL in transmit mode (default)
63 #define SX1272_LOW_PN_TX_PLL_ON 0b00000000 // 4 4 use lower phase noise PLL in transmit mode
64 
65 // SX127X_REG_SYNC_CONFIG
66 #define SX1272_FIFO_FILL_CONDITION_SYNC_ADDRESS 0b00000000 // 3 3 FIFO will be filled when sync address interrupt occurs (default)
67 #define SX1272_FIFO_FILL_CONDITION_ALWAYS 0b00001000 // 3 3 FIFO will be filled as long as this bit is set
68 
69 // SX1272_REG_AGC_REF
70 #define SX1272_AGC_REFERENCE_LEVEL 0x13 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]
71 
72 // SX1272_REG_AGC_THRESH_1
73 #define SX1272_AGC_STEP_1 0x0E // 4 0 1st AGC threshold
74 
75 // SX1272_REG_AGC_THRESH_2
76 #define SX1272_AGC_STEP_2 0x50 // 7 4 2nd AGC threshold
77 #define SX1272_AGC_STEP_3 0x0B // 4 0 3rd AGC threshold
78 
79 // SX1272_REG_AGC_THRESH_3
80 #define SX1272_AGC_STEP_4 0xD0 // 7 4 4th AGC threshold
81 #define SX1272_AGC_STEP_5 0x0B // 4 0 5th AGC threshold
82 
83 // SX1272_REG_PLL_LOW_PN
84 #define SX1272_PLL_LOW_PN_BANDWIDTH_75_KHZ 0b00000000 // 7 6 low phase noise PLL bandwidth: 75 kHz
85 #define SX1272_PLL_LOW_PN_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
86 #define SX1272_PLL_LOW_PN_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
87 #define SX1272_PLL_LOW_PN_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
88 
95 class SX1272: public SX127x {
96  public:
97 
98  // constructor
99 
105  SX1272(Module* mod);
106 
107  // basic methods
108 
133  int16_t begin(float freq = 915.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
134 
155  int16_t beginFSK(float freq = 915.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
156 
160  void reset() override;
161 
162  // configuration methods
163 
171  int16_t setFrequency(float freq);
172 
180  int16_t setBandwidth(float bw);
181 
189  int16_t setSpreadingFactor(uint8_t sf);
190 
198  int16_t setCodingRate(uint8_t cr);
199 
207  int16_t setOutputPower(int8_t power);
208 
217  int16_t setGain(uint8_t gain);
218 
227  int16_t setDataShaping(uint8_t sh) override;
228 
238  int16_t setDataShapingOOK(uint8_t sh);
239 
245  float getRSSI();
246 
254  int16_t setCRC(bool enableCRC);
255 
264  int16_t forceLDRO(bool enable);
265 
272  int16_t autoLDRO();
273 
274 #ifndef RADIOLIB_GODMODE
275  protected:
276 #endif
277  int16_t setBandwidthRaw(uint8_t newBandwidth);
278  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
279  int16_t setCodingRateRaw(uint8_t newCodingRate);
280 
281  int16_t configFSK();
282 
283 #ifndef RADIOLIB_GODMODE
284  private:
285 #endif
286  bool _ldroAuto = true;
287  bool _ldroEnabled = false;
288 
289 };
290 
291 #endif
292 
293 #endif
SX1272
Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic...
Definition: SX1272.h:95
-
SX1272::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 860.0 MHz to 1020.0 MHz.
Definition: SX1272.cpp:66
+
SX1272::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 860.0 MHz to 1020.0 MHz.
Definition: SX1272.cpp:70
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
-
SX1272::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:385
-
SX1272::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1272.cpp:236
+
SX1272::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:389
+
SX1272::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1272.cpp:240
SX1272::begin
int16_t begin(float freq=915.0, float bw=125.0, uint8_t sf=9, uint8_t cr=7, uint8_t syncWord=SX127X_SYNC_WORD, int8_t power=10, uint16_t preambleLength=8, uint8_t gain=0)
LoRa modem initialization method. Must be called at least once from Arduino sketch to initialize the ...
Definition: SX1272.cpp:8
-
SX1272::setDataShapingOOK
int16_t setDataShapingOOK(uint8_t sh)
Sets filter cutoff frequency that will be used for data shaping. Allowed values are 1 for frequency e...
Definition: SX1272.cpp:291
-
SX1272::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa link bandwidth. Allowed values are 125, 250 and 500 kHz. Only available in LoRa mode...
Definition: SX1272.cpp:77
+
SX1272::setDataShapingOOK
int16_t setDataShapingOOK(uint8_t sh)
Sets filter cutoff frequency that will be used for data shaping. Allowed values are 1 for frequency e...
Definition: SX1272.cpp:295
+
SX1272::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa link bandwidth. Allowed values are 125, 250 and 500 kHz. Only available in LoRa mode...
Definition: SX1272.cpp:81
SX1272::beginFSK
int16_t beginFSK(float freq=915.0, float br=48.0, float rxBw=125.0, float freqDev=50.0, int8_t power=10, uint16_t preambleLength=16, bool enableOOK=false)
FSK modem initialization method. Must be called at least once from Arduino sketch to initialize the m...
Definition: SX1272.cpp:40
-
SX1272::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1272.cpp:324
-
SX1272::setOutputPower
int16_t setOutputPower(int8_t power)
Sets transmission output power. Allowed values range from 2 to 17 dBm.
Definition: SX1272.cpp:207
+
SX1272::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1272.cpp:328
+
SX1272::setOutputPower
int16_t setOutputPower(int8_t power)
Sets transmission output power. Allowed values range from 2 to 17 dBm.
Definition: SX1272.cpp:211
SX1272::SX1272
SX1272(Module *mod)
Default constructor. Called from Arduino sketch when creating new LoRa instance.
Definition: SX1272.cpp:4
-
SX1272::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1272.cpp:353
+
SX1272::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1272.cpp:357
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
-
SX1272::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1272.cpp:173
-
SX1272::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1272.cpp:117
-
SX1272::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1272.cpp:261
-
SX1272::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:372
-
SX1272::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1272.cpp:58
+
SX1272::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1272.cpp:177
+
SX1272::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1272.cpp:121
+
SX1272::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1272.cpp:265
+
SX1272::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:376
+
SX1272::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1272.cpp:62
diff --git a/_s_x1278_8h_source.html b/_s_x1278_8h_source.html index a16db31a..b4cd91f5 100644 --- a/_s_x1278_8h_source.html +++ b/_s_x1278_8h_source.html @@ -85,24 +85,24 @@ $(document).ready(function(){initNavTree('_s_x1278_8h_source.html','');});
1 #if !defined(_RADIOLIB_SX1278_H)
2 #define _RADIOLIB_SX1278_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1278 specific register map
12 #define SX1278_REG_MODEM_CONFIG_3 0x26
13 #define SX1278_REG_PLL_HOP 0x44
14 #define SX1278_REG_TCXO 0x4B
15 #define SX1278_REG_PA_DAC 0x4D
16 #define SX1278_REG_FORMER_TEMP 0x5B
17 #define SX1278_REG_REG_BIT_RATE_FRAC 0x5D
18 #define SX1278_REG_AGC_REF 0x61
19 #define SX1278_REG_AGC_THRESH_1 0x62
20 #define SX1278_REG_AGC_THRESH_2 0x63
21 #define SX1278_REG_AGC_THRESH_3 0x64
22 #define SX1278_REG_PLL 0x70
23 
24 // SX1278 LoRa modem settings
25 // SX1278_REG_OP_MODE MSB LSB DESCRIPTION
26 #define SX1278_HIGH_FREQ 0b00000000 // 3 3 access HF test registers
27 #define SX1278_LOW_FREQ 0b00001000 // 3 3 access LF test registers
28 
29 // SX1278_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
30 #define SX1278_FRF_MSB 0x6C // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
31 #define SX1278_FRF_MID 0x80 // 7 0 where F(XOSC) = 32 MHz
32 #define SX1278_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
33 
34 // SX1278_REG_PA_CONFIG
35 #define SX1278_MAX_POWER 0b01110000 // 6 4 max power: P_max = 10.8 + 0.6*MAX_POWER [dBm]; P_max(MAX_POWER = 0b111) = 15 dBm
36 #define SX1278_LOW_POWER 0b00100000 // 6 4
37 
38 // SX1278_REG_LNA
39 #define SX1278_LNA_BOOST_LF_OFF 0b00000000 // 4 3 default LNA current
40 
41 // SX1278_REG_MODEM_CONFIG_1
42 #define SX1278_BW_7_80_KHZ 0b00000000 // 7 4 bandwidth: 7.80 kHz
43 #define SX1278_BW_10_40_KHZ 0b00010000 // 7 4 10.40 kHz
44 #define SX1278_BW_15_60_KHZ 0b00100000 // 7 4 15.60 kHz
45 #define SX1278_BW_20_80_KHZ 0b00110000 // 7 4 20.80 kHz
46 #define SX1278_BW_31_25_KHZ 0b01000000 // 7 4 31.25 kHz
47 #define SX1278_BW_41_70_KHZ 0b01010000 // 7 4 41.70 kHz
48 #define SX1278_BW_62_50_KHZ 0b01100000 // 7 4 62.50 kHz
49 #define SX1278_BW_125_00_KHZ 0b01110000 // 7 4 125.00 kHz
50 #define SX1278_BW_250_00_KHZ 0b10000000 // 7 4 250.00 kHz
51 #define SX1278_BW_500_00_KHZ 0b10010000 // 7 4 500.00 kHz
52 #define SX1278_CR_4_5 0b00000010 // 3 1 error coding rate: 4/5
53 #define SX1278_CR_4_6 0b00000100 // 3 1 4/6
54 #define SX1278_CR_4_7 0b00000110 // 3 1 4/7
55 #define SX1278_CR_4_8 0b00001000 // 3 1 4/8
56 #define SX1278_HEADER_EXPL_MODE 0b00000000 // 0 0 explicit header mode
57 #define SX1278_HEADER_IMPL_MODE 0b00000001 // 0 0 implicit header mode
58 
59 // SX1278_REG_MODEM_CONFIG_2
60 #define SX1278_RX_CRC_MODE_OFF 0b00000000 // 2 2 CRC disabled
61 #define SX1278_RX_CRC_MODE_ON 0b00000100 // 2 2 CRC enabled
62 
63 // SX1278_REG_MODEM_CONFIG_3
64 #define SX1278_LOW_DATA_RATE_OPT_OFF 0b00000000 // 3 3 low data rate optimization disabled
65 #define SX1278_LOW_DATA_RATE_OPT_ON 0b00001000 // 3 3 low data rate optimization enabled
66 #define SX1278_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
67 #define SX1278_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
68 
69 // SX127X_REG_VERSION
70 #define SX1278_CHIP_VERSION 0x12
71 
72 // SX1278 FSK modem settings
73 // SX127X_REG_PA_RAMP
74 #define SX1278_NO_SHAPING 0b00000000 // 6 5 data shaping: no shaping (default)
75 #define SX1278_FSK_GAUSSIAN_1_0 0b00100000 // 6 5 FSK modulation Gaussian filter, BT = 1.0
76 #define SX1278_FSK_GAUSSIAN_0_5 0b01000000 // 6 5 FSK modulation Gaussian filter, BT = 0.5
77 #define SX1278_FSK_GAUSSIAN_0_3 0b01100000 // 6 5 FSK modulation Gaussian filter, BT = 0.3
78 #define SX1278_OOK_FILTER_BR 0b00100000 // 6 5 OOK modulation filter, f_cutoff = BR
79 #define SX1278_OOK_FILTER_2BR 0b01000000 // 6 5 OOK modulation filter, f_cutoff = 2*BR
80 
81 // SX1278_REG_AGC_REF
82 #define SX1278_AGC_REFERENCE_LEVEL_LF 0x19 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]: below 525 MHz
83 #define SX1278_AGC_REFERENCE_LEVEL_HF 0x1C // 5 0 above 779 MHz
84 
85 // SX1278_REG_AGC_THRESH_1
86 #define SX1278_AGC_STEP_1_LF 0x0C // 4 0 1st AGC threshold: below 525 MHz
87 #define SX1278_AGC_STEP_1_HF 0x0E // 4 0 above 779 MHz
88 
89 // SX1278_REG_AGC_THRESH_2
90 #define SX1278_AGC_STEP_2_LF 0x40 // 7 4 2nd AGC threshold: below 525 MHz
91 #define SX1278_AGC_STEP_2_HF 0x50 // 7 4 above 779 MHz
92 #define SX1278_AGC_STEP_3 0x0B // 3 0 3rd AGC threshold
93 
94 // SX1278_REG_AGC_THRESH_3
95 #define SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold
96 #define SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold
97 
104 class SX1278: public SX127x {
105  public:
106 
107  // constructor
108 
114  SX1278(Module* mod);
115 
116  // basic methods
117 
141  int16_t begin(float freq = 434.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
142 
163  int16_t beginFSK(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
164 
168  void reset() override;
169 
170  // configuration methods
171 
179  int16_t setFrequency(float freq);
180 
188  int16_t setBandwidth(float bw);
189 
197  int16_t setSpreadingFactor(uint8_t sf);
198 
206  int16_t setCodingRate(uint8_t cr);
207 
215  int16_t setOutputPower(int8_t power);
216 
225  int16_t setGain(uint8_t gain);
226 
235  int16_t setDataShaping(uint8_t sh) override;
236 
246  int16_t setDataShapingOOK(uint8_t sh);
247 
253  float getRSSI();
254 
262  int16_t setCRC(bool enableCRC);
263 
272  int16_t forceLDRO(bool enable);
273 
280  int16_t autoLDRO();
281 
282 #ifndef RADIOLIB_GODMODE
283  protected:
284 #endif
285  int16_t setBandwidthRaw(uint8_t newBandwidth);
286  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
287  int16_t setCodingRateRaw(uint8_t newCodingRate);
288 
289  int16_t configFSK();
290 
291 #ifndef RADIOLIB_GODMODE
292  private:
293 #endif
294  bool _ldroAuto = true;
295  bool _ldroEnabled = false;
296 
297 };
298 
299 #endif
300 
301 #endif
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
-
SX1278::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1278.cpp:333
-
SX1278::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1278.cpp:395
-
SX1278::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:450
-
SX1278::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1278.cpp:308
-
SX1278::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:463
-
SX1278::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 137.0 MHz to 525.0 MHz.
Definition: SX1278.cpp:61
-
SX1278::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1278.cpp:431
+
SX1278::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1278.cpp:337
+
SX1278::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1278.cpp:399
+
SX1278::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:454
+
SX1278::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1278.cpp:312
+
SX1278::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:467
+
SX1278::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 137.0 MHz to 525.0 MHz.
Definition: SX1278.cpp:65
+
SX1278::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1278.cpp:435
SX1278::beginFSK
int16_t beginFSK(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=125.0, int8_t power=10, uint16_t preambleLength=16, bool enableOOK=false)
FSK modem initialization method. Must be called at least once from Arduino sketch to initialize the m...
Definition: SX1278.cpp:35
-
SX1278::setDataShapingOOK
int16_t setDataShapingOOK(uint8_t sh)
Sets filter cutoff frequency that will be used for data shaping. Allowed values are 1 for frequency e...
Definition: SX1278.cpp:363
+
SX1278::setDataShapingOOK
int16_t setDataShapingOOK(uint8_t sh)
Sets filter cutoff frequency that will be used for data shaping. Allowed values are 1 for frequency e...
Definition: SX1278.cpp:367
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
-
SX1278::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1278.cpp:53
+
SX1278::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1278.cpp:57
SX1278::SX1278
SX1278(Module *mod)
Default constructor. Called from Arduino sketch when creating new LoRa instance.
Definition: SX1278.cpp:4
SX1278::begin
int16_t begin(float freq=434.0, float bw=125.0, uint8_t sf=9, uint8_t cr=7, uint8_t syncWord=SX127X_SYNC_WORD, int8_t power=10, uint16_t preambleLength=8, uint8_t gain=0)
LoRa modem initialization method. Must be called at least once from Arduino sketch to initialize the ...
Definition: SX1278.cpp:8
-
SX1278::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1278.cpp:189
-
SX1278::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa link bandwidth. Allowed values are 10.4, 15.6, 20.8, 31.25, 41.7, 62.5, 125...
Definition: SX1278.cpp:135
+
SX1278::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1278.cpp:193
+
SX1278::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa link bandwidth. Allowed values are 10.4, 15.6, 20.8, 31.25, 41.7, 62.5, 125...
Definition: SX1278.cpp:139
SX1278
Derived class for SX1278 modules. Also used as base class for SX1276, SX1277, SX1279, RFM95 and RFM96. All of these modules use the same basic hardware and only differ in parameter ranges (and names).
Definition: SX1278.h:104
-
SX1278::setOutputPower
int16_t setOutputPower(int8_t power)
Sets transmission output power. Allowed values range from 2 to 17 dBm.
Definition: SX1278.cpp:279
-
SX1278::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1278.cpp:245
+
SX1278::setOutputPower
int16_t setOutputPower(int8_t power)
Sets transmission output power. Allowed values range from 2 to 17 dBm.
Definition: SX1278.cpp:283
+
SX1278::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1278.cpp:249
diff --git a/_s_x127x_8h_source.html b/_s_x127x_8h_source.html index 57d06a30..68a2ab92 100644 --- a/_s_x127x_8h_source.html +++ b/_s_x127x_8h_source.html @@ -84,56 +84,56 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x.h
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1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
946  int16_t getChipVersion();
947 
948 #ifndef RADIOLIB_GODMODE
949  protected:
950 #endif
951  Module* _mod;
952 
953  float _freq = 0;
954  float _bw = 0;
955  uint8_t _sf = 0;
956  uint8_t _cr = 0;
957  float _br = 0;
958  float _rxBw = 0;
959  bool _ook = false;
960  bool _crcEnabled = false;
961 
962  int16_t setFrequencyRaw(float newFreq);
963  int16_t config();
964  int16_t configFSK();
965  int16_t getActiveModem();
966  int16_t directMode();
967  int16_t setPacketMode(uint8_t mode, uint8_t len);
968 
969 #ifndef RADIOLIB_GODMODE
970  private:
971 #endif
972  float _dataRate = 0;
973  size_t _packetLength = 0;
974  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
975  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
976 
977  bool findChip(uint8_t ver);
978  int16_t setMode(uint8_t mode);
979  int16_t setActiveModem(uint8_t modem);
980  void clearIRQFlags();
981  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
982 };
983 
984 #endif
985 
986 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:907
+
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
946  int16_t getChipVersion();
947 
948 #ifndef RADIOLIB_GODMODE
949  protected:
950 #endif
951  Module* _mod;
952 
953  float _freq = 0;
954  float _bw = 0;
955  uint8_t _sf = 0;
956  uint8_t _cr = 0;
957  float _br = 0;
958  float _rxBw = 0;
959  bool _ook = false;
960  bool _crcEnabled = false;
961 
962  int16_t setFrequencyRaw(float newFreq);
963  int16_t config();
964  int16_t configFSK();
965  int16_t getActiveModem();
966  int16_t directMode();
967  int16_t setPacketMode(uint8_t mode, uint8_t len);
968 
969 #ifndef RADIOLIB_GODMODE
970  private:
971 #endif
972  float _dataRate = 0;
973  size_t _packetLength = 0;
974  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
975  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
976 
977  bool findChip(uint8_t ver);
978  int16_t setMode(uint8_t mode);
979  int16_t setActiveModem(uint8_t modem);
980  void clearIRQFlags();
981  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
982 };
983 
984 #endif
985 
986 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:909
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
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SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:871
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SX127x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: SX127x.cpp:489
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SX127x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Enables direct transmission mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:297
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SX127x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX127x.cpp:978
+
SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:873
+
SX127x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: SX127x.cpp:485
+
SX127x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Enables direct transmission mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:293
+
SX127x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: SX127x.cpp:980
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
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SX127x::clearDio0Action
void clearDio0Action()
Clears interrupt service routine to call when DIO0 activates.
Definition: SX127x.cpp:410
+
SX127x::clearDio0Action
void clearDio0Action()
Clears interrupt service routine to call when DIO0 activates.
Definition: SX127x.cpp:406
SX127x::reset
virtual void reset()=0
Reset method. Will reset the chip to the default state using RST pin. Declared pure virtual since SX1...
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SX127x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets FSK node address. Calling this method will enable address filtering. Only available in FSK mode...
Definition: SX127x.cpp:791
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SX127x::receive
int16_t receive(uint8_t *data, size_t len) override
Binary receive method. Will attempt to receive arbitrary binary data up to 255 bytes long using LoRa ...
Definition: SX127x.cpp:197
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SX127x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Binary transmit method. Will transmit arbitrary binary data up to 255 bytes long using LoRa or up to ...
Definition: SX127x.cpp:130
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SX127x::getSNR
float getSNR()
Gets signal-to-noise ratio of the latest received packet.
Definition: SX127x.cpp:665
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SX127x::setSyncWord
int16_t setSyncWord(uint8_t syncWord)
Sets LoRa sync word. Only available in LoRa mode.
Definition: SX127x.cpp:546
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SX127x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 1.2 to 300 kbps. Only available in FSK mode...
Definition: SX127x.cpp:680
-
SX127x::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: SX127x.cpp:837
-
SX127x::getFrequencyError
float getFrequencyError(bool autoCorrect=false)
Gets frequency error of the latest received packet.
Definition: SX127x.cpp:612
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SX127x::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Will start transmitting arbitrary binary data up to 255 byte...
Definition: SX127x.cpp:428
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SX127x::getModemStatus
uint8_t getModemStatus()
Reads modem status. Only available in LoRa mode.
Definition: SX127x.cpp:964
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SX127x::setCurrentLimit
int16_t setCurrentLimit(uint8_t currentLimit)
Sets current limit for over current protection at transmitter amplifier. Allowed values range from 45...
Definition: SX127x.cpp:559
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SX127x::sleep
int16_t sleep()
Sets the LoRa module to sleep to save power. Module will not be able to transmit or receive any data ...
Definition: SX127x.cpp:281
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SX127x::startReceive
int16_t startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)
Interrupt-driven receive method. DIO0 will be activated when full valid packet is received...
Definition: SX127x.cpp:362
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SX127x::setDio0Action
void setDio0Action(void(*func)(void))
Set interrupt service routine function to call when DIO0 activates.
Definition: SX127x.cpp:406
-
SX127x::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: SX127x.cpp:421
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SX127x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if ...
Definition: SX127x.cpp:1003
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SX127x::setNodeAddress
int16_t setNodeAddress(uint8_t nodeAddr)
Sets FSK node address. Calling this method will enable address filtering. Only available in FSK mode...
Definition: SX127x.cpp:793
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SX127x::receive
int16_t receive(uint8_t *data, size_t len) override
Binary receive method. Will attempt to receive arbitrary binary data up to 255 bytes long using LoRa ...
Definition: SX127x.cpp:193
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SX127x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Binary transmit method. Will transmit arbitrary binary data up to 255 bytes long using LoRa or up to ...
Definition: SX127x.cpp:126
+
SX127x::getSNR
float getSNR()
Gets signal-to-noise ratio of the latest received packet.
Definition: SX127x.cpp:661
+
SX127x::setSyncWord
int16_t setSyncWord(uint8_t syncWord)
Sets LoRa sync word. Only available in LoRa mode.
Definition: SX127x.cpp:542
+
SX127x::setBitRate
int16_t setBitRate(float br)
Sets FSK bit rate. Allowed values range from 1.2 to 300 kbps. Only available in FSK mode...
Definition: SX127x.cpp:676
+
SX127x::setOOK
int16_t setOOK(bool enableOOK)
Enables/disables OOK modulation instead of FSK.
Definition: SX127x.cpp:839
+
SX127x::getFrequencyError
float getFrequencyError(bool autoCorrect=false)
Gets frequency error of the latest received packet.
Definition: SX127x.cpp:608
+
SX127x::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Will start transmitting arbitrary binary data up to 255 byte...
Definition: SX127x.cpp:424
+
SX127x::getModemStatus
uint8_t getModemStatus()
Reads modem status. Only available in LoRa mode.
Definition: SX127x.cpp:966
+
SX127x::setCurrentLimit
int16_t setCurrentLimit(uint8_t currentLimit)
Sets current limit for over current protection at transmitter amplifier. Allowed values range from 45...
Definition: SX127x.cpp:555
+
SX127x::sleep
int16_t sleep()
Sets the LoRa module to sleep to save power. Module will not be able to transmit or receive any data ...
Definition: SX127x.cpp:277
+
SX127x::startReceive
int16_t startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)
Interrupt-driven receive method. DIO0 will be activated when full valid packet is received...
Definition: SX127x.cpp:358
+
SX127x::setDio0Action
void setDio0Action(void(*func)(void))
Set interrupt service routine function to call when DIO0 activates.
Definition: SX127x.cpp:402
+
SX127x::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: SX127x.cpp:417
+
SX127x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if ...
Definition: SX127x.cpp:1005
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
-
SX127x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:323
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SX127x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: SX127x.cpp:930
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SX127x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:903
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SX127x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values depend on bit rate setting and mu...
Definition: SX127x.cpp:709
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SX127x::standby
int16_t standby() override
Sets the LoRa module to standby.
Definition: SX127x.cpp:289
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SX127x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:319
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SX127x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: SX127x.cpp:932
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SX127x::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in variable packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:905
+
SX127x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values depend on bit rate setting and mu...
Definition: SX127x.cpp:705
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SX127x::standby
int16_t standby() override
Sets the LoRa module to standby.
Definition: SX127x.cpp:285
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
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SX127x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values range from 2.6 to 250 kHz. Only available in FSK mode...
Definition: SX127x.cpp:732
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SX127x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets FSK receiver bandwidth. Allowed values range from 2.6 to 250 kHz. Only available in FSK mode...
Definition: SX127x.cpp:734
SX127x::beginFSK
int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK)
Initialization method for FSK modem. Will be called with appropriate parameters when calling FSK init...
Definition: SX127x.cpp:55
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SX127x::getIRQFlags
uint16_t getIRQFlags()
Reads currently active IRQ flags, can be used to check which event caused an interrupt. In LoRa mode, this is the content of SX127X_REG_IRQ_FLAGS register. In FSK mode, this is the contents of SX127X_REG_IRQ_FLAGS_2 (MSB) and SX127X_REG_IRQ_FLAGS_1 (LSB) registers.
Definition: SX127x.cpp:949
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SX127x::getIRQFlags
uint16_t getIRQFlags()
Reads currently active IRQ flags, can be used to check which event caused an interrupt. In LoRa mode, this is the content of SX127X_REG_IRQ_FLAGS register. In FSK mode, this is the contents of SX127X_REG_IRQ_FLAGS_2 (MSB) and SX127X_REG_IRQ_FLAGS_1 (LSB) registers.
Definition: SX127x.cpp:951
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
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SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:1007
-
SX127x::scanChannel
int16_t scanChannel()
Performs scan for valid LoRa preamble in the current channel.
Definition: SX127x.cpp:242
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SX127x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX127x.cpp:974
-
SX127x::packetMode
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets. Can only be activated in FSK mode.
Definition: SX127x.cpp:353
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SX127x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables FSK address filtering.
Definition: SX127x.cpp:819
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SX127x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets FSK broadcast address. Calling this method will enable address filtering. Only available in FSK ...
Definition: SX127x.cpp:805
-
SX127x::setDio1Action
void setDio1Action(void(*func)(void))
Set interrupt service routine function to call when DIO1 activates.
Definition: SX127x.cpp:414
-
SX127x::getDataRate
float getDataRate() const
Get data rate of the latest transmitted packet.
Definition: SX127x.cpp:676
+
SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:1009
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SX127x::scanChannel
int16_t scanChannel()
Performs scan for valid LoRa preamble in the current channel.
Definition: SX127x.cpp:238
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SX127x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX127x.cpp:976
+
SX127x::packetMode
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets. Can only be activated in FSK mode.
Definition: SX127x.cpp:349
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SX127x::disableAddressFiltering
int16_t disableAddressFiltering()
Disables FSK address filtering.
Definition: SX127x.cpp:821
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SX127x::setBroadcastAddress
int16_t setBroadcastAddress(uint8_t broadAddr)
Sets FSK broadcast address. Calling this method will enable address filtering. Only available in FSK ...
Definition: SX127x.cpp:807
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SX127x::setDio1Action
void setDio1Action(void(*func)(void))
Set interrupt service routine function to call when DIO1 activates.
Definition: SX127x.cpp:410
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SX127x::getDataRate
float getDataRate() const
Get data rate of the latest transmitted packet.
Definition: SX127x.cpp:672
SX127x::SX127x
SX127x(Module *mod)
Default constructor. Called internally when creating new LoRa instance.
Definition: SX127x.cpp:4
-
SX127x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:899
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SX127x::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)
Set modem in fixed packet length mode. Available in FSK mode only.
Definition: SX127x.cpp:901
SX127x::begin
int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength)
Initialization method. Will be called with appropriate parameters when calling initialization method ...
Definition: SX127x.cpp:8
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
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SX127x::setPreambleLength
int16_t setPreambleLength(uint16_t preambleLength)
Sets LoRa or FSK preamble length. Allowed values range from 6 to 65535 in LoRa mode or 0 to 65535 in ...
Definition: SX127x.cpp:583
+
SX127x::setPreambleLength
int16_t setPreambleLength(uint16_t preambleLength)
Sets LoRa or FSK preamble length. Allowed values range from 6 to 65535 in LoRa mode or 0 to 65535 in ...
Definition: SX127x.cpp:579
diff --git a/_s_x128x_8h_source.html b/_s_x128x_8h_source.html index 066ceec1..8025c50b 100644 --- a/_s_x128x_8h_source.html +++ b/_s_x128x_8h_source.html @@ -84,31 +84,31 @@ $(document).ready(function(){initNavTree('_s_x128x_8h_source.html','');});
SX128x.h
-
1 #if !defined(_RADIOLIB_SX128X_H)
2 #define _RADIOLIB_SX128X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX128X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX128X physical layer properties
13 #define SX128X_FREQUENCY_STEP_SIZE 198.3642578
14 #define SX128X_MAX_PACKET_LENGTH 255
15 #define SX128X_CRYSTAL_FREQ 52.0
16 #define SX128X_DIV_EXPONENT 18
17 
18 // SX128X SPI commands
19 #define SX128X_CMD_NOP 0x00
20 #define SX128X_CMD_GET_STATUS 0xC0
21 #define SX128X_CMD_WRITE_REGISTER 0x18
22 #define SX128X_CMD_READ_REGISTER 0x19
23 #define SX128X_CMD_WRITE_BUFFER 0x1A
24 #define SX128X_CMD_READ_BUFFER 0x1B
25 #define SX128X_CMD_SET_SLEEP 0x84
26 #define SX128X_CMD_SET_STANDBY 0x80
27 #define SX128X_CMD_SET_FS 0xC1
28 #define SX128X_CMD_SET_TX 0x83
29 #define SX128X_CMD_SET_RX 0x82
30 #define SX128X_CMD_SET_RX_DUTY_CYCLE 0x94
31 #define SX128X_CMD_SET_CAD 0xC5
32 #define SX128X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
33 #define SX128X_CMD_SET_TX_CONTINUOUS_PREAMBLE 0xD2
34 #define SX128X_CMD_SET_PACKET_TYPE 0x8A
35 #define SX128X_CMD_GET_PACKET_TYPE 0x03
36 #define SX128X_CMD_SET_RF_FREQUENCY 0x86
37 #define SX128X_CMD_SET_TX_PARAMS 0x8E
38 #define SX128X_CMD_SET_CAD_PARAMS 0x88
39 #define SX128X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
40 #define SX128X_CMD_SET_MODULATION_PARAMS 0x8B
41 #define SX128X_CMD_SET_PACKET_PARAMS 0x8C
42 #define SX128X_CMD_GET_RX_BUFFER_STATUS 0x17
43 #define SX128X_CMD_GET_PACKET_STATUS 0x1D
44 #define SX128X_CMD_GET_RSSI_INST 0x1F
45 #define SX128X_CMD_SET_DIO_IRQ_PARAMS 0x8D
46 #define SX128X_CMD_GET_IRQ_STATUS 0x15
47 #define SX128X_CMD_CLEAR_IRQ_STATUS 0x97
48 #define SX128X_CMD_SET_REGULATOR_MODE 0x96
49 #define SX128X_CMD_SET_SAVE_CONTEXT 0xD5
50 #define SX128X_CMD_SET_AUTO_TX 0x98
51 #define SX128X_CMD_SET_AUTO_FS 0x9E
52 #define SX128X_CMD_SET_PERF_COUNTER_MODE 0x9C
53 #define SX128X_CMD_SET_LONG_PREAMBLE 0x9B
54 #define SX128X_CMD_SET_UART_SPEED 0x9D
55 #define SX128X_CMD_SET_RANGING_ROLE 0xA3
56 #define SX128X_CMD_SET_ADVANCED_RANGING 0x9A
57 
58 // SX128X register map
59 #define SX128X_REG_SYNC_WORD_1_BYTE_4 0x09CE
60 #define SX128X_REG_SYNC_WORD_1_BYTE_3 0x09CF
61 #define SX128X_REG_SYNC_WORD_1_BYTE_2 0x09D0
62 #define SX128X_REG_SYNC_WORD_1_BYTE_1 0x09D1
63 #define SX128X_REG_SYNC_WORD_1_BYTE_0 0x09D2
64 #define SX128X_REG_SYNC_WORD_2_BYTE_4 0x09D3
65 #define SX128X_REG_SYNC_WORD_2_BYTE_3 0x09D4
66 #define SX128X_REG_SYNC_WORD_2_BYTE_2 0x09D5
67 #define SX128X_REG_SYNC_WORD_2_BYTE_1 0x09D6
68 #define SX128X_REG_SYNC_WORD_2_BYTE_0 0x09D7
69 #define SX128X_REG_SYNC_WORD_3_BYTE_4 0x09D8
70 #define SX128X_REG_SYNC_WORD_3_BYTE_3 0x09D9
71 #define SX128X_REG_SYNC_WORD_3_BYTE_2 0x09DA
72 #define SX128X_REG_SYNC_WORD_3_BYTE_1 0x09DB
73 #define SX128X_REG_SYNC_WORD_3_BYTE_0 0x09DC
74 #define SX128X_REG_CRC_INITIAL_MSB 0x09C8
75 #define SX128X_REG_CRC_INITIAL_LSB 0x09C9
76 #define SX128X_REG_CRC_POLYNOMIAL_MSB 0x09C6
77 #define SX128X_REG_CRC_POLYNOMIAL_LSB 0x09C7
78 #define SX128X_REG_ACCESS_ADDRESS_BYTE_3 (SX128X_REG_SYNC_WORD_1_BYTE_3)
79 #define SX128X_REG_ACCESS_ADDRESS_BYTE_2 (SX128X_REG_SYNC_WORD_1_BYTE_2)
80 #define SX128X_REG_ACCESS_ADDRESS_BYTE_1 (SX128X_REG_SYNC_WORD_1_BYTE_1)
81 #define SX128X_REG_ACCESS_ADDRESS_BYTE_0 (SX128X_REG_SYNC_WORD_1_BYTE_0)
82 #define SX128X_REG_BLE_CRC_INITIAL_MSB 0x09C7
83 #define SX128X_REG_BLE_CRC_INITIAL_MID (SX128X_REG_CRC_INITIAL_MSB)
84 #define SX128X_REG_BLE_CRC_INITIAL_LSB (SX128X_REG_CRC_INITIAL_LSB)
85 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_3 0x0916
86 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_2 0x0917
87 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_1 0x0918
88 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_0 0x0919
89 #define SX128X_REG_SLAVE_RANGING_ADDRESS_WIDTH 0x0931
90 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_3 0x0912
91 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_2 0x0913
92 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_1 0x0914
93 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_0 0x0915
94 #define SX128X_REG_RANGING_CALIBRATION_MSB 0x092C
95 #define SX128X_REG_RANGING_CALIBRATION_LSB 0x092D
96 #define SX128X_REG_RANGING_RESULT_MSB 0x0961
97 #define SX128X_REG_RANGING_RESULT_MID 0x0962
98 #define SX128X_REG_RANGING_RESULT_LSB 0x0963
99 #define SX128X_REG_MANUAL_GAIN_CONTROL_ENABLE_1 0x089F
100 #define SX128X_REG_MANUAL_GAIN_CONTROL_ENABLE_2 0x0895
101 #define SX128X_REG_MANUAL_GAIN_SETTING 0x089E
102 #define SX128X_REG_GAIN_MODE 0x0891
103 #define SX128X_REG_LORA_FIXED_PAYLOAD_LENGTH 0x0901
104 #define SX128X_REG_LORA_SF_CONFIG 0x0925
105 #define SX128X_REG_FEI_MSB 0x0954
106 #define SX128X_REG_FEI_MID 0x0955
107 #define SX128X_REG_FEI_LSB 0x0956
108 #define SX128X_REG_RANGING_FILTER_WINDOW_SIZE 0x091E
109 #define SX128X_REG_RANGING_FILTER_RSSI_OFFSET 0x0953
110 #define SX128X_REG_RANGING_FILTER_RESET 0x0923
111 #define SX128X_REG_RANGING_LORA_CLOCK_ENABLE 0x097F
112 #define SX128X_REG_RANGING_TYPE 0x0924
113 #define SX128X_REG_RANGING_ADDRESS_SWITCH 0x0927
114 #define SX128X_REG_RANGING_ADDRESS_MSB 0x095F
115 #define SX128X_REG_RANGING_ADDRESS_LSB 0x0960
116 
117 
118 // SX128X SPI command variables
119 //SX128X_CMD_GET_STATUS MSB LSB DESCRIPTION
120 #define SX128X_STATUS_MODE_STDBY_RC 0b01000000 // 7 5 current chip mode: STDBY_RC
121 #define SX128X_STATUS_MODE_STDBY_XOSC 0b01100000 // 7 5 STDBY_XOSC
122 #define SX128X_STATUS_MODE_FS 0b10000000 // 7 5 FS
123 #define SX128X_STATUS_MODE_RX 0b10100000 // 7 5 Rx
124 #define SX128X_STATUS_MODE_TX 0b11000000 // 7 5 Tx
125 #define SX128X_STATUS_CMD_PROCESSED 0b00000100 // 4 2 command status: processing OK
126 #define SX128X_STATUS_DATA_AVAILABLE 0b00001000 // 4 2 data available
127 #define SX128X_STATUS_CMD_TIMEOUT 0b00001100 // 4 2 timeout
128 #define SX128X_STATUS_CMD_ERROR 0b00010000 // 4 2 processing error
129 #define SX128X_STATUS_CMD_FAILED 0b00010100 // 4 2 failed to execute
130 #define SX128X_STATUS_TX_DONE 0b00011000 // 4 2 transmission finished
131 #define SX128X_STATUS_BUSY 0b00000001 // 0 0 chip busy
132 #define SX128X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
133 
134 //SX128X_CMD_SET_SLEEP
135 #define SX128X_SLEEP_DATA_BUFFER_FLUSH 0b00000000 // 1 1 data buffer behavior in sleep mode: flush
136 #define SX128X_SLEEP_DATA_BUFFER_RETAIN 0b00000010 // 1 1 retain
137 #define SX128X_SLEEP_DATA_RAM_FLUSH 0b00000000 // 0 0 data RAM (configuration) behavior in sleep mode: flush
138 #define SX128X_SLEEP_DATA_RAM_RETAIN 0b00000001 // 0 0 retain
139 
140 //SX128X_CMD_SET_STANDBY
141 #define SX128X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
142 #define SX128X_STANDBY_XOSC 0x01 // 7 0 52 MHz crystal oscillator
143 
144 //SX128X_CMD_SET_TX + SX128X_CMD_SET_RX + SX128X_CMD_SET_RX_DUTY_CYCLE
145 #define SX128X_PERIOD_BASE_15_625_US 0x00 // 7 0 time period step: 15.625 us
146 #define SX128X_PERIOD_BASE_62_5_US 0x01 // 7 0 62.5 us
147 #define SX128X_PERIOD_BASE_1_MS 0x02 // 7 0 1 ms
148 #define SX128X_PERIOD_BASE_4_MS 0x03 // 7 0 4 ms
149 
150 //SX128X_CMD_SET_TX
151 #define SX128X_TX_TIMEOUT_NONE 0x0000 // 15 0 Tx timeout duration: no timeout (Tx single mode)
152 
153 //SX128X_CMD_SET_RX
154 #define SX128X_RX_TIMEOUT_NONE 0x0000 // 15 0 Rx timeout duration: no timeout (Rx single mode)
155 #define SX128X_RX_TIMEOUT_INF 0xFFFF // 15 0 infinite (Rx continuous mode)
156 
157 //SX128X_CMD_SET_PACKET_TYPE
158 #define SX128X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: (G)FSK
159 #define SX128X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
160 #define SX128X_PACKET_TYPE_RANGING 0x02 // 7 0 ranging engine
161 #define SX128X_PACKET_TYPE_FLRC 0x03 // 7 0 FLRC
162 #define SX128X_PACKET_TYPE_BLE 0x04 // 7 0 BLE
163 
164 //SX128X_CMD_SET_TX_PARAMS
165 #define SX128X_PA_RAMP_02_US 0x00 // 7 0 PA ramp time: 2 us
166 #define SX128X_PA_RAMP_04_US 0x20 // 7 0 4 us
167 #define SX128X_PA_RAMP_06_US 0x40 // 7 0 6 us
168 #define SX128X_PA_RAMP_08_US 0x60 // 7 0 8 us
169 #define SX128X_PA_RAMP_10_US 0x80 // 7 0 10 us
170 #define SX128X_PA_RAMP_12_US 0xA0 // 7 0 12 us
171 #define SX128X_PA_RAMP_16_US 0xC0 // 7 0 16 us
172 #define SX128X_PA_RAMP_20_US 0xE0 // 7 0 20 us
173 
174 //SX128X_CMD_SET_CAD_PARAMS
175 #define SX128X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
176 #define SX128X_CAD_ON_2_SYMB 0x20 // 7 0 2
177 #define SX128X_CAD_ON_4_SYMB 0x40 // 7 0 4
178 #define SX128X_CAD_ON_8_SYMB 0x60 // 7 0 8
179 #define SX128X_CAD_ON_16_SYMB 0x80 // 7 0 16
180 
181 //SX128X_CMD_SET_MODULATION_PARAMS
182 #define SX128X_BLE_GFSK_BR_2_000_BW_2_4 0x04 // 7 0 GFSK/BLE bit rate and bandwidth setting: 2.0 Mbps 2.4 MHz
183 #define SX128X_BLE_GFSK_BR_1_600_BW_2_4 0x28 // 7 0 1.6 Mbps 2.4 MHz
184 #define SX128X_BLE_GFSK_BR_1_000_BW_2_4 0x4C // 7 0 1.0 Mbps 2.4 MHz
185 #define SX128X_BLE_GFSK_BR_1_000_BW_1_2 0x45 // 7 0 1.0 Mbps 1.2 MHz
186 #define SX128X_BLE_GFSK_BR_0_800_BW_2_4 0x70 // 7 0 0.8 Mbps 2.4 MHz
187 #define SX128X_BLE_GFSK_BR_0_800_BW_1_2 0x69 // 7 0 0.8 Mbps 1.2 MHz
188 #define SX128X_BLE_GFSK_BR_0_500_BW_1_2 0x8D // 7 0 0.5 Mbps 1.2 MHz
189 #define SX128X_BLE_GFSK_BR_0_500_BW_0_6 0x86 // 7 0 0.5 Mbps 0.6 MHz
190 #define SX128X_BLE_GFSK_BR_0_400_BW_1_2 0xB1 // 7 0 0.4 Mbps 1.2 MHz
191 #define SX128X_BLE_GFSK_BR_0_400_BW_0_6 0xAA // 7 0 0.4 Mbps 0.6 MHz
192 #define SX128X_BLE_GFSK_BR_0_250_BW_0_6 0xCE // 7 0 0.25 Mbps 0.6 MHz
193 #define SX128X_BLE_GFSK_BR_0_250_BW_0_3 0xC7 // 7 0 0.25 Mbps 0.3 MHz
194 #define SX128X_BLE_GFSK_BR_0_125_BW_0_3 0xEF // 7 0 0.125 Mbps 0.3 MHz
195 #define SX128X_BLE_GFSK_MOD_IND_0_35 0x00 // 7 0 GFSK/BLE modulation index: 0.35
196 #define SX128X_BLE_GFSK_MOD_IND_0_50 0x01 // 7 0 0.50
197 #define SX128X_BLE_GFSK_MOD_IND_0_75 0x02 // 7 0 0.75
198 #define SX128X_BLE_GFSK_MOD_IND_1_00 0x03 // 7 0 1.00
199 #define SX128X_BLE_GFSK_MOD_IND_1_25 0x04 // 7 0 1.25
200 #define SX128X_BLE_GFSK_MOD_IND_1_50 0x05 // 7 0 1.50
201 #define SX128X_BLE_GFSK_MOD_IND_1_75 0x06 // 7 0 1.75
202 #define SX128X_BLE_GFSK_MOD_IND_2_00 0x07 // 7 0 2.00
203 #define SX128X_BLE_GFSK_MOD_IND_2_25 0x08 // 7 0 2.25
204 #define SX128X_BLE_GFSK_MOD_IND_2_50 0x09 // 7 0 2.50
205 #define SX128X_BLE_GFSK_MOD_IND_2_75 0x0A // 7 0 2.75
206 #define SX128X_BLE_GFSK_MOD_IND_3_00 0x0B // 7 0 3.00
207 #define SX128X_BLE_GFSK_MOD_IND_3_25 0x0C // 7 0 3.25
208 #define SX128X_BLE_GFSK_MOD_IND_3_50 0x0D // 7 0 3.50
209 #define SX128X_BLE_GFSK_MOD_IND_3_75 0x0E // 7 0 3.75
210 #define SX128X_BLE_GFSK_MOD_IND_4_00 0x0F // 7 0 4.00
211 #define SX128X_BLE_GFSK_BT_OFF 0x00 // 7 0 GFSK Gaussian filter BT product: filter disabled
212 #define SX128X_BLE_GFSK_BT_1_0 0x10 // 7 0 1.0
213 #define SX128X_BLE_GFSK_BT_0_5 0x20 // 7 0 0.5
214 #define SX128X_FLRC_BR_1_300_BW_1_2 0x45 // 7 0 FLRC bit rate and bandwidth setting: 1.3 Mbps 1.2 MHz
215 #define SX128X_FLRC_BR_1_000_BW_1_2 0x69 // 7 0 1.04 Mbps 1.2 MHz
216 #define SX128X_FLRC_BR_0_650_BW_0_6 0x86 // 7 0 0.65 Mbps 0.6 MHz
217 #define SX128X_FLRC_BR_0_520_BW_0_6 0xAA // 7 0 0.52 Mbps 0.6 MHz
218 #define SX128X_FLRC_BR_0_325_BW_0_3 0xC7 // 7 0 0.325 Mbps 0.3 MHz
219 #define SX128X_FLRC_BR_0_260_BW_0_3 0xEB // 7 0 0.260 Mbps 0.3 MHz
220 #define SX128X_FLRC_CR_1_2 0x00 // 7 0 FLRC coding rate: 1/2
221 #define SX128X_FLRC_CR_3_4 0x02 // 7 0 3/4
222 #define SX128X_FLRC_CR_1_0 0x04 // 7 0 1/1
223 #define SX128X_FLRC_BT_OFF 0x00 // 7 0 FLRC Gaussian filter BT product: filter disabled
224 #define SX128X_FLRC_BT_1_0 0x10 // 7 0 1.0
225 #define SX128X_FLRC_BT_0_5 0x20 // 7 0 0.5
226 #define SX128X_LORA_SF_5 0x50 // 7 0 LoRa spreading factor: 5
227 #define SX128X_LORA_SF_6 0x60 // 7 0 6
228 #define SX128X_LORA_SF_7 0x70 // 7 0 7
229 #define SX128X_LORA_SF_8 0x80 // 7 0 8
230 #define SX128X_LORA_SF_9 0x90 // 7 0 9
231 #define SX128X_LORA_SF_10 0xA0 // 7 0 10
232 #define SX128X_LORA_SF_11 0xB0 // 7 0 11
233 #define SX128X_LORA_SF_12 0xC0 // 7 0 12
234 #define SX128X_LORA_BW_1625_00 0x0A // 7 0 LoRa bandwidth: 1625.0 kHz
235 #define SX128X_LORA_BW_812_50 0x18 // 7 0 812.5 kHz
236 #define SX128X_LORA_BW_406_25 0x26 // 7 0 406.25 kHz
237 #define SX128X_LORA_BW_203_125 0x34 // 7 0 203.125 kHz
238 #define SX128X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
239 #define SX128X_LORA_CR_4_6 0x02 // 7 0 4/6
240 #define SX128X_LORA_CR_4_7 0x03 // 7 0 4/7
241 #define SX128X_LORA_CR_4_8 0x04 // 7 0 4/8
242 #define SX128X_LORA_CR_4_5_LI 0x05 // 7 0 4/5, long interleaving
243 #define SX128X_LORA_CR_4_6_LI 0x06 // 7 0 4/6, long interleaving
244 #define SX128X_LORA_CR_4_7_LI 0x07 // 7 0 4/7, long interleaving
245 
246 //SX128X_CMD_SET_PACKET_PARAMS
247 #define SX128X_GFSK_FLRC_SYNC_WORD_OFF 0x00 // 7 0 GFSK/FLRC sync word used: none
248 #define SX128X_GFSK_FLRC_SYNC_WORD_1 0x10 // 7 0 sync word 1
249 #define SX128X_GFSK_FLRC_SYNC_WORD_2 0x20 // 7 0 sync word 2
250 #define SX128X_GFSK_FLRC_SYNC_WORD_1_2 0x30 // 7 0 sync words 1 and 2
251 #define SX128X_GFSK_FLRC_SYNC_WORD_3 0x40 // 7 0 sync word 3
252 #define SX128X_GFSK_FLRC_SYNC_WORD_1_3 0x50 // 7 0 sync words 1 and 3
253 #define SX128X_GFSK_FLRC_SYNC_WORD_2_3 0x60 // 7 0 sync words 2 and 3
254 #define SX128X_GFSK_FLRC_SYNC_WORD_1_2_3 0x70 // 7 0 sync words 1, 2 and 3
255 #define SX128X_GFSK_FLRC_PACKET_FIXED 0x00 // 7 0 GFSK/FLRC packet length mode: fixed
256 #define SX128X_GFSK_FLRC_PACKET_VARIABLE 0x20 // 7 0 variable
257 #define SX128X_GFSK_FLRC_CRC_OFF 0x00 // 7 0 GFSK/FLRC packet CRC: none
258 #define SX128X_GFSK_FLRC_CRC_1_BYTE 0x10 // 7 0 1 byte
259 #define SX128X_GFSK_FLRC_CRC_2_BYTE 0x20 // 7 0 2 bytes
260 #define SX128X_GFSK_FLRC_CRC_3_BYTE 0x30 // 7 0 3 bytes (FLRC only)
261 #define SX128X_GFSK_BLE_WHITENING_ON 0x00 // 7 0 GFSK/BLE whitening: enabled
262 #define SX128X_GFSK_BLE_WHITENING_OFF 0x08 // 7 0 disabled
263 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_31 0x00 // 7 0 BLE maximum payload length: 31 bytes
264 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_37 0x20 // 7 0 37 bytes
265 #define SX128X_BLE_PAYLOAD_LENGTH_TEST 0x40 // 7 0 63 bytes (test mode)
266 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_255 0x80 // 7 0 255 bytes (Bluetooth 4.2 and above)
267 #define SX128X_BLE_CRC_OFF 0x00 // 7 0 BLE packet CRC: none
268 #define SX128X_BLE_CRC_3_BYTE 0x10 // 7 0 3 byte
269 #define SX128X_BLE_PRBS_9 0x00 // 7 0 BLE test payload contents: PRNG sequence using x^9 + x^5 + x
270 #define SX128X_BLE_EYELONG 0x04 // 7 0 repeated 0xF0
271 #define SX128X_BLE_EYESHORT 0x08 // 7 0 repeated 0xAA
272 #define SX128X_BLE_PRBS_15 0x0C // 7 0 PRNG sequence using x^15 + x^14 + x^13 + x^12 + x^2 + x + 1
273 #define SX128X_BLE_ALL_1 0x10 // 7 0 repeated 0xFF
274 #define SX128X_BLE_ALL_0 0x14 // 7 0 repeated 0x00
275 #define SX128X_BLE_EYELONG_INV 0x18 // 7 0 repeated 0x0F
276 #define SX128X_BLE_EYESHORT_INV 0x1C // 7 0 repeated 0x55
277 #define SX128X_FLRC_SYNC_WORD_OFF 0x00 // 7 0 FLRC sync word: disabled
278 #define SX128X_FLRC_SYNC_WORD_ON 0x04 // 7 0 enabled
279 #define SX128X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
280 #define SX128X_LORA_HEADER_IMPLICIT 0x80 // 7 0 implicit
281 #define SX128X_LORA_CRC_OFF 0x00 // 7 0 LoRa packet CRC: disabled
282 #define SX128X_LORA_CRC_ON 0x20 // 7 0 enabled
283 #define SX128X_LORA_IQ_STANDARD 0x40 // 7 0 LoRa IQ: standard
284 #define SX128X_LORA_IQ_INVERTED 0x00 // 7 0 inverted
285 
286 //SX128X_CMD_GET_PACKET_STATUS
287 #define SX128X_PACKET_STATUS_SYNC_ERROR 0b01000000 // 6 6 packet status errors byte: sync word error
288 #define SX128X_PACKET_STATUS_LENGTH_ERROR 0b00100000 // 5 5 packet length error
289 #define SX128X_PACKET_STATUS_CRC_ERROR 0b00010000 // 4 4 CRC error
290 #define SX128X_PACKET_STATUS_ABORT_ERROR 0b00001000 // 3 3 packet reception aborted
291 #define SX128X_PACKET_STATUS_HEADER_RECEIVED 0b00000100 // 2 2 header received
292 #define SX128X_PACKET_STATUS_PACKET_RECEIVED 0b00000010 // 1 1 packet received
293 #define SX128X_PACKET_STATUS_PACKET_CTRL_BUSY 0b00000001 // 0 0 packet controller is busy
294 #define SX128X_PACKET_STATUS_RX_PID 0b11000000 // 7 6 packet status status byte: PID field of the received packet
295 #define SX128X_PACKET_STATUS_NO_ACK 0b00100000 // 5 5 NO_ACK field of the received packet
296 #define SX128X_PACKET_STATUS_RX_PID_ERROR 0b00010000 // 4 4 PID field error
297 #define SX128X_PACKET_STATUS_PACKET_SENT 0b00000001 // 0 0 packet sent
298 #define SX128X_PACKET_STATUS_SYNC_DET_ERROR 0b00000000 // 2 0 packet status sync byte: sync word detection error
299 #define SX128X_PACKET_STATUS_SYNC_DET_1 0b00000001 // 2 0 detected sync word 1
300 #define SX128X_PACKET_STATUS_SYNC_DET_2 0b00000010 // 2 0 detected sync word 2
301 #define SX128X_PACKET_STATUS_SYNC_DET_3 0b00000100 // 2 0 detected sync word 3
302 
303 //SX128X_CMD_SET_DIO_IRQ_PARAMS
304 #define SX128X_IRQ_PREAMBLE_DETECTED 0x8000 // 15 15 interrupt source: preamble detected
305 #define SX128X_IRQ_ADVANCED_RANGING_DONE 0x8000 // 15 15 advanced ranging done
306 #define SX128X_IRQ_RX_TX_TIMEOUT 0x4000 // 14 14 Rx or Tx timeout
307 #define SX128X_IRQ_CAD_DETECTED 0x2000 // 13 13 channel activity detected
308 #define SX128X_IRQ_CAD_DONE 0x1000 // 12 12 CAD finished
309 #define SX128X_IRQ_RANGING_SLAVE_REQ_VALID 0x0800 // 11 11 ranging request valid (slave)
310 #define SX128X_IRQ_RANGING_MASTER_TIMEOUT 0x0400 // 10 10 ranging timeout (master)
311 #define SX128X_IRQ_RANGING_MASTER_RES_VALID 0x0200 // 9 9 ranging result valid (master)
312 #define SX128X_IRQ_RANGING_SLAVE_REQ_DISCARD 0x0100 // 8 8 ranging result valid (master)
313 #define SX128X_IRQ_RANGING_SLAVE_RESP_DONE 0x0080 // 7 7 ranging response complete (slave)
314 #define SX128X_IRQ_CRC_ERROR 0x0040 // 6 6 CRC error
315 #define SX128X_IRQ_HEADER_ERROR 0x0020 // 5 5 header error
316 #define SX128X_IRQ_HEADER_VALID 0x0010 // 4 4 header valid
317 #define SX128X_IRQ_SYNC_WORD_ERROR 0x0008 // 3 3 sync word error
318 #define SX128X_IRQ_SYNC_WORD_VALID 0x0004 // 2 2 sync word valid
319 #define SX128X_IRQ_RX_DONE 0x0002 // 1 1 Rx done
320 #define SX128X_IRQ_TX_DONE 0x0001 // 0 0 Tx done
321 #define SX128X_IRQ_NONE 0x0000 // 15 0 none
322 #define SX128X_IRQ_ALL 0xFFFF // 15 0 all
323 
324 //SX128X_CMD_SET_REGULATOR_MODE
325 #define SX128X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
326 #define SX128X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
327 
328 //SX128X_CMD_SET_RANGING_ROLE
329 #define SX128X_RANGING_ROLE_MASTER 0x01 // 7 0 ranging role: master
330 #define SX128X_RANGING_ROLE_SLAVE 0x00 // 7 0 slave
331 
332 
339 class SX128x: public PhysicalLayer {
340  public:
341  // introduce PhysicalLayer overloads
342  using PhysicalLayer::transmit;
343  using PhysicalLayer::receive;
344  using PhysicalLayer::startTransmit;
345  using PhysicalLayer::readData;
346 
352  SX128x(Module* mod);
353 
354  // basic methods
355 
373  int16_t begin(float freq = 2400.0, float bw = 812.5, uint8_t sf = 9, uint8_t cr = 7, int8_t power = 10, uint16_t preambleLength = 12);
374 
390  int16_t beginGFSK(float freq = 2400.0, uint16_t br = 800, float freqDev = 400.0, int8_t power = 10, uint16_t preambleLength = 16);
391 
407  int16_t beginBLE(float freq = 2400.0, uint16_t br = 800, float freqDev = 400.0, int8_t power = 10, uint8_t dataShaping = RADIOLIB_SHAPING_0_5);
408 
426  int16_t beginFLRC(float freq = 2400.0, uint16_t br = 650, uint8_t cr = 3, int8_t power = 10, uint16_t preambleLength = 16, uint8_t dataShaping = RADIOLIB_SHAPING_0_5);
427 
436  int16_t reset(bool verify = true);
437 
450  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
451 
462  int16_t receive(uint8_t* data, size_t len) override;
463 
471  int16_t transmitDirect(uint32_t frf = 0) override;
472 
479  int16_t receiveDirect() override;
480 
486  int16_t scanChannel();
487 
495  int16_t sleep(bool retainConfig = true);
496 
502  int16_t standby() override;
503 
511  int16_t standby(uint8_t mode);
512 
513  // interrupt methods
514 
520  void setDio1Action(void (*func)(void));
521 
525  void clearDio1Action();
526 
539  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
540 
548  int16_t startReceive(uint16_t timeout = SX128X_RX_TIMEOUT_INF);
549 
559  int16_t readData(uint8_t* data, size_t len) override;
560 
561  // configuration methods
562 
570  int16_t setFrequency(float freq);
571 
579  int16_t setBandwidth(float bw);
580 
588  int16_t setSpreadingFactor(uint8_t sf);
589 
599  int16_t setCodingRate(uint8_t cr, bool longInterleaving = false);
600 
608  int16_t setOutputPower(int8_t power);
609 
617  int16_t setPreambleLength(uint32_t preambleLength);
618 
626  int16_t setBitRate(uint16_t br);
627 
635  int16_t setFrequencyDeviation(float freqDev) override;
636 
645  int16_t setDataShaping(uint8_t sh) override;
646 
656  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
657 
669  int16_t setCRC(uint8_t len, uint32_t initial = 0x1D0F, uint16_t polynomial = 0x1021);
670 
678  int16_t setWhitening(bool enabled);
679 
687  int16_t setAccessAddress(uint32_t addr);
688 
694  float getRSSI();
695 
701  float getSNR();
702 
710  size_t getPacketLength(bool update = true) override;
711 
719  uint32_t getTimeOnAir(size_t len);
720 
726  int16_t implicitHeader(size_t len);
727 
735  int16_t explicitHeader();
736 
744  int16_t setEncoding(uint8_t encoding) override;
745 
754  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
755 
761  uint8_t random();
762 
763 #ifndef RADIOLIB_GODMODE
764  protected:
765 #endif
766  Module* _mod;
767 
768  // cached LoRa parameters
769  float _bwKhz = 0;
770  uint8_t _bw = 0, _sf = 0, _cr = 0;
771  uint8_t _preambleLengthLoRa = 0, _headerType = 0, _payloadLen = 0, _crcLoRa = 0;
772 
773  // SX128x SPI command implementations
774  uint8_t getStatus();
775  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
776  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
777  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
778  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
779  int16_t setTx(uint16_t periodBaseCount = SX128X_TX_TIMEOUT_NONE, uint8_t periodBase = SX128X_PERIOD_BASE_15_625_US);
780  int16_t setRx(uint16_t periodBaseCount, uint8_t periodBase = SX128X_PERIOD_BASE_15_625_US);
781  int16_t setCad();
782  uint8_t getPacketType();
783  int16_t setRfFrequency(uint32_t frf);
784  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX128X_PA_RAMP_10_US);
785  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
786  int16_t setModulationParams(uint8_t modParam1, uint8_t modParam2, uint8_t modParam3);
787  int16_t setPacketParamsGFSK(uint8_t preambleLen, uint8_t syncWordLen, uint8_t syncWordMatch, uint8_t crcLen, uint8_t whitening, uint8_t payloadLen = 0xFF, uint8_t headerType = SX128X_GFSK_FLRC_PACKET_VARIABLE);
788  int16_t setPacketParamsBLE(uint8_t connState, uint8_t crcLen, uint8_t bleTestPayload, uint8_t whitening);
789  int16_t setPacketParamsLoRa(uint8_t preambleLen, uint8_t headerType, uint8_t payloadLen, uint8_t crc, uint8_t invertIQ = SX128X_LORA_IQ_STANDARD);
790  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX128X_IRQ_NONE, uint16_t dio3Mask = SX128X_IRQ_NONE);
791  uint16_t getIrqStatus();
792  int16_t clearIrqStatus(uint16_t clearIrqParams = SX128X_IRQ_ALL);
793  int16_t setRangingRole(uint8_t role);
794  int16_t setPacketType(uint8_t type);
795 
796  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
797 
798 #ifndef RADIOLIB_GODMODE
799  private:
800 #endif
801  // common parameters
802  uint8_t _pwr = 0;
803 
804  // cached GFSK parameters
805  float _modIndexReal = 0;
806  uint16_t _brKbps = 0;
807  uint8_t _br = 0, _modIndex = 0, _shaping = 0;
808  uint8_t _preambleLengthGFSK = 0, _syncWordLen = 0, _syncWordMatch = 0, _crcGFSK = 0, _whitening = 0;
809 
810  // cached FLRC parameters
811  uint8_t _crFLRC = 0;
812 
813  // cached BLE parameters
814  uint8_t _connectionState = 0, _crcBLE = 0, _bleTestPayload = 0;
815 
816  int16_t config(uint8_t modem);
817 
818  // common low-level SPI interface
819  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
820  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
821  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
822  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
823  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
824 };
825 
826 #endif
827 
828 #endif
SX128x::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX128x.cpp:1117
-
SX128x::setAccessAddress
int16_t setAccessAddress(uint32_t addr)
Sets BLE access address.
Definition: SX128x.cpp:987
+
1 #if !defined(_RADIOLIB_SX128X_H)
2 #define _RADIOLIB_SX128X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX128X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX128X physical layer properties
13 #define SX128X_FREQUENCY_STEP_SIZE 198.3642578
14 #define SX128X_MAX_PACKET_LENGTH 255
15 #define SX128X_CRYSTAL_FREQ 52.0
16 #define SX128X_DIV_EXPONENT 18
17 
18 // SX128X SPI commands
19 #define SX128X_CMD_NOP 0x00
20 #define SX128X_CMD_GET_STATUS 0xC0
21 #define SX128X_CMD_WRITE_REGISTER 0x18
22 #define SX128X_CMD_READ_REGISTER 0x19
23 #define SX128X_CMD_WRITE_BUFFER 0x1A
24 #define SX128X_CMD_READ_BUFFER 0x1B
25 #define SX128X_CMD_SET_SLEEP 0x84
26 #define SX128X_CMD_SET_STANDBY 0x80
27 #define SX128X_CMD_SET_FS 0xC1
28 #define SX128X_CMD_SET_TX 0x83
29 #define SX128X_CMD_SET_RX 0x82
30 #define SX128X_CMD_SET_RX_DUTY_CYCLE 0x94
31 #define SX128X_CMD_SET_CAD 0xC5
32 #define SX128X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1
33 #define SX128X_CMD_SET_TX_CONTINUOUS_PREAMBLE 0xD2
34 #define SX128X_CMD_SET_PACKET_TYPE 0x8A
35 #define SX128X_CMD_GET_PACKET_TYPE 0x03
36 #define SX128X_CMD_SET_RF_FREQUENCY 0x86
37 #define SX128X_CMD_SET_TX_PARAMS 0x8E
38 #define SX128X_CMD_SET_CAD_PARAMS 0x88
39 #define SX128X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F
40 #define SX128X_CMD_SET_MODULATION_PARAMS 0x8B
41 #define SX128X_CMD_SET_PACKET_PARAMS 0x8C
42 #define SX128X_CMD_GET_RX_BUFFER_STATUS 0x17
43 #define SX128X_CMD_GET_PACKET_STATUS 0x1D
44 #define SX128X_CMD_GET_RSSI_INST 0x1F
45 #define SX128X_CMD_SET_DIO_IRQ_PARAMS 0x8D
46 #define SX128X_CMD_GET_IRQ_STATUS 0x15
47 #define SX128X_CMD_CLEAR_IRQ_STATUS 0x97
48 #define SX128X_CMD_SET_REGULATOR_MODE 0x96
49 #define SX128X_CMD_SET_SAVE_CONTEXT 0xD5
50 #define SX128X_CMD_SET_AUTO_TX 0x98
51 #define SX128X_CMD_SET_AUTO_FS 0x9E
52 #define SX128X_CMD_SET_PERF_COUNTER_MODE 0x9C
53 #define SX128X_CMD_SET_LONG_PREAMBLE 0x9B
54 #define SX128X_CMD_SET_UART_SPEED 0x9D
55 #define SX128X_CMD_SET_RANGING_ROLE 0xA3
56 #define SX128X_CMD_SET_ADVANCED_RANGING 0x9A
57 
58 // SX128X register map
59 #define SX128X_REG_SYNC_WORD_1_BYTE_4 0x09CE
60 #define SX128X_REG_SYNC_WORD_1_BYTE_3 0x09CF
61 #define SX128X_REG_SYNC_WORD_1_BYTE_2 0x09D0
62 #define SX128X_REG_SYNC_WORD_1_BYTE_1 0x09D1
63 #define SX128X_REG_SYNC_WORD_1_BYTE_0 0x09D2
64 #define SX128X_REG_SYNC_WORD_2_BYTE_4 0x09D3
65 #define SX128X_REG_SYNC_WORD_2_BYTE_3 0x09D4
66 #define SX128X_REG_SYNC_WORD_2_BYTE_2 0x09D5
67 #define SX128X_REG_SYNC_WORD_2_BYTE_1 0x09D6
68 #define SX128X_REG_SYNC_WORD_2_BYTE_0 0x09D7
69 #define SX128X_REG_SYNC_WORD_3_BYTE_4 0x09D8
70 #define SX128X_REG_SYNC_WORD_3_BYTE_3 0x09D9
71 #define SX128X_REG_SYNC_WORD_3_BYTE_2 0x09DA
72 #define SX128X_REG_SYNC_WORD_3_BYTE_1 0x09DB
73 #define SX128X_REG_SYNC_WORD_3_BYTE_0 0x09DC
74 #define SX128X_REG_CRC_INITIAL_MSB 0x09C8
75 #define SX128X_REG_CRC_INITIAL_LSB 0x09C9
76 #define SX128X_REG_CRC_POLYNOMIAL_MSB 0x09C6
77 #define SX128X_REG_CRC_POLYNOMIAL_LSB 0x09C7
78 #define SX128X_REG_ACCESS_ADDRESS_BYTE_3 (SX128X_REG_SYNC_WORD_1_BYTE_3)
79 #define SX128X_REG_ACCESS_ADDRESS_BYTE_2 (SX128X_REG_SYNC_WORD_1_BYTE_2)
80 #define SX128X_REG_ACCESS_ADDRESS_BYTE_1 (SX128X_REG_SYNC_WORD_1_BYTE_1)
81 #define SX128X_REG_ACCESS_ADDRESS_BYTE_0 (SX128X_REG_SYNC_WORD_1_BYTE_0)
82 #define SX128X_REG_BLE_CRC_INITIAL_MSB 0x09C7
83 #define SX128X_REG_BLE_CRC_INITIAL_MID (SX128X_REG_CRC_INITIAL_MSB)
84 #define SX128X_REG_BLE_CRC_INITIAL_LSB (SX128X_REG_CRC_INITIAL_LSB)
85 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_3 0x0916
86 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_2 0x0917
87 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_1 0x0918
88 #define SX128X_REG_SLAVE_RANGING_ADDRESS_BYTE_0 0x0919
89 #define SX128X_REG_SLAVE_RANGING_ADDRESS_WIDTH 0x0931
90 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_3 0x0912
91 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_2 0x0913
92 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_1 0x0914
93 #define SX128X_REG_MASTER_RANGING_ADDRESS_BYTE_0 0x0915
94 #define SX128X_REG_RANGING_CALIBRATION_MSB 0x092C
95 #define SX128X_REG_RANGING_CALIBRATION_LSB 0x092D
96 #define SX128X_REG_RANGING_RESULT_MSB 0x0961
97 #define SX128X_REG_RANGING_RESULT_MID 0x0962
98 #define SX128X_REG_RANGING_RESULT_LSB 0x0963
99 #define SX128X_REG_MANUAL_GAIN_CONTROL_ENABLE_1 0x089F
100 #define SX128X_REG_MANUAL_GAIN_CONTROL_ENABLE_2 0x0895
101 #define SX128X_REG_MANUAL_GAIN_SETTING 0x089E
102 #define SX128X_REG_GAIN_MODE 0x0891
103 #define SX128X_REG_LORA_FIXED_PAYLOAD_LENGTH 0x0901
104 #define SX128X_REG_LORA_SF_CONFIG 0x0925
105 #define SX128X_REG_FEI_MSB 0x0954
106 #define SX128X_REG_FEI_MID 0x0955
107 #define SX128X_REG_FEI_LSB 0x0956
108 #define SX128X_REG_RANGING_FILTER_WINDOW_SIZE 0x091E
109 #define SX128X_REG_RANGING_FILTER_RSSI_OFFSET 0x0953
110 #define SX128X_REG_RANGING_FILTER_RESET 0x0923
111 #define SX128X_REG_RANGING_LORA_CLOCK_ENABLE 0x097F
112 #define SX128X_REG_RANGING_TYPE 0x0924
113 #define SX128X_REG_RANGING_ADDRESS_SWITCH 0x0927
114 #define SX128X_REG_RANGING_ADDRESS_MSB 0x095F
115 #define SX128X_REG_RANGING_ADDRESS_LSB 0x0960
116 
117 
118 // SX128X SPI command variables
119 //SX128X_CMD_GET_STATUS MSB LSB DESCRIPTION
120 #define SX128X_STATUS_MODE_STDBY_RC 0b01000000 // 7 5 current chip mode: STDBY_RC
121 #define SX128X_STATUS_MODE_STDBY_XOSC 0b01100000 // 7 5 STDBY_XOSC
122 #define SX128X_STATUS_MODE_FS 0b10000000 // 7 5 FS
123 #define SX128X_STATUS_MODE_RX 0b10100000 // 7 5 Rx
124 #define SX128X_STATUS_MODE_TX 0b11000000 // 7 5 Tx
125 #define SX128X_STATUS_CMD_PROCESSED 0b00000100 // 4 2 command status: processing OK
126 #define SX128X_STATUS_DATA_AVAILABLE 0b00001000 // 4 2 data available
127 #define SX128X_STATUS_CMD_TIMEOUT 0b00001100 // 4 2 timeout
128 #define SX128X_STATUS_CMD_ERROR 0b00010000 // 4 2 processing error
129 #define SX128X_STATUS_CMD_FAILED 0b00010100 // 4 2 failed to execute
130 #define SX128X_STATUS_TX_DONE 0b00011000 // 4 2 transmission finished
131 #define SX128X_STATUS_BUSY 0b00000001 // 0 0 chip busy
132 #define SX128X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed
133 
134 //SX128X_CMD_SET_SLEEP
135 #define SX128X_SLEEP_DATA_BUFFER_FLUSH 0b00000000 // 1 1 data buffer behavior in sleep mode: flush
136 #define SX128X_SLEEP_DATA_BUFFER_RETAIN 0b00000010 // 1 1 retain
137 #define SX128X_SLEEP_DATA_RAM_FLUSH 0b00000000 // 0 0 data RAM (configuration) behavior in sleep mode: flush
138 #define SX128X_SLEEP_DATA_RAM_RETAIN 0b00000001 // 0 0 retain
139 
140 //SX128X_CMD_SET_STANDBY
141 #define SX128X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator
142 #define SX128X_STANDBY_XOSC 0x01 // 7 0 52 MHz crystal oscillator
143 
144 //SX128X_CMD_SET_TX + SX128X_CMD_SET_RX + SX128X_CMD_SET_RX_DUTY_CYCLE
145 #define SX128X_PERIOD_BASE_15_625_US 0x00 // 7 0 time period step: 15.625 us
146 #define SX128X_PERIOD_BASE_62_5_US 0x01 // 7 0 62.5 us
147 #define SX128X_PERIOD_BASE_1_MS 0x02 // 7 0 1 ms
148 #define SX128X_PERIOD_BASE_4_MS 0x03 // 7 0 4 ms
149 
150 //SX128X_CMD_SET_TX
151 #define SX128X_TX_TIMEOUT_NONE 0x0000 // 15 0 Tx timeout duration: no timeout (Tx single mode)
152 
153 //SX128X_CMD_SET_RX
154 #define SX128X_RX_TIMEOUT_NONE 0x0000 // 15 0 Rx timeout duration: no timeout (Rx single mode)
155 #define SX128X_RX_TIMEOUT_INF 0xFFFF // 15 0 infinite (Rx continuous mode)
156 
157 //SX128X_CMD_SET_PACKET_TYPE
158 #define SX128X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: (G)FSK
159 #define SX128X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa
160 #define SX128X_PACKET_TYPE_RANGING 0x02 // 7 0 ranging engine
161 #define SX128X_PACKET_TYPE_FLRC 0x03 // 7 0 FLRC
162 #define SX128X_PACKET_TYPE_BLE 0x04 // 7 0 BLE
163 
164 //SX128X_CMD_SET_TX_PARAMS
165 #define SX128X_PA_RAMP_02_US 0x00 // 7 0 PA ramp time: 2 us
166 #define SX128X_PA_RAMP_04_US 0x20 // 7 0 4 us
167 #define SX128X_PA_RAMP_06_US 0x40 // 7 0 6 us
168 #define SX128X_PA_RAMP_08_US 0x60 // 7 0 8 us
169 #define SX128X_PA_RAMP_10_US 0x80 // 7 0 10 us
170 #define SX128X_PA_RAMP_12_US 0xA0 // 7 0 12 us
171 #define SX128X_PA_RAMP_16_US 0xC0 // 7 0 16 us
172 #define SX128X_PA_RAMP_20_US 0xE0 // 7 0 20 us
173 
174 //SX128X_CMD_SET_CAD_PARAMS
175 #define SX128X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1
176 #define SX128X_CAD_ON_2_SYMB 0x20 // 7 0 2
177 #define SX128X_CAD_ON_4_SYMB 0x40 // 7 0 4
178 #define SX128X_CAD_ON_8_SYMB 0x60 // 7 0 8
179 #define SX128X_CAD_ON_16_SYMB 0x80 // 7 0 16
180 
181 //SX128X_CMD_SET_MODULATION_PARAMS
182 #define SX128X_BLE_GFSK_BR_2_000_BW_2_4 0x04 // 7 0 GFSK/BLE bit rate and bandwidth setting: 2.0 Mbps 2.4 MHz
183 #define SX128X_BLE_GFSK_BR_1_600_BW_2_4 0x28 // 7 0 1.6 Mbps 2.4 MHz
184 #define SX128X_BLE_GFSK_BR_1_000_BW_2_4 0x4C // 7 0 1.0 Mbps 2.4 MHz
185 #define SX128X_BLE_GFSK_BR_1_000_BW_1_2 0x45 // 7 0 1.0 Mbps 1.2 MHz
186 #define SX128X_BLE_GFSK_BR_0_800_BW_2_4 0x70 // 7 0 0.8 Mbps 2.4 MHz
187 #define SX128X_BLE_GFSK_BR_0_800_BW_1_2 0x69 // 7 0 0.8 Mbps 1.2 MHz
188 #define SX128X_BLE_GFSK_BR_0_500_BW_1_2 0x8D // 7 0 0.5 Mbps 1.2 MHz
189 #define SX128X_BLE_GFSK_BR_0_500_BW_0_6 0x86 // 7 0 0.5 Mbps 0.6 MHz
190 #define SX128X_BLE_GFSK_BR_0_400_BW_1_2 0xB1 // 7 0 0.4 Mbps 1.2 MHz
191 #define SX128X_BLE_GFSK_BR_0_400_BW_0_6 0xAA // 7 0 0.4 Mbps 0.6 MHz
192 #define SX128X_BLE_GFSK_BR_0_250_BW_0_6 0xCE // 7 0 0.25 Mbps 0.6 MHz
193 #define SX128X_BLE_GFSK_BR_0_250_BW_0_3 0xC7 // 7 0 0.25 Mbps 0.3 MHz
194 #define SX128X_BLE_GFSK_BR_0_125_BW_0_3 0xEF // 7 0 0.125 Mbps 0.3 MHz
195 #define SX128X_BLE_GFSK_MOD_IND_0_35 0x00 // 7 0 GFSK/BLE modulation index: 0.35
196 #define SX128X_BLE_GFSK_MOD_IND_0_50 0x01 // 7 0 0.50
197 #define SX128X_BLE_GFSK_MOD_IND_0_75 0x02 // 7 0 0.75
198 #define SX128X_BLE_GFSK_MOD_IND_1_00 0x03 // 7 0 1.00
199 #define SX128X_BLE_GFSK_MOD_IND_1_25 0x04 // 7 0 1.25
200 #define SX128X_BLE_GFSK_MOD_IND_1_50 0x05 // 7 0 1.50
201 #define SX128X_BLE_GFSK_MOD_IND_1_75 0x06 // 7 0 1.75
202 #define SX128X_BLE_GFSK_MOD_IND_2_00 0x07 // 7 0 2.00
203 #define SX128X_BLE_GFSK_MOD_IND_2_25 0x08 // 7 0 2.25
204 #define SX128X_BLE_GFSK_MOD_IND_2_50 0x09 // 7 0 2.50
205 #define SX128X_BLE_GFSK_MOD_IND_2_75 0x0A // 7 0 2.75
206 #define SX128X_BLE_GFSK_MOD_IND_3_00 0x0B // 7 0 3.00
207 #define SX128X_BLE_GFSK_MOD_IND_3_25 0x0C // 7 0 3.25
208 #define SX128X_BLE_GFSK_MOD_IND_3_50 0x0D // 7 0 3.50
209 #define SX128X_BLE_GFSK_MOD_IND_3_75 0x0E // 7 0 3.75
210 #define SX128X_BLE_GFSK_MOD_IND_4_00 0x0F // 7 0 4.00
211 #define SX128X_BLE_GFSK_BT_OFF 0x00 // 7 0 GFSK Gaussian filter BT product: filter disabled
212 #define SX128X_BLE_GFSK_BT_1_0 0x10 // 7 0 1.0
213 #define SX128X_BLE_GFSK_BT_0_5 0x20 // 7 0 0.5
214 #define SX128X_FLRC_BR_1_300_BW_1_2 0x45 // 7 0 FLRC bit rate and bandwidth setting: 1.3 Mbps 1.2 MHz
215 #define SX128X_FLRC_BR_1_000_BW_1_2 0x69 // 7 0 1.04 Mbps 1.2 MHz
216 #define SX128X_FLRC_BR_0_650_BW_0_6 0x86 // 7 0 0.65 Mbps 0.6 MHz
217 #define SX128X_FLRC_BR_0_520_BW_0_6 0xAA // 7 0 0.52 Mbps 0.6 MHz
218 #define SX128X_FLRC_BR_0_325_BW_0_3 0xC7 // 7 0 0.325 Mbps 0.3 MHz
219 #define SX128X_FLRC_BR_0_260_BW_0_3 0xEB // 7 0 0.260 Mbps 0.3 MHz
220 #define SX128X_FLRC_CR_1_2 0x00 // 7 0 FLRC coding rate: 1/2
221 #define SX128X_FLRC_CR_3_4 0x02 // 7 0 3/4
222 #define SX128X_FLRC_CR_1_0 0x04 // 7 0 1/1
223 #define SX128X_FLRC_BT_OFF 0x00 // 7 0 FLRC Gaussian filter BT product: filter disabled
224 #define SX128X_FLRC_BT_1_0 0x10 // 7 0 1.0
225 #define SX128X_FLRC_BT_0_5 0x20 // 7 0 0.5
226 #define SX128X_LORA_SF_5 0x50 // 7 0 LoRa spreading factor: 5
227 #define SX128X_LORA_SF_6 0x60 // 7 0 6
228 #define SX128X_LORA_SF_7 0x70 // 7 0 7
229 #define SX128X_LORA_SF_8 0x80 // 7 0 8
230 #define SX128X_LORA_SF_9 0x90 // 7 0 9
231 #define SX128X_LORA_SF_10 0xA0 // 7 0 10
232 #define SX128X_LORA_SF_11 0xB0 // 7 0 11
233 #define SX128X_LORA_SF_12 0xC0 // 7 0 12
234 #define SX128X_LORA_BW_1625_00 0x0A // 7 0 LoRa bandwidth: 1625.0 kHz
235 #define SX128X_LORA_BW_812_50 0x18 // 7 0 812.5 kHz
236 #define SX128X_LORA_BW_406_25 0x26 // 7 0 406.25 kHz
237 #define SX128X_LORA_BW_203_125 0x34 // 7 0 203.125 kHz
238 #define SX128X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5
239 #define SX128X_LORA_CR_4_6 0x02 // 7 0 4/6
240 #define SX128X_LORA_CR_4_7 0x03 // 7 0 4/7
241 #define SX128X_LORA_CR_4_8 0x04 // 7 0 4/8
242 #define SX128X_LORA_CR_4_5_LI 0x05 // 7 0 4/5, long interleaving
243 #define SX128X_LORA_CR_4_6_LI 0x06 // 7 0 4/6, long interleaving
244 #define SX128X_LORA_CR_4_7_LI 0x07 // 7 0 4/7, long interleaving
245 
246 //SX128X_CMD_SET_PACKET_PARAMS
247 #define SX128X_GFSK_FLRC_SYNC_WORD_OFF 0x00 // 7 0 GFSK/FLRC sync word used: none
248 #define SX128X_GFSK_FLRC_SYNC_WORD_1 0x10 // 7 0 sync word 1
249 #define SX128X_GFSK_FLRC_SYNC_WORD_2 0x20 // 7 0 sync word 2
250 #define SX128X_GFSK_FLRC_SYNC_WORD_1_2 0x30 // 7 0 sync words 1 and 2
251 #define SX128X_GFSK_FLRC_SYNC_WORD_3 0x40 // 7 0 sync word 3
252 #define SX128X_GFSK_FLRC_SYNC_WORD_1_3 0x50 // 7 0 sync words 1 and 3
253 #define SX128X_GFSK_FLRC_SYNC_WORD_2_3 0x60 // 7 0 sync words 2 and 3
254 #define SX128X_GFSK_FLRC_SYNC_WORD_1_2_3 0x70 // 7 0 sync words 1, 2 and 3
255 #define SX128X_GFSK_FLRC_PACKET_FIXED 0x00 // 7 0 GFSK/FLRC packet length mode: fixed
256 #define SX128X_GFSK_FLRC_PACKET_VARIABLE 0x20 // 7 0 variable
257 #define SX128X_GFSK_FLRC_CRC_OFF 0x00 // 7 0 GFSK/FLRC packet CRC: none
258 #define SX128X_GFSK_FLRC_CRC_1_BYTE 0x10 // 7 0 1 byte
259 #define SX128X_GFSK_FLRC_CRC_2_BYTE 0x20 // 7 0 2 bytes
260 #define SX128X_GFSK_FLRC_CRC_3_BYTE 0x30 // 7 0 3 bytes (FLRC only)
261 #define SX128X_GFSK_BLE_WHITENING_ON 0x00 // 7 0 GFSK/BLE whitening: enabled
262 #define SX128X_GFSK_BLE_WHITENING_OFF 0x08 // 7 0 disabled
263 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_31 0x00 // 7 0 BLE maximum payload length: 31 bytes
264 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_37 0x20 // 7 0 37 bytes
265 #define SX128X_BLE_PAYLOAD_LENGTH_TEST 0x40 // 7 0 63 bytes (test mode)
266 #define SX128X_BLE_PAYLOAD_LENGTH_MAX_255 0x80 // 7 0 255 bytes (Bluetooth 4.2 and above)
267 #define SX128X_BLE_CRC_OFF 0x00 // 7 0 BLE packet CRC: none
268 #define SX128X_BLE_CRC_3_BYTE 0x10 // 7 0 3 byte
269 #define SX128X_BLE_PRBS_9 0x00 // 7 0 BLE test payload contents: PRNG sequence using x^9 + x^5 + x
270 #define SX128X_BLE_EYELONG 0x04 // 7 0 repeated 0xF0
271 #define SX128X_BLE_EYESHORT 0x08 // 7 0 repeated 0xAA
272 #define SX128X_BLE_PRBS_15 0x0C // 7 0 PRNG sequence using x^15 + x^14 + x^13 + x^12 + x^2 + x + 1
273 #define SX128X_BLE_ALL_1 0x10 // 7 0 repeated 0xFF
274 #define SX128X_BLE_ALL_0 0x14 // 7 0 repeated 0x00
275 #define SX128X_BLE_EYELONG_INV 0x18 // 7 0 repeated 0x0F
276 #define SX128X_BLE_EYESHORT_INV 0x1C // 7 0 repeated 0x55
277 #define SX128X_FLRC_SYNC_WORD_OFF 0x00 // 7 0 FLRC sync word: disabled
278 #define SX128X_FLRC_SYNC_WORD_ON 0x04 // 7 0 enabled
279 #define SX128X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit
280 #define SX128X_LORA_HEADER_IMPLICIT 0x80 // 7 0 implicit
281 #define SX128X_LORA_CRC_OFF 0x00 // 7 0 LoRa packet CRC: disabled
282 #define SX128X_LORA_CRC_ON 0x20 // 7 0 enabled
283 #define SX128X_LORA_IQ_STANDARD 0x40 // 7 0 LoRa IQ: standard
284 #define SX128X_LORA_IQ_INVERTED 0x00 // 7 0 inverted
285 
286 //SX128X_CMD_GET_PACKET_STATUS
287 #define SX128X_PACKET_STATUS_SYNC_ERROR 0b01000000 // 6 6 packet status errors byte: sync word error
288 #define SX128X_PACKET_STATUS_LENGTH_ERROR 0b00100000 // 5 5 packet length error
289 #define SX128X_PACKET_STATUS_CRC_ERROR 0b00010000 // 4 4 CRC error
290 #define SX128X_PACKET_STATUS_ABORT_ERROR 0b00001000 // 3 3 packet reception aborted
291 #define SX128X_PACKET_STATUS_HEADER_RECEIVED 0b00000100 // 2 2 header received
292 #define SX128X_PACKET_STATUS_PACKET_RECEIVED 0b00000010 // 1 1 packet received
293 #define SX128X_PACKET_STATUS_PACKET_CTRL_BUSY 0b00000001 // 0 0 packet controller is busy
294 #define SX128X_PACKET_STATUS_RX_PID 0b11000000 // 7 6 packet status status byte: PID field of the received packet
295 #define SX128X_PACKET_STATUS_NO_ACK 0b00100000 // 5 5 NO_ACK field of the received packet
296 #define SX128X_PACKET_STATUS_RX_PID_ERROR 0b00010000 // 4 4 PID field error
297 #define SX128X_PACKET_STATUS_PACKET_SENT 0b00000001 // 0 0 packet sent
298 #define SX128X_PACKET_STATUS_SYNC_DET_ERROR 0b00000000 // 2 0 packet status sync byte: sync word detection error
299 #define SX128X_PACKET_STATUS_SYNC_DET_1 0b00000001 // 2 0 detected sync word 1
300 #define SX128X_PACKET_STATUS_SYNC_DET_2 0b00000010 // 2 0 detected sync word 2
301 #define SX128X_PACKET_STATUS_SYNC_DET_3 0b00000100 // 2 0 detected sync word 3
302 
303 //SX128X_CMD_SET_DIO_IRQ_PARAMS
304 #define SX128X_IRQ_PREAMBLE_DETECTED 0x8000 // 15 15 interrupt source: preamble detected
305 #define SX128X_IRQ_ADVANCED_RANGING_DONE 0x8000 // 15 15 advanced ranging done
306 #define SX128X_IRQ_RX_TX_TIMEOUT 0x4000 // 14 14 Rx or Tx timeout
307 #define SX128X_IRQ_CAD_DETECTED 0x2000 // 13 13 channel activity detected
308 #define SX128X_IRQ_CAD_DONE 0x1000 // 12 12 CAD finished
309 #define SX128X_IRQ_RANGING_SLAVE_REQ_VALID 0x0800 // 11 11 ranging request valid (slave)
310 #define SX128X_IRQ_RANGING_MASTER_TIMEOUT 0x0400 // 10 10 ranging timeout (master)
311 #define SX128X_IRQ_RANGING_MASTER_RES_VALID 0x0200 // 9 9 ranging result valid (master)
312 #define SX128X_IRQ_RANGING_SLAVE_REQ_DISCARD 0x0100 // 8 8 ranging result valid (master)
313 #define SX128X_IRQ_RANGING_SLAVE_RESP_DONE 0x0080 // 7 7 ranging response complete (slave)
314 #define SX128X_IRQ_CRC_ERROR 0x0040 // 6 6 CRC error
315 #define SX128X_IRQ_HEADER_ERROR 0x0020 // 5 5 header error
316 #define SX128X_IRQ_HEADER_VALID 0x0010 // 4 4 header valid
317 #define SX128X_IRQ_SYNC_WORD_ERROR 0x0008 // 3 3 sync word error
318 #define SX128X_IRQ_SYNC_WORD_VALID 0x0004 // 2 2 sync word valid
319 #define SX128X_IRQ_RX_DONE 0x0002 // 1 1 Rx done
320 #define SX128X_IRQ_TX_DONE 0x0001 // 0 0 Tx done
321 #define SX128X_IRQ_NONE 0x0000 // 15 0 none
322 #define SX128X_IRQ_ALL 0xFFFF // 15 0 all
323 
324 //SX128X_CMD_SET_REGULATOR_MODE
325 #define SX128X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default)
326 #define SX128X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC
327 
328 //SX128X_CMD_SET_RANGING_ROLE
329 #define SX128X_RANGING_ROLE_MASTER 0x01 // 7 0 ranging role: master
330 #define SX128X_RANGING_ROLE_SLAVE 0x00 // 7 0 slave
331 
332 
339 class SX128x: public PhysicalLayer {
340  public:
341  // introduce PhysicalLayer overloads
342  using PhysicalLayer::transmit;
343  using PhysicalLayer::receive;
344  using PhysicalLayer::startTransmit;
345  using PhysicalLayer::readData;
346 
352  SX128x(Module* mod);
353 
354  // basic methods
355 
373  int16_t begin(float freq = 2400.0, float bw = 812.5, uint8_t sf = 9, uint8_t cr = 7, int8_t power = 10, uint16_t preambleLength = 12);
374 
390  int16_t beginGFSK(float freq = 2400.0, uint16_t br = 800, float freqDev = 400.0, int8_t power = 10, uint16_t preambleLength = 16);
391 
407  int16_t beginBLE(float freq = 2400.0, uint16_t br = 800, float freqDev = 400.0, int8_t power = 10, uint8_t dataShaping = RADIOLIB_SHAPING_0_5);
408 
426  int16_t beginFLRC(float freq = 2400.0, uint16_t br = 650, uint8_t cr = 3, int8_t power = 10, uint16_t preambleLength = 16, uint8_t dataShaping = RADIOLIB_SHAPING_0_5);
427 
436  int16_t reset(bool verify = true);
437 
450  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
451 
462  int16_t receive(uint8_t* data, size_t len) override;
463 
471  int16_t transmitDirect(uint32_t frf = 0) override;
472 
479  int16_t receiveDirect() override;
480 
486  int16_t scanChannel();
487 
495  int16_t sleep(bool retainConfig = true);
496 
502  int16_t standby() override;
503 
511  int16_t standby(uint8_t mode);
512 
513  // interrupt methods
514 
520  void setDio1Action(void (*func)(void));
521 
525  void clearDio1Action();
526 
539  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
540 
548  int16_t startReceive(uint16_t timeout = SX128X_RX_TIMEOUT_INF);
549 
559  int16_t readData(uint8_t* data, size_t len) override;
560 
561  // configuration methods
562 
570  int16_t setFrequency(float freq);
571 
579  int16_t setBandwidth(float bw);
580 
588  int16_t setSpreadingFactor(uint8_t sf);
589 
599  int16_t setCodingRate(uint8_t cr, bool longInterleaving = false);
600 
608  int16_t setOutputPower(int8_t power);
609 
617  int16_t setPreambleLength(uint32_t preambleLength);
618 
626  int16_t setBitRate(uint16_t br);
627 
635  int16_t setFrequencyDeviation(float freqDev) override;
636 
645  int16_t setDataShaping(uint8_t sh) override;
646 
656  int16_t setSyncWord(uint8_t* syncWord, uint8_t len);
657 
669  int16_t setCRC(uint8_t len, uint32_t initial = 0x1D0F, uint16_t polynomial = 0x1021);
670 
678  int16_t setWhitening(bool enabled);
679 
687  int16_t setAccessAddress(uint32_t addr);
688 
694  float getRSSI();
695 
701  float getSNR();
702 
710  size_t getPacketLength(bool update = true) override;
711 
719  uint32_t getTimeOnAir(size_t len);
720 
726  int16_t implicitHeader(size_t len);
727 
735  int16_t explicitHeader();
736 
744  int16_t setEncoding(uint8_t encoding) override;
745 
754  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
755 
761  uint8_t random();
762 
763 #ifndef RADIOLIB_GODMODE
764  protected:
765 #endif
766  Module* _mod;
767 
768  // cached LoRa parameters
769  float _bwKhz = 0;
770  uint8_t _bw = 0, _sf = 0, _cr = 0;
771  uint8_t _preambleLengthLoRa = 0, _headerType = 0, _payloadLen = 0, _crcLoRa = 0;
772 
773  // SX128x SPI command implementations
774  uint8_t getStatus();
775  int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
776  int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
777  int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
778  int16_t readBuffer(uint8_t* data, uint8_t numBytes);
779  int16_t setTx(uint16_t periodBaseCount = SX128X_TX_TIMEOUT_NONE, uint8_t periodBase = SX128X_PERIOD_BASE_15_625_US);
780  int16_t setRx(uint16_t periodBaseCount, uint8_t periodBase = SX128X_PERIOD_BASE_15_625_US);
781  int16_t setCad();
782  uint8_t getPacketType();
783  int16_t setRfFrequency(uint32_t frf);
784  int16_t setTxParams(uint8_t power, uint8_t rampTime = SX128X_PA_RAMP_10_US);
785  int16_t setBufferBaseAddress(uint8_t txBaseAddress = 0x00, uint8_t rxBaseAddress = 0x00);
786  int16_t setModulationParams(uint8_t modParam1, uint8_t modParam2, uint8_t modParam3);
787  int16_t setPacketParamsGFSK(uint8_t preambleLen, uint8_t syncWordLen, uint8_t syncWordMatch, uint8_t crcLen, uint8_t whitening, uint8_t payloadLen = 0xFF, uint8_t headerType = SX128X_GFSK_FLRC_PACKET_VARIABLE);
788  int16_t setPacketParamsBLE(uint8_t connState, uint8_t crcLen, uint8_t bleTestPayload, uint8_t whitening);
789  int16_t setPacketParamsLoRa(uint8_t preambleLen, uint8_t headerType, uint8_t payloadLen, uint8_t crc, uint8_t invertIQ = SX128X_LORA_IQ_STANDARD);
790  int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX128X_IRQ_NONE, uint16_t dio3Mask = SX128X_IRQ_NONE);
791  uint16_t getIrqStatus();
792  int16_t clearIrqStatus(uint16_t clearIrqParams = SX128X_IRQ_ALL);
793  int16_t setRangingRole(uint8_t role);
794  int16_t setPacketType(uint8_t type);
795 
796  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
797 
798 #ifndef RADIOLIB_GODMODE
799  private:
800 #endif
801  // common parameters
802  uint8_t _pwr = 0;
803 
804  // cached GFSK parameters
805  float _modIndexReal = 0;
806  uint16_t _brKbps = 0;
807  uint8_t _br = 0, _modIndex = 0, _shaping = 0;
808  uint8_t _preambleLengthGFSK = 0, _syncWordLen = 0, _syncWordMatch = 0, _crcGFSK = 0, _whitening = 0;
809 
810  // cached FLRC parameters
811  uint8_t _crFLRC = 0;
812 
813  // cached BLE parameters
814  uint8_t _connectionState = 0, _crcBLE = 0, _bleTestPayload = 0;
815 
816  int16_t config(uint8_t modem);
817 
818  // common low-level SPI interface
819  int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
820  int16_t SPIwriteCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
821  int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
822  int16_t SPIreadCommand(uint8_t* cmd, uint8_t cmdLen, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
823  int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy, uint32_t timeout = 5000);
824 };
825 
826 #endif
827 
828 #endif
SX128x::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX128x.cpp:1123
+
SX128x::setAccessAddress
int16_t setAccessAddress(uint32_t addr)
Sets BLE access address.
Definition: SX128x.cpp:993
SX128x::receive
int16_t receive(uint8_t *data, size_t len) override
Blocking binary receive method. Overloads for string-based transmissions are implemented in PhysicalL...
Definition: SX128x.cpp:312
SX128x::standby
int16_t standby() override
Sets the module to standby mode (overload for PhysicalLayer compatibility, uses 13 MHz RC oscillator)...
Definition: SX128x.cpp:434
SX128x::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: SX128x.cpp:450
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
RADIOLIB_SHAPING_0_5
#define RADIOLIB_SHAPING_0_5
Gaussin shaping filter, BT = 0.5.
Definition: TypeDef.h:110
SX128x::sleep
int16_t sleep(bool retainConfig=true)
Sets the module to sleep mode.
Definition: SX128x.cpp:418
-
SX128x::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX128x.cpp:1113
-
SX128x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Serves only as alias for PhysicalLayer compatibility. ...
Definition: SX128x.cpp:1121
+
SX128x::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX128x.cpp:1119
+
SX128x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Serves only as alias for PhysicalLayer compatibility. ...
Definition: SX128x.cpp:1127
SX128x::reset
int16_t reset(bool verify=true)
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX128x.cpp:231
-
SX128x::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, uint8_t len)
Sets FSK/FLRC sync word in the form of array of up to 5 bytes (FSK). For FLRC modem, the sync word must be exactly 4 bytes long.
Definition: SX128x.cpp:855
+
SX128x::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, uint8_t len)
Sets FSK/FLRC sync word in the form of array of up to 5 bytes (FSK). For FLRC modem, the sync word must be exactly 4 bytes long.
Definition: SX128x.cpp:861
SX128x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: SX128x.cpp:264
-
SX128x::getSNR
float getSNR()
Gets SNR (Signal to Noise Ratio) of the last received packet. Only available for LoRa or ranging mode...
Definition: SX128x.cpp:1022
+
SX128x::getSNR
float getSNR()
Gets SNR (Signal to Noise Ratio) of the last received packet. Only available for LoRa or ranging mode...
Definition: SX128x.cpp:1028
SX128x::setBitRate
int16_t setBitRate(uint16_t br)
Sets FSK or FLRC bit rate. Allowed values are 125, 250, 400, 500, 800, 1000, 1600 and 2000 kbps (for ...
Definition: SX128x.cpp:741
-
SX128x::getTimeOnAir
uint32_t getTimeOnAir(size_t len)
Get expected time-on-air for a given size of payload.
Definition: SX128x.cpp:1049
+
SX128x::getTimeOnAir
uint32_t getTimeOnAir(size_t len)
Get expected time-on-air for a given size of payload.
Definition: SX128x.cpp:1055
SX128x::beginGFSK
int16_t beginGFSK(float freq=2400.0, uint16_t br=800, float freqDev=400.0, int8_t power=10, uint16_t preambleLength=16)
Initialization method for GFSK modem.
Definition: SX128x.cpp:60
-
SX128x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX128x.cpp:1042
+
SX128x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX128x.cpp:1048
SX128x::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa spreading factor. Allowed values range from 5 to 12.
Definition: SX128x.cpp:625
-
SX128x::setWhitening
int16_t setWhitening(bool enabled)
Sets whitening parameters, not available for LoRa or FLRC modem.
Definition: SX128x.cpp:967
-
SX128x::random
uint8_t random()
Dummy random method, to ensure PhysicalLayer compatibility.
Definition: SX128x.cpp:1129
+
SX128x::setWhitening
int16_t setWhitening(bool enabled)
Sets whitening parameters, not available for LoRa or FLRC modem.
Definition: SX128x.cpp:973
+
SX128x::random
uint8_t random()
Dummy random method, to ensure PhysicalLayer compatibility.
Definition: SX128x.cpp:1135
SX128x::setBandwidth
int16_t setBandwidth(float bw)
Sets LoRa bandwidth. Allowed values are 203.125, 406.25, 812.5 and 1625.0 kHz.
Definition: SX128x.cpp:595
-
SX128x::setCRC
int16_t setCRC(uint8_t len, uint32_t initial=0x1D0F, uint16_t polynomial=0x1021)
Sets CRC configuration.
Definition: SX128x.cpp:903
+
SX128x::setCRC
int16_t setCRC(uint8_t len, uint32_t initial=0x1D0F, uint16_t polynomial=0x1021)
Sets CRC configuration.
Definition: SX128x.cpp:909
SX128x::receiveDirect
int16_t receiveDirect() override
Starts direct mode reception. Only implemented for PhysicalLayer compatibility, as SX128x series does...
Definition: SX128x.cpp:365
-
SX128x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX128x.cpp:1125
+
SX128x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX128x.cpp:1131
SX128x::setDio1Action
void setDio1Action(void(*func)(void))
Sets interrupt service routine to call when DIO1 activates.
Definition: SX128x.cpp:446
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
@@ -120,13 +120,13 @@ $(document).ready(function(){initNavTree('_s_x128x_8h_source.html','');});
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
SX128x::scanChannel
int16_t scanChannel()
Performs scan for LoRa transmission in the current channel. Detects both preamble and payload...
Definition: SX128x.cpp:373
SX128x::SX128x
SX128x(Module *mod)
Default constructor.
Definition: SX128x.cpp:4
-
SX128x::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: SX128x.cpp:998
+
SX128x::getRSSI
float getRSSI()
Gets RSSI (Recorded Signal Strength Indicator) of the last received packet.
Definition: SX128x.cpp:1004
SX128x::setPreambleLength
int16_t setPreambleLength(uint32_t preambleLength)
Sets preamble length for currently active modem. Allowed values range from 1 to 65535.
Definition: SX128x.cpp:693
SX128x::setCodingRate
int16_t setCodingRate(uint8_t cr, bool longInterleaving=false)
Sets LoRa coding rate denominator. Allowed values range from 5 to 8.
Definition: SX128x.cpp:659
SX128x::beginFLRC
int16_t beginFLRC(float freq=2400.0, uint16_t br=650, uint8_t cr=3, int8_t power=10, uint16_t preambleLength=16, uint8_t dataShaping=RADIOLIB_SHAPING_0_5)
Initialization method for FLRC modem.
Definition: SX128x.cpp:172
SX128x::begin
int16_t begin(float freq=2400.0, float bw=812.5, uint8_t sf=9, uint8_t cr=7, int8_t power=10, uint16_t preambleLength=12)
Initialization method for LoRa modem.
Definition: SX128x.cpp:8
SX128x::startReceive
int16_t startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)
Interrupt-driven receive method. DIO1 will be activated when full packet is received.
Definition: SX128x.cpp:518
-
SX128x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets time-bandwidth product of Gaussian filter applied for shaping. Allowed values are RADIOLIB_SHAPI...
Definition: SX128x.cpp:825
+
SX128x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets time-bandwidth product of Gaussian filter applied for shaping. Allowed values are RADIOLIB_SHAPI...
Definition: SX128x.cpp:831
SX128x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation. Allowed values range from 0.0 to 3200.0 kHz.
Definition: SX128x.cpp:798
SX128x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Starts direct mode transmission.
Definition: SX128x.cpp:350
SX128x::setOutputPower
int16_t setOutputPower(int8_t power)
Sets output power. Allowed values are in range from -18 to 13 dBm.
Definition: SX128x.cpp:687
diff --git a/_si443x_8h_source.html b/_si443x_8h_source.html index 2a9c276f..ce3c5f09 100644 --- a/_si443x_8h_source.html +++ b/_si443x_8h_source.html @@ -84,20 +84,20 @@ $(document).ready(function(){initNavTree('_si443x_8h_source.html','');});
Si443x.h
-
1 #if !defined(_RADIOLIB_SI443X_H)
2 #define _RADIOLIB_SI443X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SI443X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // Si443x physical layer properties
13 #define SI443X_FREQUENCY_STEP_SIZE 156.25
14 #define SI443X_MAX_PACKET_LENGTH 64
15 
16 // Si443x series common registers
17 #define SI443X_REG_DEVICE_TYPE 0x00
18 #define SI443X_REG_DEVICE_VERSION 0x01
19 #define SI443X_REG_DEVICE_STATUS 0x02
20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03
21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04
22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05
23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06
24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07
25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08
26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09
27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A
28 #define SI443X_REG_GPIO0_CONFIG 0x0B
29 #define SI443X_REG_GPIO1_CONFIG 0x0C
30 #define SI443X_REG_GPIO2_CONFIG 0x0D
31 #define SI443X_REG_IO_PORT_CONFIG 0x0E
32 #define SI443X_REG_ADC_CONFIG 0x0F
33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10
34 #define SI443X_REG_ADC_VALUE 0x11
35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12
36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13
37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14
38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15
39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16
40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17
41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18
42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19
43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A
44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B
45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C
46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D
47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E
48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F
49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20
50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21
51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22
52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23
53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24
54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25
55 #define SI443X_REG_RSSI 0x26
56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27
57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28
58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29
59 #define SI443X_REG_AFC_LIMITER 0x2A
60 #define SI443X_REG_AFC_CORRECTION 0x2B
61 #define SI443X_REG_OOK_COUNTER_1 0x2C
62 #define SI443X_REG_OOK_COUNTER_2 0x2D
63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E
64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30
65 #define SI443X_REG_EZMAC_STATUS 0x31
66 #define SI443X_REG_HEADER_CONTROL_1 0x32
67 #define SI443X_REG_HEADER_CONTROL_2 0x33
68 #define SI443X_REG_PREAMBLE_LENGTH 0x34
69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35
70 #define SI443X_REG_SYNC_WORD_3 0x36
71 #define SI443X_REG_SYNC_WORD_2 0x37
72 #define SI443X_REG_SYNC_WORD_1 0x38
73 #define SI443X_REG_SYNC_WORD_0 0x39
74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A
75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B
76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C
77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D
78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E
79 #define SI443X_REG_CHECK_HEADER_3 0x3F
80 #define SI443X_REG_CHECK_HEADER_2 0x40
81 #define SI443X_REG_CHECK_HEADER_1 0x41
82 #define SI443X_REG_CHECK_HEADER_0 0x42
83 #define SI443X_REG_HEADER_ENABLE_3 0x43
84 #define SI443X_REG_HEADER_ENABLE_2 0x44
85 #define SI443X_REG_HEADER_ENABLE_1 0x45
86 #define SI443X_REG_HEADER_ENABLE_0 0x46
87 #define SI443X_REG_RECEIVED_HEADER_3 0x47
88 #define SI443X_REG_RECEIVED_HEADER_2 0x48
89 #define SI443X_REG_RECEIVED_HEADER_1 0x49
90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A
91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B
92 #define SI443X_REG_ADC8_CONTROL 0x4F
93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60
94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62
95 #define SI443X_REG_AGC_OVERRIDE_1 0x69
96 #define SI443X_REG_TX_POWER 0x6D
97 #define SI443X_REG_TX_DATA_RATE_1 0x6E
98 #define SI443X_REG_TX_DATA_RATE_0 0x6F
99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70
100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71
101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72
102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73
103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74
104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75
105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76
106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77
107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79
108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A
109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C
110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D
111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E
112 #define SI443X_REG_FIFO_ACCESS 0x7F
113 
114 // SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION
115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register
116 
117 // SI443X_REG_DEVICE_VERSION
118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register
119 
120 // SI443X_REG_DEVICE_STATUS
121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag
122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag
123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag
124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag
125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range)
126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx
127 #define SI443X_RX 0b00000001 // 1 0 Rx
128 #define SI443X_IDLE 0b00000000 // 1 0 idle
129 
130 // SI443X_REG_INTERRUPT_STATUS_1
131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow
132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full
133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty
134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full
135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx
136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done
137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received
138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed
139 
140 // SI443X_REG_INTERRUPT_STATUS_2
141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected
142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected
143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected
144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold
145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired
146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected
147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected
148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected
149 
150 // SI443X_REG_INTERRUPT_ENABLE_1
151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled
152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled
153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled
154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled
155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled
156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled
157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled
158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled
159 
160 // SI443X_REG_INTERRUPT_ENABLE_2
161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled
162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled
163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled
164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled
165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled
166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled
167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled
168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled
169 
170 // SI443X_REG_OP_FUNC_CONTROL_1
171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values
172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection
173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer
174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default)
175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator
176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode
177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode
178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode)
179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode)
180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode)
181 
182 // SI443X_REG_OP_FUNC_CONTROL_2
183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default)
184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low
185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high
186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high
187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low
188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high
189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low
190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high
191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default)
192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled
193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default)
194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled
195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default)
196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled
197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first)
198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second)
199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first)
200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second)
201 
202 // SI443X_REG_XOSC_LOAD_CAPACITANCE
203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration:
204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT
205 
206 // SI443X_REG_MCU_OUTPUT_CLOCK
207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default)
208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128
209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256
210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512
211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default)
212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled
213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz
214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz
215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz
216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz
217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz
218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz
219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default)
220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz
221 
222 // SI443X_REG_GPIO0_CONFIG + SI443X_REG_GPIO1_CONFIG + SI443X_REG_GPIO2_CONFIG
223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive)
224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default)
225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled
226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default)
227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default)
228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default)
229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output
230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output
231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output
232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge
233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge
234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change
235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input
236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input
237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input
238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input
239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output
240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output
241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output
242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output
243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode
244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode
245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input
246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output
247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output
248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output
249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output
250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output
251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1
252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2
253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output
254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output
255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output
256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output
257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD
258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND
259 
260 // SI443X_REG_IO_PORT_CONFIG
261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2
262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1
263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0
264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default)
265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled
266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2
267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1
268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0
269 
270 // SI443X_REG_ADC_CONFIG
271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement
272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress
273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done
274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default)
275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0
276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1
277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2
278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-)
279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-)
280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-)
281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND
282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default)
283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3
284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2
285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain
286 
287 // SI443X_REG_ADC_SENSOR_AMP_OFFSET
288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset
289 
290 // SI443X_REG_TEMP_SENSOR_CONTROL
291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default)
292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution
293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution
294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution
295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled
296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default)
297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default)
298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled
299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value
300 
301 // SI443X_REG_WAKEUP_TIMER_PERIOD_1
302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent
303 
304 // SI443X_REG_WAKEUP_TIMER_PERIOD_2 + SI443X_REG_WAKEUP_TIMER_PERIOD_3
305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value:
306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
307 
308 // SI443X_REG_LOW_DC_MODE_DURATION
309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
310 
311 // SI443X_REG_LOW_BATT_DET_THRESHOLD
312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V)
313 
314 // SI443X_REG_IF_FILTER_BANDWIDTH
315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default)
316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled
317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate
318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection
319 
320 // SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE
321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default)
322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled
323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled
324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default)
325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting
326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default)
327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB
328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb
329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default)
330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default)
331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases
332 
333 // SI443X_REG_AFC_TIMING_CONTROL
334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching
335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction
336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time
337 
338 // SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE
339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value
340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value
341 
342 // SI443X_REG_CLOCK_REC_OVERSAMP_RATIO
343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit
344 
345 // SI443X_REG_CLOCK_REC_OFFSET_2
346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit
347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold
348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB
349 
350 // SI443X_REG_CLOCK_REC_OFFSET_1
351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID
352 
353 // SI443X_REG_CLOCK_REC_OFFSET_0
354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB
355 
356 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1
357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default)
358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled
359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default)
360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled
361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB
362 
363 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0
364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB
365 
366 // SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD
367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold
368 
369 // SI443X_REG_AFC_LIMITER
370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value
371 
372 // SI443X_REG_OOK_COUNTER_1
373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default)
374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled
375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled
376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default)
377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled
378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default)
379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB
380 
381 // SI443X_REG_OOK_COUNTER_2
382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB
383 
384 // SI443X_REG_SLICER_PEAK_HOLD
385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time
386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time
387 
388 // SI443X_REG_DATA_ACCESS_CONTROL
389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled
390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default)
391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default)
392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled
393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default)
394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled
395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default)
396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled
397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled
398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default)
399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled
400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default)
401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT
402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default)
403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16
404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva
405 
406 // SI443X_REG_EZMAC_STATUS
407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones
408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet
409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet
410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received
411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed
412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet
413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent
414 
415 // SI443X_REG_HEADER_CONTROL_1
416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default)
417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0
418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1
419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2
420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3
421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none
422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0
423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1
424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default)
425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default)
426 
427 // SI443X_REG_HEADER_CONTROL_2
428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default)
429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled
430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none
431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3
432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2
433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default)
434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0
435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default)
436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled
437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3
438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default)
439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1
440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0
441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB
442 
443 // SI443X_REG_PREAMBLE_LENGTH
444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits
445 
446 // SI443X_REG_PREAMBLE_DET_CONTROL
447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits
448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB
449 
450 // SI443X_REG_SYNC_WORD_3 - SI443X_REG_SYNC_WORD_0
451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB)
452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte
453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte
454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB)
455 
456 // SI443X_REG_CHANNEL_FILTER_COEFF
457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles
458 
459 // SI443X_REG_XOSC_CONTROL_TEST
460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power
461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready
462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune
463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx
464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx
465 
466 // SI443X_REG_AGC_OVERRIDE_1
467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default)
468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled
469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled
470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default)
471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default)
472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB
473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB
474 
475 // SI443X_REG_TX_POWER
476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled
477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default)
478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max
479 
480 // SI443X_REG_TX_DATA_RATE_1 + SI443X_REG_TX_DATA_RATE_0
481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or
482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps)
483 
484 // SI443X_REG_MODULATION_MODE_CONTROL_1
485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default)
486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps
487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default)
488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled
489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low
490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default)
491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled
492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default)
493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default)
494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled
495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default)
496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled
497 
498 // SI443X_REG_MODULATION_MODE_CONTROL_2
499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default)
500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin
501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin
502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin
503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default)
504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin
505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO
506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal
507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default)
508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled
509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB
510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default)
511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK
512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK
513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK
514 
515 // SI443X_REG_FREQUENCY_DEVIATION
516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz
517 
518 // SI443X_REG_FREQUENCY_OFFSET_1 + SI443X_REG_FREQUENCY_OFFSET_2
519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset:
520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz
521 
522 // SI443X_REG_FREQUENCY_BAND_SELECT
523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default)
524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency
525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz
526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default)
527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select
528 
529 // SI443X_REG_NOM_CARRIER_FREQUENCY_1 + SI443X_REG_NOM_CARRIER_FREQUENCY_0
530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency:
531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz]
532 
533 // SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL
534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number
535 
536 // SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE
537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size
538 
539 // SI443X_REG_TX_FIFO_CONTROL_1
540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold
541 
542 // SI443X_REG_TX_FIFO_CONTROL_2
543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold
544 
545 // SI443X_REG_RX_FIFO_CONTROL
546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold
547 
554 class Si443x: public PhysicalLayer {
555  public:
556  // introduce PhysicalLayer overloads
557  using PhysicalLayer::transmit;
558  using PhysicalLayer::receive;
559  using PhysicalLayer::startTransmit;
560  using PhysicalLayer::readData;
561 
562  // constructor
563 
569  Si443x(Module* mod);
570 
571  // basic methods
572 
586  int16_t begin(float br, float freqDev, float rxBw, uint8_t preambleLen);
587 
591  void reset();
592 
605  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
606 
617  int16_t receive(uint8_t* data, size_t len) override;
618 
625  int16_t sleep();
626 
632  int16_t standby() override;
633 
641  int16_t transmitDirect(uint32_t frf = 0) override;
642 
648  int16_t receiveDirect() override;
649 
655  int16_t packetMode();
656 
657  // interrupt methods
658 
664  void setIrqAction(void (*func)(void));
665 
669  void clearIrqAction();
670 
682  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
683 
689  int16_t startReceive();
690 
700  int16_t readData(uint8_t* data, size_t len) override;
701 
702  // configuration methods
703 
711  int16_t setBitRate(float br);
712 
720  int16_t setFrequencyDeviation(float freqDev) override;
721 
729  int16_t setRxBandwidth(float rxBw);
730 
738  int16_t setSyncWord(uint8_t* syncWord, size_t len);
739 
747  int16_t setPreambleLength(uint8_t preambleLen);
748 
756  size_t getPacketLength(bool update = true) override;
757 
766  int16_t setEncoding(uint8_t encoding) override;
767 
776  int16_t setDataShaping(uint8_t sh) override;
777 
786  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
787 
793  uint8_t random();
794 
800  int16_t getChipVersion();
801 
802 #ifndef RADIOLIB_GODMODE
803  protected:
804 #endif
805  Module* _mod;
806 
807  float _br = 0;
808  float _freqDev = 0;
809  float _freq = 0;
810 
811  size_t _packetLength = 0;
812  bool _packetLengthQueried = false;
813 
814  int16_t setFrequencyRaw(float newFreq);
815 
816 #ifndef RADIOLIB_GODMODE
817  private:
818 #endif
819  bool findChip();
820  void clearIRQFlags();
821  int16_t config();
822  int16_t updateClockRecovery();
823  int16_t directMode();
824 };
825 
826 #endif
827 
828 #endif
Si443x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:364
+
1 #if !defined(_RADIOLIB_SI443X_H)
2 #define _RADIOLIB_SI443X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SI443X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // Si443x physical layer properties
13 #define SI443X_FREQUENCY_STEP_SIZE 156.25
14 #define SI443X_MAX_PACKET_LENGTH 64
15 
16 // Si443x series common registers
17 #define SI443X_REG_DEVICE_TYPE 0x00
18 #define SI443X_REG_DEVICE_VERSION 0x01
19 #define SI443X_REG_DEVICE_STATUS 0x02
20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03
21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04
22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05
23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06
24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07
25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08
26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09
27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A
28 #define SI443X_REG_GPIO0_CONFIG 0x0B
29 #define SI443X_REG_GPIO1_CONFIG 0x0C
30 #define SI443X_REG_GPIO2_CONFIG 0x0D
31 #define SI443X_REG_IO_PORT_CONFIG 0x0E
32 #define SI443X_REG_ADC_CONFIG 0x0F
33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10
34 #define SI443X_REG_ADC_VALUE 0x11
35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12
36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13
37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14
38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15
39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16
40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17
41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18
42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19
43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A
44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B
45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C
46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D
47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E
48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F
49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20
50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21
51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22
52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23
53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24
54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25
55 #define SI443X_REG_RSSI 0x26
56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27
57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28
58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29
59 #define SI443X_REG_AFC_LIMITER 0x2A
60 #define SI443X_REG_AFC_CORRECTION 0x2B
61 #define SI443X_REG_OOK_COUNTER_1 0x2C
62 #define SI443X_REG_OOK_COUNTER_2 0x2D
63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E
64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30
65 #define SI443X_REG_EZMAC_STATUS 0x31
66 #define SI443X_REG_HEADER_CONTROL_1 0x32
67 #define SI443X_REG_HEADER_CONTROL_2 0x33
68 #define SI443X_REG_PREAMBLE_LENGTH 0x34
69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35
70 #define SI443X_REG_SYNC_WORD_3 0x36
71 #define SI443X_REG_SYNC_WORD_2 0x37
72 #define SI443X_REG_SYNC_WORD_1 0x38
73 #define SI443X_REG_SYNC_WORD_0 0x39
74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A
75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B
76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C
77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D
78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E
79 #define SI443X_REG_CHECK_HEADER_3 0x3F
80 #define SI443X_REG_CHECK_HEADER_2 0x40
81 #define SI443X_REG_CHECK_HEADER_1 0x41
82 #define SI443X_REG_CHECK_HEADER_0 0x42
83 #define SI443X_REG_HEADER_ENABLE_3 0x43
84 #define SI443X_REG_HEADER_ENABLE_2 0x44
85 #define SI443X_REG_HEADER_ENABLE_1 0x45
86 #define SI443X_REG_HEADER_ENABLE_0 0x46
87 #define SI443X_REG_RECEIVED_HEADER_3 0x47
88 #define SI443X_REG_RECEIVED_HEADER_2 0x48
89 #define SI443X_REG_RECEIVED_HEADER_1 0x49
90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A
91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B
92 #define SI443X_REG_ADC8_CONTROL 0x4F
93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60
94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62
95 #define SI443X_REG_AGC_OVERRIDE_1 0x69
96 #define SI443X_REG_TX_POWER 0x6D
97 #define SI443X_REG_TX_DATA_RATE_1 0x6E
98 #define SI443X_REG_TX_DATA_RATE_0 0x6F
99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70
100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71
101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72
102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73
103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74
104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75
105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76
106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77
107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79
108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A
109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C
110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D
111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E
112 #define SI443X_REG_FIFO_ACCESS 0x7F
113 
114 // SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION
115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register
116 
117 // SI443X_REG_DEVICE_VERSION
118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register
119 
120 // SI443X_REG_DEVICE_STATUS
121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag
122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag
123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag
124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag
125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range)
126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx
127 #define SI443X_RX 0b00000001 // 1 0 Rx
128 #define SI443X_IDLE 0b00000000 // 1 0 idle
129 
130 // SI443X_REG_INTERRUPT_STATUS_1
131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow
132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full
133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty
134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full
135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx
136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done
137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received
138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed
139 
140 // SI443X_REG_INTERRUPT_STATUS_2
141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected
142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected
143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected
144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold
145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired
146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected
147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected
148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected
149 
150 // SI443X_REG_INTERRUPT_ENABLE_1
151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled
152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled
153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled
154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled
155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled
156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled
157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled
158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled
159 
160 // SI443X_REG_INTERRUPT_ENABLE_2
161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled
162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled
163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled
164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled
165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled
166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled
167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled
168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled
169 
170 // SI443X_REG_OP_FUNC_CONTROL_1
171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values
172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection
173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer
174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default)
175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator
176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode
177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode
178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode)
179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode)
180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode)
181 
182 // SI443X_REG_OP_FUNC_CONTROL_2
183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default)
184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low
185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high
186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high
187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low
188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high
189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low
190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high
191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default)
192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled
193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default)
194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled
195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default)
196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled
197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first)
198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second)
199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first)
200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second)
201 
202 // SI443X_REG_XOSC_LOAD_CAPACITANCE
203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration:
204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT
205 
206 // SI443X_REG_MCU_OUTPUT_CLOCK
207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default)
208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128
209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256
210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512
211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default)
212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled
213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz
214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz
215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz
216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz
217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz
218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz
219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default)
220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz
221 
222 // SI443X_REG_GPIO0_CONFIG + SI443X_REG_GPIO1_CONFIG + SI443X_REG_GPIO2_CONFIG
223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive)
224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default)
225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled
226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default)
227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default)
228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default)
229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output
230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output
231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output
232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge
233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge
234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change
235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input
236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input
237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input
238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input
239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output
240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output
241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output
242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output
243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode
244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode
245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input
246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output
247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output
248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output
249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output
250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output
251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1
252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2
253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output
254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output
255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output
256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output
257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD
258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND
259 
260 // SI443X_REG_IO_PORT_CONFIG
261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2
262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1
263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0
264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default)
265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled
266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2
267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1
268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0
269 
270 // SI443X_REG_ADC_CONFIG
271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement
272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress
273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done
274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default)
275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0
276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1
277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2
278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-)
279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-)
280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-)
281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND
282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default)
283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3
284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2
285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain
286 
287 // SI443X_REG_ADC_SENSOR_AMP_OFFSET
288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset
289 
290 // SI443X_REG_TEMP_SENSOR_CONTROL
291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default)
292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution
293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution
294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution
295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled
296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default)
297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default)
298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled
299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value
300 
301 // SI443X_REG_WAKEUP_TIMER_PERIOD_1
302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent
303 
304 // SI443X_REG_WAKEUP_TIMER_PERIOD_2 + SI443X_REG_WAKEUP_TIMER_PERIOD_3
305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value:
306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
307 
308 // SI443X_REG_LOW_DC_MODE_DURATION
309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
310 
311 // SI443X_REG_LOW_BATT_DET_THRESHOLD
312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V)
313 
314 // SI443X_REG_IF_FILTER_BANDWIDTH
315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default)
316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled
317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate
318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection
319 
320 // SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE
321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default)
322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled
323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled
324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default)
325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting
326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default)
327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB
328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb
329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default)
330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default)
331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases
332 
333 // SI443X_REG_AFC_TIMING_CONTROL
334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching
335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction
336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time
337 
338 // SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE
339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value
340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value
341 
342 // SI443X_REG_CLOCK_REC_OVERSAMP_RATIO
343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit
344 
345 // SI443X_REG_CLOCK_REC_OFFSET_2
346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit
347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold
348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB
349 
350 // SI443X_REG_CLOCK_REC_OFFSET_1
351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID
352 
353 // SI443X_REG_CLOCK_REC_OFFSET_0
354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB
355 
356 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1
357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default)
358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled
359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default)
360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled
361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB
362 
363 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0
364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB
365 
366 // SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD
367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold
368 
369 // SI443X_REG_AFC_LIMITER
370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value
371 
372 // SI443X_REG_OOK_COUNTER_1
373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default)
374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled
375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled
376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default)
377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled
378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default)
379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB
380 
381 // SI443X_REG_OOK_COUNTER_2
382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB
383 
384 // SI443X_REG_SLICER_PEAK_HOLD
385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time
386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time
387 
388 // SI443X_REG_DATA_ACCESS_CONTROL
389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled
390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default)
391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default)
392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled
393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default)
394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled
395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default)
396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled
397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled
398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default)
399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled
400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default)
401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT
402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default)
403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16
404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva
405 
406 // SI443X_REG_EZMAC_STATUS
407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones
408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet
409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet
410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received
411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed
412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet
413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent
414 
415 // SI443X_REG_HEADER_CONTROL_1
416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default)
417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0
418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1
419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2
420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3
421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none
422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0
423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1
424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default)
425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default)
426 
427 // SI443X_REG_HEADER_CONTROL_2
428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default)
429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled
430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none
431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3
432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2
433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default)
434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0
435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default)
436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled
437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3
438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default)
439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1
440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0
441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB
442 
443 // SI443X_REG_PREAMBLE_LENGTH
444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits
445 
446 // SI443X_REG_PREAMBLE_DET_CONTROL
447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits
448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB
449 
450 // SI443X_REG_SYNC_WORD_3 - SI443X_REG_SYNC_WORD_0
451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB)
452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte
453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte
454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB)
455 
456 // SI443X_REG_CHANNEL_FILTER_COEFF
457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles
458 
459 // SI443X_REG_XOSC_CONTROL_TEST
460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power
461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready
462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune
463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx
464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx
465 
466 // SI443X_REG_AGC_OVERRIDE_1
467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default)
468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled
469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled
470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default)
471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default)
472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB
473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB
474 
475 // SI443X_REG_TX_POWER
476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled
477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default)
478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max
479 
480 // SI443X_REG_TX_DATA_RATE_1 + SI443X_REG_TX_DATA_RATE_0
481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or
482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps)
483 
484 // SI443X_REG_MODULATION_MODE_CONTROL_1
485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default)
486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps
487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default)
488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled
489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low
490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default)
491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled
492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default)
493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default)
494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled
495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default)
496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled
497 
498 // SI443X_REG_MODULATION_MODE_CONTROL_2
499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default)
500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin
501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin
502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin
503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default)
504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin
505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO
506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal
507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default)
508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled
509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB
510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default)
511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK
512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK
513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK
514 
515 // SI443X_REG_FREQUENCY_DEVIATION
516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz
517 
518 // SI443X_REG_FREQUENCY_OFFSET_1 + SI443X_REG_FREQUENCY_OFFSET_2
519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset:
520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz
521 
522 // SI443X_REG_FREQUENCY_BAND_SELECT
523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default)
524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency
525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz
526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default)
527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select
528 
529 // SI443X_REG_NOM_CARRIER_FREQUENCY_1 + SI443X_REG_NOM_CARRIER_FREQUENCY_0
530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency:
531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz]
532 
533 // SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL
534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number
535 
536 // SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE
537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size
538 
539 // SI443X_REG_TX_FIFO_CONTROL_1
540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold
541 
542 // SI443X_REG_TX_FIFO_CONTROL_2
543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold
544 
545 // SI443X_REG_RX_FIFO_CONTROL
546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold
547 
554 class Si443x: public PhysicalLayer {
555  public:
556  // introduce PhysicalLayer overloads
557  using PhysicalLayer::transmit;
558  using PhysicalLayer::receive;
559  using PhysicalLayer::startTransmit;
560  using PhysicalLayer::readData;
561 
562  // constructor
563 
569  Si443x(Module* mod);
570 
571  // basic methods
572 
586  int16_t begin(float br, float freqDev, float rxBw, uint8_t preambleLen);
587 
591  void reset();
592 
605  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
606 
617  int16_t receive(uint8_t* data, size_t len) override;
618 
625  int16_t sleep();
626 
632  int16_t standby() override;
633 
641  int16_t transmitDirect(uint32_t frf = 0) override;
642 
648  int16_t receiveDirect() override;
649 
655  int16_t packetMode();
656 
657  // interrupt methods
658 
664  void setIrqAction(void (*func)(void));
665 
669  void clearIrqAction();
670 
682  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
683 
689  int16_t startReceive();
690 
700  int16_t readData(uint8_t* data, size_t len) override;
701 
702  // configuration methods
703 
711  int16_t setBitRate(float br);
712 
720  int16_t setFrequencyDeviation(float freqDev) override;
721 
729  int16_t setRxBandwidth(float rxBw);
730 
738  int16_t setSyncWord(uint8_t* syncWord, size_t len);
739 
747  int16_t setPreambleLength(uint8_t preambleLen);
748 
756  size_t getPacketLength(bool update = true) override;
757 
766  int16_t setEncoding(uint8_t encoding) override;
767 
776  int16_t setDataShaping(uint8_t sh) override;
777 
786  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
787 
793  uint8_t random();
794 
800  int16_t getChipVersion();
801 
802 #ifndef RADIOLIB_GODMODE
803  protected:
804 #endif
805  Module* _mod;
806 
807  float _br = 0;
808  float _freqDev = 0;
809  float _freq = 0;
810 
811  size_t _packetLength = 0;
812  bool _packetLengthQueried = false;
813 
814  int16_t setFrequencyRaw(float newFreq);
815 
816 #ifndef RADIOLIB_GODMODE
817  private:
818 #endif
819  bool findChip();
820  void clearIRQFlags();
821  int16_t config();
822  int16_t updateClockRecovery();
823  int16_t directMode();
824 };
825 
826 #endif
827 
828 #endif
Si443x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:359
Si443x::startReceive
int16_t startReceive()
Interrupt-driven receive method. IRQ will be activated when full valid packet is received.
Definition: Si443x.cpp:254
-
Si443x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: Si443x.cpp:533
+
Si443x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: Si443x.cpp:528
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
-
Si443x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and work...
Definition: Si443x.cpp:575
-
Si443x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: Si443x.cpp:552
-
Si443x::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len)
Sets sync word. Up to 4 bytes can be set as sync word.
Definition: Si443x.cpp:471
+
Si443x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and work...
Definition: Si443x.cpp:570
+
Si443x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: Si443x.cpp:547
+
Si443x::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len)
Sets sync word. Up to 4 bytes can be set as sync word.
Definition: Si443x.cpp:466
Si443x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode. While in direct mode, the module will not be able to transmit or recei...
Definition: Si443x.cpp:189
Si443x::packetMode
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets.
Definition: Si443x.cpp:202
Si443x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: Si443x.cpp:279
Si443x::Si443x
Si443x(Module *mod)
Default constructor.
Definition: Si443x.cpp:4
-
Si443x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: Si443x.cpp:514
+
Si443x::setEncoding
int16_t setEncoding(uint8_t encoding) override
Sets transmission encoding. Only available in FSK mode. Allowed values are RADIOLIB_ENCODING_NRZ, RADIOLIB_ENCODING_MANCHESTER and RADIOLIB_ENCODING_WHITENING.
Definition: Si443x.cpp:509
Si443x::reset
void reset()
Reset method. Will reset the chip to the default state using SDN pin.
Definition: Si443x.cpp:60
-
Si443x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: Si443x.cpp:504
+
Si443x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: Si443x.cpp:499
Si443x::standby
int16_t standby() override
Sets the module to standby.
Definition: Si443x.cpp:139
Si443x::receive
int16_t receive(uint8_t *data, size_t len) override
Binary receive method. Will attempt to receive arbitrary binary data up to 64 bytes long...
Definition: Si443x.cpp:101
Si443x::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Binary transmit method. Will transmit arbitrary binary data up to 64 bytes long. For overloads to tra...
Definition: Si443x.cpp:68
@@ -108,13 +108,13 @@ $(document).ready(function(){initNavTree('_si443x_8h_source.html','');});
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
Si443x::setIrqAction
void setIrqAction(void(*func)(void))
Sets interrupt service routine to call when IRQ activates.
Definition: Si443x.cpp:206
-
Si443x::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: Si443x.cpp:488
+
Si443x::setPreambleLength
int16_t setPreambleLength(uint8_t preambleLen)
Sets preamble length.
Definition: Si443x.cpp:483
PhysicalLayer::receive
int16_t receive(String &str, size_t len=0)
Arduino String receive method.
Definition: PhysicalLayer.cpp:98
Si443x::transmitDirect
int16_t transmitDirect(uint32_t frf=0) override
Enables direct transmission mode. While in direct mode, the module will not be able to transmit or re...
Definition: Si443x.cpp:147
Si443x::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets FSK frequency deviation from carrier frequency. Allowed values range from 0.625 to 320...
Definition: Si443x.cpp:336
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
Si443x::sleep
int16_t sleep()
Sets the module to sleep to save power. Module will not be able to transmit or receive any data while...
Definition: Si443x.cpp:123
-
Si443x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: Si443x.cpp:556
+
Si443x::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: Si443x.cpp:551
Si443x::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Will start transmitting arbitrary binary data up to 64 bytes...
Definition: Si443x.cpp:214
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
diff --git a/class_a_f_s_k_client-members.html b/class_a_f_s_k_client-members.html index 656d70f8..5290d588 100644 --- a/class_a_f_s_k_client-members.html +++ b/class_a_f_s_k_client-members.html @@ -89,12 +89,13 @@ $(document).ready(function(){initNavTree('class_a_f_s_k_client.html','');}); - - - - - - + + + + + + +
AFSKClient(PhysicalLayer *phy, RADIOLIB_PIN_TYPE pin)AFSKClient
AX25Client (defined in AFSKClient)AFSKClientfriend
HellClient (defined in AFSKClient)AFSKClientfriend
MorseClient (defined in AFSKClient)AFSKClientfriend
noTone()AFSKClient
RTTYClient (defined in AFSKClient)AFSKClientfriend
SSTVClient (defined in AFSKClient)AFSKClientfriend
tone(uint16_t freq, bool autoStart=true)AFSKClient
begin()AFSKClient
HellClient (defined in AFSKClient)AFSKClientfriend
MorseClient (defined in AFSKClient)AFSKClientfriend
noTone()AFSKClient
RTTYClient (defined in AFSKClient)AFSKClientfriend
SSTVClient (defined in AFSKClient)AFSKClientfriend
tone(uint16_t freq, bool autoStart=true)AFSKClient
diff --git a/class_a_f_s_k_client.html b/class_a_f_s_k_client.html index d02ba065..6e748866 100644 --- a/class_a_f_s_k_client.html +++ b/class_a_f_s_k_client.html @@ -99,6 +99,9 @@ Public Member Functions  AFSKClient (PhysicalLayer *phy, RADIOLIB_PIN_TYPE pin)  Default contructor. More...
  +int16_t begin () + Initialization method. More...
+  int16_t tone (uint16_t freq, bool autoStart=true)  Start transmitting audio tone. More...
  @@ -165,6 +168,26 @@ class AX25Client<

Member Function Documentation

+ +

◆ begin()

+ +
+
+ + + + + + + +
int16_t AFSKClient::begin ()
+
+ +

Initialization method.

+
Returns
Status Codes
+ +
+

◆ noTone()

diff --git a/class_a_f_s_k_client.js b/class_a_f_s_k_client.js index b18893c1..cabc4316 100644 --- a/class_a_f_s_k_client.js +++ b/class_a_f_s_k_client.js @@ -1,6 +1,7 @@ var class_a_f_s_k_client = [ [ "AFSKClient", "class_a_f_s_k_client.html#acfe53917bcba7f79611e01865c42fefd", null ], + [ "begin", "class_a_f_s_k_client.html#a30b86bb7cd087b3bc3c45a011ba266c3", null ], [ "noTone", "class_a_f_s_k_client.html#ade91356bb158bbc820d28855dd5818d1", null ], [ "tone", "class_a_f_s_k_client.html#a6d2341901c83e45f853c077e60f1fa33", null ], [ "AX25Client", "class_a_f_s_k_client.html#a0012621c1414f4c7573e961b57884a5b", null ], diff --git a/class_c_c1101-members.html b/class_c_c1101-members.html index e9291403..435a9dec 100644 --- a/class_c_c1101-members.html +++ b/class_c_c1101-members.html @@ -128,16 +128,17 @@ $(document).ready(function(){initNavTree('class_c_c1101.html','');}); setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 setSyncWord(uint8_t *syncWord, uint8_t len, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 standby() overrideCC1101virtual - startReceive()CC1101 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideCC1101virtual - variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)CC1101 + startDirect()PhysicalLayer + startReceive()CC1101 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideCC1101virtual + variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)CC1101 diff --git a/class_c_c1101.html b/class_c_c1101.html index 2d0c0d57..d9f8899d 100644 --- a/class_c_c1101.html +++ b/class_c_c1101.html @@ -261,6 +261,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Control class for CC1101 module.

diff --git a/class_physical_layer-members.html b/class_physical_layer-members.html index 6a96a610..726a4085 100644 --- a/class_physical_layer-members.html +++ b/class_physical_layer-members.html @@ -102,14 +102,15 @@ $(document).ready(function(){initNavTree('class_physical_layer.html','');}); setEncoding(uint8_t encoding)=0PhysicalLayerpure virtual setFrequencyDeviation(float freqDev)=0PhysicalLayerpure virtual standby()=0PhysicalLayerpure virtual - startTransmit(String &str, uint8_t addr=0)PhysicalLayer - startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - startTransmit(uint8_t *data, size_t len, uint8_t addr=0)=0PhysicalLayerpure virtual - transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - transmit(String &str, uint8_t addr=0)PhysicalLayer - transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0)=0PhysicalLayerpure virtual - transmitDirect(uint32_t frf=0)=0PhysicalLayerpure virtual + startDirect()PhysicalLayer + startTransmit(String &str, uint8_t addr=0)PhysicalLayer + startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + startTransmit(uint8_t *data, size_t len, uint8_t addr=0)=0PhysicalLayerpure virtual + transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + transmit(String &str, uint8_t addr=0)PhysicalLayer + transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0)=0PhysicalLayerpure virtual + transmitDirect(uint32_t frf=0)=0PhysicalLayerpure virtual
diff --git a/class_physical_layer.html b/class_physical_layer.html index fff41057..83c53439 100644 --- a/class_physical_layer.html +++ b/class_physical_layer.html @@ -196,6 +196,9 @@ Public Member Functions virtual uint8_t random ()=0  Get one truly random byte from RSSI noise. Must be implemented in module class. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN. Also extracts some common module-independent methods. Using this interface class allows to use the protocols on various modules without much code duplicity. Because this class is used mainly as interface, all of its virtual members must be implemented in the module class.

@@ -731,6 +734,26 @@ Public Member Functions

Implemented in SX127x, Si443x, CC1101, RF69, SX128x, SX126x, and nRF24.

+
+ + +

◆ startDirect()

+ +
+
+ + + + + + + +
int16_t PhysicalLayer::startDirect ()
+
+ +

Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode.

+
Returns
Status Codes
+
diff --git a/class_physical_layer.js b/class_physical_layer.js index 781401b7..e36a4889 100644 --- a/class_physical_layer.js +++ b/class_physical_layer.js @@ -15,6 +15,7 @@ var class_physical_layer = [ "setEncoding", "class_physical_layer.html#a7d3419227d201d6912b77784636d437d", null ], [ "setFrequencyDeviation", "class_physical_layer.html#ab9060e8ab7a2da192b3bf53b3501553b", null ], [ "standby", "class_physical_layer.html#a0e77da761a2cbb5c9535df0bdea993f9", null ], + [ "startDirect", "class_physical_layer.html#a88a10657bd2215a11a2331f937414b55", null ], [ "startTransmit", "class_physical_layer.html#af068e6e862c99e39d0261a7971dd56db", null ], [ "startTransmit", "class_physical_layer.html#a923654706eff5118ef6e84214e837f27", null ], [ "startTransmit", "class_physical_layer.html#a41a1de0ebffe7b65de6fd8cceb9a5123", null ], diff --git a/class_r_f69-members.html b/class_r_f69-members.html index c994414f..afb0cc19 100644 --- a/class_r_f69-members.html +++ b/class_r_f69-members.html @@ -133,16 +133,17 @@ $(document).ready(function(){initNavTree('class_r_f69.html','');}); setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 sleep()RF69 standby() overrideRF69virtual - startReceive()RF69 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideRF69virtual - variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 + startDirect()PhysicalLayer + startReceive()RF69 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideRF69virtual + variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 diff --git a/class_r_f69.html b/class_r_f69.html index 9a37097a..66a830cf 100644 --- a/class_r_f69.html +++ b/class_r_f69.html @@ -278,6 +278,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Control class for RF69 module. Also serves as base class for SX1231.

diff --git a/class_r_f_m95-members.html b/class_r_f_m95-members.html index af2636f4..aced2c7a 100644 --- a/class_r_f_m95-members.html +++ b/class_r_f_m95-members.html @@ -146,18 +146,19 @@ $(document).ready(function(){initNavTree('class_r_f_m95.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_r_f_m95.html b/class_r_f_m95.html index bdfcd1e6..a2bfc689 100644 --- a/class_r_f_m95.html +++ b/class_r_f_m95.html @@ -332,6 +332,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for RFM95 modules. Overrides some methods from SX1278 due to different parameter ranges.

diff --git a/class_r_f_m96-members.html b/class_r_f_m96-members.html index 49f6c062..3bba9c94 100644 --- a/class_r_f_m96-members.html +++ b/class_r_f_m96-members.html @@ -146,18 +146,19 @@ $(document).ready(function(){initNavTree('class_r_f_m96.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_r_f_m96.html b/class_r_f_m96.html index a73db89f..f5bc2d6e 100644 --- a/class_r_f_m96.html +++ b/class_r_f_m96.html @@ -331,6 +331,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for RFM96 modules. Overrides some methods from SX1278 due to different parameter ranges.

diff --git a/class_r_f_m97-members.html b/class_r_f_m97-members.html index 88e0658a..9ac08235 100644 --- a/class_r_f_m97-members.html +++ b/class_r_f_m97-members.html @@ -147,18 +147,19 @@ $(document).ready(function(){initNavTree('class_r_f_m97.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_r_f_m97.html b/class_r_f_m97.html index 45a78de4..44a2aa3a 100644 --- a/class_r_f_m97.html +++ b/class_r_f_m97.html @@ -339,6 +339,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for RFM97 modules. Overrides some methods from RFM95 due to different parameter ranges.

diff --git a/class_s_x1231-members.html b/class_s_x1231-members.html index 6d8b163b..2921a665 100644 --- a/class_s_x1231-members.html +++ b/class_s_x1231-members.html @@ -133,17 +133,18 @@ $(document).ready(function(){initNavTree('class_s_x1231.html','');}); setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 sleep()RF69 standby() overrideRF69virtual - startReceive()RF69 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1231(Module *mod)SX1231 - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideRF69virtual - variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 + startDirect()PhysicalLayer + startReceive()RF69 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1231(Module *mod)SX1231 + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideRF69virtual + variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69
diff --git a/class_s_x1231.html b/class_s_x1231.html index 92e25aa9..a58f381c 100644 --- a/class_s_x1231.html +++ b/class_s_x1231.html @@ -285,6 +285,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Control class for SX1231 module. Overrides some methods from RF69 due to different register values.

diff --git a/class_s_x1261-members.html b/class_s_x1261-members.html index 8df2a5d7..a9285367 100644 --- a/class_s_x1261-members.html +++ b/class_s_x1261-members.html @@ -145,21 +145,22 @@ $(document).ready(function(){initNavTree('class_s_x1261.html','');}); sleep(bool retainConfig=true)SX126x standby() overrideSX126xvirtual standby(uint8_t mode)SX126x - startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x - startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x - startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1261(Module *mod)SX1261 - SX1262(Module *mod)SX1262 - SX126x(Module *mod)SX126x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX126xvirtual - variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x + startDirect()PhysicalLayer + startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x + startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x + startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1261(Module *mod)SX1261 + SX1262(Module *mod)SX1262 + SX126x(Module *mod)SX126x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX126xvirtual + variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x
diff --git a/class_s_x1261.html b/class_s_x1261.html index 837de922..d0f7d32b 100644 --- a/class_s_x1261.html +++ b/class_s_x1261.html @@ -332,6 +332,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1261 modules.

diff --git a/class_s_x1262-members.html b/class_s_x1262-members.html index 7f704cb5..7d31435a 100644 --- a/class_s_x1262-members.html +++ b/class_s_x1262-members.html @@ -145,20 +145,21 @@ $(document).ready(function(){initNavTree('class_s_x1262.html','');}); sleep(bool retainConfig=true)SX126x standby() overrideSX126xvirtual standby(uint8_t mode)SX126x - startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x - startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x - startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1262(Module *mod)SX1262 - SX126x(Module *mod)SX126x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX126xvirtual - variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x + startDirect()PhysicalLayer + startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x + startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x + startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1262(Module *mod)SX1262 + SX126x(Module *mod)SX126x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX126xvirtual + variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x
diff --git a/class_s_x1262.html b/class_s_x1262.html index e19784f8..4e1ae7b5 100644 --- a/class_s_x1262.html +++ b/class_s_x1262.html @@ -325,6 +325,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1262 modules.

diff --git a/class_s_x1268-members.html b/class_s_x1268-members.html index 69b01b68..e397d8b1 100644 --- a/class_s_x1268-members.html +++ b/class_s_x1268-members.html @@ -145,20 +145,21 @@ $(document).ready(function(){initNavTree('class_s_x1268.html','');}); sleep(bool retainConfig=true)SX126x standby() overrideSX126xvirtual standby(uint8_t mode)SX126x - startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x - startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x - startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1268(Module *mod)SX1268 - SX126x(Module *mod)SX126x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX126xvirtual - variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x + startDirect()PhysicalLayer + startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x + startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x + startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1268(Module *mod)SX1268 + SX126x(Module *mod)SX126x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX126xvirtual + variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x
diff --git a/class_s_x1268.html b/class_s_x1268.html index 1dac3dd7..db0c8807 100644 --- a/class_s_x1268.html +++ b/class_s_x1268.html @@ -324,6 +324,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1268 modules.

diff --git a/class_s_x126x-members.html b/class_s_x126x-members.html index 5c097da3..f0f80bfa 100644 --- a/class_s_x126x-members.html +++ b/class_s_x126x-members.html @@ -141,19 +141,20 @@ $(document).ready(function(){initNavTree('class_s_x126x.html','');}); sleep(bool retainConfig=true)SX126x standby() overrideSX126xvirtual standby(uint8_t mode)SX126x - startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x - startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x - startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX126x(Module *mod)SX126x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX126xvirtual - variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x + startDirect()PhysicalLayer + startReceive(uint32_t timeout=SX126X_RX_TIMEOUT_INF)SX126x + startReceiveDutyCycle(uint32_t rxPeriod, uint32_t sleepPeriod)SX126x + startReceiveDutyCycleAuto(uint16_t senderPreambleLength=0, uint16_t minSymbols=8)SX126x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX126x(Module *mod)SX126x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX126xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX126xvirtual + variablePacketLengthMode(uint8_t maxLen=SX126X_MAX_PACKET_LENGTH)SX126x
diff --git a/class_s_x126x.html b/class_s_x126x.html index d07b0f97..b0bfda7c 100644 --- a/class_s_x126x.html +++ b/class_s_x126x.html @@ -310,6 +310,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Base class for SX126x series. All derived classes for SX126x (e.g. SX1262 or SX1268) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes.

diff --git a/class_s_x1272-members.html b/class_s_x1272-members.html index 1cae2f1b..488952a6 100644 --- a/class_s_x1272-members.html +++ b/class_s_x1272-members.html @@ -145,18 +145,19 @@ $(document).ready(function(){initNavTree('class_s_x1272.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1272(Module *mod)SX1272 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1272(Module *mod)SX1272 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1272.html b/class_s_x1272.html index f0ff176d..56cd9362 100644 --- a/class_s_x1272.html +++ b/class_s_x1272.html @@ -321,6 +321,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic hardware and only differ in parameter ranges.

diff --git a/class_s_x1273-members.html b/class_s_x1273-members.html index f8199683..f3c769e5 100644 --- a/class_s_x1273-members.html +++ b/class_s_x1273-members.html @@ -145,19 +145,20 @@ $(document).ready(function(){initNavTree('class_s_x1273.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1272(Module *mod)SX1272 - SX1273(Module *mod)SX1273 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1272(Module *mod)SX1272 + SX1273(Module *mod)SX1273 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1273.html b/class_s_x1273.html index a306bcc5..5b310f03 100644 --- a/class_s_x1273.html +++ b/class_s_x1273.html @@ -331,6 +331,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1273 modules. Overrides some methods from SX1272 due to different parameter ranges.

diff --git a/class_s_x1276-members.html b/class_s_x1276-members.html index 4cc6e49c..d9a1f9e7 100644 --- a/class_s_x1276-members.html +++ b/class_s_x1276-members.html @@ -145,19 +145,20 @@ $(document).ready(function(){initNavTree('class_s_x1276.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1276(Module *mod)SX1276 - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1276(Module *mod)SX1276 + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1276.html b/class_s_x1276.html index 70ac2102..07b7e1ba 100644 --- a/class_s_x1276.html +++ b/class_s_x1276.html @@ -334,6 +334,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1276 modules. Overrides some methods from SX1278 due to different parameter ranges.

diff --git a/class_s_x1277-members.html b/class_s_x1277-members.html index d9a21dc0..5caf39d8 100644 --- a/class_s_x1277-members.html +++ b/class_s_x1277-members.html @@ -145,19 +145,20 @@ $(document).ready(function(){initNavTree('class_s_x1277.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1277(Module *mod)SX1277 - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1277(Module *mod)SX1277 + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1277.html b/class_s_x1277.html index 0c553fde..a48a931a 100644 --- a/class_s_x1277.html +++ b/class_s_x1277.html @@ -337,6 +337,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1277 modules. Overrides some methods from SX1278 due to different parameter ranges.

diff --git a/class_s_x1278-members.html b/class_s_x1278-members.html index bcf39526..1fd2d3e6 100644 --- a/class_s_x1278-members.html +++ b/class_s_x1278-members.html @@ -145,18 +145,19 @@ $(document).ready(function(){initNavTree('class_s_x1278.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1278.html b/class_s_x1278.html index fd0e858f..7ae8997b 100644 --- a/class_s_x1278.html +++ b/class_s_x1278.html @@ -326,6 +326,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1278 modules. Also used as base class for SX1276, SX1277, SX1279, RFM95 and RFM96. All of these modules use the same basic hardware and only differ in parameter ranges (and names).

diff --git a/class_s_x1279-members.html b/class_s_x1279-members.html index ee19d22f..91297fcf 100644 --- a/class_s_x1279-members.html +++ b/class_s_x1279-members.html @@ -145,19 +145,20 @@ $(document).ready(function(){initNavTree('class_s_x1279.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX1279(Module *mod)SX1279 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX1279(Module *mod)SX1279 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x1279.html b/class_s_x1279.html index 10d8b0a6..b963912d 100644 --- a/class_s_x1279.html +++ b/class_s_x1279.html @@ -334,6 +334,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1279 modules. Overrides some methods from SX1278 due to different parameter ranges.

diff --git a/class_s_x127x-members.html b/class_s_x127x-members.html index abb32437..f39f0675 100644 --- a/class_s_x127x-members.html +++ b/class_s_x127x-members.html @@ -132,17 +132,18 @@ $(document).ready(function(){initNavTree('class_s_x127x.html','');}); setSyncWord(uint8_t *syncWord, size_t len)SX127x sleep()SX127x standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + startDirect()PhysicalLayer + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x
diff --git a/class_s_x127x.html b/class_s_x127x.html index ff988a15..4e60e878 100644 --- a/class_s_x127x.html +++ b/class_s_x127x.html @@ -285,6 +285,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes.

diff --git a/class_s_x1280-members.html b/class_s_x1280-members.html index c9ed375f..d34854c5 100644 --- a/class_s_x1280-members.html +++ b/class_s_x1280-members.html @@ -131,19 +131,20 @@ $(document).ready(function(){initNavTree('class_s_x1280.html','');}); sleep(bool retainConfig=true)SX128x standby() overrideSX128xvirtual standby(uint8_t mode)SX128x - startRanging(bool master, uint32_t addr)SX1280 - startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1280(Module *mod)SX1280 - SX1281(Module *mod)SX1281 - SX128x(Module *mod)SX128x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX128xvirtual + startDirect()PhysicalLayer + startRanging(bool master, uint32_t addr)SX1280 + startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1280(Module *mod)SX1280 + SX1281(Module *mod)SX1281 + SX128x(Module *mod)SX128x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX128xvirtual
diff --git a/class_s_x1280.html b/class_s_x1280.html index 465c5551..c648b27f 100644 --- a/class_s_x1280.html +++ b/class_s_x1280.html @@ -282,6 +282,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1280 modules.

diff --git a/class_s_x1281-members.html b/class_s_x1281-members.html index 09a25fde..172b57f3 100644 --- a/class_s_x1281-members.html +++ b/class_s_x1281-members.html @@ -129,17 +129,18 @@ $(document).ready(function(){initNavTree('class_s_x1281.html','');}); sleep(bool retainConfig=true)SX128x standby() overrideSX128xvirtual standby(uint8_t mode)SX128x - startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1281(Module *mod)SX1281 - SX128x(Module *mod)SX128x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX128xvirtual + startDirect()PhysicalLayer + startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1281(Module *mod)SX1281 + SX128x(Module *mod)SX128x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX128xvirtual
diff --git a/class_s_x1281.html b/class_s_x1281.html index 3637fb69..212da5a5 100644 --- a/class_s_x1281.html +++ b/class_s_x1281.html @@ -269,6 +269,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1281 modules.

diff --git a/class_s_x1282-members.html b/class_s_x1282-members.html index c8c62bd7..82c6ec2f 100644 --- a/class_s_x1282-members.html +++ b/class_s_x1282-members.html @@ -131,20 +131,21 @@ $(document).ready(function(){initNavTree('class_s_x1282.html','');}); sleep(bool retainConfig=true)SX128x standby() overrideSX128xvirtual standby(uint8_t mode)SX128x - startRanging(bool master, uint32_t addr)SX1280 - startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1280(Module *mod)SX1280 - SX1281(Module *mod)SX1281 - SX1282(Module *mod)SX1282 - SX128x(Module *mod)SX128x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX128xvirtual + startDirect()PhysicalLayer + startRanging(bool master, uint32_t addr)SX1280 + startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1280(Module *mod)SX1280 + SX1281(Module *mod)SX1281 + SX1282(Module *mod)SX1282 + SX128x(Module *mod)SX128x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX128xvirtual
diff --git a/class_s_x1282.html b/class_s_x1282.html index 61811000..9698f357 100644 --- a/class_s_x1282.html +++ b/class_s_x1282.html @@ -286,6 +286,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for SX1282 modules.

diff --git a/class_s_x128x-members.html b/class_s_x128x-members.html index 0589d923..6ac0000c 100644 --- a/class_s_x128x-members.html +++ b/class_s_x128x-members.html @@ -129,16 +129,17 @@ $(document).ready(function(){initNavTree('class_s_x128x.html','');}); sleep(bool retainConfig=true)SX128x standby() overrideSX128xvirtual standby(uint8_t mode)SX128x - startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX128x(Module *mod)SX128x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX128xvirtual + startDirect()PhysicalLayer + startReceive(uint16_t timeout=SX128X_RX_TIMEOUT_INF)SX128x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX128x(Module *mod)SX128x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX128xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX128xvirtual
diff --git a/class_s_x128x.html b/class_s_x128x.html index bbb43c9f..1d125a0c 100644 --- a/class_s_x128x.html +++ b/class_s_x128x.html @@ -265,6 +265,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Base class for SX128x series. All derived classes for SX128x (e.g. SX1280 or SX1281) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes.

diff --git a/class_si4430-members.html b/class_si4430-members.html index 25513ad3..f14642a7 100644 --- a/class_si4430-members.html +++ b/class_si4430-members.html @@ -120,15 +120,16 @@ $(document).ready(function(){initNavTree('class_si4430.html','');}); Si443x(Module *mod)Si443x sleep()Si443x standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + startDirect()PhysicalLayer + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual
diff --git a/class_si4430.html b/class_si4430.html index af82b73a..fecdeda2 100644 --- a/class_si4430.html +++ b/class_si4430.html @@ -246,6 +246,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for Si4430 modules.

diff --git a/class_si4431-members.html b/class_si4431-members.html index 429e7e99..9aa1f6cf 100644 --- a/class_si4431-members.html +++ b/class_si4431-members.html @@ -120,15 +120,16 @@ $(document).ready(function(){initNavTree('class_si4431.html','');}); Si443x(Module *mod)Si443x sleep()Si443x standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + startDirect()PhysicalLayer + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual
diff --git a/class_si4431.html b/class_si4431.html index a0b95c4f..167088f0 100644 --- a/class_si4431.html +++ b/class_si4431.html @@ -243,6 +243,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for Si4431 modules.

diff --git a/class_si4432-members.html b/class_si4432-members.html index c6df4975..4b022791 100644 --- a/class_si4432-members.html +++ b/class_si4432-members.html @@ -119,15 +119,16 @@ $(document).ready(function(){initNavTree('class_si4432.html','');}); Si443x(Module *mod)Si443x sleep()Si443x standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + startDirect()PhysicalLayer + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual
diff --git a/class_si4432.html b/class_si4432.html index 41f8793d..777b7133 100644 --- a/class_si4432.html +++ b/class_si4432.html @@ -234,6 +234,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Derived class for Si4432 modules.

diff --git a/class_si443x-members.html b/class_si443x-members.html index 5d1eabbe..83e72844 100644 --- a/class_si443x-members.html +++ b/class_si443x-members.html @@ -115,15 +115,16 @@ $(document).ready(function(){initNavTree('class_si443x.html','');}); Si443x(Module *mod)Si443x sleep()Si443x standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + startDirect()PhysicalLayer + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual
diff --git a/class_si443x.html b/class_si443x.html index 75eb9d8a..dc5d7347 100644 --- a/class_si443x.html +++ b/class_si443x.html @@ -221,6 +221,9 @@ void int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Base class for Si443x series. All derived classes for Si443x (e.g. Si4431 or Si4432) inherit from this base class. This class should not be instantiated directly from Arduino sketch, only from its derived classes.

diff --git a/classn_r_f24-members.html b/classn_r_f24-members.html index 65822553..5e990187 100644 --- a/classn_r_f24-members.html +++ b/classn_r_f24-members.html @@ -119,15 +119,16 @@ $(document).ready(function(){initNavTree('classn_r_f24.html','');}); setTransmitPipe(uint8_t *addr)nRF24 sleep()nRF24 standby() overridenRF24virtual - startReceive()nRF24 - startTransmit(uint8_t *data, size_t len, uint8_t addr) overridenRF24virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr) overridenRF24virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overridenRF24virtual + startDirect()PhysicalLayer + startReceive()nRF24 + startTransmit(uint8_t *data, size_t len, uint8_t addr) overridenRF24virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr) overridenRF24virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overridenRF24virtual
diff --git a/classn_r_f24.html b/classn_r_f24.html index c3d32b84..18cfa7b9 100644 --- a/classn_r_f24.html +++ b/classn_r_f24.html @@ -228,6 +228,9 @@ Public Member Functions int32_t random (int32_t min, int32_t max)  Get truly random number in range min - max. More...
  +int16_t startDirect () + Configure module parameters for direct modes. Must be called prior to "ham" modes like RTTY or AX.25. Only available in FSK mode. More...
+ 

Detailed Description

Control class for nRF24 module.

diff --git a/functions_b.html b/functions_b.html index effd7873..cf718a78 100644 --- a/functions_b.html +++ b/functions_b.html @@ -87,7 +87,8 @@ $(document).ready(function(){initNavTree('functions_b.html','');}); : Module
  • begin() -: AX25Client +: AFSKClient +, AX25Client , CC1101 , ESP8266 , HC05 diff --git a/functions_func_b.html b/functions_func_b.html index c454ce99..79bf64e4 100644 --- a/functions_func_b.html +++ b/functions_func_b.html @@ -84,7 +84,8 @@ $(document).ready(function(){initNavTree('functions_func_b.html','');});

    - b -

    • begin() -: AX25Client +: AFSKClient +, AX25Client , CC1101 , ESP8266 , HC05 @@ -100,7 +101,7 @@ $(document).ready(function(){initNavTree('functions_func_b.html','');}); , Si4431 , Si4432 , Si443x -, SSTVClient +, SSTVClient , SX1231 , SX1262 , SX1268 diff --git a/functions_func_s.html b/functions_func_s.html index 11c30ab6..b6a3d935 100644 --- a/functions_func_s.html +++ b/functions_func_s.html @@ -338,7 +338,7 @@ $(document).ready(function(){initNavTree('functions_func_s.html','');}); , RF69 , Si443x , SX126x -, SX127x +, SX127x , SX128x
    • setTCXO() @@ -403,7 +403,10 @@ $(document).ready(function(){initNavTree('functions_func_s.html','');}); , Si443x , SX126x , SX127x -, SX128x +, SX128x +
      • +
    • startDirect() +: PhysicalLayer
    • startRanging() : SX1280 @@ -429,7 +432,7 @@ $(document).ready(function(){initNavTree('functions_func_s.html','');});
    • startTransmit() : CC1101 , nRF24 -, PhysicalLayer +, PhysicalLayer , RF69 , Si443x , SX126x diff --git a/functions_s.html b/functions_s.html index 17d832d6..4cfb952e 100644 --- a/functions_s.html +++ b/functions_s.html @@ -340,7 +340,7 @@ $(document).ready(function(){initNavTree('functions_s.html','');}); : SX126x
    • setSyncWord() -: CC1101 +: CC1101 , RF69 , Si443x , SX126x @@ -411,7 +411,7 @@ $(document).ready(function(){initNavTree('functions_s.html','');}); : AX25Frame
    • SSTVClient() -: SSTVClient +: SSTVClient
    • standby() : CC1101 @@ -419,10 +419,13 @@ $(document).ready(function(){initNavTree('functions_s.html','');}); , PhysicalLayer , RF69 , Si443x -, SX126x +, SX126x , SX127x , SX128x
      • +
    • startDirect() +: PhysicalLayer +
    • startRanging() : SX1280
      • @@ -447,7 +450,7 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
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