diff --git a/_build_opt_8h_source.html b/_build_opt_8h_source.html index 91632595..cda11f74 100644 --- a/_build_opt_8h_source.html +++ b/_build_opt_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_build_opt_8h_source.html','');});
BuildOpt.h
-
1 #ifndef _RADIOLIB_BUILD_OPTIONS_H
2 #define _RADIOLIB_BUILD_OPTIONS_H
3 
4 #if ARDUINO >= 100
5  #include "Arduino.h"
6 #else
7  #error "Unsupported Arduino version (< 1.0.0)"
8 #endif
9 
10 /*
11  * Platform-specific configuration.
12  *
13  * RADIOLIB_PLATFORM - platform name, used in debugging to quickly check the correct platform is detected.
14  * RADIOLIB_PIN_TYPE - which type should be used for pin numbers in functions like digitalRead().
15  * RADIOLIB_PIN_MODE - which type should be used for pin modes in functions like pinMode().
16  * RADIOLIB_PIN_STATUS - which type should be used for pin values in functions like digitalWrite().
17  * RADIOLIB_INTERRUPT_STATUS - which type should be used for pin changes in functions like attachInterrupt().
18  * RADIOLIB_DIGITAL_PIN_TO_INTERRUPT - function/macro to be used to convert digital pin number to interrupt pin number.
19  * RADIOLIB_NC - alias for unused pin, usually the largest possible value of RADIOLIB_PIN_TYPE.
20  * RADIOLIB_DEFAULT_SPI - default SPIClass instance to use.
21  * RADIOLIB_PROGMEM - macro to place variable into program storage (usually Flash).
22  * RADIOLIB_PROGMEM_READ_BYTE - function/macro to read variables saved in program storage (usually Flash).
23  * RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED - defined if the specific platform does not support SoftwareSerial.
24  * RADIOLIB_HARDWARE_SERIAL_PORT - which hardware serial port should be used on platform that do not have SoftwareSerial support.
25  * RADIOLIB_TONE_UNSUPPORTED - some platforms do not have tone()/noTone(), which is required for AFSK.
26  *
27  * In addition, some platforms may require RadioLib to disable specific drivers (such as ESP8266).
28  *
29  * Users may also specify their own configuration by uncommenting the RADIOLIB_CUSTOM_PLATFORM,
30  * and then specifying all platform parameters in the section below. This will override automatic
31  * platform detection.
32  */
33 
34 // uncomment to enable custom platform definition
35 //#define RADIOLIB_CUSTOM_PLATFORM
36 
37 #if defined(RADIOLIB_CUSTOM_PLATFORM)
38  // name for your platform
39  #define RADIOLIB_PLATFORM "Custom"
40 
41  // the following parameters must always be defined
42  #define RADIOLIB_PIN_TYPE uint8_t
43  #define RADIOLIB_PIN_MODE uint8_t
44  #define RADIOLIB_PIN_STATUS uint8_t
45  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
46  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
47  #define RADIOLIB_NC (0xFF)
48  #define RADIOLIB_DEFAULT_SPI SPI
49  #define RADIOLIB_PROGMEM PROGMEM
50  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
51 
52  // the following must be defined if the Arduino core does not support SoftwareSerial library
53  //#define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
54  //#define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
55 
56  // the following must be defined if the Arduino core does not support tone function
57  //#define RADIOLIB_TONE_UNSUPPORTED
58 
59  // some of RadioLib drivers may be excluded, to prevent collisions with platforms (or to speed up build process)
60  // the following is a complete list of all possible exclusion macros, uncomment any of them to disable that driver
61  // NOTE: Some of the exclusion macros are dependent on each other. For example, it is not possible to exclude RF69
62  // while keeping SX1231 (because RF69 is the base class for SX1231). The dependency is always uni-directional,
63  // so excluding SX1231 and keeping RF69 is valid.
64  //#define RADIOLIB_EXCLUDE_CC1101
65  //#define RADIOLIB_EXCLUDE_ESP8266
66  //#define RADIOLIB_EXCLUDE_HC05
67  //#define RADIOLIB_EXCLUDE_JDY08
68  //#define RADIOLIB_EXCLUDE_NRF24
69  //#define RADIOLIB_EXCLUDE_RF69
70  //#define RADIOLIB_EXCLUDE_SX1231 // dependent on RADIOLIB_EXCLUDE_RF69
71  //#define RADIOLIB_EXCLUDE_SI443X
72  //#define RADIOLIB_EXCLUDE_RFM2X // dependent on RADIOLIB_EXCLUDE_SI443X
73  //#define RADIOLIB_EXCLUDE_SX127X
74  //#define RADIOLIB_EXCLUDE_RFM9X // dependent on RADIOLIB_EXCLUDE_SX127X
75  //#define RADIOLIB_EXCLUDE_SX126X
76  //#define RADIOLIB_EXCLUDE_SX128X
77  //#define RADIOLIB_EXCLUDE_XBEE
78  //#define RADIOLIB_EXCLUDE_AFSK
79  //#define RADIOLIB_EXCLUDE_AX25
80  //#define RADIOLIB_EXCLUDE_HELLSCHREIBER
81  //#define RADIOLIB_EXCLUDE_HTTP
82  //#define RADIOLIB_EXCLUDE_MORSE
83  //#define RADIOLIB_EXCLUDE_MQTT
84  //#define RADIOLIB_EXCLUDE_RTTY
85  //#define RADIOLIB_EXCLUDE_SSTV
86 
87 #else
88  #if defined(__AVR__) && !(defined(ARDUINO_AVR_UNO_WIFI_REV2) || defined(ARDUINO_AVR_NANO_EVERY) || defined(ARDUINO_ARCH_MEGAAVR))
89  // Arduino AVR boards (except for megaAVR) - Uno, Mega etc.
90  #define RADIOLIB_PLATFORM "Arduino AVR"
91  #define RADIOLIB_PIN_TYPE uint8_t
92  #define RADIOLIB_PIN_MODE uint8_t
93  #define RADIOLIB_PIN_STATUS uint8_t
94  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
95  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
96  #define RADIOLIB_NC (0xFF)
97  #define RADIOLIB_DEFAULT_SPI SPI
98  #define RADIOLIB_PROGMEM PROGMEM
99  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
100 
101  #elif defined(ESP8266)
102  // ESP8266 boards
103  #define RADIOLIB_PLATFORM "ESP8266"
104  #define RADIOLIB_PIN_TYPE uint8_t
105  #define RADIOLIB_PIN_MODE uint8_t
106  #define RADIOLIB_PIN_STATUS uint8_t
107  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
108  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
109  #define RADIOLIB_NC (0xFF)
110  #define RADIOLIB_DEFAULT_SPI SPI
111  #define RADIOLIB_PROGMEM PROGMEM
112  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
113 
114  // RadioLib has ESP8266 driver, this must be disabled to use ESP8266 as platform
115  #define RADIOLIB_EXCLUDE_ESP8266
116 
117  #elif defined(ESP32)
118  // ESP32 boards
119  #define RADIOLIB_PLATFORM "ESP32"
120  #define RADIOLIB_PIN_TYPE uint8_t
121  #define RADIOLIB_PIN_MODE uint8_t
122  #define RADIOLIB_PIN_STATUS uint8_t
123  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
124  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
125  #define RADIOLIB_NC (0xFF)
126  #define RADIOLIB_DEFAULT_SPI SPI
127  #define RADIOLIB_PROGMEM PROGMEM
128  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
129  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
130  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
131 
132  // ESP32 doesn't support tone(), but it can be emulated via LED control peripheral
133  #define RADIOLIB_TONE_UNSUPPORTED
134  #define RADIOLIB_TONE_ESP32_CHANNEL (1)
135 
136  #elif defined(ARDUINO_ARCH_STM32)
137  // official STM32 Arduino core (https://github.com/stm32duino/Arduino_Core_STM32)
138  #define RADIOLIB_PLATFORM "Arduino STM32 (official)"
139  #define RADIOLIB_PIN_TYPE uint32_t
140  #define RADIOLIB_PIN_MODE uint32_t
141  #define RADIOLIB_PIN_STATUS uint32_t
142  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
143  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
144  #define RADIOLIB_NC (0xFFFFFFFF)
145  #define RADIOLIB_DEFAULT_SPI SPI
146  #define RADIOLIB_PROGMEM PROGMEM
147  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
148  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
149  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
150 
151  // slow down SX126x/8x SPI on this platform
152  #define RADIOLIB_SPI_SLOWDOWN
153 
154  #elif defined(SAMD_SERIES)
155  // Adafruit SAMD boards (M0 and M4)
156  #define RADIOLIB_PLATFORM "Adafruit SAMD"
157  #define RADIOLIB_PIN_TYPE uint32_t
158  #define RADIOLIB_PIN_MODE uint32_t
159  #define RADIOLIB_PIN_STATUS uint32_t
160  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
161  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
162  #define RADIOLIB_NC (0xFFFFFFFF)
163  #define RADIOLIB_DEFAULT_SPI SPI
164  #define RADIOLIB_PROGMEM PROGMEM
165  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
166  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
167  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
168 
169  // slow down SX126x/8x SPI on this platform
170  #define RADIOLIB_SPI_SLOWDOWN
171 
172  #elif defined(ARDUINO_ARCH_SAMD)
173  // Arduino SAMD (Zero, MKR, etc.)
174  #define RADIOLIB_PLATFORM "Arduino SAMD"
175  #define RADIOLIB_PIN_TYPE pin_size_t
176  #define RADIOLIB_PIN_MODE PinMode
177  #define RADIOLIB_PIN_STATUS PinStatus
178  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
179  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
180  #define RADIOLIB_NC (0xFF)
181  #define RADIOLIB_DEFAULT_SPI SPI
182  #define RADIOLIB_PROGMEM PROGMEM
183  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
184  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
185  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
186 
187  #elif defined(__SAM3X8E__)
188  // Arduino Due
189  #define RADIOLIB_PLATFORM "Arduino Due"
190  #define RADIOLIB_PIN_TYPE uint32_t
191  #define RADIOLIB_PIN_MODE uint32_t
192  #define RADIOLIB_PIN_STATUS uint32_t
193  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
194  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
195  #define RADIOLIB_NC (0xFFFFFFFF)
196  #define RADIOLIB_DEFAULT_SPI SPI
197  #define RADIOLIB_PROGMEM PROGMEM
198  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
199  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
200  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
201  #define RADIOLIB_TONE_UNSUPPORTED
202 
203  #elif (defined(NRF52832_XXAA) || defined(NRF52840_XXAA)) && !defined(ARDUINO_ARDUINO_NANO33BLE)
204  // Adafruit nRF52 boards
205  #define RADIOLIB_PLATFORM "Adafruit nRF52"
206  #define RADIOLIB_PIN_TYPE uint32_t
207  #define RADIOLIB_PIN_MODE uint32_t
208  #define RADIOLIB_PIN_STATUS uint32_t
209  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
210  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
211  #define RADIOLIB_NC (0xFFFFFFFF)
212  #define RADIOLIB_DEFAULT_SPI SPI
213  #define RADIOLIB_PROGMEM PROGMEM
214  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
215 
216  #elif defined(ARDUINO_ARC32_TOOLS)
217  // Intel Curie
218  #define RADIOLIB_PLATFORM "Intel Curie"
219  #define RADIOLIB_PIN_TYPE uint8_t
220  #define RADIOLIB_PIN_MODE uint8_t
221  #define RADIOLIB_PIN_STATUS uint8_t
222  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
223  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
224  #define RADIOLIB_NC (0xFF)
225  #define RADIOLIB_DEFAULT_SPI SPI
226  #define RADIOLIB_PROGMEM PROGMEM
227  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
228 
229  #elif defined(ARDUINO_AVR_UNO_WIFI_REV2) || defined(ARDUINO_AVR_NANO_EVERY)
230  // Arduino megaAVR boards - Uno Wifi Rev.2, Nano Every
231  #define RADIOLIB_PLATFORM "Arduino megaAVR"
232  #define RADIOLIB_PIN_TYPE uint8_t
233  #define RADIOLIB_PIN_MODE PinMode
234  #define RADIOLIB_PIN_STATUS PinStatus
235  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
236  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
237  #define RADIOLIB_NC (0xFF)
238  #define RADIOLIB_DEFAULT_SPI SPI
239  #define RADIOLIB_PROGMEM PROGMEM
240  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
241 
242  #elif defined(ARDUINO_ARCH_APOLLO3)
243  // Sparkfun Apollo3 boards
244  #define RADIOLIB_PLATFORM "Sparkfun Apollo3"
245  #define RADIOLIB_PIN_TYPE pin_size_t
246  #define RADIOLIB_PIN_MODE Arduino_PinMode
247  #define RADIOLIB_PIN_STATUS PinStatus
248  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
249  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
250  #define RADIOLIB_NC (0xFF)
251  #define RADIOLIB_DEFAULT_SPI SPI
252  #define RADIOLIB_PROGMEM PROGMEM
253  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
254  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
255  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
256 
257  // Apollo3 uses mbed libraries, which already contain ESP8266 driver
258  #define RADIOLIB_EXCLUDE_ESP8266
259 
260  // slow down SX126x/8x SPI on this platform
261  #define RADIOLIB_SPI_SLOWDOWN
262 
263  #elif defined(ARDUINO_ARDUINO_NANO33BLE)
264  // Arduino Nano 33 BLE
265  #define RADIOLIB_PLATFORM "Arduino Nano 33 BLE"
266  #define RADIOLIB_PIN_TYPE pin_size_t
267  #define RADIOLIB_PIN_MODE PinMode
268  #define RADIOLIB_PIN_STATUS PinStatus
269  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
270  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
271  #define RADIOLIB_NC (0xFF)
272  #define RADIOLIB_DEFAULT_SPI SPI
273  #define RADIOLIB_PROGMEM PROGMEM
274  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
275  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
276  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
277 
278  // Nano 33 BLE uses mbed libraries, which already contain ESP8266 driver
279  #define RADIOLIB_EXCLUDE_ESP8266
280 
281  #elif defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4)
282  // Arduino Portenta H7
283  #define RADIOLIB_PLATFORM "Portenta H7"
284  #define RADIOLIB_PIN_TYPE pin_size_t
285  #define RADIOLIB_PIN_MODE PinMode
286  #define RADIOLIB_PIN_STATUS PinStatus
287  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
288  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
289  #define RADIOLIB_NC (0xFF)
290  #define RADIOLIB_DEFAULT_SPI SPI
291  #define RADIOLIB_PROGMEM PROGMEM
292  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
293  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
294  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
295 
296  // Arduino Portenta H7 uses mbed libraries, which already contain ESP8266 driver
297  #define RADIOLIB_EXCLUDE_ESP8266
298 
299  #elif defined(__STM32F4__) || defined(__STM32F1__)
300  // Arduino STM32 core by Roger Clark (https://github.com/rogerclarkmelbourne/Arduino_STM32)
301  #define RADIOLIB_PLATFORM "STM32duino (unofficial)"
302  #define RADIOLIB_PIN_TYPE uint8_t
303  #define RADIOLIB_PIN_MODE WiringPinMode
304  #define RADIOLIB_PIN_STATUS uint8_t
305  #define RADIOLIB_INTERRUPT_STATUS ExtIntTriggerMode
306  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
307  #define RADIOLIB_NC (0xFF)
308  #define RADIOLIB_DEFAULT_SPI SPI
309  #define RADIOLIB_PROGMEM PROGMEM
310  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
311  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
312  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
313 
314  #elif defined(ARDUINO_ARCH_MEGAAVR)
315  // MegaCoreX by MCUdude (https://github.com/MCUdude/MegaCoreX)
316  #define RADIOLIB_PLATFORM "MegaCoreX"
317  #define RADIOLIB_PIN_TYPE uint8_t
318  #define RADIOLIB_PIN_MODE uint8_t
319  #define RADIOLIB_PIN_STATUS uint8_t
320  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
321  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
322  #define RADIOLIB_NC (0xFF)
323  #define RADIOLIB_DEFAULT_SPI SPI
324  #define RADIOLIB_PROGMEM PROGMEM
325  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
326 
327  #else
328  // other platforms not covered by the above list - this may or may not work
329  #define RADIOLIB_PLATFORM "Unknown"
330  #define RADIOLIB_UNKNOWN_PLATFORM
331  #define RADIOLIB_PIN_TYPE uint8_t
332  #define RADIOLIB_PIN_MODE uint8_t
333  #define RADIOLIB_PIN_STATUS uint8_t
334  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
335  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
336  #define RADIOLIB_NC (0xFF)
337  #define RADIOLIB_DEFAULT_SPI SPI
338  #define RADIOLIB_PROGMEM PROGMEM
339  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
340 
341  #endif
342 #endif
343 
344 /*
345  * Uncomment to enable debug output.
346  * Warning: Debug output will slow down the whole system significantly.
347  * Also, it will result in larger compiled binary.
348  * Levels: debug - only main info
349  * verbose - full transcript of all SPI/UART communication
350  */
351 
352 //#define RADIOLIB_DEBUG
353 //#define RADIOLIB_VERBOSE
354 
355 // set which Serial port should be used for debug output
356 #define RADIOLIB_DEBUG_PORT Serial
357 
358 #if defined(RADIOLIB_DEBUG)
359  #define RADIOLIB_DEBUG_PRINT(...) { RADIOLIB_DEBUG_PORT.print(__VA_ARGS__); }
360  #define RADIOLIB_DEBUG_PRINTLN(...) { RADIOLIB_DEBUG_PORT.println(__VA_ARGS__); }
361 #else
362  #define RADIOLIB_DEBUG_PRINT(...) {}
363  #define RADIOLIB_DEBUG_PRINTLN(...) {}
364 #endif
365 
366 #if defined(RADIOLIB_VERBOSE)
367  #define RADIOLIB_VERBOSE_PRINT(...) { RADIOLIB_DEBUG_PORT.print(__VA_ARGS__); }
368  #define RADIOLIB_VERBOSE_PRINTLN(...) { RADIOLIB_DEBUG_PORT.println(__VA_ARGS__); }
369 #else
370  #define RADIOLIB_VERBOSE_PRINT(...) {}
371  #define RADIOLIB_VERBOSE_PRINTLN(...) {}
372 #endif
373 
374 /*
375  * Uncomment to enable "paranoid" SPI mode
376  * Every write to an SPI register using SPI set function will be verified by a subsequent read operation.
377  * This improves reliablility, but slightly slows down communication.
378  */
379 #define RADIOLIB_SPI_PARANOID
380 
381 /*
382  * Uncomment to enable god mode - all methods and member variables in all classes will be made public, thus making them accessible from Arduino code.
383  * Warning: Come on, it's called GOD mode - obviously only use this if you know what you're doing.
384  * Failure to heed the above warning may result in bricked module.
385  */
386 //#define RADIOLIB_GODMODE
387 
388 /*
389  * Uncomment to enable pre-defined modules when using RadioShield.
390  */
391 //#define RADIOLIB_RADIOSHIELD
392 
393 /*
394  * Uncomment to enable static-only memory management: no dynamic allocation will be performed.
395  * Warning: Large static arrays will be created in some methods. It is not advised to send large packets in this mode.
396  */
397 
398 //#define RADIOLIB_STATIC_ONLY
399 
400 // set the size of static arrays to use
401 #if !defined(RADIOLIB_STATIC_ARRAY_SIZE)
402 #define RADIOLIB_STATIC_ARRAY_SIZE 256
403 #endif
404 
408 #define RADIOLIB_ASSERT(STATEVAR) { if((STATEVAR) != ERR_NONE) { return(STATEVAR); } }
409 
413 #define RADIOLIB_CHECK_RANGE(VAR, MIN, MAX, ERR) { if(!(((VAR) >= (MIN)) && ((VAR) <= (MAX)))) { return(ERR); } }
414 
415 // version definitions
416 #define RADIOLIB_VERSION_MAJOR (0x04)
417 #define RADIOLIB_VERSION_MINOR (0x02)
418 #define RADIOLIB_VERSION_PATCH (0x00)
419 #define RADIOLIB_VERSION_EXTRA (0x00)
420 
421 #define RADIOLIB_VERSION ((RADIOLIB_VERSION_MAJOR << 24) | (RADIOLIB_VERSION_MINOR << 16) | (RADIOLIB_VERSION_PATCH << 8) | (RADIOLIB_VERSION_EXTRA))
422 
423 #endif
+
1 #ifndef _RADIOLIB_BUILD_OPTIONS_H
2 #define _RADIOLIB_BUILD_OPTIONS_H
3 
4 #if ARDUINO >= 100
5  #include "Arduino.h"
6 #else
7  #error "Unsupported Arduino version (< 1.0.0)"
8 #endif
9 
10 /*
11  * Platform-specific configuration.
12  *
13  * RADIOLIB_PLATFORM - platform name, used in debugging to quickly check the correct platform is detected.
14  * RADIOLIB_PIN_TYPE - which type should be used for pin numbers in functions like digitalRead().
15  * RADIOLIB_PIN_MODE - which type should be used for pin modes in functions like pinMode().
16  * RADIOLIB_PIN_STATUS - which type should be used for pin values in functions like digitalWrite().
17  * RADIOLIB_INTERRUPT_STATUS - which type should be used for pin changes in functions like attachInterrupt().
18  * RADIOLIB_DIGITAL_PIN_TO_INTERRUPT - function/macro to be used to convert digital pin number to interrupt pin number.
19  * RADIOLIB_NC - alias for unused pin, usually the largest possible value of RADIOLIB_PIN_TYPE.
20  * RADIOLIB_DEFAULT_SPI - default SPIClass instance to use.
21  * RADIOLIB_PROGMEM - macro to place variable into program storage (usually Flash).
22  * RADIOLIB_PROGMEM_READ_BYTE - function/macro to read variables saved in program storage (usually Flash).
23  * RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED - defined if the specific platform does not support SoftwareSerial.
24  * RADIOLIB_HARDWARE_SERIAL_PORT - which hardware serial port should be used on platform that do not have SoftwareSerial support.
25  * RADIOLIB_TONE_UNSUPPORTED - some platforms do not have tone()/noTone(), which is required for AFSK.
26  *
27  * In addition, some platforms may require RadioLib to disable specific drivers (such as ESP8266).
28  *
29  * Users may also specify their own configuration by uncommenting the RADIOLIB_CUSTOM_PLATFORM,
30  * and then specifying all platform parameters in the section below. This will override automatic
31  * platform detection.
32  */
33 
34 // uncomment to enable custom platform definition
35 //#define RADIOLIB_CUSTOM_PLATFORM
36 
37 #if defined(RADIOLIB_CUSTOM_PLATFORM)
38  // name for your platform
39  #define RADIOLIB_PLATFORM "Custom"
40 
41  // the following parameters must always be defined
42  #define RADIOLIB_PIN_TYPE uint8_t
43  #define RADIOLIB_PIN_MODE uint8_t
44  #define RADIOLIB_PIN_STATUS uint8_t
45  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
46  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
47  #define RADIOLIB_NC (0xFF)
48  #define RADIOLIB_DEFAULT_SPI SPI
49  #define RADIOLIB_PROGMEM PROGMEM
50  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
51 
52  // the following must be defined if the Arduino core does not support SoftwareSerial library
53  //#define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
54  //#define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
55 
56  // the following must be defined if the Arduino core does not support tone function
57  //#define RADIOLIB_TONE_UNSUPPORTED
58 
59  // some platforms seem to have issues with SPI modules that use a command interface
60  // this can be mitigated by adding delays into SPI communication
61  // (see https://github.com/jgromes/RadioLib/issues/158 for details)
62  //#define RADIOLIB_SPI_SLOWDOWN
63 
64  // some of RadioLib drivers may be excluded, to prevent collisions with platforms (or to speed up build process)
65  // the following is a complete list of all possible exclusion macros, uncomment any of them to disable that driver
66  // NOTE: Some of the exclusion macros are dependent on each other. For example, it is not possible to exclude RF69
67  // while keeping SX1231 (because RF69 is the base class for SX1231). The dependency is always uni-directional,
68  // so excluding SX1231 and keeping RF69 is valid.
69  //#define RADIOLIB_EXCLUDE_CC1101
70  //#define RADIOLIB_EXCLUDE_ESP8266
71  //#define RADIOLIB_EXCLUDE_HC05
72  //#define RADIOLIB_EXCLUDE_JDY08
73  //#define RADIOLIB_EXCLUDE_NRF24
74  //#define RADIOLIB_EXCLUDE_RF69
75  //#define RADIOLIB_EXCLUDE_SX1231 // dependent on RADIOLIB_EXCLUDE_RF69
76  //#define RADIOLIB_EXCLUDE_SI443X
77  //#define RADIOLIB_EXCLUDE_RFM2X // dependent on RADIOLIB_EXCLUDE_SI443X
78  //#define RADIOLIB_EXCLUDE_SX127X
79  //#define RADIOLIB_EXCLUDE_RFM9X // dependent on RADIOLIB_EXCLUDE_SX127X
80  //#define RADIOLIB_EXCLUDE_SX126X
81  //#define RADIOLIB_EXCLUDE_SX128X
82  //#define RADIOLIB_EXCLUDE_XBEE
83  //#define RADIOLIB_EXCLUDE_AFSK
84  //#define RADIOLIB_EXCLUDE_AX25
85  //#define RADIOLIB_EXCLUDE_HELLSCHREIBER
86  //#define RADIOLIB_EXCLUDE_HTTP
87  //#define RADIOLIB_EXCLUDE_MORSE
88  //#define RADIOLIB_EXCLUDE_MQTT
89  //#define RADIOLIB_EXCLUDE_RTTY
90  //#define RADIOLIB_EXCLUDE_SSTV
91 
92 #else
93  #if defined(__AVR__) && !(defined(ARDUINO_AVR_UNO_WIFI_REV2) || defined(ARDUINO_AVR_NANO_EVERY) || defined(ARDUINO_ARCH_MEGAAVR))
94  // Arduino AVR boards (except for megaAVR) - Uno, Mega etc.
95  #define RADIOLIB_PLATFORM "Arduino AVR"
96  #define RADIOLIB_PIN_TYPE uint8_t
97  #define RADIOLIB_PIN_MODE uint8_t
98  #define RADIOLIB_PIN_STATUS uint8_t
99  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
100  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
101  #define RADIOLIB_NC (0xFF)
102  #define RADIOLIB_DEFAULT_SPI SPI
103  #define RADIOLIB_PROGMEM PROGMEM
104  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
105 
106  #elif defined(ESP8266)
107  // ESP8266 boards
108  #define RADIOLIB_PLATFORM "ESP8266"
109  #define RADIOLIB_PIN_TYPE uint8_t
110  #define RADIOLIB_PIN_MODE uint8_t
111  #define RADIOLIB_PIN_STATUS uint8_t
112  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
113  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
114  #define RADIOLIB_NC (0xFF)
115  #define RADIOLIB_DEFAULT_SPI SPI
116  #define RADIOLIB_PROGMEM PROGMEM
117  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
118 
119  // RadioLib has ESP8266 driver, this must be disabled to use ESP8266 as platform
120  #define RADIOLIB_EXCLUDE_ESP8266
121 
122  #elif defined(ESP32)
123  // ESP32 boards
124  #define RADIOLIB_PLATFORM "ESP32"
125  #define RADIOLIB_PIN_TYPE uint8_t
126  #define RADIOLIB_PIN_MODE uint8_t
127  #define RADIOLIB_PIN_STATUS uint8_t
128  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
129  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
130  #define RADIOLIB_NC (0xFF)
131  #define RADIOLIB_DEFAULT_SPI SPI
132  #define RADIOLIB_PROGMEM PROGMEM
133  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
134  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
135  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
136 
137  // ESP32 doesn't support tone(), but it can be emulated via LED control peripheral
138  #define RADIOLIB_TONE_UNSUPPORTED
139  #define RADIOLIB_TONE_ESP32_CHANNEL (1)
140 
141  #elif defined(ARDUINO_ARCH_STM32)
142  // official STM32 Arduino core (https://github.com/stm32duino/Arduino_Core_STM32)
143  #define RADIOLIB_PLATFORM "Arduino STM32 (official)"
144  #define RADIOLIB_PIN_TYPE uint32_t
145  #define RADIOLIB_PIN_MODE uint32_t
146  #define RADIOLIB_PIN_STATUS uint32_t
147  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
148  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
149  #define RADIOLIB_NC (0xFFFFFFFF)
150  #define RADIOLIB_DEFAULT_SPI SPI
151  #define RADIOLIB_PROGMEM PROGMEM
152  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
153  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
154  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
155 
156  // slow down SX126x/8x SPI on this platform
157  #define RADIOLIB_SPI_SLOWDOWN
158 
159  #elif defined(SAMD_SERIES)
160  // Adafruit SAMD boards (M0 and M4)
161  #define RADIOLIB_PLATFORM "Adafruit SAMD"
162  #define RADIOLIB_PIN_TYPE uint32_t
163  #define RADIOLIB_PIN_MODE uint32_t
164  #define RADIOLIB_PIN_STATUS uint32_t
165  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
166  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
167  #define RADIOLIB_NC (0xFFFFFFFF)
168  #define RADIOLIB_DEFAULT_SPI SPI
169  #define RADIOLIB_PROGMEM PROGMEM
170  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
171  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
172  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
173 
174  // slow down SX126x/8x SPI on this platform
175  #define RADIOLIB_SPI_SLOWDOWN
176 
177  #elif defined(ARDUINO_ARCH_SAMD)
178  // Arduino SAMD (Zero, MKR, etc.)
179  #define RADIOLIB_PLATFORM "Arduino SAMD"
180  #define RADIOLIB_PIN_TYPE pin_size_t
181  #define RADIOLIB_PIN_MODE PinMode
182  #define RADIOLIB_PIN_STATUS PinStatus
183  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
184  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
185  #define RADIOLIB_NC (0xFF)
186  #define RADIOLIB_DEFAULT_SPI SPI
187  #define RADIOLIB_PROGMEM PROGMEM
188  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
189  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
190  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
191 
192  #elif defined(__SAM3X8E__)
193  // Arduino Due
194  #define RADIOLIB_PLATFORM "Arduino Due"
195  #define RADIOLIB_PIN_TYPE uint32_t
196  #define RADIOLIB_PIN_MODE uint32_t
197  #define RADIOLIB_PIN_STATUS uint32_t
198  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
199  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
200  #define RADIOLIB_NC (0xFFFFFFFF)
201  #define RADIOLIB_DEFAULT_SPI SPI
202  #define RADIOLIB_PROGMEM PROGMEM
203  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
204  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
205  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
206  #define RADIOLIB_TONE_UNSUPPORTED
207 
208  #elif (defined(NRF52832_XXAA) || defined(NRF52840_XXAA)) && !defined(ARDUINO_ARDUINO_NANO33BLE)
209  // Adafruit nRF52 boards
210  #define RADIOLIB_PLATFORM "Adafruit nRF52"
211  #define RADIOLIB_PIN_TYPE uint32_t
212  #define RADIOLIB_PIN_MODE uint32_t
213  #define RADIOLIB_PIN_STATUS uint32_t
214  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
215  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
216  #define RADIOLIB_NC (0xFFFFFFFF)
217  #define RADIOLIB_DEFAULT_SPI SPI
218  #define RADIOLIB_PROGMEM PROGMEM
219  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
220 
221  #elif defined(ARDUINO_ARC32_TOOLS)
222  // Intel Curie
223  #define RADIOLIB_PLATFORM "Intel Curie"
224  #define RADIOLIB_PIN_TYPE uint8_t
225  #define RADIOLIB_PIN_MODE uint8_t
226  #define RADIOLIB_PIN_STATUS uint8_t
227  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
228  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
229  #define RADIOLIB_NC (0xFF)
230  #define RADIOLIB_DEFAULT_SPI SPI
231  #define RADIOLIB_PROGMEM PROGMEM
232  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
233 
234  #elif defined(ARDUINO_AVR_UNO_WIFI_REV2) || defined(ARDUINO_AVR_NANO_EVERY)
235  // Arduino megaAVR boards - Uno Wifi Rev.2, Nano Every
236  #define RADIOLIB_PLATFORM "Arduino megaAVR"
237  #define RADIOLIB_PIN_TYPE uint8_t
238  #define RADIOLIB_PIN_MODE PinMode
239  #define RADIOLIB_PIN_STATUS PinStatus
240  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
241  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
242  #define RADIOLIB_NC (0xFF)
243  #define RADIOLIB_DEFAULT_SPI SPI
244  #define RADIOLIB_PROGMEM PROGMEM
245  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
246 
247  #elif defined(ARDUINO_ARCH_APOLLO3)
248  // Sparkfun Apollo3 boards
249  #define RADIOLIB_PLATFORM "Sparkfun Apollo3"
250  #define RADIOLIB_PIN_TYPE pin_size_t
251  #define RADIOLIB_PIN_MODE Arduino_PinMode
252  #define RADIOLIB_PIN_STATUS PinStatus
253  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
254  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
255  #define RADIOLIB_NC (0xFF)
256  #define RADIOLIB_DEFAULT_SPI SPI
257  #define RADIOLIB_PROGMEM PROGMEM
258  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
259  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
260  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
261 
262  // Apollo3 uses mbed libraries, which already contain ESP8266 driver
263  #define RADIOLIB_EXCLUDE_ESP8266
264 
265  // slow down SX126x/8x SPI on this platform
266  #define RADIOLIB_SPI_SLOWDOWN
267 
268  #elif defined(ARDUINO_ARDUINO_NANO33BLE)
269  // Arduino Nano 33 BLE
270  #define RADIOLIB_PLATFORM "Arduino Nano 33 BLE"
271  #define RADIOLIB_PIN_TYPE pin_size_t
272  #define RADIOLIB_PIN_MODE PinMode
273  #define RADIOLIB_PIN_STATUS PinStatus
274  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
275  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
276  #define RADIOLIB_NC (0xFF)
277  #define RADIOLIB_DEFAULT_SPI SPI
278  #define RADIOLIB_PROGMEM PROGMEM
279  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
280  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
281  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
282 
283  // Nano 33 BLE uses mbed libraries, which already contain ESP8266 driver
284  #define RADIOLIB_EXCLUDE_ESP8266
285 
286  #elif defined(ARDUINO_PORTENTA_H7_M7) || defined(ARDUINO_PORTENTA_H7_M4)
287  // Arduino Portenta H7
288  #define RADIOLIB_PLATFORM "Portenta H7"
289  #define RADIOLIB_PIN_TYPE pin_size_t
290  #define RADIOLIB_PIN_MODE PinMode
291  #define RADIOLIB_PIN_STATUS PinStatus
292  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
293  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
294  #define RADIOLIB_NC (0xFF)
295  #define RADIOLIB_DEFAULT_SPI SPI
296  #define RADIOLIB_PROGMEM PROGMEM
297  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
298  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
299  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
300 
301  // Arduino Portenta H7 uses mbed libraries, which already contain ESP8266 driver
302  #define RADIOLIB_EXCLUDE_ESP8266
303 
304  #elif defined(__STM32F4__) || defined(__STM32F1__)
305  // Arduino STM32 core by Roger Clark (https://github.com/rogerclarkmelbourne/Arduino_STM32)
306  #define RADIOLIB_PLATFORM "STM32duino (unofficial)"
307  #define RADIOLIB_PIN_TYPE uint8_t
308  #define RADIOLIB_PIN_MODE WiringPinMode
309  #define RADIOLIB_PIN_STATUS uint8_t
310  #define RADIOLIB_INTERRUPT_STATUS ExtIntTriggerMode
311  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
312  #define RADIOLIB_NC (0xFF)
313  #define RADIOLIB_DEFAULT_SPI SPI
314  #define RADIOLIB_PROGMEM PROGMEM
315  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
316  #define RADIOLIB_SOFTWARE_SERIAL_UNSUPPORTED
317  #define RADIOLIB_HARDWARE_SERIAL_PORT Serial1
318 
319  #elif defined(ARDUINO_ARCH_MEGAAVR)
320  // MegaCoreX by MCUdude (https://github.com/MCUdude/MegaCoreX)
321  #define RADIOLIB_PLATFORM "MegaCoreX"
322  #define RADIOLIB_PIN_TYPE uint8_t
323  #define RADIOLIB_PIN_MODE uint8_t
324  #define RADIOLIB_PIN_STATUS uint8_t
325  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
326  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
327  #define RADIOLIB_NC (0xFF)
328  #define RADIOLIB_DEFAULT_SPI SPI
329  #define RADIOLIB_PROGMEM PROGMEM
330  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
331 
332  #else
333  // other platforms not covered by the above list - this may or may not work
334  #define RADIOLIB_PLATFORM "Unknown"
335  #define RADIOLIB_UNKNOWN_PLATFORM
336  #define RADIOLIB_PIN_TYPE uint8_t
337  #define RADIOLIB_PIN_MODE uint8_t
338  #define RADIOLIB_PIN_STATUS uint8_t
339  #define RADIOLIB_INTERRUPT_STATUS RADIOLIB_PIN_STATUS
340  #define RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(p) digitalPinToInterrupt(p)
341  #define RADIOLIB_NC (0xFF)
342  #define RADIOLIB_DEFAULT_SPI SPI
343  #define RADIOLIB_PROGMEM PROGMEM
344  #define RADIOLIB_PROGMEM_READ_BYTE(addr) pgm_read_byte(addr)
345 
346  #endif
347 #endif
348 
349 /*
350  * Uncomment to enable debug output.
351  * Warning: Debug output will slow down the whole system significantly.
352  * Also, it will result in larger compiled binary.
353  * Levels: debug - only main info
354  * verbose - full transcript of all SPI/UART communication
355  */
356 
357 //#define RADIOLIB_DEBUG
358 //#define RADIOLIB_VERBOSE
359 
360 // set which Serial port should be used for debug output
361 #define RADIOLIB_DEBUG_PORT Serial
362 
363 #if defined(RADIOLIB_DEBUG)
364  #define RADIOLIB_DEBUG_PRINT(...) { RADIOLIB_DEBUG_PORT.print(__VA_ARGS__); }
365  #define RADIOLIB_DEBUG_PRINTLN(...) { RADIOLIB_DEBUG_PORT.println(__VA_ARGS__); }
366 #else
367  #define RADIOLIB_DEBUG_PRINT(...) {}
368  #define RADIOLIB_DEBUG_PRINTLN(...) {}
369 #endif
370 
371 #if defined(RADIOLIB_VERBOSE)
372  #define RADIOLIB_VERBOSE_PRINT(...) { RADIOLIB_DEBUG_PORT.print(__VA_ARGS__); }
373  #define RADIOLIB_VERBOSE_PRINTLN(...) { RADIOLIB_DEBUG_PORT.println(__VA_ARGS__); }
374 #else
375  #define RADIOLIB_VERBOSE_PRINT(...) {}
376  #define RADIOLIB_VERBOSE_PRINTLN(...) {}
377 #endif
378 
379 /*
380  * Uncomment to enable "paranoid" SPI mode
381  * Every write to an SPI register using SPI set function will be verified by a subsequent read operation.
382  * This improves reliablility, but slightly slows down communication.
383  * Note: Enabled by default.
384  */
385 #define RADIOLIB_SPI_PARANOID
386 
387 /*
388  * Uncomment to enable parameter range checking
389  * RadioLib will check provided parameters (such as frequency) against limits determined by the device manufacturer.
390  * It is highly advised to keep this macro defined, removing it will allow invalid values to be set,
391  * possibly leading to bricked module and/or program crashing.
392  * Note: Enabled by default.
393  */
394 #define RADIOLIB_CHECK_RANGE
395 
396 /*
397  * Uncomment to enable god mode - all methods and member variables in all classes will be made public, thus making them accessible from Arduino code.
398  * Warning: Come on, it's called GOD mode - obviously only use this if you know what you're doing.
399  * Failure to heed the above warning may result in bricked module.
400  */
401 //#define RADIOLIB_GODMODE
402 
403 /*
404  * Uncomment to enable pre-defined modules when using RadioShield.
405  */
406 //#define RADIOLIB_RADIOSHIELD
407 
408 /*
409  * Uncomment to enable static-only memory management: no dynamic allocation will be performed.
410  * Warning: Large static arrays will be created in some methods. It is not advised to send large packets in this mode.
411  */
412 //#define RADIOLIB_STATIC_ONLY
413 
414 // set the size of static arrays to use
415 #if !defined(RADIOLIB_STATIC_ARRAY_SIZE)
416 #define RADIOLIB_STATIC_ARRAY_SIZE 256
417 #endif
418 
422 #define RADIOLIB_ASSERT(STATEVAR) { if((STATEVAR) != ERR_NONE) { return(STATEVAR); } }
423 
427 #if defined(RADIOLIB_CHECK_RANGE)
428 #define RADIOLIB_CHECK_RANGE(VAR, MIN, MAX, ERR) { if(!(((VAR) >= (MIN)) && ((VAR) <= (MAX)))) { return(ERR); } }
429 #else
430 #define RADIOLIB_CHECK_RANGE(VAR, MIN, MAX, ERR) {}
431 #endif
432 
433 // version definitions
434 #define RADIOLIB_VERSION_MAJOR (0x04)
435 #define RADIOLIB_VERSION_MINOR (0x02)
436 #define RADIOLIB_VERSION_PATCH (0x00)
437 #define RADIOLIB_VERSION_EXTRA (0x00)
438 
439 #define RADIOLIB_VERSION ((RADIOLIB_VERSION_MAJOR << 24) | (RADIOLIB_VERSION_MINOR << 16) | (RADIOLIB_VERSION_PATCH << 8) | (RADIOLIB_VERSION_EXTRA))
440 
441 #endif
-
1 #if !defined(_RADIOLIB_SX1272_H)
2 #define _RADIOLIB_SX1272_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1272 specific register map
12 #define SX1272_REG_AGC_REF 0x43
13 #define SX1272_REG_AGC_THRESH_1 0x44
14 #define SX1272_REG_AGC_THRESH_2 0x45
15 #define SX1272_REG_AGC_THRESH_3 0x46
16 #define SX1272_REG_PLL_HOP 0x4B
17 #define SX1272_REG_TCXO 0x58
18 #define SX1272_REG_PA_DAC 0x5A
19 #define SX1272_REG_PLL 0x5C
20 #define SX1272_REG_PLL_LOW_PN 0x5E
21 #define SX1272_REG_FORMER_TEMP 0x6C
22 #define SX1272_REG_BIT_RATE_FRAC 0x70
23 
24 // SX1272 LoRa modem settings
25 // SX1272_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
26 #define SX1272_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
27 #define SX1272_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
28 #define SX1272_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
29 
30 // SX1272_REG_MODEM_CONFIG_1
31 #define SX1272_BW_125_00_KHZ 0b00000000 // 7 6 bandwidth: 125 kHz
32 #define SX1272_BW_250_00_KHZ 0b01000000 // 7 6 250 kHz
33 #define SX1272_BW_500_00_KHZ 0b10000000 // 7 6 500 kHz
34 #define SX1272_CR_4_5 0b00001000 // 5 3 error coding rate: 4/5
35 #define SX1272_CR_4_6 0b00010000 // 5 3 4/6
36 #define SX1272_CR_4_7 0b00011000 // 5 3 4/7
37 #define SX1272_CR_4_8 0b00100000 // 5 3 4/8
38 #define SX1272_HEADER_EXPL_MODE 0b00000000 // 2 2 explicit header mode
39 #define SX1272_HEADER_IMPL_MODE 0b00000100 // 2 2 implicit header mode
40 #define SX1272_RX_CRC_MODE_OFF 0b00000000 // 1 1 CRC disabled
41 #define SX1272_RX_CRC_MODE_ON 0b00000010 // 1 1 CRC enabled
42 #define SX1272_LOW_DATA_RATE_OPT_OFF 0b00000000 // 0 0 low data rate optimization disabled
43 #define SX1272_LOW_DATA_RATE_OPT_ON 0b00000001 // 0 0 low data rate optimization enabled, mandatory for SF 11 and 12 with BW 125 kHz
44 
45 // SX1272_REG_MODEM_CONFIG_2
46 #define SX1272_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
47 #define SX1272_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
48 
49 // SX127X_REG_VERSION
50 #define SX1272_CHIP_VERSION 0x22
51 
52 // SX1272 FSK modem settings
53 // SX127X_REG_OP_MODE
54 #define SX1272_NO_SHAPING 0b00000000 // 4 3 data shaping: no shaping (default)
55 #define SX1272_FSK_GAUSSIAN_1_0 0b00001000 // 4 3 FSK modulation Gaussian filter, BT = 1.0
56 #define SX1272_FSK_GAUSSIAN_0_5 0b00010000 // 4 3 FSK modulation Gaussian filter, BT = 0.5
57 #define SX1272_FSK_GAUSSIAN_0_3 0b00011000 // 4 3 FSK modulation Gaussian filter, BT = 0.3
58 #define SX1272_OOK_FILTER_BR 0b00001000 // 4 3 OOK modulation filter, f_cutoff = BR
59 #define SX1272_OOK_FILTER_2BR 0b00010000 // 4 3 OOK modulation filter, f_cutoff = 2*BR
60 
61 // SX127X_REG_PA_RAMP
62 #define SX1272_LOW_PN_TX_PLL_OFF 0b00010000 // 4 4 use standard PLL in transmit mode (default)
63 #define SX1272_LOW_PN_TX_PLL_ON 0b00000000 // 4 4 use lower phase noise PLL in transmit mode
64 
65 // SX127X_REG_SYNC_CONFIG
66 #define SX1272_FIFO_FILL_CONDITION_SYNC_ADDRESS 0b00000000 // 3 3 FIFO will be filled when sync address interrupt occurs (default)
67 #define SX1272_FIFO_FILL_CONDITION_ALWAYS 0b00001000 // 3 3 FIFO will be filled as long as this bit is set
68 
69 // SX1272_REG_AGC_REF
70 #define SX1272_AGC_REFERENCE_LEVEL 0x13 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]
71 
72 // SX1272_REG_AGC_THRESH_1
73 #define SX1272_AGC_STEP_1 0x0E // 4 0 1st AGC threshold
74 
75 // SX1272_REG_AGC_THRESH_2
76 #define SX1272_AGC_STEP_2 0x50 // 7 4 2nd AGC threshold
77 #define SX1272_AGC_STEP_3 0x0B // 4 0 3rd AGC threshold
78 
79 // SX1272_REG_AGC_THRESH_3
80 #define SX1272_AGC_STEP_4 0xD0 // 7 4 4th AGC threshold
81 #define SX1272_AGC_STEP_5 0x0B // 4 0 5th AGC threshold
82 
83 // SX1272_REG_PLL_LOW_PN
84 #define SX1272_PLL_LOW_PN_BANDWIDTH_75_KHZ 0b00000000 // 7 6 low phase noise PLL bandwidth: 75 kHz
85 #define SX1272_PLL_LOW_PN_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
86 #define SX1272_PLL_LOW_PN_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
87 #define SX1272_PLL_LOW_PN_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
88 
95 class SX1272: public SX127x {
96  public:
97 
98  // constructor
99 
105  SX1272(Module* mod);
106 
107  // basic methods
108 
133  int16_t begin(float freq = 915.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
134 
155  int16_t beginFSK(float freq = 915.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
156 
160  void reset() override;
161 
162  // configuration methods
163 
171  int16_t setFrequency(float freq);
172 
180  int16_t setBandwidth(float bw);
181 
189  int16_t setSpreadingFactor(uint8_t sf);
190 
198  int16_t setCodingRate(uint8_t cr);
199 
207  int16_t setOutputPower(int8_t power);
208 
217  int16_t setGain(uint8_t gain);
218 
227  int16_t setDataShaping(uint8_t sh) override;
228 
238  int16_t setDataShapingOOK(uint8_t sh);
239 
245  float getRSSI();
246 
254  int16_t setCRC(bool enableCRC);
255 
264  int16_t forceLDRO(bool enable);
265 
272  int16_t autoLDRO();
273 
274 #ifndef RADIOLIB_GODMODE
275  protected:
276 #endif
277  int16_t setBandwidthRaw(uint8_t newBandwidth);
278  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
279  int16_t setCodingRateRaw(uint8_t newCodingRate);
280 
281  int16_t configFSK();
282 
283 #ifndef RADIOLIB_GODMODE
284  private:
285 #endif
286  bool _ldroAuto = true;
287  bool _ldroEnabled = false;
288 
289 };
290 
291 #endif
292 
293 #endif
SX1272
Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic...
Definition: SX1272.h:95
+
1 #if !defined(_RADIOLIB_SX1272_H)
2 #define _RADIOLIB_SX1272_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1272 specific register map
12 #define SX1272_REG_AGC_REF 0x43
13 #define SX1272_REG_AGC_THRESH_1 0x44
14 #define SX1272_REG_AGC_THRESH_2 0x45
15 #define SX1272_REG_AGC_THRESH_3 0x46
16 #define SX1272_REG_PLL_HOP 0x4B
17 #define SX1272_REG_TCXO 0x58
18 #define SX1272_REG_PA_DAC 0x5A
19 #define SX1272_REG_PLL 0x5C
20 #define SX1272_REG_PLL_LOW_PN 0x5E
21 #define SX1272_REG_FORMER_TEMP 0x6C
22 #define SX1272_REG_BIT_RATE_FRAC 0x70
23 
24 // SX1272 LoRa modem settings
25 // SX1272_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
26 #define SX1272_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
27 #define SX1272_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
28 #define SX1272_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
29 
30 // SX127X_REG_MODEM_CONFIG_1
31 #define SX1272_BW_125_00_KHZ 0b00000000 // 7 6 bandwidth: 125 kHz
32 #define SX1272_BW_250_00_KHZ 0b01000000 // 7 6 250 kHz
33 #define SX1272_BW_500_00_KHZ 0b10000000 // 7 6 500 kHz
34 #define SX1272_CR_4_5 0b00001000 // 5 3 error coding rate: 4/5
35 #define SX1272_CR_4_6 0b00010000 // 5 3 4/6
36 #define SX1272_CR_4_7 0b00011000 // 5 3 4/7
37 #define SX1272_CR_4_8 0b00100000 // 5 3 4/8
38 #define SX1272_HEADER_EXPL_MODE 0b00000000 // 2 2 explicit header mode
39 #define SX1272_HEADER_IMPL_MODE 0b00000100 // 2 2 implicit header mode
40 #define SX1272_RX_CRC_MODE_OFF 0b00000000 // 1 1 CRC disabled
41 #define SX1272_RX_CRC_MODE_ON 0b00000010 // 1 1 CRC enabled
42 #define SX1272_LOW_DATA_RATE_OPT_OFF 0b00000000 // 0 0 low data rate optimization disabled
43 #define SX1272_LOW_DATA_RATE_OPT_ON 0b00000001 // 0 0 low data rate optimization enabled, mandatory for SF 11 and 12 with BW 125 kHz
44 
45 // SX127X_REG_MODEM_CONFIG_2
46 #define SX1272_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
47 #define SX1272_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
48 
49 // SX127X_REG_VERSION
50 #define SX1272_CHIP_VERSION 0x22
51 
52 // SX1272 FSK modem settings
53 // SX127X_REG_OP_MODE
54 #define SX1272_NO_SHAPING 0b00000000 // 4 3 data shaping: no shaping (default)
55 #define SX1272_FSK_GAUSSIAN_1_0 0b00001000 // 4 3 FSK modulation Gaussian filter, BT = 1.0
56 #define SX1272_FSK_GAUSSIAN_0_5 0b00010000 // 4 3 FSK modulation Gaussian filter, BT = 0.5
57 #define SX1272_FSK_GAUSSIAN_0_3 0b00011000 // 4 3 FSK modulation Gaussian filter, BT = 0.3
58 #define SX1272_OOK_FILTER_BR 0b00001000 // 4 3 OOK modulation filter, f_cutoff = BR
59 #define SX1272_OOK_FILTER_2BR 0b00010000 // 4 3 OOK modulation filter, f_cutoff = 2*BR
60 
61 // SX127X_REG_PA_RAMP
62 #define SX1272_LOW_PN_TX_PLL_OFF 0b00010000 // 4 4 use standard PLL in transmit mode (default)
63 #define SX1272_LOW_PN_TX_PLL_ON 0b00000000 // 4 4 use lower phase noise PLL in transmit mode
64 
65 // SX127X_REG_SYNC_CONFIG
66 #define SX1272_FIFO_FILL_CONDITION_SYNC_ADDRESS 0b00000000 // 3 3 FIFO will be filled when sync address interrupt occurs (default)
67 #define SX1272_FIFO_FILL_CONDITION_ALWAYS 0b00001000 // 3 3 FIFO will be filled as long as this bit is set
68 
69 // SX1272_REG_AGC_REF
70 #define SX1272_AGC_REFERENCE_LEVEL 0x13 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]
71 
72 // SX1272_REG_AGC_THRESH_1
73 #define SX1272_AGC_STEP_1 0x0E // 4 0 1st AGC threshold
74 
75 // SX1272_REG_AGC_THRESH_2
76 #define SX1272_AGC_STEP_2 0x50 // 7 4 2nd AGC threshold
77 #define SX1272_AGC_STEP_3 0x0B // 4 0 3rd AGC threshold
78 
79 // SX1272_REG_AGC_THRESH_3
80 #define SX1272_AGC_STEP_4 0xD0 // 7 4 4th AGC threshold
81 #define SX1272_AGC_STEP_5 0x0B // 4 0 5th AGC threshold
82 
83 // SX1272_REG_PLL_LOW_PN
84 #define SX1272_PLL_LOW_PN_BANDWIDTH_75_KHZ 0b00000000 // 7 6 low phase noise PLL bandwidth: 75 kHz
85 #define SX1272_PLL_LOW_PN_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
86 #define SX1272_PLL_LOW_PN_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
87 #define SX1272_PLL_LOW_PN_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
88 
95 class SX1272: public SX127x {
96  public:
97 
98  // constructor
99 
105  SX1272(Module* mod);
106 
107  // basic methods
108 
133  int16_t begin(float freq = 915.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
134 
155  int16_t beginFSK(float freq = 915.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
156 
160  void reset() override;
161 
162  // configuration methods
163 
171  int16_t setFrequency(float freq);
172 
180  int16_t setBandwidth(float bw);
181 
189  int16_t setSpreadingFactor(uint8_t sf);
190 
198  int16_t setCodingRate(uint8_t cr);
199 
207  int16_t setOutputPower(int8_t power);
208 
217  int16_t setGain(uint8_t gain);
218 
227  int16_t setDataShaping(uint8_t sh) override;
228 
238  int16_t setDataShapingOOK(uint8_t sh);
239 
245  float getRSSI();
246 
254  int16_t setCRC(bool enableCRC);
255 
264  int16_t forceLDRO(bool enable);
265 
272  int16_t autoLDRO();
273 
279  int16_t implicitHeader(size_t len);
280 
288  int16_t explicitHeader();
289 
290 #ifndef RADIOLIB_GODMODE
291  protected:
292 #endif
293  int16_t setBandwidthRaw(uint8_t newBandwidth);
294  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
295  int16_t setCodingRateRaw(uint8_t newCodingRate);
296  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
297 
298  int16_t configFSK();
299 
300 #ifndef RADIOLIB_GODMODE
301  private:
302 #endif
303  bool _ldroAuto = true;
304  bool _ldroEnabled = false;
305 
306 };
307 
308 #endif
309 
310 #endif
SX1272
Derived class for SX1272 modules. Also used as base class for SX1273. Both modules use the same basic...
Definition: SX1272.h:95
SX1272::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 860.0 MHz to 1020.0 MHz.
Definition: SX1272.cpp:70
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
SX1272::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:389
@@ -101,8 +101,10 @@ $(document).ready(function(){initNavTree('_s_x1272_8h_source.html','');});
SX1272::setCodingRate
int16_t setCodingRate(uint8_t cr)
Sets LoRa link coding rate denominator. Allowed values range from 5 to 8. Only available in LoRa mode...
Definition: SX1272.cpp:177
SX1272::setSpreadingFactor
int16_t setSpreadingFactor(uint8_t sf)
Sets LoRa link spreading factor. Allowed values range from 6 to 12. Only available in LoRa mode...
Definition: SX1272.cpp:121
SX1272::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1272.cpp:265
+
SX1272::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX1272.cpp:398
SX1272::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1272.cpp:376
SX1272::reset
void reset() override
Reset method. Will reset the chip to the default state using RST pin.
Definition: SX1272.cpp:62
+
SX1272::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX1272.cpp:402
diff --git a/_s_x1278_8h_source.html b/_s_x1278_8h_source.html index b4cd91f5..3ce56bbf 100644 --- a/_s_x1278_8h_source.html +++ b/_s_x1278_8h_source.html @@ -84,12 +84,14 @@ $(document).ready(function(){initNavTree('_s_x1278_8h_source.html','');});
SX1278.h
-
1 #if !defined(_RADIOLIB_SX1278_H)
2 #define _RADIOLIB_SX1278_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1278 specific register map
12 #define SX1278_REG_MODEM_CONFIG_3 0x26
13 #define SX1278_REG_PLL_HOP 0x44
14 #define SX1278_REG_TCXO 0x4B
15 #define SX1278_REG_PA_DAC 0x4D
16 #define SX1278_REG_FORMER_TEMP 0x5B
17 #define SX1278_REG_REG_BIT_RATE_FRAC 0x5D
18 #define SX1278_REG_AGC_REF 0x61
19 #define SX1278_REG_AGC_THRESH_1 0x62
20 #define SX1278_REG_AGC_THRESH_2 0x63
21 #define SX1278_REG_AGC_THRESH_3 0x64
22 #define SX1278_REG_PLL 0x70
23 
24 // SX1278 LoRa modem settings
25 // SX1278_REG_OP_MODE MSB LSB DESCRIPTION
26 #define SX1278_HIGH_FREQ 0b00000000 // 3 3 access HF test registers
27 #define SX1278_LOW_FREQ 0b00001000 // 3 3 access LF test registers
28 
29 // SX1278_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
30 #define SX1278_FRF_MSB 0x6C // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
31 #define SX1278_FRF_MID 0x80 // 7 0 where F(XOSC) = 32 MHz
32 #define SX1278_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
33 
34 // SX1278_REG_PA_CONFIG
35 #define SX1278_MAX_POWER 0b01110000 // 6 4 max power: P_max = 10.8 + 0.6*MAX_POWER [dBm]; P_max(MAX_POWER = 0b111) = 15 dBm
36 #define SX1278_LOW_POWER 0b00100000 // 6 4
37 
38 // SX1278_REG_LNA
39 #define SX1278_LNA_BOOST_LF_OFF 0b00000000 // 4 3 default LNA current
40 
41 // SX1278_REG_MODEM_CONFIG_1
42 #define SX1278_BW_7_80_KHZ 0b00000000 // 7 4 bandwidth: 7.80 kHz
43 #define SX1278_BW_10_40_KHZ 0b00010000 // 7 4 10.40 kHz
44 #define SX1278_BW_15_60_KHZ 0b00100000 // 7 4 15.60 kHz
45 #define SX1278_BW_20_80_KHZ 0b00110000 // 7 4 20.80 kHz
46 #define SX1278_BW_31_25_KHZ 0b01000000 // 7 4 31.25 kHz
47 #define SX1278_BW_41_70_KHZ 0b01010000 // 7 4 41.70 kHz
48 #define SX1278_BW_62_50_KHZ 0b01100000 // 7 4 62.50 kHz
49 #define SX1278_BW_125_00_KHZ 0b01110000 // 7 4 125.00 kHz
50 #define SX1278_BW_250_00_KHZ 0b10000000 // 7 4 250.00 kHz
51 #define SX1278_BW_500_00_KHZ 0b10010000 // 7 4 500.00 kHz
52 #define SX1278_CR_4_5 0b00000010 // 3 1 error coding rate: 4/5
53 #define SX1278_CR_4_6 0b00000100 // 3 1 4/6
54 #define SX1278_CR_4_7 0b00000110 // 3 1 4/7
55 #define SX1278_CR_4_8 0b00001000 // 3 1 4/8
56 #define SX1278_HEADER_EXPL_MODE 0b00000000 // 0 0 explicit header mode
57 #define SX1278_HEADER_IMPL_MODE 0b00000001 // 0 0 implicit header mode
58 
59 // SX1278_REG_MODEM_CONFIG_2
60 #define SX1278_RX_CRC_MODE_OFF 0b00000000 // 2 2 CRC disabled
61 #define SX1278_RX_CRC_MODE_ON 0b00000100 // 2 2 CRC enabled
62 
63 // SX1278_REG_MODEM_CONFIG_3
64 #define SX1278_LOW_DATA_RATE_OPT_OFF 0b00000000 // 3 3 low data rate optimization disabled
65 #define SX1278_LOW_DATA_RATE_OPT_ON 0b00001000 // 3 3 low data rate optimization enabled
66 #define SX1278_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
67 #define SX1278_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
68 
69 // SX127X_REG_VERSION
70 #define SX1278_CHIP_VERSION 0x12
71 
72 // SX1278 FSK modem settings
73 // SX127X_REG_PA_RAMP
74 #define SX1278_NO_SHAPING 0b00000000 // 6 5 data shaping: no shaping (default)
75 #define SX1278_FSK_GAUSSIAN_1_0 0b00100000 // 6 5 FSK modulation Gaussian filter, BT = 1.0
76 #define SX1278_FSK_GAUSSIAN_0_5 0b01000000 // 6 5 FSK modulation Gaussian filter, BT = 0.5
77 #define SX1278_FSK_GAUSSIAN_0_3 0b01100000 // 6 5 FSK modulation Gaussian filter, BT = 0.3
78 #define SX1278_OOK_FILTER_BR 0b00100000 // 6 5 OOK modulation filter, f_cutoff = BR
79 #define SX1278_OOK_FILTER_2BR 0b01000000 // 6 5 OOK modulation filter, f_cutoff = 2*BR
80 
81 // SX1278_REG_AGC_REF
82 #define SX1278_AGC_REFERENCE_LEVEL_LF 0x19 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]: below 525 MHz
83 #define SX1278_AGC_REFERENCE_LEVEL_HF 0x1C // 5 0 above 779 MHz
84 
85 // SX1278_REG_AGC_THRESH_1
86 #define SX1278_AGC_STEP_1_LF 0x0C // 4 0 1st AGC threshold: below 525 MHz
87 #define SX1278_AGC_STEP_1_HF 0x0E // 4 0 above 779 MHz
88 
89 // SX1278_REG_AGC_THRESH_2
90 #define SX1278_AGC_STEP_2_LF 0x40 // 7 4 2nd AGC threshold: below 525 MHz
91 #define SX1278_AGC_STEP_2_HF 0x50 // 7 4 above 779 MHz
92 #define SX1278_AGC_STEP_3 0x0B // 3 0 3rd AGC threshold
93 
94 // SX1278_REG_AGC_THRESH_3
95 #define SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold
96 #define SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold
97 
104 class SX1278: public SX127x {
105  public:
106 
107  // constructor
108 
114  SX1278(Module* mod);
115 
116  // basic methods
117 
141  int16_t begin(float freq = 434.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
142 
163  int16_t beginFSK(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
164 
168  void reset() override;
169 
170  // configuration methods
171 
179  int16_t setFrequency(float freq);
180 
188  int16_t setBandwidth(float bw);
189 
197  int16_t setSpreadingFactor(uint8_t sf);
198 
206  int16_t setCodingRate(uint8_t cr);
207 
215  int16_t setOutputPower(int8_t power);
216 
225  int16_t setGain(uint8_t gain);
226 
235  int16_t setDataShaping(uint8_t sh) override;
236 
246  int16_t setDataShapingOOK(uint8_t sh);
247 
253  float getRSSI();
254 
262  int16_t setCRC(bool enableCRC);
263 
272  int16_t forceLDRO(bool enable);
273 
280  int16_t autoLDRO();
281 
282 #ifndef RADIOLIB_GODMODE
283  protected:
284 #endif
285  int16_t setBandwidthRaw(uint8_t newBandwidth);
286  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
287  int16_t setCodingRateRaw(uint8_t newCodingRate);
288 
289  int16_t configFSK();
290 
291 #ifndef RADIOLIB_GODMODE
292  private:
293 #endif
294  bool _ldroAuto = true;
295  bool _ldroEnabled = false;
296 
297 };
298 
299 #endif
300 
301 #endif
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
+
1 #if !defined(_RADIOLIB_SX1278_H)
2 #define _RADIOLIB_SX1278_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 #include "SX127x.h"
10 
11 // SX1278 specific register map
12 #define SX1278_REG_MODEM_CONFIG_3 0x26
13 #define SX1278_REG_PLL_HOP 0x44
14 #define SX1278_REG_TCXO 0x4B
15 #define SX1278_REG_PA_DAC 0x4D
16 #define SX1278_REG_FORMER_TEMP 0x5B
17 #define SX1278_REG_REG_BIT_RATE_FRAC 0x5D
18 #define SX1278_REG_AGC_REF 0x61
19 #define SX1278_REG_AGC_THRESH_1 0x62
20 #define SX1278_REG_AGC_THRESH_2 0x63
21 #define SX1278_REG_AGC_THRESH_3 0x64
22 #define SX1278_REG_PLL 0x70
23 
24 // SX1278 LoRa modem settings
25 // SX1278_REG_OP_MODE MSB LSB DESCRIPTION
26 #define SX1278_HIGH_FREQ 0b00000000 // 3 3 access HF test registers
27 #define SX1278_LOW_FREQ 0b00001000 // 3 3 access LF test registers
28 
29 // SX1278_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
30 #define SX1278_FRF_MSB 0x6C // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
31 #define SX1278_FRF_MID 0x80 // 7 0 where F(XOSC) = 32 MHz
32 #define SX1278_FRF_LSB 0x00 // 7 0 FRF = 3 byte value of FRF registers
33 
34 // SX1278_REG_PA_CONFIG
35 #define SX1278_MAX_POWER 0b01110000 // 6 4 max power: P_max = 10.8 + 0.6*MAX_POWER [dBm]; P_max(MAX_POWER = 0b111) = 15 dBm
36 #define SX1278_LOW_POWER 0b00100000 // 6 4
37 
38 // SX1278_REG_LNA
39 #define SX1278_LNA_BOOST_LF_OFF 0b00000000 // 4 3 default LNA current
40 
41 // SX127X_REG_MODEM_CONFIG_1
42 #define SX1278_BW_7_80_KHZ 0b00000000 // 7 4 bandwidth: 7.80 kHz
43 #define SX1278_BW_10_40_KHZ 0b00010000 // 7 4 10.40 kHz
44 #define SX1278_BW_15_60_KHZ 0b00100000 // 7 4 15.60 kHz
45 #define SX1278_BW_20_80_KHZ 0b00110000 // 7 4 20.80 kHz
46 #define SX1278_BW_31_25_KHZ 0b01000000 // 7 4 31.25 kHz
47 #define SX1278_BW_41_70_KHZ 0b01010000 // 7 4 41.70 kHz
48 #define SX1278_BW_62_50_KHZ 0b01100000 // 7 4 62.50 kHz
49 #define SX1278_BW_125_00_KHZ 0b01110000 // 7 4 125.00 kHz
50 #define SX1278_BW_250_00_KHZ 0b10000000 // 7 4 250.00 kHz
51 #define SX1278_BW_500_00_KHZ 0b10010000 // 7 4 500.00 kHz
52 #define SX1278_CR_4_5 0b00000010 // 3 1 error coding rate: 4/5
53 #define SX1278_CR_4_6 0b00000100 // 3 1 4/6
54 #define SX1278_CR_4_7 0b00000110 // 3 1 4/7
55 #define SX1278_CR_4_8 0b00001000 // 3 1 4/8
56 #define SX1278_HEADER_EXPL_MODE 0b00000000 // 0 0 explicit header mode
57 #define SX1278_HEADER_IMPL_MODE 0b00000001 // 0 0 implicit header mode
58 
59 // SX127X_REG_MODEM_CONFIG_2
60 #define SX1278_RX_CRC_MODE_OFF 0b00000000 // 2 2 CRC disabled
61 #define SX1278_RX_CRC_MODE_ON 0b00000100 // 2 2 CRC enabled
62 
63 // SX1278_REG_MODEM_CONFIG_3
64 #define SX1278_LOW_DATA_RATE_OPT_OFF 0b00000000 // 3 3 low data rate optimization disabled
65 #define SX1278_LOW_DATA_RATE_OPT_ON 0b00001000 // 3 3 low data rate optimization enabled
66 #define SX1278_AGC_AUTO_OFF 0b00000000 // 2 2 LNA gain set by REG_LNA
67 #define SX1278_AGC_AUTO_ON 0b00000100 // 2 2 LNA gain set by internal AGC loop
68 
69 // SX127X_REG_VERSION
70 #define SX1278_CHIP_VERSION 0x12
71 
72 // SX1278 FSK modem settings
73 // SX127X_REG_PA_RAMP
74 #define SX1278_NO_SHAPING 0b00000000 // 6 5 data shaping: no shaping (default)
75 #define SX1278_FSK_GAUSSIAN_1_0 0b00100000 // 6 5 FSK modulation Gaussian filter, BT = 1.0
76 #define SX1278_FSK_GAUSSIAN_0_5 0b01000000 // 6 5 FSK modulation Gaussian filter, BT = 0.5
77 #define SX1278_FSK_GAUSSIAN_0_3 0b01100000 // 6 5 FSK modulation Gaussian filter, BT = 0.3
78 #define SX1278_OOK_FILTER_BR 0b00100000 // 6 5 OOK modulation filter, f_cutoff = BR
79 #define SX1278_OOK_FILTER_2BR 0b01000000 // 6 5 OOK modulation filter, f_cutoff = 2*BR
80 
81 // SX1278_REG_AGC_REF
82 #define SX1278_AGC_REFERENCE_LEVEL_LF 0x19 // 5 0 floor reference for AGC thresholds: AgcRef = -174 + 10*log(2*RxBw) + 8 + AGC_REFERENCE_LEVEL [dBm]: below 525 MHz
83 #define SX1278_AGC_REFERENCE_LEVEL_HF 0x1C // 5 0 above 779 MHz
84 
85 // SX1278_REG_AGC_THRESH_1
86 #define SX1278_AGC_STEP_1_LF 0x0C // 4 0 1st AGC threshold: below 525 MHz
87 #define SX1278_AGC_STEP_1_HF 0x0E // 4 0 above 779 MHz
88 
89 // SX1278_REG_AGC_THRESH_2
90 #define SX1278_AGC_STEP_2_LF 0x40 // 7 4 2nd AGC threshold: below 525 MHz
91 #define SX1278_AGC_STEP_2_HF 0x50 // 7 4 above 779 MHz
92 #define SX1278_AGC_STEP_3 0x0B // 3 0 3rd AGC threshold
93 
94 // SX1278_REG_AGC_THRESH_3
95 #define SX1278_AGC_STEP_4 0xC0 // 7 4 4th AGC threshold
96 #define SX1278_AGC_STEP_5 0x0C // 4 0 5th AGC threshold
97 
104 class SX1278: public SX127x {
105  public:
106 
107  // constructor
108 
114  SX1278(Module* mod);
115 
116  // basic methods
117 
141  int16_t begin(float freq = 434.0, float bw = 125.0, uint8_t sf = 9, uint8_t cr = 7, uint8_t syncWord = SX127X_SYNC_WORD, int8_t power = 10, uint16_t preambleLength = 8, uint8_t gain = 0);
142 
163  int16_t beginFSK(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint16_t preambleLength = 16, bool enableOOK = false);
164 
168  void reset() override;
169 
170  // configuration methods
171 
179  int16_t setFrequency(float freq);
180 
188  int16_t setBandwidth(float bw);
189 
197  int16_t setSpreadingFactor(uint8_t sf);
198 
206  int16_t setCodingRate(uint8_t cr);
207 
215  int16_t setOutputPower(int8_t power);
216 
225  int16_t setGain(uint8_t gain);
226 
235  int16_t setDataShaping(uint8_t sh) override;
236 
246  int16_t setDataShapingOOK(uint8_t sh);
247 
253  float getRSSI();
254 
262  int16_t setCRC(bool enableCRC);
263 
272  int16_t forceLDRO(bool enable);
273 
280  int16_t autoLDRO();
281 
287  int16_t implicitHeader(size_t len);
288 
296  int16_t explicitHeader();
297 
298 #ifndef RADIOLIB_GODMODE
299  protected:
300 #endif
301  int16_t setBandwidthRaw(uint8_t newBandwidth);
302  int16_t setSpreadingFactorRaw(uint8_t newSpreadingFactor);
303  int16_t setCodingRateRaw(uint8_t newCodingRate);
304  int16_t setHeaderType(uint8_t headerType, size_t len = 0xFF);
305 
306  int16_t configFSK();
307 
308 #ifndef RADIOLIB_GODMODE
309  private:
310 #endif
311  bool _ldroAuto = true;
312  bool _ldroEnabled = false;
313 
314 };
315 
316 #endif
317 
318 #endif
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
SX1278::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: SX1278.cpp:337
SX1278::getRSSI
float getRSSI()
Gets recorded signal strength indicator of the latest received packet for LoRa modem, or current RSSI level for FSK modem.
Definition: SX1278.cpp:399
SX1278::forceLDRO
int16_t forceLDRO(bool enable)
Forces LoRa low data rate optimization. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:454
+
SX1278::implicitHeader
int16_t implicitHeader(size_t len)
Set implicit header mode for future reception/transmission.
Definition: SX1278.cpp:476
SX1278::setGain
int16_t setGain(uint8_t gain)
Sets gain of receiver LNA (low-noise amplifier). Can be set to any integer in range 1 to 6 where 1 is...
Definition: SX1278.cpp:312
SX1278::autoLDRO
int16_t autoLDRO()
Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method...
Definition: SX1278.cpp:467
+
SX1278::explicitHeader
int16_t explicitHeader()
Set explicit header mode for future reception/transmission.
Definition: SX1278.cpp:480
SX1278::setFrequency
int16_t setFrequency(float freq)
Sets carrier frequency. Allowed values range from 137.0 MHz to 525.0 MHz.
Definition: SX1278.cpp:65
SX1278::setCRC
int16_t setCRC(bool enableCRC)
Enables/disables CRC check of received packets.
Definition: SX1278.cpp:435
SX1278::beginFSK
int16_t beginFSK(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=125.0, int8_t power=10, uint16_t preambleLength=16, bool enableOOK=false)
FSK modem initialization method. Must be called at least once from Arduino sketch to initialize the m...
Definition: SX1278.cpp:35
diff --git a/_s_x127x_8h_source.html b/_s_x127x_8h_source.html index 68a2ab92..5427f116 100644 --- a/_s_x127x_8h_source.html +++ b/_s_x127x_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x.h
-
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
946  int16_t getChipVersion();
947 
948 #ifndef RADIOLIB_GODMODE
949  protected:
950 #endif
951  Module* _mod;
952 
953  float _freq = 0;
954  float _bw = 0;
955  uint8_t _sf = 0;
956  uint8_t _cr = 0;
957  float _br = 0;
958  float _rxBw = 0;
959  bool _ook = false;
960  bool _crcEnabled = false;
961 
962  int16_t setFrequencyRaw(float newFreq);
963  int16_t config();
964  int16_t configFSK();
965  int16_t getActiveModem();
966  int16_t directMode();
967  int16_t setPacketMode(uint8_t mode, uint8_t len);
968 
969 #ifndef RADIOLIB_GODMODE
970  private:
971 #endif
972  float _dataRate = 0;
973  size_t _packetLength = 0;
974  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
975  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
976 
977  bool findChip(uint8_t ver);
978  int16_t setMode(uint8_t mode);
979  int16_t setActiveModem(uint8_t modem);
980  void clearIRQFlags();
981  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
982 };
983 
984 #endif
985 
986 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:909
+
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
946  int16_t getChipVersion();
947 
948 #ifndef RADIOLIB_GODMODE
949  protected:
950 #endif
951  Module* _mod;
952 
953  float _freq = 0;
954  float _bw = 0;
955  uint8_t _sf = 0;
956  uint8_t _cr = 0;
957  float _br = 0;
958  float _rxBw = 0;
959  bool _ook = false;
960  bool _crcEnabled = false;
961  size_t _packetLength = 0;
962 
963  int16_t setFrequencyRaw(float newFreq);
964  int16_t config();
965  int16_t configFSK();
966  int16_t getActiveModem();
967  int16_t directMode();
968  int16_t setPacketMode(uint8_t mode, uint8_t len);
969 
970 #ifndef RADIOLIB_GODMODE
971  private:
972 #endif
973  float _dataRate = 0;
974  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
975  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
976 
977  bool findChip(uint8_t ver);
978  int16_t setMode(uint8_t mode);
979  int16_t setActiveModem(uint8_t modem);
980  void clearIRQFlags();
981  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
982 };
983 
984 #endif
985 
986 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:909
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:873
SX127x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: SX127x.cpp:485
diff --git a/class_r_f69.html b/class_r_f69.html index 66a830cf..58eb266b 100644 --- a/class_r_f69.html +++ b/class_r_f69.html @@ -890,7 +890,7 @@ void 
Parameters
- +
crcOnSet or unset promiscuous mode.
crcOnSet or unset CRC filtering.
diff --git a/class_r_f_m95-members.html b/class_r_f_m95-members.html index aced2c7a..1cdb3927 100644 --- a/class_r_f_m95-members.html +++ b/class_r_f_m95-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_r_f_m95.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_r_f_m95.html b/class_r_f_m95.html index a2bfc689..bfec4068 100644 --- a/class_r_f_m95.html +++ b/class_r_f_m95.html @@ -166,6 +166,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_r_f_m96-members.html b/class_r_f_m96-members.html index 3bba9c94..5c747c82 100644 --- a/class_r_f_m96-members.html +++ b/class_r_f_m96-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_r_f_m96.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_r_f_m96.html b/class_r_f_m96.html index f5bc2d6e..f51438f8 100644 --- a/class_r_f_m96.html +++ b/class_r_f_m96.html @@ -165,6 +165,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_r_f_m97-members.html b/class_r_f_m97-members.html index 9ac08235..9bf59942 100644 --- a/class_r_f_m97-members.html +++ b/class_r_f_m97-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_r_f_m97.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_r_f_m97.html b/class_r_f_m97.html index 44a2aa3a..9b4669fe 100644 --- a/class_r_f_m97.html +++ b/class_r_f_m97.html @@ -173,6 +173,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_s_x1272-members.html b/class_s_x1272-members.html index 488952a6..b75c8a7f 100644 --- a/class_s_x1272-members.html +++ b/class_s_x1272-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1272.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1272 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1272 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1272 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1272 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1272 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1272 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1272.html b/class_s_x1272.html index 56cd9362..f85de0a6 100644 --- a/class_s_x1272.html +++ b/class_s_x1272.html @@ -155,6 +155,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
@@ -526,6 +532,32 @@ void 
Returns
Status Codes
+
+
+ +

◆ explicitHeader()

+ +
+
+ + + + + + + +
int16_t SX1272::explicitHeader ()
+
+ +

Set explicit header mode for future reception/transmission.

+
Parameters
+ + +
lenPayload length in bytes.
+
+
+
Returns
Status Codes
+
@@ -573,6 +605,27 @@ void 
Returns
Last packet RSSI for LoRa modem, or current RSSI level for FSK modem.
+
+
+ +

◆ implicitHeader()

+ +
+
+ + + + + + + + +
int16_t SX1272::implicitHeader (size_t len)
+
+ +

Set implicit header mode for future reception/transmission.

+
Returns
Status Codes
+
diff --git a/class_s_x1272.js b/class_s_x1272.js index 809ea5f5..d7599161 100644 --- a/class_s_x1272.js +++ b/class_s_x1272.js @@ -4,8 +4,10 @@ var class_s_x1272 = [ "autoLDRO", "class_s_x1272.html#abb4bbfe8acc6026c833d267d78417b63", null ], [ "begin", "class_s_x1272.html#aaa5a787164fb216c12b8dea4d810f7f3", null ], [ "beginFSK", "class_s_x1272.html#a2ee9fb48eeaf41876de00d3774be78cf", null ], + [ "explicitHeader", "class_s_x1272.html#ae3c9704cb58232f696b5f90f69c115f7", null ], [ "forceLDRO", "class_s_x1272.html#a4aaf9d61310fa7b4fce413ae53d30ac0", null ], [ "getRSSI", "class_s_x1272.html#af5a7dee50a1a7d8261bc62bb869cda92", null ], + [ "implicitHeader", "class_s_x1272.html#a4ee36122f8aca42b27a8412e0c362dd3", null ], [ "reset", "class_s_x1272.html#a0978cc9ecbb7b9d3a017c133506e57ac", null ], [ "setBandwidth", "class_s_x1272.html#a0cc8eeb00241031796fc73b08711469b", null ], [ "setCodingRate", "class_s_x1272.html#a960913438feccad4c1913a9222384a5f", null ], diff --git a/class_s_x1273-members.html b/class_s_x1273-members.html index f3c769e5..f656bd6a 100644 --- a/class_s_x1273-members.html +++ b/class_s_x1273-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1273.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1272 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1272 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1272 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1272 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1272 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1272 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1273.html b/class_s_x1273.html index 5b310f03..db57e8a2 100644 --- a/class_s_x1273.html +++ b/class_s_x1273.html @@ -165,6 +165,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_s_x1276-members.html b/class_s_x1276-members.html index d9a1f9e7..18fa1c44 100644 --- a/class_s_x1276-members.html +++ b/class_s_x1276-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1276.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1276.html b/class_s_x1276.html index 07b7e1ba..f4a3d6d2 100644 --- a/class_s_x1276.html +++ b/class_s_x1276.html @@ -168,6 +168,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_s_x1277-members.html b/class_s_x1277-members.html index 5caf39d8..ec090b6c 100644 --- a/class_s_x1277-members.html +++ b/class_s_x1277-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1277.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1277.html b/class_s_x1277.html index a48a931a..faaaa9e3 100644 --- a/class_s_x1277.html +++ b/class_s_x1277.html @@ -171,6 +171,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/class_s_x1278-members.html b/class_s_x1278-members.html index 1fd2d3e6..8a3957c9 100644 --- a/class_s_x1278-members.html +++ b/class_s_x1278-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1278.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1278.html b/class_s_x1278.html index 7ae8997b..c397458d 100644 --- a/class_s_x1278.html +++ b/class_s_x1278.html @@ -160,6 +160,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
@@ -531,6 +537,32 @@ void 
Returns
Status Codes
+ + + +

◆ explicitHeader()

+ +
+
+ + + + + + + +
int16_t SX1278::explicitHeader ()
+
+ +

Set explicit header mode for future reception/transmission.

+
Parameters
+ + +
lenPayload length in bytes.
+
+
+
Returns
Status Codes
+
@@ -578,6 +610,27 @@ void 
Returns
Last packet RSSI for LoRa modem, or current RSSI level for FSK modem.
+ + + +

◆ implicitHeader()

+ +
+
+ + + + + + + + +
int16_t SX1278::implicitHeader (size_t len)
+
+ +

Set implicit header mode for future reception/transmission.

+
Returns
Status Codes
+
diff --git a/class_s_x1278.js b/class_s_x1278.js index c873becc..4144220c 100644 --- a/class_s_x1278.js +++ b/class_s_x1278.js @@ -4,8 +4,10 @@ var class_s_x1278 = [ "autoLDRO", "class_s_x1278.html#ae02adcde8c2978c0d1b157729dd5df1e", null ], [ "begin", "class_s_x1278.html#af7d9dc775820f7b260b578908cea3dbe", null ], [ "beginFSK", "class_s_x1278.html#a33dc718c83c233a1f93d6bdf2ec31783", null ], + [ "explicitHeader", "class_s_x1278.html#a7c7717f09820a8e9a93621b0a00713f1", null ], [ "forceLDRO", "class_s_x1278.html#a6d6398c4d4fde302d6d4752708bce856", null ], [ "getRSSI", "class_s_x1278.html#a0b1fe4d0b1acfa454d7bab59cdf319fe", null ], + [ "implicitHeader", "class_s_x1278.html#a47f5ac7dd6587b86c5f2c2b16336612e", null ], [ "reset", "class_s_x1278.html#a6d60902ac59b653a9eb83e82a932f7ad", null ], [ "setBandwidth", "class_s_x1278.html#a46c27ed1ebaae4e3ed8afe3ae6941dd6", null ], [ "setCodingRate", "class_s_x1278.html#a834f26a0bd3fc8a03fa7e68aa4daf9e1", null ], diff --git a/class_s_x1279-members.html b/class_s_x1279-members.html index 91297fcf..4512785a 100644 --- a/class_s_x1279-members.html +++ b/class_s_x1279-members.html @@ -95,18 +95,20 @@ $(document).ready(function(){initNavTree('class_s_x1279.html','');}); clearDio0Action()SX127x clearDio1Action()SX127x disableAddressFiltering()SX127x - fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - forceLDRO(bool enable)SX1278 - getChipVersion()SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x + explicitHeader()SX1278 + fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + forceLDRO(bool enable)SX1278 + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + implicitHeader(size_t len)SX1278 packetMode()SX127x PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer random()SX127xvirtual diff --git a/class_s_x1279.html b/class_s_x1279.html index b963912d..65345742 100644 --- a/class_s_x1279.html +++ b/class_s_x1279.html @@ -168,6 +168,12 @@ void int16_t autoLDRO ()  Re-enables automatic LDRO configuration. Only available in LoRa mode. After calling this method, LDRO will be enabled automatically when symbol length exceeds 16 ms. More...
  +int16_t implicitHeader (size_t len) + Set implicit header mode for future reception/transmission. More...
+  +int16_t explicitHeader () + Set explicit header mode for future reception/transmission. More...
+  - Public Member Functions inherited from SX127x  SX127x (Module *mod)  Default constructor. Called internally when creating new LoRa instance. More...
diff --git a/functions_e.html b/functions_e.html index 83412fe8..f85eb610 100644 --- a/functions_e.html +++ b/functions_e.html @@ -95,6 +95,8 @@ $(document).ready(function(){initNavTree('functions_e.html','');});
  • explicitHeader() : SX126x +, SX1272 +, SX1278 , SX128x
    • diff --git a/functions_func_e.html b/functions_func_e.html index ef7980c2..3afd462c 100644 --- a/functions_func_e.html +++ b/functions_func_e.html @@ -95,6 +95,8 @@ $(document).ready(function(){initNavTree('functions_func_e.html','');});
  • explicitHeader() : SX126x +, SX1272 +, SX1278 , SX128x
    • diff --git a/functions_func_i.html b/functions_func_i.html index 26cf5531..55486b36 100644 --- a/functions_func_i.html +++ b/functions_func_i.html @@ -89,6 +89,8 @@ $(document).ready(function(){initNavTree('functions_func_i.html','');});
  • implicitHeader() : SX126x +, SX1272 +, SX1278 , SX128x
  • init() @@ -98,7 +100,7 @@ $(document).ready(function(){initNavTree('functions_func_i.html','');}); : nRF24
  • ITA2String() -: ITA2String +: ITA2String
    • diff --git a/functions_i.html b/functions_i.html index 59ccd8b9..e987a1c9 100644 --- a/functions_i.html +++ b/functions_i.html @@ -89,6 +89,8 @@ $(document).ready(function(){initNavTree('functions_i.html','');});
  • implicitHeader() : SX126x +, SX1272 +, SX1278 , SX128x
  • info @@ -104,7 +106,7 @@ $(document).ready(function(){initNavTree('functions_i.html','');}); : nRF24
  • ITA2String() -: ITA2String +: ITA2String
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