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CC1101.h
-
1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION_CURRENT 0x14
459 #define CC1101_VERSION_LEGACY 0x04
460 
461 // CC1101_REG_MARCSTATE
462 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
463 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
464 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
465 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
466 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
467 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
468 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
469 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
470 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
471 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
472 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
473 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
474 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
475 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
476 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
477 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
478 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
479 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
480 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
481 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
482 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
483 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
484 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
485 
486 // CC1101_REG_WORTIME1 + REG_WORTIME0
487 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
488 #define CC1101_WORTIME_LSB 0x00 // 7 0
489 
490 // CC1101_REG_PKTSTATUS
491 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
492 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
493 #define CC1101_CS 0b01000000 // 6 6 carrier sense
494 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
495 #define CC1101_CCA 0b00010000 // 4 4 channel clear
496 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
497 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
498 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
499 
505 class CC1101: public PhysicalLayer {
506  public:
507  // introduce PhysicalLayer overloads
508  using PhysicalLayer::transmit;
509  using PhysicalLayer::receive;
510  using PhysicalLayer::startTransmit;
511  using PhysicalLayer::readData;
512 
518  CC1101(Module* module);
519 
520  // basic methods
521 
539  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
540 
553  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
554 
565  int16_t receive(uint8_t* data, size_t len) override;
566 
572  int16_t standby() override;
573 
581  int16_t transmitDirect(uint32_t frf = 0) override;
582 
588  int16_t receiveDirect() override;
589 
593  int16_t packetMode();
594 
595  // interrupt methods
596 
604  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
605 
609  void clearGdo0Action();
610 
618  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
619 
623  void clearGdo2Action();
624 
637  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
638 
644  int16_t startReceive();
645 
655  int16_t readData(uint8_t* data, size_t len) override;
656 
657  // configuration methods
658 
666  int16_t setFrequency(float freq);
667 
675  int16_t setBitRate(float br);
676 
684  int16_t setRxBandwidth(float rxBw);
685 
693  int16_t setFrequencyDeviation(float freqDev) override;
694 
702  int16_t setOutputPower(int8_t power);
703 
717  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
718 
732  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
733 
741  int16_t setPreambleLength(uint8_t preambleLength);
742 
752  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
753 
759  int16_t disableAddressFiltering();
760 
768  int16_t setOOK(bool enableOOK);
769 
775  float getRSSI() const;
776 
782  uint8_t getLQI() const;
783 
791  size_t getPacketLength(bool update = true) override;
792 
800  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
801 
809  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
810 
820  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
821 
829  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
830 
838  int16_t setCrcFiltering(bool crcOn = true);
839 
847  int16_t setPromiscuousMode(bool promiscuous = true);
848 
857  int16_t setDataShaping(uint8_t sh) override;
858 
866  int16_t setEncoding(uint8_t encoding) override;
867 
876  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
877 
883  uint8_t random();
884 
885 #ifndef RADIOLIB_GODMODE
886  private:
887 #endif
888  Module* _mod;
889 
890  float _freq = 0;
891  uint8_t _rawRSSI = 0;
892  uint8_t _rawLQI = 0;
893  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
894 
895  size_t _packetLength = 0;
896  bool _packetLengthQueried = false;
897  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
898 
899  bool _promiscuous = false;
900  bool _crcOn = true;
901 
902  uint8_t _syncWordLength = 2;
903  int8_t _power = 0;
904 
905  int16_t config();
906  int16_t directMode();
907  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
908  int16_t setPacketMode(uint8_t mode, uint8_t len);
909 
910  // SPI read overrides to set bit for burst write and status registers access
911  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
912  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
913  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
914  uint8_t SPIreadRegister(uint8_t reg);
915  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
916  void SPIwriteRegister(uint8_t reg, uint8_t data);
917 
918  void SPIsendCommand(uint8_t cmd);
919 };
920 
921 #endif
CC1101::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: CC1101.cpp:735
+
1 #if !defined(_RADIOLIB_CC1101_H) && !defined(RADIOLIB_EXCLUDE_CC1101)
2 #define _RADIOLIB_CC1101_H
3 
4 #include "../../TypeDef.h"
5 #include "../../Module.h"
6 
7 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
8 
9 // CC1101 physical layer properties
10 #define CC1101_FREQUENCY_STEP_SIZE 396.7285156
11 #define CC1101_MAX_PACKET_LENGTH 63
12 #define CC1101_CRYSTAL_FREQ 26.0
13 #define CC1101_DIV_EXPONENT 16
14 
15 // CC1101 SPI commands
16 #define CC1101_CMD_READ 0b10000000
17 #define CC1101_CMD_WRITE 0b00000000
18 #define CC1101_CMD_BURST 0b01000000
19 #define CC1101_CMD_ACCESS_STATUS_REG 0b01000000
20 #define CC1101_CMD_FIFO_RX 0b10000000
21 #define CC1101_CMD_FIFO_TX 0b00000000
22 #define CC1101_CMD_RESET 0x30
23 #define CC1101_CMD_FSTXON 0x31
24 #define CC1101_CMD_XOFF 0x32
25 #define CC1101_CMD_CAL 0x33
26 #define CC1101_CMD_RX 0x34
27 #define CC1101_CMD_TX 0x35
28 #define CC1101_CMD_IDLE 0x36
29 #define CC1101_CMD_WOR 0x38
30 #define CC1101_CMD_POWER_DOWN 0x39
31 #define CC1101_CMD_FLUSH_RX 0x3A
32 #define CC1101_CMD_FLUSH_TX 0x3B
33 #define CC1101_CMD_WOR_RESET 0x3C
34 #define CC1101_CMD_NOP 0x3D
35 
36 // CC1101 register map
37 #define CC1101_REG_IOCFG2 0x00
38 #define CC1101_REG_IOCFG1 0x01
39 #define CC1101_REG_IOCFG0 0x02
40 #define CC1101_REG_FIFOTHR 0x03
41 #define CC1101_REG_SYNC1 0x04
42 #define CC1101_REG_SYNC0 0x05
43 #define CC1101_REG_PKTLEN 0x06
44 #define CC1101_REG_PKTCTRL1 0x07
45 #define CC1101_REG_PKTCTRL0 0x08
46 #define CC1101_REG_ADDR 0x09
47 #define CC1101_REG_CHANNR 0x0A
48 #define CC1101_REG_FSCTRL1 0x0B
49 #define CC1101_REG_FSCTRL0 0x0C
50 #define CC1101_REG_FREQ2 0x0D
51 #define CC1101_REG_FREQ1 0x0E
52 #define CC1101_REG_FREQ0 0x0F
53 #define CC1101_REG_MDMCFG4 0x10
54 #define CC1101_REG_MDMCFG3 0x11
55 #define CC1101_REG_MDMCFG2 0x12
56 #define CC1101_REG_MDMCFG1 0x13
57 #define CC1101_REG_MDMCFG0 0x14
58 #define CC1101_REG_DEVIATN 0x15
59 #define CC1101_REG_MCSM2 0x16
60 #define CC1101_REG_MCSM1 0x17
61 #define CC1101_REG_MCSM0 0x18
62 #define CC1101_REG_FOCCFG 0x19
63 #define CC1101_REG_BSCFG 0x1A
64 #define CC1101_REG_AGCCTRL2 0x1B
65 #define CC1101_REG_AGCCTRL1 0x1C
66 #define CC1101_REG_AGCCTRL0 0x1D
67 #define CC1101_REG_WOREVT1 0x1E
68 #define CC1101_REG_WOREVT0 0x1F
69 #define CC1101_REG_WORCTRL 0x20
70 #define CC1101_REG_FREND1 0x21
71 #define CC1101_REG_FREND0 0x22
72 #define CC1101_REG_FSCAL3 0x23
73 #define CC1101_REG_FSCAL2 0x24
74 #define CC1101_REG_FSCAL1 0x25
75 #define CC1101_REG_FSCAL0 0x26
76 #define CC1101_REG_RCCTRL1 0x27
77 #define CC1101_REG_RCCTRL0 0x28
78 #define CC1101_REG_FSTEST 0x29
79 #define CC1101_REG_PTEST 0x2A
80 #define CC1101_REG_AGCTEST 0x2B
81 #define CC1101_REG_TEST2 0x2C
82 #define CC1101_REG_TEST1 0x2D
83 #define CC1101_REG_TEST0 0x2E
84 #define CC1101_REG_PARTNUM 0x30
85 #define CC1101_REG_VERSION 0x31
86 #define CC1101_REG_FREQEST 0x32
87 #define CC1101_REG_LQI 0x33
88 #define CC1101_REG_RSSI 0x34
89 #define CC1101_REG_MARCSTATE 0x35
90 #define CC1101_REG_WORTIME1 0x36
91 #define CC1101_REG_WORTIME0 0x37
92 #define CC1101_REG_PKTSTATUS 0x38
93 #define CC1101_REG_VCO_VC_DAC 0x39
94 #define CC1101_REG_TXBYTES 0x3A
95 #define CC1101_REG_RXBYTES 0x3B
96 #define CC1101_REG_RCCTRL1_STATUS 0x3C
97 #define CC1101_REG_RCCTRL0_STATUS 0x3D
98 #define CC1101_REG_PATABLE 0x3E
99 #define CC1101_REG_FIFO 0x3F
100 
101 // CC1101_REG_IOCFG2 MSB LSB DESCRIPTION
102 #define CC1101_GDO2_NORM 0b00000000 // 6 6 GDO2 output: active high (default)
103 #define CC1101_GDO2_INV 0b01000000 // 6 6 active low
104 
105 // CC1101_REG_IOCFG1
106 #define CC1101_GDO1_DS_LOW 0b00000000 // 7 7 GDO1 output drive strength: low (default)
107 #define CC1101_GDO1_DS_HIGH 0b10000000 // 7 7 high
108 #define CC1101_GDO1_NORM 0b00000000 // 6 6 GDO1 output: active high (default)
109 #define CC1101_GDO1_INV 0b01000000 // 6 6 active low
110 
111 // CC1101_REG_IOCFG0
112 #define CC1101_GDO0_TEMP_SENSOR_OFF 0b00000000 // 7 7 analog temperature sensor output: disabled (default)
113 #define CC1101_GDO0_TEMP_SENSOR_ON 0b10000000 // 7 0 enabled
114 #define CC1101_GDO0_NORM 0b00000000 // 6 6 GDO0 output: active high (default)
115 #define CC1101_GDO0_INV 0b01000000 // 6 6 active low
116 
117 // CC1101_REG_IOCFG2 + REG_IOCFG1 + REG_IOCFG0
118 #define CC1101_GDOX_RX_FIFO_FULL 0x00 // 5 0 Rx FIFO full or above threshold
119 #define CC1101_GDOX_RX_FIFO_FULL_OR_PKT_END 0x01 // 5 0 Rx FIFO full or above threshold or reached packet end
120 #define CC1101_GDOX_TX_FIFO_ABOVE_THR 0x02 // 5 0 Tx FIFO above threshold
121 #define CC1101_GDOX_TX_FIFO_FULL 0x03 // 5 0 Tx FIFO full
122 #define CC1101_GDOX_RX_FIFO_OVERFLOW 0x04 // 5 0 Rx FIFO overflowed
123 #define CC1101_GDOX_TX_FIFO_UNDERFLOW 0x05 // 5 0 Tx FIFO underflowed
124 #define CC1101_GDOX_SYNC_WORD_SENT_OR_RECEIVED 0x06 // 5 0 sync word was sent or received
125 #define CC1101_GDOX_PKT_RECEIVED_CRC_OK 0x07 // 5 0 packet received and CRC check passed
126 #define CC1101_GDOX_PREAMBLE_QUALITY_REACHED 0x08 // 5 0 received preamble quality is above threshold
127 #define CC1101_GDOX_CHANNEL_CLEAR 0x09 // 5 0 RSSI level below threshold (channel is clear)
128 #define CC1101_GDOX_PLL_LOCKED 0x0A // 5 0 PLL is locked
129 #define CC1101_GDOX_SERIAL_CLOCK 0x0B // 5 0 serial data clock
130 #define CC1101_GDOX_SERIAL_DATA_SYNC 0x0C // 5 0 serial data output in: synchronous mode
131 #define CC1101_GDOX_SERIAL_DATA_ASYNC 0x0D // 5 0 asynchronous mode
132 #define CC1101_GDOX_CARRIER_SENSE 0x0E // 5 0 RSSI above threshold
133 #define CC1101_GDOX_CRC_OK 0x0F // 5 0 CRC check passed
134 #define CC1101_GDOX_RX_HARD_DATA1 0x16 // 5 0 direct access to demodulated data
135 #define CC1101_GDOX_RX_HARD_DATA0 0x17 // 5 0 direct access to demodulated data
136 #define CC1101_GDOX_PA_PD 0x1B // 5 0 power amplifier circuit is powered down
137 #define CC1101_GDOX_LNA_PD 0x1C // 5 0 low-noise amplifier circuit is powered down
138 #define CC1101_GDOX_RX_SYMBOL_TICK 0x1D // 5 0 direct access to symbol tick of received data
139 #define CC1101_GDOX_WOR_EVNT0 0x24 // 5 0 wake-on-radio event 0
140 #define CC1101_GDOX_WOR_EVNT1 0x25 // 5 0 wake-on-radio event 1
141 #define CC1101_GDOX_CLK_256 0x26 // 5 0 256 Hz clock
142 #define CC1101_GDOX_CLK_32K 0x27 // 5 0 32 kHz clock
143 #define CC1101_GDOX_CHIP_RDYN 0x29 // 5 0 (default for GDO2)
144 #define CC1101_GDOX_XOSC_STABLE 0x2B // 5 0
145 #define CC1101_GDOX_HIGH_Z 0x2E // 5 0 high impedance state (default for GDO1)
146 #define CC1101_GDOX_HW_TO_0 0x2F // 5 0
147 #define CC1101_GDOX_CLOCK_XOSC_1 0x30 // 5 0 crystal oscillator clock: f = f(XOSC)/1
148 #define CC1101_GDOX_CLOCK_XOSC_1_5 0x31 // 5 0 f = f(XOSC)/1.5
149 #define CC1101_GDOX_CLOCK_XOSC_2 0x32 // 5 0 f = f(XOSC)/2
150 #define CC1101_GDOX_CLOCK_XOSC_3 0x33 // 5 0 f = f(XOSC)/3
151 #define CC1101_GDOX_CLOCK_XOSC_4 0x34 // 5 0 f = f(XOSC)/4
152 #define CC1101_GDOX_CLOCK_XOSC_6 0x35 // 5 0 f = f(XOSC)/6
153 #define CC1101_GDOX_CLOCK_XOSC_8 0x36 // 5 0 f = f(XOSC)/8
154 #define CC1101_GDOX_CLOCK_XOSC_12 0x37 // 5 0 f = f(XOSC)/12
155 #define CC1101_GDOX_CLOCK_XOSC_16 0x38 // 5 0 f = f(XOSC)/16
156 #define CC1101_GDOX_CLOCK_XOSC_24 0x39 // 5 0 f = f(XOSC)/24
157 #define CC1101_GDOX_CLOCK_XOSC_32 0x3A // 5 0 f = f(XOSC)/32
158 #define CC1101_GDOX_CLOCK_XOSC_48 0x3B // 5 0 f = f(XOSC)/48
159 #define CC1101_GDOX_CLOCK_XOSC_64 0x3C // 5 0 f = f(XOSC)/64
160 #define CC1101_GDOX_CLOCK_XOSC_96 0x3D // 5 0 f = f(XOSC)/96
161 #define CC1101_GDOX_CLOCK_XOSC_128 0x3E // 5 0 f = f(XOSC)/128
162 #define CC1101_GDOX_CLOCK_XOSC_192 0x3F // 5 0 f = f(XOSC)/192 (default for GDO0)
163 
164 // CC1101_REG_FIFOTHR
165 #define CC1101_ADC_RETENTION_OFF 0b00000000 // 6 6 do not retain ADC settings in sleep mode (default)
166 #define CC1101_ADC_RETENTION_ON 0b01000000 // 6 6 retain ADC settings in sleep mode
167 #define CC1101_RX_ATTEN_0_DB 0b00000000 // 5 4 Rx attenuation: 0 dB (default)
168 #define CC1101_RX_ATTEN_6_DB 0b00010000 // 5 4 6 dB
169 #define CC1101_RX_ATTEN_12_DB 0b00100000 // 5 4 12 dB
170 #define CC1101_RX_ATTEN_18_DB 0b00110000 // 5 4 18 dB
171 #define CC1101_FIFO_THR 0b00000111 // 5 4 Rx FIFO threshold [bytes] = CC1101_FIFO_THR * 4; Tx FIFO threshold [bytes] = 65 - (CC1101_FIFO_THR * 4)
172 
173 // CC1101_REG_SYNC1
174 #define CC1101_SYNC_WORD_MSB 0xD3 // 7 0 sync word MSB
175 
176 // CC1101_REG_SYNC0
177 #define CC1101_SYNC_WORD_LSB 0x91 // 7 0 sync word LSB
178 
179 // CC1101_REG_PKTLEN
180 #define CC1101_PACKET_LENGTH 0xFF // 7 0 packet length in bytes
181 
182 // CC1101_REG_PKTCTRL1
183 #define CC1101_PQT 0x00 // 7 5 preamble quality threshold
184 #define CC1101_CRC_AUTOFLUSH_OFF 0b00000000 // 3 3 automatic Rx FIFO flush on CRC check fail: disabled (default)
185 #define CC1101_CRC_AUTOFLUSH_ON 0b00001000 // 3 3 enabled
186 #define CC1101_APPEND_STATUS_OFF 0b00000000 // 2 2 append 2 status bytes to packet: disabled
187 #define CC1101_APPEND_STATUS_ON 0b00000100 // 2 2 enabled (default)
188 #define CC1101_ADR_CHK_NONE 0b00000000 // 1 0 address check: none (default)
189 #define CC1101_ADR_CHK_NO_BROADCAST 0b00000001 // 1 0 without broadcast
190 #define CC1101_ADR_CHK_SINGLE_BROADCAST 0b00000010 // 1 0 broadcast address 0x00
191 #define CC1101_ADR_CHK_DOUBLE_BROADCAST 0b00000011 // 1 0 broadcast addresses 0x00 and 0xFF
192 
193 // CC1101_REG_PKTCTRL0
194 #define CC1101_WHITE_DATA_OFF 0b00000000 // 6 6 data whitening: disabled
195 #define CC1101_WHITE_DATA_ON 0b01000000 // 6 6 enabled (default)
196 #define CC1101_PKT_FORMAT_NORMAL 0b00000000 // 5 4 packet format: normal (FIFOs)
197 #define CC1101_PKT_FORMAT_SYNCHRONOUS 0b00010000 // 5 4 synchronous serial
198 #define CC1101_PKT_FORMAT_RANDOM 0b00100000 // 5 4 random transmissions
199 #define CC1101_PKT_FORMAT_ASYNCHRONOUS 0b00110000 // 5 4 asynchronous serial
200 #define CC1101_CRC_OFF 0b00000000 // 2 2 CRC disabled
201 #define CC1101_CRC_ON 0b00000100 // 2 2 CRC enabled (default)
202 #define CC1101_LENGTH_CONFIG_FIXED 0b00000000 // 1 0 packet length: fixed
203 #define CC1101_LENGTH_CONFIG_VARIABLE 0b00000001 // 1 0 variable (default)
204 #define CC1101_LENGTH_CONFIG_INFINITE 0b00000010 // 1 0 infinite
205 
206 // CC1101_REG_ADDR
207 #define CC1101_DEVICE_ADDR 0x00 // 7 0 device address
208 
209 // CC1101_REG_CHANNR
210 #define CC1101_CHAN 0x00 // 7 0 channel number
211 
212 // CC1101_REG_FSCTRL1
213 #define CC1101_FREQ_IF 0x0F // 4 0 IF frequency setting; f_IF = (f(XOSC) / 2^10) * CC1101_FREQ_IF
214 
215 // CC1101_REG_FSCTRL0
216 #define CC1101_FREQOFF 0x00 // 7 0 base frequency offset (2s-compliment)
217 
218 // CC1101_REG_FREQ2 + REG_FREQ1 + REG_FREQ0
219 #define CC1101_FREQ_MSB 0x1E // 5 0 base frequency setting: f_carrier = (f(XOSC) / 2^16) * FREQ
220 #define CC1101_FREQ_MID 0xC4 // 7 0 where f(XOSC) = 26 MHz
221 #define CC1101_FREQ_LSB 0xEC // 7 0 FREQ = 3-byte value of FREQ registers
222 
223 // CC1101_REG_MDMCFG4
224 #define CC1101_CHANBW_E 0b10000000 // 7 6 channel bandwidth: BW_channel = f(XOSC) / (8 * (4 + CHANBW_M)*2^CHANBW_E) [Hz]
225 #define CC1101_CHANBW_M 0b00000000 // 5 4 default value for 26 MHz crystal: 203 125 Hz
226 #define CC1101_DRATE_E 0x0C // 3 0 symbol rate: R_data = (((256 + DRATE_M) * 2^DRATE_E) / 2^28) * f(XOSC) [Baud]
227 
228 // CC1101_REG_MDMCFG3
229 #define CC1101_DRATE_M 0x22 // 7 0 default value for 26 MHz crystal: 115 051 Baud
230 
231 // CC1101_REG_MDMCFG2
232 #define CC1101_DEM_DCFILT_OFF 0b10000000 // 7 7 digital DC filter: disabled
233 #define CC1101_DEM_DCFILT_ON 0b00000000 // 7 7 enabled - only for data rates above 250 kBaud (default)
234 #define CC1101_MOD_FORMAT_2_FSK 0b00000000 // 6 4 modulation format: 2-FSK (default)
235 #define CC1101_MOD_FORMAT_GFSK 0b00010000 // 6 4 GFSK
236 #define CC1101_MOD_FORMAT_ASK_OOK 0b00110000 // 6 4 ASK/OOK
237 #define CC1101_MOD_FORMAT_4_FSK 0b01000000 // 6 4 4-FSK
238 #define CC1101_MOD_FORMAT_MFSK 0b01110000 // 6 4 MFSK - only for data rates above 26 kBaud
239 #define CC1101_MANCHESTER_EN_OFF 0b00000000 // 3 3 Manchester encoding: disabled (default)
240 #define CC1101_MANCHESTER_EN_ON 0b00001000 // 3 3 enabled
241 #define CC1101_SYNC_MODE_NONE 0b00000000 // 2 0 synchronization: no preamble/sync
242 #define CC1101_SYNC_MODE_15_16 0b00000001 // 2 0 15/16 sync word bits
243 #define CC1101_SYNC_MODE_16_16 0b00000010 // 2 0 16/16 sync word bits (default)
244 #define CC1101_SYNC_MODE_30_32 0b00000011 // 2 0 30/32 sync word bits
245 #define CC1101_SYNC_MODE_NONE_THR 0b00000100 // 2 0 no preamble sync, carrier sense above threshold
246 #define CC1101_SYNC_MODE_15_16_THR 0b00000101 // 2 0 15/16 sync word bits, carrier sense above threshold
247 #define CC1101_SYNC_MODE_16_16_THR 0b00000110 // 2 0 16/16 sync word bits, carrier sense above threshold
248 #define CC1101_SYNC_MODE_30_32_THR 0b00000111 // 2 0 30/32 sync word bits, carrier sense above threshold
249 
250 // CC1101_REG_MDMCFG1
251 #define CC1101_FEC_OFF 0b00000000 // 7 7 forward error correction: disabled (default)
252 #define CC1101_FEC_ON 0b10000000 // 7 7 enabled - only for fixed packet length
253 #define CC1101_NUM_PREAMBLE_2 0b00000000 // 6 4 number of preamble bytes: 2
254 #define CC1101_NUM_PREAMBLE_3 0b00010000 // 6 4 3
255 #define CC1101_NUM_PREAMBLE_4 0b00100000 // 6 4 4 (default)
256 #define CC1101_NUM_PREAMBLE_6 0b00110000 // 6 4 6
257 #define CC1101_NUM_PREAMBLE_8 0b01000000 // 6 4 8
258 #define CC1101_NUM_PREAMBLE_12 0b01010000 // 6 4 12
259 #define CC1101_NUM_PREAMBLE_16 0b01100000 // 6 4 16
260 #define CC1101_NUM_PREAMBLE_24 0b01110000 // 6 4 24
261 #define CC1101_CHANSPC_E 0x02 // 1 0 channel spacing: df_channel = (f(XOSC) / 2^18) * (256 + CHANSPC_M) * 2^CHANSPC_E [Hz]
262 
263 // CC1101_REG_MDMCFG0
264 #define CC1101_CHANSPC_M 0xF8 // 7 0 default value for 26 MHz crystal: 199 951 kHz
265 
266 // CC1101_REG_DEVIATN
267 #define CC1101_DEVIATION_E 0b01000000 // 6 4 frequency deviation: f_dev = (f(XOSC) / 2^17) * (8 + DEVIATION_M) * 2^DEVIATION_E [Hz]
268 #define CC1101_DEVIATION_M 0b00000111 // 2 0 default value for 26 MHz crystal: +- 47 607 Hz
269 #define CC1101_MSK_PHASE_CHANGE_PERIOD 0x07 // 2 0 phase change symbol period fraction: 1 / (MSK_PHASE_CHANGE_PERIOD + 1)
270 
271 // CC1101_REG_MCSM2
272 #define CC1101_RX_TIMEOUT_RSSI_OFF 0b00000000 // 4 4 Rx timeout based on RSSI value: disabled (default)
273 #define CC1101_RX_TIMEOUT_RSSI_ON 0b00010000 // 4 4 enabled
274 #define CC1101_RX_TIMEOUT_QUAL_OFF 0b00000000 // 3 3 check for sync word on Rx timeout
275 #define CC1101_RX_TIMEOUT_QUAL_ON 0b00001000 // 3 3 check for PQI set on Rx timeout
276 #define CC1101_RX_TIMEOUT_OFF 0b00000111 // 2 0 Rx timeout: disabled (default)
277 #define CC1101_RX_TIMEOUT_MAX 0b00000000 // 2 0 max value (actual value depends on WOR_RES, EVENT0 and f(XOSC))
278 
279 // CC1101_REG_MCSM1
280 #define CC1101_CCA_MODE_ALWAYS 0b00000000 // 5 4 clear channel indication: always
281 #define CC1101_CCA_MODE_RSSI_THR 0b00010000 // 5 4 RSSI below threshold
282 #define CC1101_CCA_MODE_RX_PKT 0b00100000 // 5 4 unless receiving packet
283 #define CC1101_CCA_MODE_RSSI_THR_RX_PKT 0b00110000 // 5 4 RSSI below threshold unless receiving packet (default)
284 #define CC1101_RXOFF_IDLE 0b00000000 // 3 2 next mode after packet reception: idle (default)
285 #define CC1101_RXOFF_FSTXON 0b00000100 // 3 2 FSTxOn
286 #define CC1101_RXOFF_TX 0b00001000 // 3 2 Tx
287 #define CC1101_RXOFF_RX 0b00001100 // 3 2 Rx
288 #define CC1101_TXOFF_IDLE 0b00000000 // 1 0 next mode after packet transmission: idle (default)
289 #define CC1101_TXOFF_FSTXON 0b00000001 // 1 0 FSTxOn
290 #define CC1101_TXOFF_TX 0b00000010 // 1 0 Tx
291 #define CC1101_TXOFF_RX 0b00000011 // 1 0 Rx
292 
293 // CC1101_REG_MCSM0
294 #define CC1101_FS_AUTOCAL_NEVER 0b00000000 // 5 4 automatic calibration: never (default)
295 #define CC1101_FS_AUTOCAL_IDLE_TO_RXTX 0b00010000 // 5 4 every transition from idle to Rx/Tx
296 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE 0b00100000 // 5 4 every transition from Rx/Tx to idle
297 #define CC1101_FS_AUTOCAL_RXTX_TO_IDLE_4TH 0b00110000 // 5 4 every 4th transition from Rx/Tx to idle
298 #define CC1101_PO_TIMEOUT_COUNT_1 0b00000000 // 3 2 number of counter expirations before CHP_RDYN goes low: 1 (default)
299 #define CC1101_PO_TIMEOUT_COUNT_16 0b00000100 // 3 2 16
300 #define CC1101_PO_TIMEOUT_COUNT_64 0b00001000 // 3 2 64
301 #define CC1101_PO_TIMEOUT_COUNT_256 0b00001100 // 3 2 256
302 #define CC1101_PIN_CTRL_OFF 0b00000000 // 1 1 pin radio control: disabled (default)
303 #define CC1101_PIN_CTRL_ON 0b00000010 // 1 1 enabled
304 #define CC1101_XOSC_FORCE_OFF 0b00000000 // 0 0 do not force XOSC to remain on in sleep (default)
305 #define CC1101_XOSC_FORCE_ON 0b00000001 // 0 0 force XOSC to remain on in sleep
306 
307 // CC1101_REG_FOCCFG
308 #define CC1101_FOC_BS_CS_GATE_OFF 0b00000000 // 5 5 do not freeze frequency compensation until CS goes high
309 #define CC1101_FOC_BS_CS_GATE_ON 0b00100000 // 5 5 freeze frequency compensation until CS goes high (default)
310 #define CC1101_FOC_PRE_K 0b00000000 // 4 3 frequency compensation loop gain before sync word: K
311 #define CC1101_FOC_PRE_2K 0b00001000 // 4 3 2K
312 #define CC1101_FOC_PRE_3K 0b00010000 // 4 3 3K (default)
313 #define CC1101_FOC_PRE_4K 0b00011000 // 4 3 4K
314 #define CC1101_FOC_POST_K 0b00000000 // 2 2 frequency compensation loop gain after sync word: same as FOC_PRE
315 #define CC1101_FOC_POST_K_2 0b00000100 // 2 2 K/2 (default)
316 #define CC1101_FOC_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 frequency compensation saturation point: no compensation - required for ASK/OOK
317 #define CC1101_FOC_LIMIT_BW_CHAN_8 0b00000001 // 1 0 +- BW_chan/8
318 #define CC1101_FOC_LIMIT_BW_CHAN_4 0b00000010 // 1 0 +- BW_chan/4 (default)
319 #define CC1101_FOC_LIMIT_BW_CHAN_2 0b00000011 // 1 0 +- BW_chan/2
320 
321 // CC1101_REG_BSCFG
322 #define CC1101_BS_PRE_KI 0b00000000 // 7 6 clock recovery integral gain before sync word: Ki
323 #define CC1101_BS_PRE_2KI 0b01000000 // 7 6 2Ki (default)
324 #define CC1101_BS_PRE_3KI 0b10000000 // 7 6 3Ki
325 #define CC1101_BS_PRE_4KI 0b11000000 // 7 6 4Ki
326 #define CC1101_BS_PRE_KP 0b00000000 // 5 4 clock recovery proportional gain before sync word: Kp
327 #define CC1101_BS_PRE_2KP 0b00010000 // 5 4 2Kp
328 #define CC1101_BS_PRE_3KP 0b00100000 // 5 4 3Kp (default)
329 #define CC1101_BS_PRE_4KP 0b00110000 // 5 4 4Kp
330 #define CC1101_BS_POST_KI 0b00000000 // 3 3 clock recovery integral gain after sync word: same as BS_PRE
331 #define CC1101_BS_POST_KI_2 0b00001000 // 3 3 Ki/2 (default)
332 #define CC1101_BS_POST_KP 0b00000000 // 2 2 clock recovery proportional gain after sync word: same as BS_PRE
333 #define CC1101_BS_POST_KP_1 0b00000100 // 2 2 Kp (default)
334 #define CC1101_BS_LIMIT_NO_COMPENSATION 0b00000000 // 1 0 data rate compensation saturation point: no compensation
335 #define CC1101_BS_LIMIT_3_125 0b00000001 // 1 0 +- 3.125 %
336 #define CC1101_BS_LIMIT_6_25 0b00000010 // 1 0 +- 6.25 %
337 #define CC1101_BS_LIMIT_12_5 0b00000011 // 1 0 +- 12.5 %
338 
339 // CC1101_REG_AGCCTRL2
340 #define CC1101_MAX_DVGA_GAIN_0 0b00000000 // 7 6 reduce maximum available DVGA gain: no reduction (default)
341 #define CC1101_MAX_DVGA_GAIN_1 0b01000000 // 7 6 disable top gain setting
342 #define CC1101_MAX_DVGA_GAIN_2 0b10000000 // 7 6 disable top two gain setting
343 #define CC1101_MAX_DVGA_GAIN_3 0b11000000 // 7 6 disable top three gain setting
344 #define CC1101_LNA_GAIN_REDUCE_0_DB 0b00000000 // 5 3 reduce maximum LNA gain by: 0 dB (default)
345 #define CC1101_LNA_GAIN_REDUCE_2_6_DB 0b00001000 // 5 3 2.6 dB
346 #define CC1101_LNA_GAIN_REDUCE_6_1_DB 0b00010000 // 5 3 6.1 dB
347 #define CC1101_LNA_GAIN_REDUCE_7_4_DB 0b00011000 // 5 3 7.4 dB
348 #define CC1101_LNA_GAIN_REDUCE_9_2_DB 0b00100000 // 5 3 9.2 dB
349 #define CC1101_LNA_GAIN_REDUCE_11_5_DB 0b00101000 // 5 3 11.5 dB
350 #define CC1101_LNA_GAIN_REDUCE_14_6_DB 0b00110000 // 5 3 14.6 dB
351 #define CC1101_LNA_GAIN_REDUCE_17_1_DB 0b00111000 // 5 3 17.1 dB
352 #define CC1101_MAGN_TARGET_24_DB 0b00000000 // 2 0 average amplitude target for filter: 24 dB
353 #define CC1101_MAGN_TARGET_27_DB 0b00000001 // 2 0 27 dB
354 #define CC1101_MAGN_TARGET_30_DB 0b00000010 // 2 0 30 dB
355 #define CC1101_MAGN_TARGET_33_DB 0b00000011 // 2 0 33 dB (default)
356 #define CC1101_MAGN_TARGET_36_DB 0b00000100 // 2 0 36 dB
357 #define CC1101_MAGN_TARGET_38_DB 0b00000101 // 2 0 38 dB
358 #define CC1101_MAGN_TARGET_40_DB 0b00000110 // 2 0 40 dB
359 #define CC1101_MAGN_TARGET_42_DB 0b00000111 // 2 0 42 dB
360 
361 // CC1101_REG_AGCCTRL1
362 #define CC1101_AGC_LNA_PRIORITY_LNA2 0b00000000 // 6 6 LNA priority setting: LNA2 first
363 #define CC1101_AGC_LNA_PRIORITY_LNA 0b01000000 // 6 6 LNA first (default)
364 #define CC1101_CARRIER_SENSE_REL_THR_OFF 0b00000000 // 5 4 RSSI relative change to assert carrier sense: disabled (default)
365 #define CC1101_CARRIER_SENSE_REL_THR_6_DB 0b00010000 // 5 4 6 dB
366 #define CC1101_CARRIER_SENSE_REL_THR_10_DB 0b00100000 // 5 4 10 dB
367 #define CC1101_CARRIER_SENSE_REL_THR_14_DB 0b00110000 // 5 4 14 dB
368 #define CC1101_CARRIER_SENSE_ABS_THR 0x00 // 3 0 RSSI threshold to assert carrier sense in 2s compliment, Thr = MAGN_TARGET + CARRIER_SENSE_ABS_TH [dB]
369 
370 // CC1101_REG_AGCCTRL0
371 #define CC1101_HYST_LEVEL_NONE 0b00000000 // 7 6 AGC hysteresis level: none
372 #define CC1101_HYST_LEVEL_LOW 0b01000000 // 7 6 low
373 #define CC1101_HYST_LEVEL_MEDIUM 0b10000000 // 7 6 medium (default)
374 #define CC1101_HYST_LEVEL_HIGH 0b11000000 // 7 6 high
375 #define CC1101_WAIT_TIME_8_SAMPLES 0b00000000 // 5 4 AGC wait time: 8 samples
376 #define CC1101_WAIT_TIME_16_SAMPLES 0b00010000 // 5 4 16 samples (default)
377 #define CC1101_WAIT_TIME_24_SAMPLES 0b00100000 // 5 4 24 samples
378 #define CC1101_WAIT_TIME_32_SAMPLES 0b00110000 // 5 4 32 samples
379 #define CC1101_AGC_FREEZE_NEVER 0b00000000 // 3 2 freeze AGC gain: never (default)
380 #define CC1101_AGC_FREEZE_SYNC_WORD 0b00000100 // 3 2 when sync word is found
381 #define CC1101_AGC_FREEZE_MANUAL_A 0b00001000 // 3 2 manually freeze analog control
382 #define CC1101_AGC_FREEZE_MANUAL_AD 0b00001100 // 3 2 manually freeze analog and digital control
383 #define CC1101_FILTER_LENGTH_8 0b00000000 // 1 0 averaging length for channel filter: 8 samples
384 #define CC1101_FILTER_LENGTH_16 0b00000001 // 1 0 16 samples (default)
385 #define CC1101_FILTER_LENGTH_32 0b00000010 // 1 0 32 samples
386 #define CC1101_FILTER_LENGTH_64 0b00000011 // 1 0 64 samples
387 #define CC1101_ASK_OOK_BOUNDARY_4_DB 0b00000000 // 1 0 ASK/OOK decision boundary: 4 dB
388 #define CC1101_ASK_OOK_BOUNDARY_8_DB 0b00000001 // 1 0 8 dB (default)
389 #define CC1101_ASK_OOK_BOUNDARY_12_DB 0b00000010 // 1 0 12 dB
390 #define CC1101_ASK_OOK_BOUNDARY_16_DB 0b00000011 // 1 0 16 dB
391 
392 // CC1101_REG_WOREVT1 + REG_WOREVT0
393 #define CC1101_EVENT0_TIMEOUT_MSB 0x87 // 7 0 EVENT0 timeout: t_event0 = (750 / f(XOSC)) * EVENT0_TIMEOUT * 2^(5 * WOR_RES) [s]
394 #define CC1101_EVENT0_TIMEOUT_LSB 0x6B // 7 0 default value for 26 MHz crystal: 1.0 s
395 
396 // CC1101_REG_WORCTRL
397 #define CC1101_RC_POWER_UP 0b00000000 // 7 7 power up RC oscillator
398 #define CC1101_RC_POWER_DOWN 0b10000000 // 7 7 power down RC oscillator
399 #define CC1101_EVENT1_TIMEOUT_4 0b00000000 // 6 4 EVENT1 timeout: 4 RC periods
400 #define CC1101_EVENT1_TIMEOUT_6 0b00010000 // 6 4 6 RC periods
401 #define CC1101_EVENT1_TIMEOUT_8 0b00100000 // 6 4 8 RC periods
402 #define CC1101_EVENT1_TIMEOUT_12 0b00110000 // 6 4 12 RC periods
403 #define CC1101_EVENT1_TIMEOUT_16 0b01000000 // 6 4 16 RC periods
404 #define CC1101_EVENT1_TIMEOUT_24 0b01010000 // 6 4 24 RC periods
405 #define CC1101_EVENT1_TIMEOUT_32 0b01100000 // 6 4 32 RC periods
406 #define CC1101_EVENT1_TIMEOUT_48 0b01110000 // 6 4 48 RC periods (default)
407 #define CC1101_RC_CAL_OFF 0b00000000 // 3 3 disable RC oscillator calibration
408 #define CC1101_RC_CAL_ON 0b00001000 // 3 3 enable RC oscillator calibration (default)
409 #define CC1101_WOR_RES_1 0b00000000 // 1 0 EVENT0 resolution: 1 period (default)
410 #define CC1101_WOR_RES_2_5 0b00000001 // 1 0 2^5 periods
411 #define CC1101_WOR_RES_2_10 0b00000010 // 1 0 2^10 periods
412 #define CC1101_WOR_RES_2_15 0b00000011 // 1 0 2^15 periods
413 
414 // CC1101_REG_FREND1
415 #define CC1101_LNA_CURRENT 0x01 // 7 6 front-end LNA PTAT current output adjustment
416 #define CC1101_LNA2MIX_CURRENT 0x01 // 5 4 front-end PTAT output adjustment
417 #define CC1101_LODIV_BUF_CURRENT_RX 0x01 // 3 2 Rx LO buffer current adjustment
418 #define CC1101_MIX_CURRENT 0x02 // 1 0 mixer current adjustment
419 
420 // CC1101_REG_FREND0
421 #define CC1101_LODIV_BUF_CURRENT_TX 0x01 // 5 4 Tx LO buffer current adjustment
422 #define CC1101_PA_POWER 0x00 // 2 0 set power amplifier power according to PATABLE
423 
424 // CC1101_REG_FSCAL3
425 #define CC1101_CHP_CURR_CAL_OFF 0b00000000 // 5 4 disable charge pump calibration
426 #define CC1101_CHP_CURR_CAL_ON 0b00100000 // 5 4 enable charge pump calibration (default)
427 #define CC1101_FSCAL3 0x09 // 3 0 charge pump output current: I_out = I_0 * 2^(FSCAL3/4) [A]
428 
429 // CC1101_REG_FSCAL2
430 #define CC1101_VCO_CORE_LOW 0b00000000 // 5 5 VCO: low (default)
431 #define CC1101_VCO_CORE_HIGH 0b00100000 // 5 5 high
432 #define CC1101_FSCAL2 0x0A // 4 0 VCO current result/override
433 
434 // CC1101_REG_FSCAL1
435 #define CC1101_FSCAL1 0x20 // 5 0 capacitor array setting for coarse VCO tuning
436 
437 // CC1101_REG_FSCAL0
438 #define CC1101_FSCAL0 0x0D // 6 0 frequency synthesizer calibration setting
439 
440 // CC1101_REG_RCCTRL1
441 #define CC1101_RCCTRL1 0x41 // 6 0 RC oscillator configuration
442 
443 // CC1101_REG_RCCTRL0
444 #define CC1101_RCCTRL0 0x00 // 6 0 RC oscillator configuration
445 
446 // CC1101_REG_PTEST
447 #define CC1101_TEMP_SENS_IDLE_OFF 0x7F // 7 0 temperature sensor will not be available in idle mode (default)
448 #define CC1101_TEMP_SENS_IDLE_ON 0xBF // 7 0 temperature sensor will be available in idle mode
449 
450 // CC1101_REG_TEST0
451 #define CC1101_VCO_SEL_CAL_OFF 0b00000000 // 1 1 disable VCO selection calibration stage
452 #define CC1101_VCO_SEL_CAL_ON 0b00000010 // 1 1 enable VCO selection calibration stage
453 
454 // CC1101_REG_PARTNUM
455 #define CC1101_PARTNUM 0x00
456 
457 // CC1101_REG_VERSION
458 #define CC1101_VERSION_CURRENT 0x14
459 #define CC1101_VERSION_LEGACY 0x04
460 
461 // CC1101_REG_MARCSTATE
462 #define CC1101_MARC_STATE_SLEEP 0x00 // 4 0 main radio control state: sleep
463 #define CC1101_MARC_STATE_IDLE 0x01 // 4 0 idle
464 #define CC1101_MARC_STATE_XOFF 0x02 // 4 0 XOFF
465 #define CC1101_MARC_STATE_VCOON_MC 0x03 // 4 0 VCOON_MC
466 #define CC1101_MARC_STATE_REGON_MC 0x04 // 4 0 REGON_MC
467 #define CC1101_MARC_STATE_MANCAL 0x05 // 4 0 MANCAL
468 #define CC1101_MARC_STATE_VCOON 0x06 // 4 0 VCOON
469 #define CC1101_MARC_STATE_REGON 0x07 // 4 0 REGON
470 #define CC1101_MARC_STATE_STARTCAL 0x08 // 4 0 STARTCAL
471 #define CC1101_MARC_STATE_BWBOOST 0x09 // 4 0 BWBOOST
472 #define CC1101_MARC_STATE_FS_LOCK 0x0A // 4 0 FS_LOCK
473 #define CC1101_MARC_STATE_IFADCON 0x0B // 4 0 IFADCON
474 #define CC1101_MARC_STATE_ENDCAL 0x0C // 4 0 ENDCAL
475 #define CC1101_MARC_STATE_RX 0x0D // 4 0 RX
476 #define CC1101_MARC_STATE_RX_END 0x0E // 4 0 RX_END
477 #define CC1101_MARC_STATE_RX_RST 0x0F // 4 0 RX_RST
478 #define CC1101_MARC_STATE_TXRX_SWITCH 0x10 // 4 0 TXRX_SWITCH
479 #define CC1101_MARC_STATE_RXFIFO_OVERFLOW 0x11 // 4 0 RXFIFO_OVERFLOW
480 #define CC1101_MARC_STATE_FSTXON 0x12 // 4 0 FSTXON
481 #define CC1101_MARC_STATE_TX 0x13 // 4 0 TX
482 #define CC1101_MARC_STATE_TX_END 0x14 // 4 0 TX_END
483 #define CC1101_MARC_STATE_RXTX_SWITCH 0x15 // 4 0 RXTX_SWITCH
484 #define CC1101_MARC_STATE_TXFIFO_UNDERFLOW 0x16 // 4 0 TXFIFO_UNDERFLOW
485 
486 // CC1101_REG_WORTIME1 + REG_WORTIME0
487 #define CC1101_WORTIME_MSB 0x00 // 7 0 WOR timer value
488 #define CC1101_WORTIME_LSB 0x00 // 7 0
489 
490 // CC1101_REG_PKTSTATUS
491 #define CC1101_CRC_OK 0b10000000 // 7 7 CRC check passed
492 #define CC1101_CRC_ERROR 0b00000000 // 7 7 CRC check failed
493 #define CC1101_CS 0b01000000 // 6 6 carrier sense
494 #define CC1101_PQT_REACHED 0b00100000 // 5 5 preamble quality reached
495 #define CC1101_CCA 0b00010000 // 4 4 channel clear
496 #define CC1101_SFD 0b00001000 // 3 3 start of frame delimiter - sync word received
497 #define CC1101_GDO2_ACTIVE 0b00000100 // 2 2 GDO2 is active/asserted
498 #define CC1101_GDO0_ACTIVE 0b00000001 // 0 0 GDO0 is active/asserted
499 
505 class CC1101: public PhysicalLayer {
506  public:
507  // introduce PhysicalLayer overloads
508  using PhysicalLayer::transmit;
509  using PhysicalLayer::receive;
510  using PhysicalLayer::startTransmit;
511  using PhysicalLayer::readData;
512 
518  CC1101(Module* module);
519 
520  // basic methods
521 
539  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 48.0, float rxBw = 135.0, int8_t power = 10, uint8_t preambleLength = 16);
540 
553  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
554 
565  int16_t receive(uint8_t* data, size_t len) override;
566 
572  int16_t standby() override;
573 
581  int16_t transmitDirect(uint32_t frf = 0) override;
582 
588  int16_t receiveDirect() override;
589 
593  int16_t packetMode();
594 
595  // interrupt methods
596 
604  void setGdo0Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
605 
609  void clearGdo0Action();
610 
618  void setGdo2Action(void (*func)(void), RADIOLIB_INTERRUPT_STATUS dir = FALLING);
619 
623  void clearGdo2Action();
624 
637  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
638 
644  int16_t startReceive();
645 
655  int16_t readData(uint8_t* data, size_t len) override;
656 
657  // configuration methods
658 
666  int16_t setFrequency(float freq);
667 
675  int16_t setBitRate(float br);
676 
684  int16_t setRxBandwidth(float rxBw);
685 
693  int16_t setFrequencyDeviation(float freqDev) override;
694 
702  int16_t setOutputPower(int8_t power);
703 
717  int16_t setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
718 
732  int16_t setSyncWord(uint8_t* syncWord, uint8_t len, uint8_t maxErrBits = 0, bool requireCarrierSense = false);
733 
741  int16_t setPreambleLength(uint8_t preambleLength);
742 
752  int16_t setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs = 0);
753 
759  int16_t disableAddressFiltering();
760 
768  int16_t setOOK(bool enableOOK);
769 
775  float getRSSI() const;
776 
782  uint8_t getLQI() const;
783 
791  size_t getPacketLength(bool update = true) override;
792 
800  int16_t fixedPacketLengthMode(uint8_t len = CC1101_MAX_PACKET_LENGTH);
801 
809  int16_t variablePacketLengthMode(uint8_t maxLen = CC1101_MAX_PACKET_LENGTH);
810 
820  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0, bool requireCarrierSense = false);
821 
829  int16_t disableSyncWordFiltering(bool requireCarrierSense = false);
830 
838  int16_t setCrcFiltering(bool crcOn = true);
839 
847  int16_t setPromiscuousMode(bool promiscuous = true);
848 
857  int16_t setDataShaping(uint8_t sh) override;
858 
866  int16_t setEncoding(uint8_t encoding) override;
867 
876  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
877 
883  uint8_t random();
884 
890  int16_t getChipVersion();
891 
892 #ifndef RADIOLIB_GODMODE
893  private:
894 #endif
895  Module* _mod;
896 
897  float _freq = 0;
898  uint8_t _rawRSSI = 0;
899  uint8_t _rawLQI = 0;
900  uint8_t _modulation = CC1101_MOD_FORMAT_2_FSK;
901 
902  size_t _packetLength = 0;
903  bool _packetLengthQueried = false;
904  uint8_t _packetLengthConfig = CC1101_LENGTH_CONFIG_VARIABLE;
905 
906  bool _promiscuous = false;
907  bool _crcOn = true;
908 
909  uint8_t _syncWordLength = 2;
910  int8_t _power = 0;
911 
912  int16_t config();
913  int16_t directMode();
914  static void getExpMant(float target, uint16_t mantOffset, uint8_t divExp, uint8_t expMax, uint8_t& exp, uint8_t& mant);
915  int16_t setPacketMode(uint8_t mode, uint8_t len);
916 
917  // SPI read overrides to set bit for burst write and status registers access
918  int16_t SPIgetRegValue(uint8_t reg, uint8_t msb = 7, uint8_t lsb = 0);
919  int16_t SPIsetRegValue(uint8_t reg, uint8_t value, uint8_t msb = 7, uint8_t lsb = 0, uint8_t checkInterval = 2);
920  void SPIreadRegisterBurst(uint8_t reg, uint8_t numBytes, uint8_t* inBytes);
921  uint8_t SPIreadRegister(uint8_t reg);
922  void SPIwriteRegisterBurst(uint8_t reg, uint8_t* data, size_t len);
923  void SPIwriteRegister(uint8_t reg, uint8_t data);
924 
925  void SPIsendCommand(uint8_t cmd);
926 };
927 
928 #endif
CC1101::random
uint8_t random()
Get one truly random byte from RSSI noise.
Definition: CC1101.cpp:735
CC1101::packetMode
int16_t packetMode()
Stops direct mode. It is required to call this method to switch from direct transmissions to packet-b...
Definition: CC1101.cpp:185
CC1101::begin
int16_t begin(float freq=434.0, float br=48.0, float freqDev=48.0, float rxBw=135.0, int8_t power=10, uint8_t preambleLength=16)
Initialization method.
Definition: CC1101.cpp:8
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
@@ -106,6 +106,7 @@ $(document).ready(function(){initNavTree('_c_c1101_8h_source.html','');});
CC1101::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: CC1101.cpp:215
CC1101::standby
int16_t standby() override
Sets the module to standby mode.
Definition: CC1101.cpp:141
CC1101::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: CC1101.cpp:731
+
CC1101::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return CC1101_VERSION_LEGACY (0x04) or CC1101_VERSION_CURRENT (0x14...
Definition: CC1101.cpp:755
CC1101::fixedPacketLengthMode
int16_t fixedPacketLengthMode(uint8_t len=CC1101_MAX_PACKET_LENGTH)
Set modem in fixed packet length mode.
Definition: CC1101.cpp:624
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
diff --git a/_r_f69_8h_source.html b/_r_f69_8h_source.html index dbe2a67e..bbf26598 100644 --- a/_r_f69_8h_source.html +++ b/_r_f69_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_r_f69_8h_source.html','');});
RF69.h
-
1 #if !defined(_RADIOLIB_RF69_H)
2 #define _RADIOLIB_RF69_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_RF69)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // RF69 physical layer properties
13 #define RF69_FREQUENCY_STEP_SIZE 61.03515625
14 #define RF69_MAX_PACKET_LENGTH 64
15 #define RF69_CRYSTAL_FREQ 32.0
16 #define RF69_DIV_EXPONENT 19
17 
18 // RF69 register map
19 #define RF69_REG_FIFO 0x00
20 #define RF69_REG_OP_MODE 0x01
21 #define RF69_REG_DATA_MODUL 0x02
22 #define RF69_REG_BITRATE_MSB 0x03
23 #define RF69_REG_BITRATE_LSB 0x04
24 #define RF69_REG_FDEV_MSB 0x05
25 #define RF69_REG_FDEV_LSB 0x06
26 #define RF69_REG_FRF_MSB 0x07
27 #define RF69_REG_FRF_MID 0x08
28 #define RF69_REG_FRF_LSB 0x09
29 #define RF69_REG_OSC_1 0x0A
30 #define RF69_REG_AFC_CTRL 0x0B
31 #define RF69_REG_LISTEN_1 0x0D
32 #define RF69_REG_LISTEN_2 0x0E
33 #define RF69_REG_LISTEN_3 0x0F
34 #define RF69_REG_VERSION 0x10
35 #define RF69_REG_PA_LEVEL 0x11
36 #define RF69_REG_PA_RAMP 0x12
37 #define RF69_REG_OCP 0x13
38 #define RF69_REG_LNA 0x18
39 #define RF69_REG_RX_BW 0x19
40 #define RF69_REG_AFC_BW 0x1A
41 #define RF69_REG_OOK_PEAK 0x1B
42 #define RF69_REG_OOK_AVG 0x1C
43 #define RF69_REG_OOK_FIX 0x1D
44 #define RF69_REG_AFC_FEI 0x1E
45 #define RF69_REG_AFC_MSB 0x1F
46 #define RF69_REG_AFC_LSB 0x20
47 #define RF69_REG_FEI_MSB 0x21
48 #define RF69_REG_FEI_LSB 0x22
49 #define RF69_REG_RSSI_CONFIG 0x23
50 #define RF69_REG_RSSI_VALUE 0x24
51 #define RF69_REG_DIO_MAPPING_1 0x25
52 #define RF69_REG_DIO_MAPPING_2 0x26
53 #define RF69_REG_IRQ_FLAGS_1 0x27
54 #define RF69_REG_IRQ_FLAGS_2 0x28
55 #define RF69_REG_RSSI_THRESH 0x29
56 #define RF69_REG_RX_TIMEOUT_1 0x2A
57 #define RF69_REG_RX_TIMEOUT_2 0x2B
58 #define RF69_REG_PREAMBLE_MSB 0x2C
59 #define RF69_REG_PREAMBLE_LSB 0x2D
60 #define RF69_REG_SYNC_CONFIG 0x2E
61 #define RF69_REG_SYNC_VALUE_1 0x2F
62 #define RF69_REG_SYNC_VALUE_2 0x30
63 #define RF69_REG_SYNC_VALUE_3 0x31
64 #define RF69_REG_SYNC_VALUE_4 0x32
65 #define RF69_REG_SYNC_VALUE_5 0x33
66 #define RF69_REG_SYNC_VALUE_6 0x34
67 #define RF69_REG_SYNC_VALUE_7 0x35
68 #define RF69_REG_SYNC_VALUE_8 0x36
69 #define RF69_REG_PACKET_CONFIG_1 0x37
70 #define RF69_REG_PAYLOAD_LENGTH 0x38
71 #define RF69_REG_NODE_ADRS 0x39
72 #define RF69_REG_BROADCAST_ADRS 0x3A
73 #define RF69_REG_AUTO_MODES 0x3B
74 #define RF69_REG_FIFO_THRESH 0x3C
75 #define RF69_REG_PACKET_CONFIG_2 0x3D
76 #define RF69_REG_AES_KEY_1 0x3E
77 #define RF69_REG_AES_KEY_2 0x3F
78 #define RF69_REG_AES_KEY_3 0x40
79 #define RF69_REG_AES_KEY_4 0x41
80 #define RF69_REG_AES_KEY_5 0x42
81 #define RF69_REG_AES_KEY_6 0x43
82 #define RF69_REG_AES_KEY_7 0x44
83 #define RF69_REG_AES_KEY_8 0x45
84 #define RF69_REG_AES_KEY_9 0x46
85 #define RF69_REG_AES_KEY_10 0x47
86 #define RF69_REG_AES_KEY_11 0x48
87 #define RF69_REG_AES_KEY_12 0x49
88 #define RF69_REG_AES_KEY_13 0x4A
89 #define RF69_REG_AES_KEY_14 0x4B
90 #define RF69_REG_AES_KEY_15 0x4C
91 #define RF69_REG_AES_KEY_16 0x4D
92 #define RF69_REG_TEMP_1 0x4E
93 #define RF69_REG_TEMP_2 0x4F
94 #define RF69_REG_TEST_PA1 0x5A
95 #define RF69_REG_TEST_PA2 0x5C
96 #define RF69_REG_TEST_DAGC 0x6F
97 
98 // RF69 modem settings
99 // RF69_REG_OP_MODE MSB LSB DESCRIPTION
100 #define RF69_SEQUENCER_OFF 0b00000000 // 7 7 disable automatic sequencer
101 #define RF69_SEQUENCER_ON 0b10000000 // 7 7 enable automatic sequencer
102 #define RF69_LISTEN_OFF 0b00000000 // 6 6 disable Listen mode
103 #define RF69_LISTEN_ON 0b01000000 // 6 6 enable Listen mode
104 #define RF69_LISTEN_ABORT 0b00100000 // 5 5 abort Listen mode (has to be set together with RF69_LISTEN_OFF)
105 #define RF69_SLEEP 0b00000000 // 4 2 sleep
106 #define RF69_STANDBY 0b00000100 // 4 2 standby
107 #define RF69_FS 0b00001000 // 4 2 frequency synthesis
108 #define RF69_TX 0b00001100 // 4 2 transmit
109 #define RF69_RX 0b00010000 // 4 2 receive
110 
111 // RF69_REG_DATA_MODUL
112 #define RF69_PACKET_MODE 0b00000000 // 6 5 packet mode (default)
113 #define RF69_CONTINUOUS_MODE_WITH_SYNC 0b01000000 // 6 5 continuous mode with bit synchronizer
114 #define RF69_CONTINUOUS_MODE 0b01100000 // 6 5 continuous mode without bit synchronizer
115 #define RF69_FSK 0b00000000 // 4 3 modulation: FSK (default)
116 #define RF69_OOK 0b00001000 // 4 3 OOK
117 #define RF69_NO_SHAPING 0b00000000 // 1 0 modulation shaping: no shaping (default)
118 #define RF69_FSK_GAUSSIAN_1_0 0b00000001 // 1 0 FSK modulation Gaussian filter, BT = 1.0
119 #define RF69_FSK_GAUSSIAN_0_5 0b00000010 // 1 0 FSK modulation Gaussian filter, BT = 0.5
120 #define RF69_FSK_GAUSSIAN_0_3 0b00000011 // 1 0 FSK modulation Gaussian filter, BT = 0.3
121 #define RF69_OOK_FILTER_BR 0b00000001 // 1 0 OOK modulation filter, f_cutoff = BR
122 #define RF69_OOK_FILTER_2BR 0b00000010 // 1 0 OOK modulation filter, f_cutoff = 2*BR
123 
124 // RF69_REG_BITRATE_MSB + REG_BITRATE_LSB
125 #define RF69_BITRATE_MSB 0x1A // 7 0 bit rate setting: rate = F(XOSC) / BITRATE
126 #define RF69_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps 0x40 // 7 0
127 
128 // RF69_REG_FDEV_MSB + REG_FDEV_LSB
129 #define RF69_FDEV_MSB 0x00 // 5 0 frequency deviation: f_dev = f_step * FDEV
130 #define RF69_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
131 
132 // RF69_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
133 #define RF69_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
134 #define RF69_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
135 #define RF69_FRF_LSB 0x00 // 7 0 default value: 915 MHz
136 
137 // RF69_REG_OSC_1
138 #define RF69_RC_CAL_START 0b10000000 // 7 7 force RC oscillator calibration
139 #define RF69_RC_CAL_RUNNING 0b00000000 // 6 6 RC oscillator calibration is still running
140 #define RF69_RC_CAL_DONE 0b00000000 // 5 5 RC oscillator calibration has finished
141 
142 // RF69_REG_AFC_CTRL
143 #define RF69_AFC_LOW_BETA_OFF 0b00000000 // 5 5 standard AFC routine
144 #define RF69_AFC_LOW_BETA_ON 0b00100000 // 5 5 improved AFC routine for signals with modulation index less than 2
145 
146 // RF69_REG_LISTEN_1
147 #define RF69_LISTEN_RES_IDLE_64_US 0b01000000 // 7 6 resolution of Listen mode idle time: 64 us
148 #define RF69_LISTEN_RES_IDLE_4_1_MS 0b10000000 // 7 6 4.1 ms (default)
149 #define RF69_LISTEN_RES_IDLE_262_MS 0b11000000 // 7 6 262 ms
150 #define RF69_LISTEN_RES_RX_64_US 0b00010000 // 5 4 resolution of Listen mode rx time: 64 us (default)
151 #define RF69_LISTEN_RES_RX_4_1_MS 0b00100000 // 5 4 4.1 ms
152 #define RF69_LISTEN_RES_RX_262_MS 0b00110000 // 5 4 262 ms
153 #define RF69_LISTEN_ACCEPT_ABOVE_RSSI_THRESH 0b00000000 // 3 3 packet acceptance criteria: RSSI above threshold
154 #define RF69_LISTEN_ACCEPT_MATCH_SYNC_ADDRESS 0b00001000 // 3 3 RSSI above threshold AND sync address matched
155 #define RF69_LISTEN_END_KEEP_RX 0b00000000 // 2 1 action after packet acceptance: stay in Rx mode
156 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT 0b00000010 // 2 1 stay in Rx mode until timeout (default)
157 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT_RESUME 0b00000100 // 2 1 stay in Rx mode until timeout, Listen mode will resume
158 
159 // RF69_REG_LISTEN_2
160 #define RF69_LISTEN_COEF_IDLE 0xF5 // 7 0 duration of idle phase in Listen mode
161 
162 // RF69_REG_LISTEN_3
163 #define RF69_LISTEN_COEF_RX 0x20 // 7 0 duration of Rx phase in Listen mode
164 
165 // RF69_REG_PA_LEVEL
166 #define RF69_PA0_OFF 0b00000000 // 7 7 PA0 disabled
167 #define RF69_PA0_ON 0b10000000 // 7 7 PA0 enabled (default)
168 #define RF69_PA1_OFF 0b00000000 // 6 6 PA1 disabled (default)
169 #define RF69_PA1_ON 0b01000000 // 6 6 PA1 enabled
170 #define RF69_PA2_OFF 0b00000000 // 5 5 PA2 disabled (default)
171 #define RF69_PA2_ON 0b00100000 // 5 5 PA2 enabled
172 #define RF69_OUTPUT_POWER 0b00011111 // 4 0 output power: P_out = -18 + OUTPUT_POWER
173 
174 // RF69_REG_PA_RAMP
175 #define RF69_PA_RAMP_3_4_MS 0b00000000 // 3 0 PA ramp rise/fall time: 3.4 ms
176 #define RF69_PA_RAMP_2_MS 0b00000001 // 3 0 2 ms
177 #define RF69_PA_RAMP_1_MS 0b00000010 // 3 0 1 ms
178 #define RF69_PA_RAMP_500_US 0b00000011 // 3 0 500 us
179 #define RF69_PA_RAMP_250_US 0b00000100 // 3 0 250 us
180 #define RF69_PA_RAMP_125_US 0b00000101 // 3 0 125 us
181 #define RF69_PA_RAMP_100_US 0b00000110 // 3 0 100 us
182 #define RF69_PA_RAMP_62_US 0b00000111 // 3 0 62 us
183 #define RF69_PA_RAMP_50_US 0b00001000 // 3 0 50 us
184 #define RF69_PA_RAMP_40_US 0b00001001 // 3 0 40 us (default)
185 #define RF69_PA_RAMP_31_US 0b00001010 // 3 0 31 us
186 #define RF69_PA_RAMP_25_US 0b00001011 // 3 0 25 us
187 #define RF69_PA_RAMP_20_US 0b00001100 // 3 0 20 us
188 #define RF69_PA_RAMP_15_US 0b00001101 // 3 0 15 us
189 #define RF69_PA_RAMP_12_US 0b00001110 // 3 0 12 us
190 #define RF69_PA_RAMP_10_US 0b00001111 // 3 0 10 us
191 
192 // RF69_REG_OCP
193 #define RF69_OCP_OFF 0b00000000 // 4 4 PA overload current protection disabled
194 #define RF69_OCP_ON 0b00010000 // 4 4 PA overload current protection enabled
195 #define RF69_OCP_TRIM 0b00001010 // 3 0 OCP current: I_max(OCP_TRIM = 0b1010) = 95 mA
196 
197 // RF69_REG_LNA
198 #define RF69_LNA_Z_IN_50_OHM 0b00000000 // 7 7 LNA input impedance: 50 ohm
199 #define RF69_LNA_Z_IN_200_OHM 0b10000000 // 7 7 200 ohm
200 #define RF69_LNA_CURRENT_GAIN 0b00001000 // 5 3 manually set LNA current gain
201 #define RF69_LNA_GAIN_AUTO 0b00000000 // 2 0 LNA gain setting: set automatically by AGC
202 #define RF69_LNA_GAIN_MAX 0b00000001 // 2 0 max gain
203 #define RF69_LNA_GAIN_MAX_6_DB 0b00000010 // 2 0 max gain - 6 dB
204 #define RF69_LNA_GAIN_MAX_12_DB 0b00000011 // 2 0 max gain - 12 dB
205 #define RF69_LNA_GAIN_MAX_24_DB 0b00000100 // 2 0 max gain - 24 dB
206 #define RF69_LNA_GAIN_MAX_36_DB 0b00000101 // 2 0 max gain - 36 dB
207 #define RF69_LNA_GAIN_MAX_48_DB 0b00000110 // 2 0 max gain - 48 dB
208 
209 // RF69_REG_RX_BW
210 #define RF69_DCC_FREQ 0b01000000 // 7 5 DC offset canceller cutoff frequency (4% Rx BW by default)
211 #define RF69_RX_BW_MANT_16 0b00000000 // 4 3 Channel filter bandwidth FSK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 2))
212 #define RF69_RX_BW_MANT_20 0b00001000 // 4 3 OOK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 3))
213 #define RF69_RX_BW_MANT_24 0b00010000 // 4 3
214 #define RF69_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp value = 5
215 
216 // RF69_REG_AFC_BW
217 #define RF69_DCC_FREQ_AFC 0b10000000 // 7 5 default DccFreq parameter for AFC
218 #define RF69_DCC_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter for AFC
219 #define RF69_DCC_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter for AFC
220 
221 // RF69_REG_OOK_PEAK
222 #define RF69_OOK_THRESH_FIXED 0b00000000 // 7 6 OOK threshold type: fixed
223 #define RF69_OOK_THRESH_PEAK 0b01000000 // 7 6 peak (default)
224 #define RF69_OOK_THRESH_AVERAGE 0b10000000 // 7 6 average
225 #define RF69_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 5 3 OOK demodulator step size: 0.5 dB (default)
226 #define RF69_OOK_PEAK_THRESH_STEP_1_0_DB 0b00001000 // 5 3 1.0 dB
227 #define RF69_OOK_PEAK_THRESH_STEP_1_5_DB 0b00010000 // 5 3 1.5 dB
228 #define RF69_OOK_PEAK_THRESH_STEP_2_0_DB 0b00011000 // 5 3 2.0 dB
229 #define RF69_OOK_PEAK_THRESH_STEP_3_0_DB 0b00100000 // 5 3 3.0 dB
230 #define RF69_OOK_PEAK_THRESH_STEP_4_0_DB 0b00101000 // 5 3 4.0 dB
231 #define RF69_OOK_PEAK_THRESH_STEP_5_0_DB 0b00110000 // 5 3 5.0 dB
232 #define RF69_OOK_PEAK_THRESH_STEP_6_0_DB 0b00111000 // 5 3 6.0 dB
233 #define RF69_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 2 0 OOK demodulator step period: once per chip (default)
234 #define RF69_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00000001 // 2 0 once every 2 chips
235 #define RF69_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b00000010 // 2 0 once every 4 chips
236 #define RF69_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b00000011 // 2 0 once every 8 chips
237 #define RF69_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b00000100 // 2 0 2 times per chip
238 #define RF69_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b00000101 // 2 0 4 times per chip
239 #define RF69_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b00000110 // 2 0 8 times per chip
240 #define RF69_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b00000111 // 2 0 16 times per chip
241 
242 // RF69_REG_OOK_AVG
243 #define RF69_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 7 6 OOK average filter coefficient: chip rate / 32*pi
244 #define RF69_OOK_AVG_THRESH_FILT_8_PI 0b01000000 // 7 6 chip rate / 8*pi
245 #define RF69_OOK_AVG_THRESH_FILT_4_PI 0b10000000 // 7 6 chip rate / 4*pi (default)
246 #define RF69_OOK_AVG_THRESH_FILT_2_PI 0b11000000 // 7 6 chip rate / 2*pi
247 
248 // RF69_REG_OOK_FIX
249 #define RF69_OOK_FIXED_THRESH 0b00000110 // 7 0 default OOK fixed threshold (6 dB)
250 
251 // RF69_REG_AFC_FEI
252 #define RF69_FEI_RUNNING 0b00000000 // 6 6 FEI status: on-going
253 #define RF69_FEI_DONE 0b01000000 // 6 6 done
254 #define RF69_FEI_START 0b00100000 // 5 5 force new FEI measurement
255 #define RF69_AFC_RUNNING 0b00000000 // 4 4 AFC status: on-going
256 #define RF69_AFC_DONE 0b00010000 // 4 4 done
257 #define RF69_AFC_AUTOCLEAR_OFF 0b00000000 // 3 3 AFC register autoclear disabled
258 #define RF69_AFC_AUTOCLEAR_ON 0b00001000 // 3 3 AFC register autoclear enabled
259 #define RF69_AFC_AUTO_OFF 0b00000000 // 2 2 perform AFC only manually
260 #define RF69_AFC_AUTO_ON 0b00000100 // 2 2 perform AFC each time Rx mode is started
261 #define RF69_AFC_CLEAR 0b00000010 // 1 1 clear AFC register
262 #define RF69_AFC_START 0b00000001 // 0 0 start AFC
263 
264 // RF69_REG_RSSI_CONFIG
265 #define RF69_RSSI_RUNNING 0b00000000 // 1 1 RSSI status: on-going
266 #define RF69_RSSI_DONE 0b00000010 // 1 1 done
267 #define RF69_RSSI_START 0b00000001 // 0 0 start RSSI measurement
268 
269 // RF69_REG_DIO_MAPPING_1
270 #define RF69_DIO0_CONT_MODE_READY 0b11000000 // 7 6
271 #define RF69_DIO0_CONT_PLL_LOCK 0b00000000 // 7 6
272 #define RF69_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
273 #define RF69_DIO0_CONT_TIMEOUT 0b01000000 // 7 6
274 #define RF69_DIO0_CONT_RSSI 0b10000000 // 7 6
275 #define RF69_DIO0_CONT_TX_READY 0b01000000 // 7 6
276 #define RF69_DIO0_PACK_PLL_LOCK 0b11000000 // 7 6
277 #define RF69_DIO0_PACK_CRC_OK 0b00000000 // 7 6
278 #define RF69_DIO0_PACK_PAYLOAD_READY 0b01000000 // 7 6
279 #define RF69_DIO0_PACK_SYNC_ADDRESS 0b10000000 // 7 6
280 #define RF69_DIO0_PACK_RSSI 0b11000000 // 7 6
281 #define RF69_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
282 #define RF69_DIO0_PACK_TX_READY 0b01000000 // 7 6
283 #define RF69_DIO1_CONT_PLL_LOCK 0b00110000 // 5 4
284 #define RF69_DIO1_CONT_DCLK 0b00000000 // 5 4
285 #define RF69_DIO1_CONT_RX_READY 0b00010000 // 5 4
286 #define RF69_DIO1_CONT_SYNC_ADDRESS 0b00110000 // 5 4
287 #define RF69_DIO1_CONT_TX_READY 0b00010000 // 5 4
288 #define RF69_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
289 #define RF69_DIO1_PACK_FIFO_FULL 0b00010000 // 5 4
290 #define RF69_DIO1_PACK_FIFO_NOT_EMPTY 0b00100000 // 5 4
291 #define RF69_DIO1_PACK_PLL_LOCK 0b00110000 // 5 4
292 #define RF69_DIO1_PACK_TIMEOUT 0b00110000 // 5 4
293 #define RF69_DIO2_CONT_DATA 0b00000000 // 3 2
294 
295 // RF69_REG_DIO_MAPPING_2
296 #define RF69_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
297 #define RF69_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
298 #define RF69_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
299 #define RF69_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
300 #define RF69_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
301 #define RF69_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 31
302 #define RF69_CLK_OUT_RC 0b00000110 // 2 0 RC
303 #define RF69_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
304 
305 // RF69_REG_IRQ_FLAGS_1
306 #define RF69_IRQ_MODE_READY 0b10000000 // 7 7 requested mode was set
307 #define RF69_IRQ_RX_READY 0b01000000 // 6 6 Rx mode ready
308 #define RF69_IRQ_TX_READY 0b00100000 // 5 5 Tx mode ready
309 #define RF69_IRQ_PLL_LOCK 0b00010000 // 4 4 PLL is locked
310 #define RF69_IRQ_RSSI 0b00001000 // 3 3 RSSI value exceeded RssiThreshold
311 #define RF69_IRQ_TIMEOUT 0b00000100 // 2 2 timeout occurred
312 #define RF69_IRQ_AUTO_MODE 0b00000010 // 1 1 entered intermediate mode
313 #define RF69_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address detected
314 
315 // RF69_REG_IRQ_FLAGS_2
316 #define RF69_IRQ_FIFO_FULL 0b10000000 // 7 7 FIFO is full
317 #define RF69_IRQ_FIFO_NOT_EMPTY 0b01000000 // 6 6 FIFO contains at least 1 byte
318 #define RF69_IRQ_FIFO_LEVEL 0b00100000 // 5 5 FIFO contains more than FifoThreshold bytes
319 #define RF69_IRQ_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
320 #define RF69_IRQ_PACKET_SENT 0b00001000 // 3 3 packet was sent
321 #define RF69_IRQ_PAYLOAD_READY 0b00000100 // 2 2 last payload byte received and CRC check passed
322 #define RF69_IRQ_CRC_OK 0b00000010 // 1 1 CRC check passed
323 
324 // RF69_REG_RSSI_THRESH
325 #define RF69_RSSI_THRESHOLD 0xE4 // 7 0 RSSI threshold level (2 dB by default)
326 
327 // RF69_REG_RX_TIMEOUT_1
328 #define RF69_TIMEOUT_RX_START_OFF 0x00 // 7 0 RSSI interrupt timeout disabled (default)
329 #define RF69_TIMEOUT_RX_START 0xFF // 7 0 timeout will occur if RSSI interrupt is not received
330 
331 // RF69_REG_RX_TIMEOUT_2
332 #define RF69_TIMEOUT_RSSI_THRESH_OFF 0x00 // 7 0 PayloadReady interrupt timeout disabled (default)
333 #define RF69_TIMEOUT_RSSI_THRESH 0xFF // 7 0 timeout will occur if PayloadReady interrupt is not received
334 
335 // RF69_REG_PREAMBLE_MSB + REG_PREAMBLE_MSB
336 #define RF69_PREAMBLE_MSB 0x00 // 7 0 2-byte preamble size value
337 #define RF69_PREAMBLE_LSB 0x03 // 7 0
338 
339 // RF69_REG_SYNC_CONFIG
340 #define RF69_SYNC_OFF 0b00000000 // 7 7 sync word detection off
341 #define RF69_SYNC_ON 0b10000000 // 7 7 sync word detection on (default)
342 #define RF69_FIFO_FILL_CONDITION_SYNC 0b00000000 // 6 6 FIFO fill condition: on SyncAddress interrupt (default)
343 #define RF69_FIFO_FILL_CONDITION 0b01000000 // 6 6 as long as the bit is set
344 #define RF69_SYNC_SIZE 0b00001000 // 5 3 size of sync word: SyncSize + 1 bytes
345 #define RF69_SYNC_TOL 0b00000000 // 2 0 number of tolerated errors in sync word
346 
347 // RF69_REG_SYNC_VALUE_1 - SYNC_VALUE_8
348 #define RF69_SYNC_BYTE_1 0x01 // 7 0 sync word: 1st byte (MSB)
349 #define RF69_SYNC_BYTE_2 0x01 // 7 0 2nd byte
350 #define RF69_SYNC_BYTE_3 0x01 // 7 0 3rd byte
351 #define RF69_SYNC_BYTE_4 0x01 // 7 0 4th byte
352 #define RF69_SYNC_BYTE_5 0x01 // 7 0 5th byte
353 #define RF69_SYNC_BYTE_6 0x01 // 7 0 6th byte
354 #define RF69_SYNC_BYTE_7 0x01 // 7 0 7th byte
355 #define RF69_SYNC_BYTE_8 0x01 // 7 0 8th byte (LSB)
356 
357 // RF69_REG_PACKET_CONFIG_1
358 #define RF69_PACKET_FORMAT_FIXED 0b00000000 // 7 7 fixed packet length (default)
359 #define RF69_PACKET_FORMAT_VARIABLE 0b10000000 // 7 7 variable packet length
360 #define RF69_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: none (default)
361 #define RF69_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
362 #define RF69_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
363 #define RF69_CRC_OFF 0b00000000 // 4 4 CRC disabled
364 #define RF69_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
365 #define RF69_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 discard packet when CRC check fails (default)
366 #define RF69_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep packet when CRC check fails
367 #define RF69_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
368 #define RF69_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
369 #define RF69_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
370 
371 // RF69_REG_PAYLOAD_LENGTH
372 #define RF69_PAYLOAD_LENGTH 0xFF // 7 0 payload length
373 
374 // RF69_REG_AUTO_MODES
375 #define RF69_ENTER_COND_NONE 0b00000000 // 7 5 condition for entering intermediate mode: none, AutoModes disabled (default)
376 #define RF69_ENTER_COND_FIFO_NOT_EMPTY 0b00100000 // 7 5 FifoNotEmpty rising edge
377 #define RF69_ENTER_COND_FIFO_LEVEL 0b01000000 // 7 5 FifoLevel rising edge
378 #define RF69_ENTER_COND_CRC_OK 0b01100000 // 7 5 CrcOk rising edge
379 #define RF69_ENTER_COND_PAYLOAD_READY 0b10000000 // 7 5 PayloadReady rising edge
380 #define RF69_ENTER_COND_SYNC_ADDRESS 0b10100000 // 7 5 SyncAddress rising edge
381 #define RF69_ENTER_COND_PACKET_SENT 0b11000000 // 7 5 PacketSent rising edge
382 #define RF69_ENTER_COND_FIFO_EMPTY 0b11100000 // 7 5 FifoNotEmpty falling edge
383 #define RF69_EXIT_COND_NONE 0b00000000 // 4 2 condition for exiting intermediate mode: none, AutoModes disabled (default)
384 #define RF69_EXIT_COND_FIFO_EMPTY 0b00100000 // 4 2 FifoNotEmpty falling edge
385 #define RF69_EXIT_COND_FIFO_LEVEL 0b01000000 // 4 2 FifoLevel rising edge
386 #define RF69_EXIT_COND_CRC_OK 0b01100000 // 4 2 CrcOk rising edge
387 #define RF69_EXIT_COND_PAYLOAD_READY 0b10000000 // 4 2 PayloadReady rising edge
388 #define RF69_EXIT_COND_SYNC_ADDRESS 0b10100000 // 4 2 SyncAddress rising edge
389 #define RF69_EXIT_COND_PACKET_SENT 0b11000000 // 4 2 PacketSent rising edge
390 #define RF69_EXIT_COND_TIMEOUT 0b11100000 // 4 2 timeout rising edge
391 #define RF69_INTER_MODE_SLEEP 0b00000000 // 1 0 intermediate mode: sleep (default)
392 #define RF69_INTER_MODE_STANDBY 0b00000001 // 1 0 standby
393 #define RF69_INTER_MODE_RX 0b00000010 // 1 0 Rx
394 #define RF69_INTER_MODE_TX 0b00000011 // 1 0 Tx
395 
396 // RF69_REG_FIFO_THRESH
397 #define RF69_TX_START_CONDITION_FIFO_LEVEL 0b00000000 // 7 7 packet transmission start condition: FifoLevel
398 #define RF69_TX_START_CONDITION_FIFO_NOT_EMPTY 0b10000000 // 7 7 FifoNotEmpty (default)
399 #define RF69_FIFO_THRESHOLD 0b00001111 // 6 0 default threshold to trigger FifoLevel interrupt
400 
401 // RF69_REG_PACKET_CONFIG_2
402 #define RF69_INTER_PACKET_RX_DELAY 0b00000000 // 7 4 delay between FIFO empty and start of new RSSI phase
403 #define RF69_RESTART_RX 0b00000100 // 2 2 force receiver into wait mode
404 #define RF69_AUTO_RX_RESTART_OFF 0b00000000 // 1 1 auto Rx restart disabled
405 #define RF69_AUTO_RX_RESTART_ON 0b00000010 // 1 1 auto Rx restart enabled (default)
406 #define RF69_AES_OFF 0b00000000 // 0 0 AES encryption disabled (default)
407 #define RF69_AES_ON 0b00000001 // 0 0 AES encryption enabled, payload size limited to 66 bytes
408 
409 // RF69_REG_TEMP_1
410 #define RF69_TEMP_MEAS_START 0b00001000 // 3 3 trigger temperature measurement
411 #define RF69_TEMP_MEAS_RUNNING 0b00000100 // 2 2 temperature measurement status: on-going
412 #define RF69_TEMP_MEAS_DONE 0b00000000 // 2 2 done
413 
414 // RF69_REG_TEST_DAGC
415 #define RF69_CONTINUOUS_DAGC_NORMAL 0x00 // 7 0 fading margin improvement: normal mode
416 #define RF69_CONTINUOUS_DAGC_LOW_BETA_ON 0x20 // 7 0 improved mode for AfcLowBetaOn
417 #define RF69_CONTINUOUS_DAGC_LOW_BETA_OFF 0x30 // 7 0 improved mode for AfcLowBetaOff (default)
418 
419 // RF69_REG_TEST_PA1
420 #define RF69_PA1_NORMAL 0x55 // 7 0 PA_BOOST: none
421 #define RF69_PA1_20_DBM 0x5D // 7 0 +20 dBm
422 
423 // RF69_REG_TEST_PA2
424 #define RF69_PA2_NORMAL 0x70 // 7 0 PA_BOOST: none
425 #define RF69_PA2_20_DBM 0x7C // 7 0 +20 dBm
426 
432 class RF69: public PhysicalLayer {
433  public:
434  // introduce PhysicalLayer overloads
435  using PhysicalLayer::transmit;
436  using PhysicalLayer::receive;
437  using PhysicalLayer::startTransmit;
438  using PhysicalLayer::readData;
439 
445  RF69(Module* module);
446 
447  // basic methods
448 
466  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint8_t preambleLen = 16);
467 
471  void reset();
472 
485  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
486 
497  int16_t receive(uint8_t* data, size_t len) override;
498 
504  int16_t sleep();
505 
511  int16_t standby() override;
512 
520  int16_t transmitDirect(uint32_t frf = 0) override;
521 
527  int16_t receiveDirect() override;
528 
532  int16_t packetMode();
533 
534  // hardware AES support
535 
541  void setAESKey(uint8_t* key);
542 
548  int16_t enableAES();
549 
555  int16_t disableAES();
556 
557  // interrupt methods
558 
564  void setDio0Action(void (*func)(void));
565 
569  void clearDio0Action();
570 
576  void setDio1Action(void (*func)(void));
577 
581  void clearDio1Action();
582 
595  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
596 
602  int16_t startReceive();
603 
613  int16_t readData(uint8_t* data, size_t len) override;
614 
615  // configuration methods
616 
624  int16_t setFrequency(float freq);
625 
633  int16_t setBitRate(float br);
634 
642  int16_t setRxBandwidth(float rxBw);
643 
651  int16_t setFrequencyDeviation(float freqDev) override;
652 
662  int16_t setOutputPower(int8_t power, bool highPower = false);
663 
673  int16_t setSyncWord(uint8_t* syncWord, size_t len, uint8_t maxErrBits = 0);
674 
682  int16_t setPreambleLength(uint8_t preambleLen);
683 
691  int16_t setNodeAddress(uint8_t nodeAddr);
692 
700  int16_t setBroadcastAddress(uint8_t broadAddr);
701 
707  int16_t disableAddressFiltering();
708 
709  // measurement methods
710 
716  void setAmbientTemperature(int16_t tempAmbient);
717 
723  int16_t getTemperature();
724 
732  size_t getPacketLength(bool update = true) override;
733 
741  int16_t fixedPacketLengthMode(uint8_t len = RF69_MAX_PACKET_LENGTH);
742 
750  int16_t variablePacketLengthMode(uint8_t maxLen = RF69_MAX_PACKET_LENGTH);
751 
759  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0);
760 
766  int16_t disableSyncWordFiltering();
767 
775  int16_t setCrcFiltering(bool crcOn = true);
776 
784  int16_t setPromiscuousMode(bool promiscuous = true);
785 
794  int16_t setDataShaping(uint8_t sh) override;
795 
804  int16_t setEncoding(uint8_t encoding) override;
805 
811  float getRSSI();
812 
821  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
822 
828  uint8_t random();
829 
830 #ifndef RADIOLIB_GODMODE
831  protected:
832 #endif
833  Module* _mod;
834 
835  float _br = 0;
836  float _rxBw = 0;
837  int16_t _tempOffset = 0;
838  int8_t _power = 0;
839 
840  size_t _packetLength = 0;
841  bool _packetLengthQueried = false;
842  uint8_t _packetLengthConfig = RF69_PACKET_FORMAT_VARIABLE;
843 
844  bool _promiscuous = false;
845 
846  uint8_t _syncWordLength = 2;
847 
848  int16_t config();
849  int16_t directMode();
850  int16_t setPacketMode(uint8_t mode, uint8_t len);
851 
852 #ifndef RADIOLIB_GODMODE
853  private:
854 #endif
855  int16_t setMode(uint8_t mode);
856  void clearIRQFlags();
857 };
858 
859 #endif
860 
861 #endif
RF69::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets frequency deviation.
Definition: RF69.cpp:507
+
1 #if !defined(_RADIOLIB_RF69_H)
2 #define _RADIOLIB_RF69_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_RF69)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // RF69 physical layer properties
13 #define RF69_FREQUENCY_STEP_SIZE 61.03515625
14 #define RF69_MAX_PACKET_LENGTH 64
15 #define RF69_CRYSTAL_FREQ 32.0
16 #define RF69_DIV_EXPONENT 19
17 
18 // RF69 register map
19 #define RF69_REG_FIFO 0x00
20 #define RF69_REG_OP_MODE 0x01
21 #define RF69_REG_DATA_MODUL 0x02
22 #define RF69_REG_BITRATE_MSB 0x03
23 #define RF69_REG_BITRATE_LSB 0x04
24 #define RF69_REG_FDEV_MSB 0x05
25 #define RF69_REG_FDEV_LSB 0x06
26 #define RF69_REG_FRF_MSB 0x07
27 #define RF69_REG_FRF_MID 0x08
28 #define RF69_REG_FRF_LSB 0x09
29 #define RF69_REG_OSC_1 0x0A
30 #define RF69_REG_AFC_CTRL 0x0B
31 #define RF69_REG_LISTEN_1 0x0D
32 #define RF69_REG_LISTEN_2 0x0E
33 #define RF69_REG_LISTEN_3 0x0F
34 #define RF69_REG_VERSION 0x10
35 #define RF69_REG_PA_LEVEL 0x11
36 #define RF69_REG_PA_RAMP 0x12
37 #define RF69_REG_OCP 0x13
38 #define RF69_REG_LNA 0x18
39 #define RF69_REG_RX_BW 0x19
40 #define RF69_REG_AFC_BW 0x1A
41 #define RF69_REG_OOK_PEAK 0x1B
42 #define RF69_REG_OOK_AVG 0x1C
43 #define RF69_REG_OOK_FIX 0x1D
44 #define RF69_REG_AFC_FEI 0x1E
45 #define RF69_REG_AFC_MSB 0x1F
46 #define RF69_REG_AFC_LSB 0x20
47 #define RF69_REG_FEI_MSB 0x21
48 #define RF69_REG_FEI_LSB 0x22
49 #define RF69_REG_RSSI_CONFIG 0x23
50 #define RF69_REG_RSSI_VALUE 0x24
51 #define RF69_REG_DIO_MAPPING_1 0x25
52 #define RF69_REG_DIO_MAPPING_2 0x26
53 #define RF69_REG_IRQ_FLAGS_1 0x27
54 #define RF69_REG_IRQ_FLAGS_2 0x28
55 #define RF69_REG_RSSI_THRESH 0x29
56 #define RF69_REG_RX_TIMEOUT_1 0x2A
57 #define RF69_REG_RX_TIMEOUT_2 0x2B
58 #define RF69_REG_PREAMBLE_MSB 0x2C
59 #define RF69_REG_PREAMBLE_LSB 0x2D
60 #define RF69_REG_SYNC_CONFIG 0x2E
61 #define RF69_REG_SYNC_VALUE_1 0x2F
62 #define RF69_REG_SYNC_VALUE_2 0x30
63 #define RF69_REG_SYNC_VALUE_3 0x31
64 #define RF69_REG_SYNC_VALUE_4 0x32
65 #define RF69_REG_SYNC_VALUE_5 0x33
66 #define RF69_REG_SYNC_VALUE_6 0x34
67 #define RF69_REG_SYNC_VALUE_7 0x35
68 #define RF69_REG_SYNC_VALUE_8 0x36
69 #define RF69_REG_PACKET_CONFIG_1 0x37
70 #define RF69_REG_PAYLOAD_LENGTH 0x38
71 #define RF69_REG_NODE_ADRS 0x39
72 #define RF69_REG_BROADCAST_ADRS 0x3A
73 #define RF69_REG_AUTO_MODES 0x3B
74 #define RF69_REG_FIFO_THRESH 0x3C
75 #define RF69_REG_PACKET_CONFIG_2 0x3D
76 #define RF69_REG_AES_KEY_1 0x3E
77 #define RF69_REG_AES_KEY_2 0x3F
78 #define RF69_REG_AES_KEY_3 0x40
79 #define RF69_REG_AES_KEY_4 0x41
80 #define RF69_REG_AES_KEY_5 0x42
81 #define RF69_REG_AES_KEY_6 0x43
82 #define RF69_REG_AES_KEY_7 0x44
83 #define RF69_REG_AES_KEY_8 0x45
84 #define RF69_REG_AES_KEY_9 0x46
85 #define RF69_REG_AES_KEY_10 0x47
86 #define RF69_REG_AES_KEY_11 0x48
87 #define RF69_REG_AES_KEY_12 0x49
88 #define RF69_REG_AES_KEY_13 0x4A
89 #define RF69_REG_AES_KEY_14 0x4B
90 #define RF69_REG_AES_KEY_15 0x4C
91 #define RF69_REG_AES_KEY_16 0x4D
92 #define RF69_REG_TEMP_1 0x4E
93 #define RF69_REG_TEMP_2 0x4F
94 #define RF69_REG_TEST_PA1 0x5A
95 #define RF69_REG_TEST_PA2 0x5C
96 #define RF69_REG_TEST_DAGC 0x6F
97 
98 // RF69 modem settings
99 // RF69_REG_OP_MODE MSB LSB DESCRIPTION
100 #define RF69_SEQUENCER_OFF 0b00000000 // 7 7 disable automatic sequencer
101 #define RF69_SEQUENCER_ON 0b10000000 // 7 7 enable automatic sequencer
102 #define RF69_LISTEN_OFF 0b00000000 // 6 6 disable Listen mode
103 #define RF69_LISTEN_ON 0b01000000 // 6 6 enable Listen mode
104 #define RF69_LISTEN_ABORT 0b00100000 // 5 5 abort Listen mode (has to be set together with RF69_LISTEN_OFF)
105 #define RF69_SLEEP 0b00000000 // 4 2 sleep
106 #define RF69_STANDBY 0b00000100 // 4 2 standby
107 #define RF69_FS 0b00001000 // 4 2 frequency synthesis
108 #define RF69_TX 0b00001100 // 4 2 transmit
109 #define RF69_RX 0b00010000 // 4 2 receive
110 
111 // RF69_REG_DATA_MODUL
112 #define RF69_PACKET_MODE 0b00000000 // 6 5 packet mode (default)
113 #define RF69_CONTINUOUS_MODE_WITH_SYNC 0b01000000 // 6 5 continuous mode with bit synchronizer
114 #define RF69_CONTINUOUS_MODE 0b01100000 // 6 5 continuous mode without bit synchronizer
115 #define RF69_FSK 0b00000000 // 4 3 modulation: FSK (default)
116 #define RF69_OOK 0b00001000 // 4 3 OOK
117 #define RF69_NO_SHAPING 0b00000000 // 1 0 modulation shaping: no shaping (default)
118 #define RF69_FSK_GAUSSIAN_1_0 0b00000001 // 1 0 FSK modulation Gaussian filter, BT = 1.0
119 #define RF69_FSK_GAUSSIAN_0_5 0b00000010 // 1 0 FSK modulation Gaussian filter, BT = 0.5
120 #define RF69_FSK_GAUSSIAN_0_3 0b00000011 // 1 0 FSK modulation Gaussian filter, BT = 0.3
121 #define RF69_OOK_FILTER_BR 0b00000001 // 1 0 OOK modulation filter, f_cutoff = BR
122 #define RF69_OOK_FILTER_2BR 0b00000010 // 1 0 OOK modulation filter, f_cutoff = 2*BR
123 
124 // RF69_REG_BITRATE_MSB + REG_BITRATE_LSB
125 #define RF69_BITRATE_MSB 0x1A // 7 0 bit rate setting: rate = F(XOSC) / BITRATE
126 #define RF69_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps 0x40 // 7 0
127 
128 // RF69_REG_FDEV_MSB + REG_FDEV_LSB
129 #define RF69_FDEV_MSB 0x00 // 5 0 frequency deviation: f_dev = f_step * FDEV
130 #define RF69_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
131 
132 // RF69_REG_FRF_MSB + REG_FRF_MID + REG_FRF_LSB
133 #define RF69_FRF_MSB 0xE4 // 7 0 carrier frequency setting: f_RF = (F(XOSC) * FRF)/2^19
134 #define RF69_FRF_MID 0xC0 // 7 0 where F(XOSC) = 32 MHz
135 #define RF69_FRF_LSB 0x00 // 7 0 default value: 915 MHz
136 
137 // RF69_REG_OSC_1
138 #define RF69_RC_CAL_START 0b10000000 // 7 7 force RC oscillator calibration
139 #define RF69_RC_CAL_RUNNING 0b00000000 // 6 6 RC oscillator calibration is still running
140 #define RF69_RC_CAL_DONE 0b00000000 // 5 5 RC oscillator calibration has finished
141 
142 // RF69_REG_AFC_CTRL
143 #define RF69_AFC_LOW_BETA_OFF 0b00000000 // 5 5 standard AFC routine
144 #define RF69_AFC_LOW_BETA_ON 0b00100000 // 5 5 improved AFC routine for signals with modulation index less than 2
145 
146 // RF69_REG_LISTEN_1
147 #define RF69_LISTEN_RES_IDLE_64_US 0b01000000 // 7 6 resolution of Listen mode idle time: 64 us
148 #define RF69_LISTEN_RES_IDLE_4_1_MS 0b10000000 // 7 6 4.1 ms (default)
149 #define RF69_LISTEN_RES_IDLE_262_MS 0b11000000 // 7 6 262 ms
150 #define RF69_LISTEN_RES_RX_64_US 0b00010000 // 5 4 resolution of Listen mode rx time: 64 us (default)
151 #define RF69_LISTEN_RES_RX_4_1_MS 0b00100000 // 5 4 4.1 ms
152 #define RF69_LISTEN_RES_RX_262_MS 0b00110000 // 5 4 262 ms
153 #define RF69_LISTEN_ACCEPT_ABOVE_RSSI_THRESH 0b00000000 // 3 3 packet acceptance criteria: RSSI above threshold
154 #define RF69_LISTEN_ACCEPT_MATCH_SYNC_ADDRESS 0b00001000 // 3 3 RSSI above threshold AND sync address matched
155 #define RF69_LISTEN_END_KEEP_RX 0b00000000 // 2 1 action after packet acceptance: stay in Rx mode
156 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT 0b00000010 // 2 1 stay in Rx mode until timeout (default)
157 #define RF69_LISTEN_END_KEEP_RX_TIMEOUT_RESUME 0b00000100 // 2 1 stay in Rx mode until timeout, Listen mode will resume
158 
159 // RF69_REG_LISTEN_2
160 #define RF69_LISTEN_COEF_IDLE 0xF5 // 7 0 duration of idle phase in Listen mode
161 
162 // RF69_REG_LISTEN_3
163 #define RF69_LISTEN_COEF_RX 0x20 // 7 0 duration of Rx phase in Listen mode
164 
165 // RF69_REG_VERSION
166 #define RF69_CHIP_VERSION 0x24 // 7 0
167 
168 // RF69_REG_PA_LEVEL
169 #define RF69_PA0_OFF 0b00000000 // 7 7 PA0 disabled
170 #define RF69_PA0_ON 0b10000000 // 7 7 PA0 enabled (default)
171 #define RF69_PA1_OFF 0b00000000 // 6 6 PA1 disabled (default)
172 #define RF69_PA1_ON 0b01000000 // 6 6 PA1 enabled
173 #define RF69_PA2_OFF 0b00000000 // 5 5 PA2 disabled (default)
174 #define RF69_PA2_ON 0b00100000 // 5 5 PA2 enabled
175 #define RF69_OUTPUT_POWER 0b00011111 // 4 0 output power: P_out = -18 + OUTPUT_POWER
176 
177 // RF69_REG_PA_RAMP
178 #define RF69_PA_RAMP_3_4_MS 0b00000000 // 3 0 PA ramp rise/fall time: 3.4 ms
179 #define RF69_PA_RAMP_2_MS 0b00000001 // 3 0 2 ms
180 #define RF69_PA_RAMP_1_MS 0b00000010 // 3 0 1 ms
181 #define RF69_PA_RAMP_500_US 0b00000011 // 3 0 500 us
182 #define RF69_PA_RAMP_250_US 0b00000100 // 3 0 250 us
183 #define RF69_PA_RAMP_125_US 0b00000101 // 3 0 125 us
184 #define RF69_PA_RAMP_100_US 0b00000110 // 3 0 100 us
185 #define RF69_PA_RAMP_62_US 0b00000111 // 3 0 62 us
186 #define RF69_PA_RAMP_50_US 0b00001000 // 3 0 50 us
187 #define RF69_PA_RAMP_40_US 0b00001001 // 3 0 40 us (default)
188 #define RF69_PA_RAMP_31_US 0b00001010 // 3 0 31 us
189 #define RF69_PA_RAMP_25_US 0b00001011 // 3 0 25 us
190 #define RF69_PA_RAMP_20_US 0b00001100 // 3 0 20 us
191 #define RF69_PA_RAMP_15_US 0b00001101 // 3 0 15 us
192 #define RF69_PA_RAMP_12_US 0b00001110 // 3 0 12 us
193 #define RF69_PA_RAMP_10_US 0b00001111 // 3 0 10 us
194 
195 // RF69_REG_OCP
196 #define RF69_OCP_OFF 0b00000000 // 4 4 PA overload current protection disabled
197 #define RF69_OCP_ON 0b00010000 // 4 4 PA overload current protection enabled
198 #define RF69_OCP_TRIM 0b00001010 // 3 0 OCP current: I_max(OCP_TRIM = 0b1010) = 95 mA
199 
200 // RF69_REG_LNA
201 #define RF69_LNA_Z_IN_50_OHM 0b00000000 // 7 7 LNA input impedance: 50 ohm
202 #define RF69_LNA_Z_IN_200_OHM 0b10000000 // 7 7 200 ohm
203 #define RF69_LNA_CURRENT_GAIN 0b00001000 // 5 3 manually set LNA current gain
204 #define RF69_LNA_GAIN_AUTO 0b00000000 // 2 0 LNA gain setting: set automatically by AGC
205 #define RF69_LNA_GAIN_MAX 0b00000001 // 2 0 max gain
206 #define RF69_LNA_GAIN_MAX_6_DB 0b00000010 // 2 0 max gain - 6 dB
207 #define RF69_LNA_GAIN_MAX_12_DB 0b00000011 // 2 0 max gain - 12 dB
208 #define RF69_LNA_GAIN_MAX_24_DB 0b00000100 // 2 0 max gain - 24 dB
209 #define RF69_LNA_GAIN_MAX_36_DB 0b00000101 // 2 0 max gain - 36 dB
210 #define RF69_LNA_GAIN_MAX_48_DB 0b00000110 // 2 0 max gain - 48 dB
211 
212 // RF69_REG_RX_BW
213 #define RF69_DCC_FREQ 0b01000000 // 7 5 DC offset canceller cutoff frequency (4% Rx BW by default)
214 #define RF69_RX_BW_MANT_16 0b00000000 // 4 3 Channel filter bandwidth FSK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 2))
215 #define RF69_RX_BW_MANT_20 0b00001000 // 4 3 OOK: RxBw = F(XOSC)/(RxBwMant * 2^(RxBwExp + 3))
216 #define RF69_RX_BW_MANT_24 0b00010000 // 4 3
217 #define RF69_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp value = 5
218 
219 // RF69_REG_AFC_BW
220 #define RF69_DCC_FREQ_AFC 0b10000000 // 7 5 default DccFreq parameter for AFC
221 #define RF69_DCC_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter for AFC
222 #define RF69_DCC_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter for AFC
223 
224 // RF69_REG_OOK_PEAK
225 #define RF69_OOK_THRESH_FIXED 0b00000000 // 7 6 OOK threshold type: fixed
226 #define RF69_OOK_THRESH_PEAK 0b01000000 // 7 6 peak (default)
227 #define RF69_OOK_THRESH_AVERAGE 0b10000000 // 7 6 average
228 #define RF69_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 5 3 OOK demodulator step size: 0.5 dB (default)
229 #define RF69_OOK_PEAK_THRESH_STEP_1_0_DB 0b00001000 // 5 3 1.0 dB
230 #define RF69_OOK_PEAK_THRESH_STEP_1_5_DB 0b00010000 // 5 3 1.5 dB
231 #define RF69_OOK_PEAK_THRESH_STEP_2_0_DB 0b00011000 // 5 3 2.0 dB
232 #define RF69_OOK_PEAK_THRESH_STEP_3_0_DB 0b00100000 // 5 3 3.0 dB
233 #define RF69_OOK_PEAK_THRESH_STEP_4_0_DB 0b00101000 // 5 3 4.0 dB
234 #define RF69_OOK_PEAK_THRESH_STEP_5_0_DB 0b00110000 // 5 3 5.0 dB
235 #define RF69_OOK_PEAK_THRESH_STEP_6_0_DB 0b00111000 // 5 3 6.0 dB
236 #define RF69_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 2 0 OOK demodulator step period: once per chip (default)
237 #define RF69_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00000001 // 2 0 once every 2 chips
238 #define RF69_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b00000010 // 2 0 once every 4 chips
239 #define RF69_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b00000011 // 2 0 once every 8 chips
240 #define RF69_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b00000100 // 2 0 2 times per chip
241 #define RF69_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b00000101 // 2 0 4 times per chip
242 #define RF69_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b00000110 // 2 0 8 times per chip
243 #define RF69_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b00000111 // 2 0 16 times per chip
244 
245 // RF69_REG_OOK_AVG
246 #define RF69_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 7 6 OOK average filter coefficient: chip rate / 32*pi
247 #define RF69_OOK_AVG_THRESH_FILT_8_PI 0b01000000 // 7 6 chip rate / 8*pi
248 #define RF69_OOK_AVG_THRESH_FILT_4_PI 0b10000000 // 7 6 chip rate / 4*pi (default)
249 #define RF69_OOK_AVG_THRESH_FILT_2_PI 0b11000000 // 7 6 chip rate / 2*pi
250 
251 // RF69_REG_OOK_FIX
252 #define RF69_OOK_FIXED_THRESH 0b00000110 // 7 0 default OOK fixed threshold (6 dB)
253 
254 // RF69_REG_AFC_FEI
255 #define RF69_FEI_RUNNING 0b00000000 // 6 6 FEI status: on-going
256 #define RF69_FEI_DONE 0b01000000 // 6 6 done
257 #define RF69_FEI_START 0b00100000 // 5 5 force new FEI measurement
258 #define RF69_AFC_RUNNING 0b00000000 // 4 4 AFC status: on-going
259 #define RF69_AFC_DONE 0b00010000 // 4 4 done
260 #define RF69_AFC_AUTOCLEAR_OFF 0b00000000 // 3 3 AFC register autoclear disabled
261 #define RF69_AFC_AUTOCLEAR_ON 0b00001000 // 3 3 AFC register autoclear enabled
262 #define RF69_AFC_AUTO_OFF 0b00000000 // 2 2 perform AFC only manually
263 #define RF69_AFC_AUTO_ON 0b00000100 // 2 2 perform AFC each time Rx mode is started
264 #define RF69_AFC_CLEAR 0b00000010 // 1 1 clear AFC register
265 #define RF69_AFC_START 0b00000001 // 0 0 start AFC
266 
267 // RF69_REG_RSSI_CONFIG
268 #define RF69_RSSI_RUNNING 0b00000000 // 1 1 RSSI status: on-going
269 #define RF69_RSSI_DONE 0b00000010 // 1 1 done
270 #define RF69_RSSI_START 0b00000001 // 0 0 start RSSI measurement
271 
272 // RF69_REG_DIO_MAPPING_1
273 #define RF69_DIO0_CONT_MODE_READY 0b11000000 // 7 6
274 #define RF69_DIO0_CONT_PLL_LOCK 0b00000000 // 7 6
275 #define RF69_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
276 #define RF69_DIO0_CONT_TIMEOUT 0b01000000 // 7 6
277 #define RF69_DIO0_CONT_RSSI 0b10000000 // 7 6
278 #define RF69_DIO0_CONT_TX_READY 0b01000000 // 7 6
279 #define RF69_DIO0_PACK_PLL_LOCK 0b11000000 // 7 6
280 #define RF69_DIO0_PACK_CRC_OK 0b00000000 // 7 6
281 #define RF69_DIO0_PACK_PAYLOAD_READY 0b01000000 // 7 6
282 #define RF69_DIO0_PACK_SYNC_ADDRESS 0b10000000 // 7 6
283 #define RF69_DIO0_PACK_RSSI 0b11000000 // 7 6
284 #define RF69_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
285 #define RF69_DIO0_PACK_TX_READY 0b01000000 // 7 6
286 #define RF69_DIO1_CONT_PLL_LOCK 0b00110000 // 5 4
287 #define RF69_DIO1_CONT_DCLK 0b00000000 // 5 4
288 #define RF69_DIO1_CONT_RX_READY 0b00010000 // 5 4
289 #define RF69_DIO1_CONT_SYNC_ADDRESS 0b00110000 // 5 4
290 #define RF69_DIO1_CONT_TX_READY 0b00010000 // 5 4
291 #define RF69_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
292 #define RF69_DIO1_PACK_FIFO_FULL 0b00010000 // 5 4
293 #define RF69_DIO1_PACK_FIFO_NOT_EMPTY 0b00100000 // 5 4
294 #define RF69_DIO1_PACK_PLL_LOCK 0b00110000 // 5 4
295 #define RF69_DIO1_PACK_TIMEOUT 0b00110000 // 5 4
296 #define RF69_DIO2_CONT_DATA 0b00000000 // 3 2
297 
298 // RF69_REG_DIO_MAPPING_2
299 #define RF69_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
300 #define RF69_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
301 #define RF69_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
302 #define RF69_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
303 #define RF69_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
304 #define RF69_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 31
305 #define RF69_CLK_OUT_RC 0b00000110 // 2 0 RC
306 #define RF69_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
307 
308 // RF69_REG_IRQ_FLAGS_1
309 #define RF69_IRQ_MODE_READY 0b10000000 // 7 7 requested mode was set
310 #define RF69_IRQ_RX_READY 0b01000000 // 6 6 Rx mode ready
311 #define RF69_IRQ_TX_READY 0b00100000 // 5 5 Tx mode ready
312 #define RF69_IRQ_PLL_LOCK 0b00010000 // 4 4 PLL is locked
313 #define RF69_IRQ_RSSI 0b00001000 // 3 3 RSSI value exceeded RssiThreshold
314 #define RF69_IRQ_TIMEOUT 0b00000100 // 2 2 timeout occurred
315 #define RF69_IRQ_AUTO_MODE 0b00000010 // 1 1 entered intermediate mode
316 #define RF69_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address detected
317 
318 // RF69_REG_IRQ_FLAGS_2
319 #define RF69_IRQ_FIFO_FULL 0b10000000 // 7 7 FIFO is full
320 #define RF69_IRQ_FIFO_NOT_EMPTY 0b01000000 // 6 6 FIFO contains at least 1 byte
321 #define RF69_IRQ_FIFO_LEVEL 0b00100000 // 5 5 FIFO contains more than FifoThreshold bytes
322 #define RF69_IRQ_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
323 #define RF69_IRQ_PACKET_SENT 0b00001000 // 3 3 packet was sent
324 #define RF69_IRQ_PAYLOAD_READY 0b00000100 // 2 2 last payload byte received and CRC check passed
325 #define RF69_IRQ_CRC_OK 0b00000010 // 1 1 CRC check passed
326 
327 // RF69_REG_RSSI_THRESH
328 #define RF69_RSSI_THRESHOLD 0xE4 // 7 0 RSSI threshold level (2 dB by default)
329 
330 // RF69_REG_RX_TIMEOUT_1
331 #define RF69_TIMEOUT_RX_START_OFF 0x00 // 7 0 RSSI interrupt timeout disabled (default)
332 #define RF69_TIMEOUT_RX_START 0xFF // 7 0 timeout will occur if RSSI interrupt is not received
333 
334 // RF69_REG_RX_TIMEOUT_2
335 #define RF69_TIMEOUT_RSSI_THRESH_OFF 0x00 // 7 0 PayloadReady interrupt timeout disabled (default)
336 #define RF69_TIMEOUT_RSSI_THRESH 0xFF // 7 0 timeout will occur if PayloadReady interrupt is not received
337 
338 // RF69_REG_PREAMBLE_MSB + REG_PREAMBLE_MSB
339 #define RF69_PREAMBLE_MSB 0x00 // 7 0 2-byte preamble size value
340 #define RF69_PREAMBLE_LSB 0x03 // 7 0
341 
342 // RF69_REG_SYNC_CONFIG
343 #define RF69_SYNC_OFF 0b00000000 // 7 7 sync word detection off
344 #define RF69_SYNC_ON 0b10000000 // 7 7 sync word detection on (default)
345 #define RF69_FIFO_FILL_CONDITION_SYNC 0b00000000 // 6 6 FIFO fill condition: on SyncAddress interrupt (default)
346 #define RF69_FIFO_FILL_CONDITION 0b01000000 // 6 6 as long as the bit is set
347 #define RF69_SYNC_SIZE 0b00001000 // 5 3 size of sync word: SyncSize + 1 bytes
348 #define RF69_SYNC_TOL 0b00000000 // 2 0 number of tolerated errors in sync word
349 
350 // RF69_REG_SYNC_VALUE_1 - SYNC_VALUE_8
351 #define RF69_SYNC_BYTE_1 0x01 // 7 0 sync word: 1st byte (MSB)
352 #define RF69_SYNC_BYTE_2 0x01 // 7 0 2nd byte
353 #define RF69_SYNC_BYTE_3 0x01 // 7 0 3rd byte
354 #define RF69_SYNC_BYTE_4 0x01 // 7 0 4th byte
355 #define RF69_SYNC_BYTE_5 0x01 // 7 0 5th byte
356 #define RF69_SYNC_BYTE_6 0x01 // 7 0 6th byte
357 #define RF69_SYNC_BYTE_7 0x01 // 7 0 7th byte
358 #define RF69_SYNC_BYTE_8 0x01 // 7 0 8th byte (LSB)
359 
360 // RF69_REG_PACKET_CONFIG_1
361 #define RF69_PACKET_FORMAT_FIXED 0b00000000 // 7 7 fixed packet length (default)
362 #define RF69_PACKET_FORMAT_VARIABLE 0b10000000 // 7 7 variable packet length
363 #define RF69_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: none (default)
364 #define RF69_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
365 #define RF69_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
366 #define RF69_CRC_OFF 0b00000000 // 4 4 CRC disabled
367 #define RF69_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
368 #define RF69_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 discard packet when CRC check fails (default)
369 #define RF69_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep packet when CRC check fails
370 #define RF69_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
371 #define RF69_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
372 #define RF69_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
373 
374 // RF69_REG_PAYLOAD_LENGTH
375 #define RF69_PAYLOAD_LENGTH 0xFF // 7 0 payload length
376 
377 // RF69_REG_AUTO_MODES
378 #define RF69_ENTER_COND_NONE 0b00000000 // 7 5 condition for entering intermediate mode: none, AutoModes disabled (default)
379 #define RF69_ENTER_COND_FIFO_NOT_EMPTY 0b00100000 // 7 5 FifoNotEmpty rising edge
380 #define RF69_ENTER_COND_FIFO_LEVEL 0b01000000 // 7 5 FifoLevel rising edge
381 #define RF69_ENTER_COND_CRC_OK 0b01100000 // 7 5 CrcOk rising edge
382 #define RF69_ENTER_COND_PAYLOAD_READY 0b10000000 // 7 5 PayloadReady rising edge
383 #define RF69_ENTER_COND_SYNC_ADDRESS 0b10100000 // 7 5 SyncAddress rising edge
384 #define RF69_ENTER_COND_PACKET_SENT 0b11000000 // 7 5 PacketSent rising edge
385 #define RF69_ENTER_COND_FIFO_EMPTY 0b11100000 // 7 5 FifoNotEmpty falling edge
386 #define RF69_EXIT_COND_NONE 0b00000000 // 4 2 condition for exiting intermediate mode: none, AutoModes disabled (default)
387 #define RF69_EXIT_COND_FIFO_EMPTY 0b00100000 // 4 2 FifoNotEmpty falling edge
388 #define RF69_EXIT_COND_FIFO_LEVEL 0b01000000 // 4 2 FifoLevel rising edge
389 #define RF69_EXIT_COND_CRC_OK 0b01100000 // 4 2 CrcOk rising edge
390 #define RF69_EXIT_COND_PAYLOAD_READY 0b10000000 // 4 2 PayloadReady rising edge
391 #define RF69_EXIT_COND_SYNC_ADDRESS 0b10100000 // 4 2 SyncAddress rising edge
392 #define RF69_EXIT_COND_PACKET_SENT 0b11000000 // 4 2 PacketSent rising edge
393 #define RF69_EXIT_COND_TIMEOUT 0b11100000 // 4 2 timeout rising edge
394 #define RF69_INTER_MODE_SLEEP 0b00000000 // 1 0 intermediate mode: sleep (default)
395 #define RF69_INTER_MODE_STANDBY 0b00000001 // 1 0 standby
396 #define RF69_INTER_MODE_RX 0b00000010 // 1 0 Rx
397 #define RF69_INTER_MODE_TX 0b00000011 // 1 0 Tx
398 
399 // RF69_REG_FIFO_THRESH
400 #define RF69_TX_START_CONDITION_FIFO_LEVEL 0b00000000 // 7 7 packet transmission start condition: FifoLevel
401 #define RF69_TX_START_CONDITION_FIFO_NOT_EMPTY 0b10000000 // 7 7 FifoNotEmpty (default)
402 #define RF69_FIFO_THRESHOLD 0b00001111 // 6 0 default threshold to trigger FifoLevel interrupt
403 
404 // RF69_REG_PACKET_CONFIG_2
405 #define RF69_INTER_PACKET_RX_DELAY 0b00000000 // 7 4 delay between FIFO empty and start of new RSSI phase
406 #define RF69_RESTART_RX 0b00000100 // 2 2 force receiver into wait mode
407 #define RF69_AUTO_RX_RESTART_OFF 0b00000000 // 1 1 auto Rx restart disabled
408 #define RF69_AUTO_RX_RESTART_ON 0b00000010 // 1 1 auto Rx restart enabled (default)
409 #define RF69_AES_OFF 0b00000000 // 0 0 AES encryption disabled (default)
410 #define RF69_AES_ON 0b00000001 // 0 0 AES encryption enabled, payload size limited to 66 bytes
411 
412 // RF69_REG_TEMP_1
413 #define RF69_TEMP_MEAS_START 0b00001000 // 3 3 trigger temperature measurement
414 #define RF69_TEMP_MEAS_RUNNING 0b00000100 // 2 2 temperature measurement status: on-going
415 #define RF69_TEMP_MEAS_DONE 0b00000000 // 2 2 done
416 
417 // RF69_REG_TEST_DAGC
418 #define RF69_CONTINUOUS_DAGC_NORMAL 0x00 // 7 0 fading margin improvement: normal mode
419 #define RF69_CONTINUOUS_DAGC_LOW_BETA_ON 0x20 // 7 0 improved mode for AfcLowBetaOn
420 #define RF69_CONTINUOUS_DAGC_LOW_BETA_OFF 0x30 // 7 0 improved mode for AfcLowBetaOff (default)
421 
422 // RF69_REG_TEST_PA1
423 #define RF69_PA1_NORMAL 0x55 // 7 0 PA_BOOST: none
424 #define RF69_PA1_20_DBM 0x5D // 7 0 +20 dBm
425 
426 // RF69_REG_TEST_PA2
427 #define RF69_PA2_NORMAL 0x70 // 7 0 PA_BOOST: none
428 #define RF69_PA2_20_DBM 0x7C // 7 0 +20 dBm
429 
435 class RF69: public PhysicalLayer {
436  public:
437  // introduce PhysicalLayer overloads
438  using PhysicalLayer::transmit;
439  using PhysicalLayer::receive;
440  using PhysicalLayer::startTransmit;
441  using PhysicalLayer::readData;
442 
448  RF69(Module* module);
449 
450  // basic methods
451 
469  int16_t begin(float freq = 434.0, float br = 48.0, float freqDev = 50.0, float rxBw = 125.0, int8_t power = 10, uint8_t preambleLen = 16);
470 
474  void reset();
475 
488  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
489 
500  int16_t receive(uint8_t* data, size_t len) override;
501 
507  int16_t sleep();
508 
514  int16_t standby() override;
515 
523  int16_t transmitDirect(uint32_t frf = 0) override;
524 
530  int16_t receiveDirect() override;
531 
535  int16_t packetMode();
536 
537  // hardware AES support
538 
544  void setAESKey(uint8_t* key);
545 
551  int16_t enableAES();
552 
558  int16_t disableAES();
559 
560  // interrupt methods
561 
567  void setDio0Action(void (*func)(void));
568 
572  void clearDio0Action();
573 
579  void setDio1Action(void (*func)(void));
580 
584  void clearDio1Action();
585 
598  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
599 
605  int16_t startReceive();
606 
616  int16_t readData(uint8_t* data, size_t len) override;
617 
618  // configuration methods
619 
627  int16_t setFrequency(float freq);
628 
636  int16_t setBitRate(float br);
637 
645  int16_t setRxBandwidth(float rxBw);
646 
654  int16_t setFrequencyDeviation(float freqDev) override;
655 
665  int16_t setOutputPower(int8_t power, bool highPower = false);
666 
676  int16_t setSyncWord(uint8_t* syncWord, size_t len, uint8_t maxErrBits = 0);
677 
685  int16_t setPreambleLength(uint8_t preambleLen);
686 
694  int16_t setNodeAddress(uint8_t nodeAddr);
695 
703  int16_t setBroadcastAddress(uint8_t broadAddr);
704 
710  int16_t disableAddressFiltering();
711 
712  // measurement methods
713 
719  void setAmbientTemperature(int16_t tempAmbient);
720 
726  int16_t getTemperature();
727 
735  size_t getPacketLength(bool update = true) override;
736 
744  int16_t fixedPacketLengthMode(uint8_t len = RF69_MAX_PACKET_LENGTH);
745 
753  int16_t variablePacketLengthMode(uint8_t maxLen = RF69_MAX_PACKET_LENGTH);
754 
762  int16_t enableSyncWordFiltering(uint8_t maxErrBits = 0);
763 
769  int16_t disableSyncWordFiltering();
770 
778  int16_t setCrcFiltering(bool crcOn = true);
779 
787  int16_t setPromiscuousMode(bool promiscuous = true);
788 
797  int16_t setDataShaping(uint8_t sh) override;
798 
807  int16_t setEncoding(uint8_t encoding) override;
808 
814  float getRSSI();
815 
824  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
825 
831  uint8_t random();
832 
838  int16_t getChipVersion();
839 
840 #ifndef RADIOLIB_GODMODE
841  protected:
842 #endif
843  Module* _mod;
844 
845  float _br = 0;
846  float _rxBw = 0;
847  int16_t _tempOffset = 0;
848  int8_t _power = 0;
849 
850  size_t _packetLength = 0;
851  bool _packetLengthQueried = false;
852  uint8_t _packetLengthConfig = RF69_PACKET_FORMAT_VARIABLE;
853 
854  bool _promiscuous = false;
855 
856  uint8_t _syncWordLength = 2;
857 
858  int16_t config();
859  int16_t directMode();
860  int16_t setPacketMode(uint8_t mode, uint8_t len);
861 
862 #ifndef RADIOLIB_GODMODE
863  private:
864 #endif
865  int16_t setMode(uint8_t mode);
866  void clearIRQFlags();
867 };
868 
869 #endif
870 
871 #endif
RF69::setFrequencyDeviation
int16_t setFrequencyDeviation(float freqDev) override
Sets frequency deviation.
Definition: RF69.cpp:507
RF69::disableAddressFiltering
int16_t disableAddressFiltering()
Disables address filtering. Calling this method will also erase previously set addresses.
Definition: RF69.cpp:615
RF69::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)
Sets sync word. Up to 8 bytes can be set as sync word.
Definition: RF69.cpp:563
RF69::setPromiscuousMode
int16_t setPromiscuousMode(bool promiscuous=true)
Set modem in "sniff" mode: no packet filtering (e.g., no preamble, sync word, address, CRC).
Definition: RF69.cpp:695
@@ -104,7 +104,7 @@ $(document).ready(function(){initNavTree('_r_f69_8h_source.html','');});
RF69::sleep
int16_t sleep()
Sets the module to sleep mode.
Definition: RF69.cpp:163
RF69::disableAES
int16_t disableAES()
Disables AES encryption.
Definition: RF69.cpp:237
RF69::variablePacketLengthMode
int16_t variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)
Set modem in variable packet length mode.
Definition: RF69.cpp:666
-
RF69
Control class for RF69 module. Also serves as base class for SX1231.
Definition: RF69.h:432
+
RF69
Control class for RF69 module. Also serves as base class for SX1231.
Definition: RF69.h:435
RF69::transmit
int16_t transmit(uint8_t *data, size_t len, uint8_t addr=0) override
Blocking binary transmit method. Overloads for string-based transmissions are implemented in Physical...
Definition: RF69.cpp:110
RF69::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: RF69.cpp:285
RF69::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Allowed values are RA...
Definition: RF69.cpp:721
@@ -132,6 +132,7 @@ $(document).ready(function(){initNavTree('_r_f69_8h_source.html','');});
RF69::RF69
RF69(Module *module)
Default constructor.
Definition: RF69.cpp:4
RF69::receiveDirect
int16_t receiveDirect() override
Starts direct mode reception.
Definition: RF69.cpp:200
PhysicalLayer::readData
int16_t readData(String &str, size_t len=0)
Reads data that was received after calling startReceive method.
Definition: PhysicalLayer.cpp:57
+
RF69::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working...
Definition: RF69.cpp:786
RF69::enableSyncWordFiltering
int16_t enableSyncWordFiltering(uint8_t maxErrBits=0)
Enable sync word filtering and generation.
Definition: RF69.cpp:670
RF69::startTransmit
int16_t startTransmit(uint8_t *data, size_t len, uint8_t addr=0) override
Interrupt-driven binary transmit method. Overloads for string-based transmissions are implemented in ...
Definition: RF69.cpp:292
RF69::getTemperature
int16_t getTemperature()
Measures temperature.
Definition: RF69.cpp:632
diff --git a/_s_x1231_8h_source.html b/_s_x1231_8h_source.html index 74345cbc..95a5a19e 100644 --- a/_s_x1231_8h_source.html +++ b/_s_x1231_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_s_x1231_8h_source.html','');});
SX1231.h
-
1 #if !defined(_RADIOLIB_SX1231_H)
2 #define _RADIOLIB_SX1231_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX1231)
7 
8 #include "../../Module.h"
9 #include "../RF69/RF69.h"
10 
11 #define SX1231_CHIP_REVISION_2_A 0x21
12 #define SX1231_CHIP_REVISION_2_B 0x22
13 #define SX1231_CHIP_REVISION_2_C 0x23
14 
15 //SX1231 specific register map
16 #define SX1231_REG_TEST_OOK 0x6E
17 
18 //SX1231_REG_TEST_OOK
19 #define SX1231_OOK_DELTA_THRESHOLD 0x0C
20 
26 class SX1231: public RF69 {
27  public:
33  SX1231(Module* mod);
34 
52  int16_t begin(float freq = 434.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint8_t preambleLen = 16);
53 
54 #ifndef RADIOLIB_GODMODE
55  private:
56 #endif
57  uint8_t _chipRevision = 0;
58 };
59 
60 #endif
61 
62 #endif
RF69
Control class for RF69 module. Also serves as base class for SX1231.
Definition: RF69.h:432
+
1 #if !defined(_RADIOLIB_SX1231_H)
2 #define _RADIOLIB_SX1231_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX1231)
7 
8 #include "../../Module.h"
9 #include "../RF69/RF69.h"
10 
11 #define SX1231_CHIP_REVISION_2_A 0x21
12 #define SX1231_CHIP_REVISION_2_B 0x22
13 #define SX1231_CHIP_REVISION_2_C 0x23
14 
15 //SX1231 specific register map
16 #define SX1231_REG_TEST_OOK 0x6E
17 
18 //SX1231_REG_TEST_OOK
19 #define SX1231_OOK_DELTA_THRESHOLD 0x0C
20 
26 class SX1231: public RF69 {
27  public:
33  SX1231(Module* mod);
34 
52  int16_t begin(float freq = 434.0, float br = 48.0, float rxBw = 125.0, float freqDev = 50.0, int8_t power = 10, uint8_t preambleLen = 16);
53 
54 #ifndef RADIOLIB_GODMODE
55  private:
56 #endif
57  uint8_t _chipRevision = 0;
58 };
59 
60 #endif
61 
62 #endif
RF69
Control class for RF69 module. Also serves as base class for SX1231.
Definition: RF69.h:435
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
SX1231
Control class for SX1231 module. Overrides some methods from RF69 due to different register values...
Definition: SX1231.h:26
SX1231::begin
int16_t begin(float freq=434.0, float br=48.0, float rxBw=125.0, float freqDev=50.0, int8_t power=10, uint8_t preambleLen=16)
Initialization method.
Definition: SX1231.cpp:8
diff --git a/_s_x127x_8h_source.html b/_s_x127x_8h_source.html index 93cf8178..9971f627 100644 --- a/_s_x127x_8h_source.html +++ b/_s_x127x_8h_source.html @@ -84,7 +84,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x.h
-
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
941 #ifndef RADIOLIB_GODMODE
942  protected:
943 #endif
944  Module* _mod;
945 
946  float _freq = 0;
947  float _bw = 0;
948  uint8_t _sf = 0;
949  uint8_t _cr = 0;
950  float _br = 0;
951  float _rxBw = 0;
952  bool _ook = false;
953  bool _crcEnabled = false;
954 
955  int16_t setFrequencyRaw(float newFreq);
956  int16_t config();
957  int16_t configFSK();
958  int16_t getActiveModem();
959  int16_t directMode();
960  int16_t setPacketMode(uint8_t mode, uint8_t len);
961 
962 #ifndef RADIOLIB_GODMODE
963  private:
964 #endif
965  float _dataRate = 0;
966  size_t _packetLength = 0;
967  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
968  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
969 
970  bool findChip(uint8_t ver);
971  int16_t setMode(uint8_t mode);
972  int16_t setActiveModem(uint8_t modem);
973  void clearIRQFlags();
974  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
975 };
976 
977 #endif
978 
979 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:897
+
1 #if !defined(_RADIOLIB_SX127X_H)
2 #define _RADIOLIB_SX127X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SX127X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // SX127x physical layer properties
13 #define SX127X_FREQUENCY_STEP_SIZE 61.03515625
14 #define SX127X_MAX_PACKET_LENGTH 255
15 #define SX127X_MAX_PACKET_LENGTH_FSK 64
16 #define SX127X_CRYSTAL_FREQ 32.0
17 #define SX127X_DIV_EXPONENT 19
18 
19 // SX127x series common LoRa registers
20 #define SX127X_REG_FIFO 0x00
21 #define SX127X_REG_OP_MODE 0x01
22 #define SX127X_REG_FRF_MSB 0x06
23 #define SX127X_REG_FRF_MID 0x07
24 #define SX127X_REG_FRF_LSB 0x08
25 #define SX127X_REG_PA_CONFIG 0x09
26 #define SX127X_REG_PA_RAMP 0x0A
27 #define SX127X_REG_OCP 0x0B
28 #define SX127X_REG_LNA 0x0C
29 #define SX127X_REG_FIFO_ADDR_PTR 0x0D
30 #define SX127X_REG_FIFO_TX_BASE_ADDR 0x0E
31 #define SX127X_REG_FIFO_RX_BASE_ADDR 0x0F
32 #define SX127X_REG_FIFO_RX_CURRENT_ADDR 0x10
33 #define SX127X_REG_IRQ_FLAGS_MASK 0x11
34 #define SX127X_REG_IRQ_FLAGS 0x12
35 #define SX127X_REG_RX_NB_BYTES 0x13
36 #define SX127X_REG_RX_HEADER_CNT_VALUE_MSB 0x14
37 #define SX127X_REG_RX_HEADER_CNT_VALUE_LSB 0x15
38 #define SX127X_REG_RX_PACKET_CNT_VALUE_MSB 0x16
39 #define SX127X_REG_RX_PACKET_CNT_VALUE_LSB 0x17
40 #define SX127X_REG_MODEM_STAT 0x18
41 #define SX127X_REG_PKT_SNR_VALUE 0x19
42 #define SX127X_REG_PKT_RSSI_VALUE 0x1A
43 #define SX127X_REG_RSSI_VALUE 0x1B
44 #define SX127X_REG_HOP_CHANNEL 0x1C
45 #define SX127X_REG_MODEM_CONFIG_1 0x1D
46 #define SX127X_REG_MODEM_CONFIG_2 0x1E
47 #define SX127X_REG_SYMB_TIMEOUT_LSB 0x1F
48 #define SX127X_REG_PREAMBLE_MSB 0x20
49 #define SX127X_REG_PREAMBLE_LSB 0x21
50 #define SX127X_REG_PAYLOAD_LENGTH 0x22
51 #define SX127X_REG_MAX_PAYLOAD_LENGTH 0x23
52 #define SX127X_REG_HOP_PERIOD 0x24
53 #define SX127X_REG_FIFO_RX_BYTE_ADDR 0x25
54 #define SX127X_REG_FEI_MSB 0x28
55 #define SX127X_REG_FEI_MID 0x29
56 #define SX127X_REG_FEI_LSB 0x2A
57 #define SX127X_REG_RSSI_WIDEBAND 0x2C
58 #define SX127X_REG_DETECT_OPTIMIZE 0x31
59 #define SX127X_REG_INVERT_IQ 0x33
60 #define SX127X_REG_DETECTION_THRESHOLD 0x37
61 #define SX127X_REG_SYNC_WORD 0x39
62 #define SX127X_REG_DIO_MAPPING_1 0x40
63 #define SX127X_REG_DIO_MAPPING_2 0x41
64 #define SX127X_REG_VERSION 0x42
65 
66 // SX127x common LoRa modem settings
67 // SX127X_REG_OP_MODE MSB LSB DESCRIPTION
68 #define SX127X_FSK_OOK 0b00000000 // 7 7 FSK/OOK mode
69 #define SX127X_LORA 0b10000000 // 7 7 LoRa mode
70 #define SX127X_ACCESS_SHARED_REG_OFF 0b00000000 // 6 6 access LoRa registers (0x0D:0x3F) in LoRa mode
71 #define SX127X_ACCESS_SHARED_REG_ON 0b01000000 // 6 6 access FSK registers (0x0D:0x3F) in LoRa mode
72 #define SX127X_SLEEP 0b00000000 // 2 0 sleep
73 #define SX127X_STANDBY 0b00000001 // 2 0 standby
74 #define SX127X_FSTX 0b00000010 // 2 0 frequency synthesis TX
75 #define SX127X_TX 0b00000011 // 2 0 transmit
76 #define SX127X_FSRX 0b00000100 // 2 0 frequency synthesis RX
77 #define SX127X_RXCONTINUOUS 0b00000101 // 2 0 receive continuous
78 #define SX127X_RXSINGLE 0b00000110 // 2 0 receive single
79 #define SX127X_CAD 0b00000111 // 2 0 channel activity detection
80 
81 // SX127X_REG_PA_CONFIG
82 #define SX127X_PA_SELECT_RFO 0b00000000 // 7 7 RFO pin output, power limited to +14 dBm
83 #define SX127X_PA_SELECT_BOOST 0b10000000 // 7 7 PA_BOOST pin output, power limited to +20 dBm
84 #define SX127X_OUTPUT_POWER 0b00001111 // 3 0 output power: P_out = 2 + OUTPUT_POWER [dBm] for PA_SELECT_BOOST
85  // P_out = -1 + OUTPUT_POWER [dBm] for PA_SELECT_RFO
86 
87 // SX127X_REG_OCP
88 #define SX127X_OCP_OFF 0b00000000 // 5 5 PA overload current protection disabled
89 #define SX127X_OCP_ON 0b00100000 // 5 5 PA overload current protection enabled
90 #define SX127X_OCP_TRIM 0b00001011 // 4 0 OCP current: I_max(OCP_TRIM = 0b1011) = 100 mA
91 
92 // SX127X_REG_LNA
93 #define SX127X_LNA_GAIN_1 0b00100000 // 7 5 LNA gain setting: max gain
94 #define SX127X_LNA_GAIN_2 0b01000000 // 7 5 .
95 #define SX127X_LNA_GAIN_3 0b01100000 // 7 5 .
96 #define SX127X_LNA_GAIN_4 0b10000000 // 7 5 .
97 #define SX127X_LNA_GAIN_5 0b10100000 // 7 5 .
98 #define SX127X_LNA_GAIN_6 0b11000000 // 7 5 min gain
99 #define SX127X_LNA_BOOST_OFF 0b00000000 // 1 0 default LNA current
100 #define SX127X_LNA_BOOST_ON 0b00000011 // 1 0 150% LNA current
101 
102 // SX127X_REG_MODEM_CONFIG_2
103 #define SX127X_SF_6 0b01100000 // 7 4 spreading factor: 64 chips/bit
104 #define SX127X_SF_7 0b01110000 // 7 4 128 chips/bit
105 #define SX127X_SF_8 0b10000000 // 7 4 256 chips/bit
106 #define SX127X_SF_9 0b10010000 // 7 4 512 chips/bit
107 #define SX127X_SF_10 0b10100000 // 7 4 1024 chips/bit
108 #define SX127X_SF_11 0b10110000 // 7 4 2048 chips/bit
109 #define SX127X_SF_12 0b11000000 // 7 4 4096 chips/bit
110 #define SX127X_TX_MODE_SINGLE 0b00000000 // 3 3 single TX
111 #define SX127X_TX_MODE_CONT 0b00001000 // 3 3 continuous TX
112 #define SX127X_RX_TIMEOUT_MSB 0b00000000 // 1 0
113 
114 // SX127X_REG_SYMB_TIMEOUT_LSB
115 #define SX127X_RX_TIMEOUT_LSB 0b01100100 // 7 0 10 bit RX operation timeout
116 
117 // SX127X_REG_PREAMBLE_MSB + REG_PREAMBLE_LSB
118 #define SX127X_PREAMBLE_LENGTH_MSB 0b00000000 // 7 0 2 byte preamble length setting: l_P = PREAMBLE_LENGTH + 4.25
119 #define SX127X_PREAMBLE_LENGTH_LSB 0b00001000 // 7 0 where l_p = preamble length
120 
121 // SX127X_REG_DETECT_OPTIMIZE
122 #define SX127X_DETECT_OPTIMIZE_SF_6 0b00000101 // 2 0 SF6 detection optimization
123 #define SX127X_DETECT_OPTIMIZE_SF_7_12 0b00000011 // 2 0 SF7 to SF12 detection optimization
124 
125 // SX127X_REG_DETECTION_THRESHOLD
126 #define SX127X_DETECTION_THRESHOLD_SF_6 0b00001100 // 7 0 SF6 detection threshold
127 #define SX127X_DETECTION_THRESHOLD_SF_7_12 0b00001010 // 7 0 SF7 to SF12 detection threshold
128 
129 // SX127X_REG_PA_DAC
130 #define SX127X_PA_BOOST_OFF 0b00000100 // 2 0 PA_BOOST disabled
131 #define SX127X_PA_BOOST_ON 0b00000111 // 2 0 +20 dBm on PA_BOOST when OUTPUT_POWER = 0b1111
132 
133 // SX127X_REG_HOP_PERIOD
134 #define SX127X_HOP_PERIOD_OFF 0b00000000 // 7 0 number of periods between frequency hops; 0 = disabled
135 #define SX127X_HOP_PERIOD_MAX 0b11111111 // 7 0
136 
137 // SX127X_REG_DIO_MAPPING_1
138 #define SX127X_DIO0_RX_DONE 0b00000000 // 7 6
139 #define SX127X_DIO0_TX_DONE 0b01000000 // 7 6
140 #define SX127X_DIO0_CAD_DONE 0b10000000 // 7 6
141 #define SX127X_DIO1_RX_TIMEOUT 0b00000000 // 5 4
142 #define SX127X_DIO1_FHSS_CHANGE_CHANNEL 0b00010000 // 5 4
143 #define SX127X_DIO1_CAD_DETECTED 0b00100000 // 5 4
144 
145 // SX127X_REG_IRQ_FLAGS
146 #define SX127X_CLEAR_IRQ_FLAG_RX_TIMEOUT 0b10000000 // 7 7 timeout
147 #define SX127X_CLEAR_IRQ_FLAG_RX_DONE 0b01000000 // 6 6 packet reception complete
148 #define SX127X_CLEAR_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b00100000 // 5 5 payload CRC error
149 #define SX127X_CLEAR_IRQ_FLAG_VALID_HEADER 0b00010000 // 4 4 valid header received
150 #define SX127X_CLEAR_IRQ_FLAG_TX_DONE 0b00001000 // 3 3 payload transmission complete
151 #define SX127X_CLEAR_IRQ_FLAG_CAD_DONE 0b00000100 // 2 2 CAD complete
152 #define SX127X_CLEAR_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b00000010 // 1 1 FHSS change channel
153 #define SX127X_CLEAR_IRQ_FLAG_CAD_DETECTED 0b00000001 // 0 0 valid LoRa signal detected during CAD operation
154 
155 // SX127X_REG_IRQ_FLAGS_MASK
156 #define SX127X_MASK_IRQ_FLAG_RX_TIMEOUT 0b01111111 // 7 7 timeout
157 #define SX127X_MASK_IRQ_FLAG_RX_DONE 0b10111111 // 6 6 packet reception complete
158 #define SX127X_MASK_IRQ_FLAG_PAYLOAD_CRC_ERROR 0b11011111 // 5 5 payload CRC error
159 #define SX127X_MASK_IRQ_FLAG_VALID_HEADER 0b11101111 // 4 4 valid header received
160 #define SX127X_MASK_IRQ_FLAG_TX_DONE 0b11110111 // 3 3 payload transmission complete
161 #define SX127X_MASK_IRQ_FLAG_CAD_DONE 0b11111011 // 2 2 CAD complete
162 #define SX127X_MASK_IRQ_FLAG_FHSS_CHANGE_CHANNEL 0b11111101 // 1 1 FHSS change channel
163 #define SX127X_MASK_IRQ_FLAG_CAD_DETECTED 0b11111110 // 0 0 valid LoRa signal detected during CAD operation
164 
165 // SX127X_REG_FIFO_TX_BASE_ADDR
166 #define SX127X_FIFO_TX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for TX only
167 
168 // SX127X_REG_FIFO_RX_BASE_ADDR
169 #define SX127X_FIFO_RX_BASE_ADDR_MAX 0b00000000 // 7 0 allocate the entire FIFO buffer for RX only
170 
171 // SX127X_REG_SYNC_WORD
172 #define SX127X_SYNC_WORD 0x12 // 7 0 default LoRa sync word
173 #define SX127X_SYNC_WORD_LORAWAN 0x34 // 7 0 sync word reserved for LoRaWAN networks
174 
175 // SX127x series common FSK registers
176 // NOTE: FSK register names that are conflicting with LoRa registers are marked with "_FSK" suffix
177 #define SX127X_REG_BITRATE_MSB 0x02
178 #define SX127X_REG_BITRATE_LSB 0x03
179 #define SX127X_REG_FDEV_MSB 0x04
180 #define SX127X_REG_FDEV_LSB 0x05
181 #define SX127X_REG_RX_CONFIG 0x0D
182 #define SX127X_REG_RSSI_CONFIG 0x0E
183 #define SX127X_REG_RSSI_COLLISION 0x0F
184 #define SX127X_REG_RSSI_THRESH 0x10
185 #define SX127X_REG_RSSI_VALUE_FSK 0x11
186 #define SX127X_REG_RX_BW 0x12
187 #define SX127X_REG_AFC_BW 0x13
188 #define SX127X_REG_OOK_PEAK 0x14
189 #define SX127X_REG_OOK_FIX 0x15
190 #define SX127X_REG_OOK_AVG 0x16
191 #define SX127X_REG_AFC_FEI 0x1A
192 #define SX127X_REG_AFC_MSB 0x1B
193 #define SX127X_REG_AFC_LSB 0x1C
194 #define SX127X_REG_FEI_MSB_FSK 0x1D
195 #define SX127X_REG_FEI_LSB_FSK 0x1E
196 #define SX127X_REG_PREAMBLE_DETECT 0x1F
197 #define SX127X_REG_RX_TIMEOUT_1 0x20
198 #define SX127X_REG_RX_TIMEOUT_2 0x21
199 #define SX127X_REG_RX_TIMEOUT_3 0x22
200 #define SX127X_REG_RX_DELAY 0x23
201 #define SX127X_REG_OSC 0x24
202 #define SX127X_REG_PREAMBLE_MSB_FSK 0x25
203 #define SX127X_REG_PREAMBLE_LSB_FSK 0x26
204 #define SX127X_REG_SYNC_CONFIG 0x27
205 #define SX127X_REG_SYNC_VALUE_1 0x28
206 #define SX127X_REG_SYNC_VALUE_2 0x29
207 #define SX127X_REG_SYNC_VALUE_3 0x2A
208 #define SX127X_REG_SYNC_VALUE_4 0x2B
209 #define SX127X_REG_SYNC_VALUE_5 0x2C
210 #define SX127X_REG_SYNC_VALUE_6 0x2D
211 #define SX127X_REG_SYNC_VALUE_7 0x2E
212 #define SX127X_REG_SYNC_VALUE_8 0x2F
213 #define SX127X_REG_PACKET_CONFIG_1 0x30
214 #define SX127X_REG_PACKET_CONFIG_2 0x31
215 #define SX127X_REG_PAYLOAD_LENGTH_FSK 0x32
216 #define SX127X_REG_NODE_ADRS 0x33
217 #define SX127X_REG_BROADCAST_ADRS 0x34
218 #define SX127X_REG_FIFO_THRESH 0x35
219 #define SX127X_REG_SEQ_CONFIG_1 0x36
220 #define SX127X_REG_SEQ_CONFIG_2 0x37
221 #define SX127X_REG_TIMER_RESOL 0x38
222 #define SX127X_REG_TIMER1_COEF 0x39
223 #define SX127X_REG_TIMER2_COEF 0x3A
224 #define SX127X_REG_IMAGE_CAL 0x3B
225 #define SX127X_REG_TEMP 0x3C
226 #define SX127X_REG_LOW_BAT 0x3D
227 #define SX127X_REG_IRQ_FLAGS_1 0x3E
228 #define SX127X_REG_IRQ_FLAGS_2 0x3F
229 
230 // SX127x common FSK modem settings
231 // SX127X_REG_OP_MODE
232 #define SX127X_MODULATION_FSK 0b00000000 // 6 5 FSK modulation scheme
233 #define SX127X_MODULATION_OOK 0b00100000 // 6 5 OOK modulation scheme
234 #define SX127X_RX 0b00000101 // 2 0 receiver mode
235 
236 // SX127X_REG_BITRATE_MSB + SX127X_REG_BITRATE_LSB
237 #define SX127X_BITRATE_MSB 0x1A // 7 0 bit rate setting: BitRate = F(XOSC)/(BITRATE + BITRATE_FRAC/16)
238 #define SX127X_BITRATE_LSB 0x0B // 7 0 default value: 4.8 kbps
239 
240 // SX127X_REG_FDEV_MSB + SX127X_REG_FDEV_LSB
241 #define SX127X_FDEV_MSB 0x00 // 5 0 frequency deviation: Fdev = Fstep * FDEV
242 #define SX127X_FDEV_LSB 0x52 // 7 0 default value: 5 kHz
243 
244 // SX127X_REG_RX_CONFIG
245 #define SX127X_RESTART_RX_ON_COLLISION_OFF 0b00000000 // 7 7 automatic receiver restart disabled (default)
246 #define SX127X_RESTART_RX_ON_COLLISION_ON 0b10000000 // 7 7 automatically restart receiver if it gets saturated or on packet collision
247 #define SX127X_RESTART_RX_WITHOUT_PLL_LOCK 0b01000000 // 6 6 manually restart receiver without frequency change
248 #define SX127X_RESTART_RX_WITH_PLL_LOCK 0b00100000 // 5 5 manually restart receiver with frequency change
249 #define SX127X_AFC_AUTO_OFF 0b00000000 // 4 4 no AFC performed (default)
250 #define SX127X_AFC_AUTO_ON 0b00010000 // 4 4 AFC performed at each receiver startup
251 #define SX127X_AGC_AUTO_OFF 0b00000000 // 3 3 LNA gain set manually by register
252 #define SX127X_AGC_AUTO_ON 0b00001000 // 3 3 LNA gain controlled by AGC
253 #define SX127X_RX_TRIGGER_NONE 0b00000000 // 2 0 receiver startup at: none
254 #define SX127X_RX_TRIGGER_RSSI_INTERRUPT 0b00000001 // 2 0 RSSI interrupt
255 #define SX127X_RX_TRIGGER_PREAMBLE_DETECT 0b00000110 // 2 0 preamble detected
256 #define SX127X_RX_TRIGGER_BOTH 0b00000111 // 2 0 RSSI interrupt and preamble detected
257 
258 // SX127X_REG_RSSI_CONFIG
259 #define SX127X_RSSI_SMOOTHING_SAMPLES_2 0b00000000 // 2 0 number of samples for RSSI average: 2
260 #define SX127X_RSSI_SMOOTHING_SAMPLES_4 0b00000001 // 2 0 4
261 #define SX127X_RSSI_SMOOTHING_SAMPLES_8 0b00000010 // 2 0 8 (default)
262 #define SX127X_RSSI_SMOOTHING_SAMPLES_16 0b00000011 // 2 0 16
263 #define SX127X_RSSI_SMOOTHING_SAMPLES_32 0b00000100 // 2 0 32
264 #define SX127X_RSSI_SMOOTHING_SAMPLES_64 0b00000101 // 2 0 64
265 #define SX127X_RSSI_SMOOTHING_SAMPLES_128 0b00000110 // 2 0 128
266 #define SX127X_RSSI_SMOOTHING_SAMPLES_256 0b00000111 // 2 0 256
267 
268 // SX127X_REG_RSSI_COLLISION
269 #define SX127X_RSSI_COLLISION_THRESHOLD 0x0A // 7 0 RSSI threshold in dB that will be considered a collision, default value: 10 dB
270 
271 // SX127X_REG_RSSI_THRESH
272 #define SX127X_RSSI_THRESHOLD 0xFF // 7 0 RSSI threshold that will trigger RSSI interrupt, RssiThreshold = RSSI_THRESHOLD / 2 [dBm]
273 
274 // SX127X_REG_RX_BW
275 #define SX127X_RX_BW_MANT_16 0b00000000 // 4 3 channel filter bandwidth: RxBw = F(XOSC) / (RxBwMant * 2^(RxBwExp + 2)) [kHz]
276 #define SX127X_RX_BW_MANT_20 0b00001000 // 4 3
277 #define SX127X_RX_BW_MANT_24 0b00010000 // 4 3 default RxBwMant parameter
278 #define SX127X_RX_BW_EXP 0b00000101 // 2 0 default RxBwExp parameter
279 
280 // SX127X_REG_AFC_BW
281 #define SX127X_RX_BW_MANT_AFC 0b00001000 // 4 3 default RxBwMant parameter used during AFC
282 #define SX127X_RX_BW_EXP_AFC 0b00000011 // 2 0 default RxBwExp parameter used during AFC
283 
284 // SX127X_REG_OOK_PEAK
285 #define SX127X_BIT_SYNC_OFF 0b00000000 // 5 5 bit synchronizer disabled (not allowed in packet mode)
286 #define SX127X_BIT_SYNC_ON 0b00100000 // 5 5 bit synchronizer enabled (default)
287 #define SX127X_OOK_THRESH_FIXED 0b00000000 // 4 3 OOK threshold type: fixed value
288 #define SX127X_OOK_THRESH_PEAK 0b00001000 // 4 3 peak mode (default)
289 #define SX127X_OOK_THRESH_AVERAGE 0b00010000 // 4 3 average mode
290 #define SX127X_OOK_PEAK_THRESH_STEP_0_5_DB 0b00000000 // 2 0 OOK demodulator step size: 0.5 dB (default)
291 #define SX127X_OOK_PEAK_THRESH_STEP_1_0_DB 0b00000001 // 2 0 1.0 dB
292 #define SX127X_OOK_PEAK_THRESH_STEP_1_5_DB 0b00000010 // 2 0 1.5 dB
293 #define SX127X_OOK_PEAK_THRESH_STEP_2_0_DB 0b00000011 // 2 0 2.0 dB
294 #define SX127X_OOK_PEAK_THRESH_STEP_3_0_DB 0b00000100 // 2 0 3.0 dB
295 #define SX127X_OOK_PEAK_THRESH_STEP_4_0_DB 0b00000101 // 2 0 4.0 dB
296 #define SX127X_OOK_PEAK_THRESH_STEP_5_0_DB 0b00000110 // 2 0 5.0 dB
297 #define SX127X_OOK_PEAK_THRESH_STEP_6_0_DB 0b00000111 // 2 0 6.0 dB
298 
299 // SX127X_REG_OOK_FIX
300 #define SX127X_OOK_FIXED_THRESHOLD 0x0C // 7 0 default fixed threshold for OOK data slicer
301 
302 // SX127X_REG_OOK_AVG
303 #define SX127X_OOK_PEAK_THRESH_DEC_1_1_CHIP 0b00000000 // 7 5 OOK demodulator step period: once per chip (default)
304 #define SX127X_OOK_PEAK_THRESH_DEC_1_2_CHIP 0b00100000 // 7 5 once every 2 chips
305 #define SX127X_OOK_PEAK_THRESH_DEC_1_4_CHIP 0b01000000 // 7 5 once every 4 chips
306 #define SX127X_OOK_PEAK_THRESH_DEC_1_8_CHIP 0b01100000 // 7 5 once every 8 chips
307 #define SX127X_OOK_PEAK_THRESH_DEC_2_1_CHIP 0b10000000 // 7 5 2 times per chip
308 #define SX127X_OOK_PEAK_THRESH_DEC_4_1_CHIP 0b10100000 // 7 5 4 times per chip
309 #define SX127X_OOK_PEAK_THRESH_DEC_8_1_CHIP 0b11000000 // 7 5 8 times per chip
310 #define SX127X_OOK_PEAK_THRESH_DEC_16_1_CHIP 0b11100000 // 7 5 16 times per chip
311 #define SX127X_OOK_AVERAGE_OFFSET_0_DB 0b00000000 // 3 2 OOK average threshold offset: 0.0 dB (default)
312 #define SX127X_OOK_AVERAGE_OFFSET_2_DB 0b00000100 // 3 2 2.0 dB
313 #define SX127X_OOK_AVERAGE_OFFSET_4_DB 0b00001000 // 3 2 4.0 dB
314 #define SX127X_OOK_AVERAGE_OFFSET_6_DB 0b00001100 // 3 2 6.0 dB
315 #define SX127X_OOK_AVG_THRESH_FILT_32_PI 0b00000000 // 1 0 OOK average filter coefficient: chip rate / 32*pi
316 #define SX127X_OOK_AVG_THRESH_FILT_8_PI 0b00000001 // 1 0 chip rate / 8*pi
317 #define SX127X_OOK_AVG_THRESH_FILT_4_PI 0b00000010 // 1 0 chip rate / 4*pi (default)
318 #define SX127X_OOK_AVG_THRESH_FILT_2_PI 0b00000011 // 1 0 chip rate / 2*pi
319 
320 // SX127X_REG_AFC_FEI
321 #define SX127X_AGC_START 0b00010000 // 4 4 manually start AGC sequence
322 #define SX127X_AFC_CLEAR 0b00000010 // 1 1 manually clear AFC register
323 #define SX127X_AFC_AUTO_CLEAR_OFF 0b00000000 // 0 0 AFC register will not be cleared at the start of AFC (default)
324 #define SX127X_AFC_AUTO_CLEAR_ON 0b00000001 // 0 0 AFC register will be cleared at the start of AFC
325 
326 // SX127X_REG_PREAMBLE_DETECT
327 #define SX127X_PREAMBLE_DETECTOR_OFF 0b00000000 // 7 7 preamble detection disabled
328 #define SX127X_PREAMBLE_DETECTOR_ON 0b10000000 // 7 7 preamble detection enabled (default)
329 #define SX127X_PREAMBLE_DETECTOR_1_BYTE 0b00000000 // 6 5 preamble detection size: 1 byte (default)
330 #define SX127X_PREAMBLE_DETECTOR_2_BYTE 0b00100000 // 6 5 2 bytes
331 #define SX127X_PREAMBLE_DETECTOR_3_BYTE 0b01000000 // 6 5 3 bytes
332 #define SX127X_PREAMBLE_DETECTOR_TOL 0x0A // 4 0 default number of tolerated errors per chip (4 chips per bit)
333 
334 // SX127X_REG_RX_TIMEOUT_1
335 #define SX127X_TIMEOUT_RX_RSSI_OFF 0x00 // 7 0 disable receiver timeout when RSSI interrupt doesn't occur (default)
336 
337 // SX127X_REG_RX_TIMEOUT_2
338 #define SX127X_TIMEOUT_RX_PREAMBLE_OFF 0x00 // 7 0 disable receiver timeout when preamble interrupt doesn't occur (default)
339 
340 // SX127X_REG_RX_TIMEOUT_3
341 #define SX127X_TIMEOUT_SIGNAL_SYNC_OFF 0x00 // 7 0 disable receiver timeout when sync address interrupt doesn't occur (default)
342 
343 // SX127X_REG_OSC
344 #define SX127X_RC_CAL_START 0b00000000 // 3 3 manually start RC oscillator calibration
345 #define SX127X_CLK_OUT_FXOSC 0b00000000 // 2 0 ClkOut frequency: F(XOSC)
346 #define SX127X_CLK_OUT_FXOSC_2 0b00000001 // 2 0 F(XOSC) / 2
347 #define SX127X_CLK_OUT_FXOSC_4 0b00000010 // 2 0 F(XOSC) / 4
348 #define SX127X_CLK_OUT_FXOSC_8 0b00000011 // 2 0 F(XOSC) / 8
349 #define SX127X_CLK_OUT_FXOSC_16 0b00000100 // 2 0 F(XOSC) / 16
350 #define SX127X_CLK_OUT_FXOSC_32 0b00000101 // 2 0 F(XOSC) / 32
351 #define SX127X_CLK_OUT_RC 0b00000110 // 2 0 RC
352 #define SX127X_CLK_OUT_OFF 0b00000111 // 2 0 disabled (default)
353 
354 // SX127X_REG_PREAMBLE_MSB_FSK + SX127X_REG_PREAMBLE_LSB_FSK
355 #define SX127X_PREAMBLE_SIZE_MSB 0x00 // 7 0 preamble size in bytes
356 #define SX127X_PREAMBLE_SIZE_LSB 0x03 // 7 0 default value: 3 bytes
357 
358 // SX127X_REG_SYNC_CONFIG
359 #define SX127X_AUTO_RESTART_RX_MODE_OFF 0b00000000 // 7 6 Rx mode restart after packet reception: disabled
360 #define SX127X_AUTO_RESTART_RX_MODE_NO_PLL 0b01000000 // 7 6 enabled, don't wait for PLL lock
361 #define SX127X_AUTO_RESTART_RX_MODE_PLL 0b10000000 // 7 6 enabled, wait for PLL lock (default)
362 #define SX127X_PREAMBLE_POLARITY_AA 0b00000000 // 5 5 preamble polarity: 0xAA = 0b10101010 (default)
363 #define SX127X_PREAMBLE_POLARITY_55 0b00100000 // 5 5 0x55 = 0b01010101
364 #define SX127X_SYNC_OFF 0b00000000 // 4 4 sync word disabled
365 #define SX127X_SYNC_ON 0b00010000 // 4 4 sync word enabled (default)
366 #define SX127X_SYNC_SIZE 0x03 // 2 0 sync word size in bytes, SyncSize = SYNC_SIZE + 1 bytes
367 
368 // SX127X_REG_SYNC_VALUE_1 - SX127X_REG_SYNC_VALUE_8
369 #define SX127X_SYNC_VALUE_1 0x01 // 7 0 sync word: 1st byte (MSB)
370 #define SX127X_SYNC_VALUE_2 0x01 // 7 0 2nd byte
371 #define SX127X_SYNC_VALUE_3 0x01 // 7 0 3rd byte
372 #define SX127X_SYNC_VALUE_4 0x01 // 7 0 4th byte
373 #define SX127X_SYNC_VALUE_5 0x01 // 7 0 5th byte
374 #define SX127X_SYNC_VALUE_6 0x01 // 7 0 6th byte
375 #define SX127X_SYNC_VALUE_7 0x01 // 7 0 7th byte
376 #define SX127X_SYNC_VALUE_8 0x01 // 7 0 8th byte (LSB)
377 
378 // SX127X_REG_PACKET_CONFIG_1
379 #define SX127X_PACKET_FIXED 0b00000000 // 7 7 packet format: fixed length
380 #define SX127X_PACKET_VARIABLE 0b10000000 // 7 7 variable length (default)
381 #define SX127X_DC_FREE_NONE 0b00000000 // 6 5 DC-free encoding: disabled (default)
382 #define SX127X_DC_FREE_MANCHESTER 0b00100000 // 6 5 Manchester
383 #define SX127X_DC_FREE_WHITENING 0b01000000 // 6 5 Whitening
384 #define SX127X_CRC_OFF 0b00000000 // 4 4 CRC disabled
385 #define SX127X_CRC_ON 0b00010000 // 4 4 CRC enabled (default)
386 #define SX127X_CRC_AUTOCLEAR_OFF 0b00001000 // 3 3 keep FIFO on CRC mismatch, issue payload ready interrupt
387 #define SX127X_CRC_AUTOCLEAR_ON 0b00000000 // 3 3 clear FIFO on CRC mismatch, do not issue payload ready interrupt
388 #define SX127X_ADDRESS_FILTERING_OFF 0b00000000 // 2 1 address filtering: none (default)
389 #define SX127X_ADDRESS_FILTERING_NODE 0b00000010 // 2 1 node
390 #define SX127X_ADDRESS_FILTERING_NODE_BROADCAST 0b00000100 // 2 1 node or broadcast
391 #define SX127X_CRC_WHITENING_TYPE_CCITT 0b00000000 // 0 0 CRC and whitening algorithms: CCITT CRC with standard whitening (default)
392 #define SX127X_CRC_WHITENING_TYPE_IBM 0b00000001 // 0 0 IBM CRC with alternate whitening
393 
394 // SX127X_REG_PACKET_CONFIG_2
395 #define SX127X_DATA_MODE_PACKET 0b01000000 // 6 6 data mode: packet (default)
396 #define SX127X_DATA_MODE_CONTINUOUS 0b00000000 // 6 6 continuous
397 #define SX127X_IO_HOME_OFF 0b00000000 // 5 5 io-homecontrol compatibility disabled (default)
398 #define SX127X_IO_HOME_ON 0b00100000 // 5 5 io-homecontrol compatibility enabled
399 
400 // SX127X_REG_FIFO_THRESH
401 #define SX127X_TX_START_FIFO_LEVEL 0b00000000 // 7 7 start packet transmission when: number of bytes in FIFO exceeds FIFO_THRESHOLD
402 #define SX127X_TX_START_FIFO_NOT_EMPTY 0b10000000 // 7 7 at least one byte in FIFO (default)
403 #define SX127X_FIFO_THRESH 0x0F // 5 0 FIFO level threshold
404 
405 // SX127X_REG_SEQ_CONFIG_1
406 #define SX127X_SEQUENCER_START 0b10000000 // 7 7 manually start sequencer
407 #define SX127X_SEQUENCER_STOP 0b01000000 // 6 6 manually stop sequencer
408 #define SX127X_IDLE_MODE_STANDBY 0b00000000 // 5 5 chip mode during sequencer idle mode: standby (default)
409 #define SX127X_IDLE_MODE_SLEEP 0b00100000 // 5 5 sleep
410 #define SX127X_FROM_START_LP_SELECTION 0b00000000 // 4 3 mode that will be set after starting sequencer: low power selection (default)
411 #define SX127X_FROM_START_RECEIVE 0b00001000 // 4 3 receive
412 #define SX127X_FROM_START_TRANSMIT 0b00010000 // 4 3 transmit
413 #define SX127X_FROM_START_TRANSMIT_FIFO_LEVEL 0b00011000 // 4 3 transmit on a FIFO level interrupt
414 #define SX127X_LP_SELECTION_SEQ_OFF 0b00000000 // 2 2 mode that will be set after exiting low power selection: sequencer off (default)
415 #define SX127X_LP_SELECTION_IDLE 0b00000100 // 2 2 idle state
416 #define SX127X_FROM_IDLE_TRANSMIT 0b00000000 // 1 1 mode that will be set after exiting idle mode: transmit (default)
417 #define SX127X_FROM_IDLE_RECEIVE 0b00000010 // 1 1 receive
418 #define SX127X_FROM_TRANSMIT_LP_SELECTION 0b00000000 // 0 0 mode that will be set after exiting transmit mode: low power selection (default)
419 #define SX127X_FROM_TRANSMIT_RECEIVE 0b00000001 // 0 0 receive
420 
421 // SX127X_REG_SEQ_CONFIG_2
422 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_PAYLOAD 0b00100000 // 7 5 mode that will be set after exiting receive mode: packet received on payload ready interrupt (default)
423 #define SX127X_FROM_RECEIVE_LP_SELECTION 0b01000000 // 7 5 low power selection
424 #define SX127X_FROM_RECEIVE_PACKET_RECEIVED_CRC_OK 0b01100000 // 7 5 packet received on CRC OK interrupt
425 #define SX127X_FROM_RECEIVE_SEQ_OFF_RSSI 0b10000000 // 7 5 sequencer off on RSSI interrupt
426 #define SX127X_FROM_RECEIVE_SEQ_OFF_SYNC_ADDR 0b10100000 // 7 5 sequencer off on sync address interrupt
427 #define SX127X_FROM_RECEIVE_SEQ_OFF_PREAMBLE_DETECT 0b11000000 // 7 5 sequencer off on preamble detect interrupt
428 #define SX127X_FROM_RX_TIMEOUT_RECEIVE 0b00000000 // 4 3 mode that will be set after Rx timeout: receive (default)
429 #define SX127X_FROM_RX_TIMEOUT_TRANSMIT 0b00001000 // 4 3 transmit
430 #define SX127X_FROM_RX_TIMEOUT_LP_SELECTION 0b00010000 // 4 3 low power selection
431 #define SX127X_FROM_RX_TIMEOUT_SEQ_OFF 0b00011000 // 4 3 sequencer off
432 #define SX127X_FROM_PACKET_RECEIVED_SEQ_OFF 0b00000000 // 2 0 mode that will be set after packet received: sequencer off (default)
433 #define SX127X_FROM_PACKET_RECEIVED_TRANSMIT 0b00000001 // 2 0 transmit
434 #define SX127X_FROM_PACKET_RECEIVED_LP_SELECTION 0b00000010 // 2 0 low power selection
435 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE_FS 0b00000011 // 2 0 receive via FS
436 #define SX127X_FROM_PACKET_RECEIVED_RECEIVE 0b00000100 // 2 0 receive
437 
438 // SX127X_REG_TIMER_RESOL
439 #define SX127X_TIMER1_OFF 0b00000000 // 3 2 timer 1 resolution: disabled (default)
440 #define SX127X_TIMER1_RESOLUTION_64_US 0b00000100 // 3 2 64 us
441 #define SX127X_TIMER1_RESOLUTION_4_1_MS 0b00001000 // 3 2 4.1 ms
442 #define SX127X_TIMER1_RESOLUTION_262_MS 0b00001100 // 3 2 262 ms
443 #define SX127X_TIMER2_OFF 0b00000000 // 3 2 timer 2 resolution: disabled (default)
444 #define SX127X_TIMER2_RESOLUTION_64_US 0b00000001 // 3 2 64 us
445 #define SX127X_TIMER2_RESOLUTION_4_1_MS 0b00000010 // 3 2 4.1 ms
446 #define SX127X_TIMER2_RESOLUTION_262_MS 0b00000011 // 3 2 262 ms
447 
448 // SX127X_REG_TIMER1_COEF
449 #define SX127X_TIMER1_COEFFICIENT 0xF5 // 7 0 multiplication coefficient for timer 1
450 
451 // SX127X_REG_TIMER2_COEF
452 #define SX127X_TIMER2_COEFFICIENT 0x20 // 7 0 multiplication coefficient for timer 2
453 
454 // SX127X_REG_IMAGE_CAL
455 #define SX127X_AUTO_IMAGE_CAL_OFF 0b00000000 // 7 7 temperature calibration disabled (default)
456 #define SX127X_AUTO_IMAGE_CAL_ON 0b10000000 // 7 7 temperature calibration enabled
457 #define SX127X_IMAGE_CAL_START 0b01000000 // 6 6 start temperature calibration
458 #define SX127X_IMAGE_CAL_RUNNING 0b00100000 // 5 5 temperature calibration is on-going
459 #define SX127X_IMAGE_CAL_COMPLETE 0b00000000 // 5 5 temperature calibration finished
460 #define SX127X_TEMP_CHANGED 0b00001000 // 3 3 temperature changed more than TEMP_THRESHOLD since last calibration
461 #define SX127X_TEMP_THRESHOLD_5_DEG_C 0b00000000 // 2 1 temperature change threshold: 5 deg. C
462 #define SX127X_TEMP_THRESHOLD_10_DEG_C 0b00000010 // 2 1 10 deg. C (default)
463 #define SX127X_TEMP_THRESHOLD_15_DEG_C 0b00000100 // 2 1 15 deg. C
464 #define SX127X_TEMP_THRESHOLD_20_DEG_C 0b00000110 // 2 1 20 deg. C
465 #define SX127X_TEMP_MONITOR_ON 0b00000000 // 0 0 temperature monitoring enabled (default)
466 #define SX127X_TEMP_MONITOR_OFF 0b00000001 // 0 0 temperature monitoring disabled
467 
468 // SX127X_REG_LOW_BAT
469 #define SX127X_LOW_BAT_OFF 0b00000000 // 3 3 low battery detector disabled
470 #define SX127X_LOW_BAT_ON 0b00001000 // 3 3 low battery detector enabled
471 #define SX127X_LOW_BAT_TRIM_1_695_V 0b00000000 // 2 0 battery voltage threshold: 1.695 V
472 #define SX127X_LOW_BAT_TRIM_1_764_V 0b00000001 // 2 0 1.764 V
473 #define SX127X_LOW_BAT_TRIM_1_835_V 0b00000010 // 2 0 1.835 V (default)
474 #define SX127X_LOW_BAT_TRIM_1_905_V 0b00000011 // 2 0 1.905 V
475 #define SX127X_LOW_BAT_TRIM_1_976_V 0b00000100 // 2 0 1.976 V
476 #define SX127X_LOW_BAT_TRIM_2_045_V 0b00000101 // 2 0 2.045 V
477 #define SX127X_LOW_BAT_TRIM_2_116_V 0b00000110 // 2 0 2.116 V
478 #define SX127X_LOW_BAT_TRIM_2_185_V 0b00000111 // 2 0 2.185 V
479 
480 // SX127X_REG_IRQ_FLAGS_1
481 #define SX127X_FLAG_MODE_READY 0b10000000 // 7 7 requested mode is ready
482 #define SX127X_FLAG_RX_READY 0b01000000 // 6 6 reception ready (after RSSI, AGC, AFC)
483 #define SX127X_FLAG_TX_READY 0b00100000 // 5 5 transmission ready (after PA ramp-up)
484 #define SX127X_FLAG_PLL_LOCK 0b00010000 // 4 4 PLL locked
485 #define SX127X_FLAG_RSSI 0b00001000 // 3 3 RSSI value exceeds RSSI threshold
486 #define SX127X_FLAG_TIMEOUT 0b00000100 // 2 2 timeout occurred
487 #define SX127X_FLAG_PREAMBLE_DETECT 0b00000010 // 1 1 valid preamble was detected
488 #define SX127X_FLAG_SYNC_ADDRESS_MATCH 0b00000001 // 0 0 sync address matched
489 
490 // SX127X_REG_IRQ_FLAGS_2
491 #define SX127X_FLAG_FIFO_FULL 0b10000000 // 7 7 FIFO is full
492 #define SX127X_FLAG_FIFO_EMPTY 0b01000000 // 6 6 FIFO is empty
493 #define SX127X_FLAG_FIFO_LEVEL 0b00100000 // 5 5 number of bytes in FIFO exceeds FIFO_THRESHOLD
494 #define SX127X_FLAG_FIFO_OVERRUN 0b00010000 // 4 4 FIFO overrun occurred
495 #define SX127X_FLAG_PACKET_SENT 0b00001000 // 3 3 packet was successfully sent
496 #define SX127X_FLAG_PAYLOAD_READY 0b00000100 // 2 2 packet was successfully received
497 #define SX127X_FLAG_CRC_OK 0b00000010 // 1 1 CRC check passed
498 #define SX127X_FLAG_LOW_BAT 0b00000001 // 0 0 battery voltage dropped below threshold
499 
500 // SX127X_REG_DIO_MAPPING_1
501 #define SX127X_DIO0_CONT_SYNC_ADDRESS 0b00000000 // 7 6
502 #define SX127X_DIO0_CONT_TX_READY 0b00000000 // 7 6
503 #define SX127X_DIO0_CONT_RSSI_PREAMBLE_DETECTED 0b01000000 // 7 6
504 #define SX127X_DIO0_CONT_RX_READY 0b10000000 // 7 6
505 #define SX127X_DIO0_PACK_PAYLOAD_READY 0b00000000 // 7 6
506 #define SX127X_DIO0_PACK_PACKET_SENT 0b00000000 // 7 6
507 #define SX127X_DIO0_PACK_CRC_OK 0b01000000 // 7 6
508 #define SX127X_DIO0_PACK_TEMP_CHANGE_LOW_BAT 0b11000000 // 7 6
509 #define SX127X_DIO1_CONT_DCLK 0b00000000 // 5 4
510 #define SX127X_DIO1_CONT_RSSI_PREAMBLE_DETECTED 0b00010000 // 5 4
511 #define SX127X_DIO1_PACK_FIFO_LEVEL 0b00000000 // 5 4
512 #define SX127X_DIO1_PACK_FIFO_EMPTY 0b00010000 // 5 4
513 #define SX127X_DIO1_PACK_FIFO_FULL 0b00100000 // 5 4
514 #define SX127X_DIO2_CONT_DATA 0b00000000 // 3 2
515 
516 // SX1272_REG_PLL_HOP + SX1278_REG_PLL_HOP
517 #define SX127X_FAST_HOP_OFF 0b00000000 // 7 7 carrier frequency validated when FRF registers are written
518 #define SX127X_FAST_HOP_ON 0b10000000 // 7 7 carrier frequency validated when FS modes are requested
519 
520 // SX1272_REG_TCXO + SX1278_REG_TCXO
521 #define SX127X_TCXO_INPUT_EXTERNAL 0b00000000 // 4 4 use external crystal oscillator
522 #define SX127X_TCXO_INPUT_EXTERNAL_CLIPPED 0b00010000 // 4 4 use external crystal oscillator clipped sine connected to XTA pin
523 
524 // SX1272_REG_PLL + SX1278_REG_PLL
525 #define SX127X_PLL_BANDWIDTH_75_KHZ 0b00000000 // 7 6 PLL bandwidth: 75 kHz
526 #define SX127X_PLL_BANDWIDTH_150_KHZ 0b01000000 // 7 6 150 kHz
527 #define SX127X_PLL_BANDWIDTH_225_KHZ 0b10000000 // 7 6 225 kHz
528 #define SX127X_PLL_BANDWIDTH_300_KHZ 0b11000000 // 7 6 300 kHz (default)
529 
536 class SX127x: public PhysicalLayer {
537  public:
538  // introduce PhysicalLayer overloads
539  using PhysicalLayer::transmit;
540  using PhysicalLayer::receive;
541  using PhysicalLayer::startTransmit;
542  using PhysicalLayer::readData;
543 
544  // constructor
545 
551  SX127x(Module* mod);
552 
553  // basic methods
554 
566  int16_t begin(uint8_t chipVersion, uint8_t syncWord, uint16_t preambleLength);
567 
571  virtual void reset() = 0;
572 
590  int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK);
591 
604  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
605 
616  int16_t receive(uint8_t* data, size_t len) override;
617 
623  int16_t scanChannel();
624 
631  int16_t sleep();
632 
638  int16_t standby() override;
639 
648  int16_t transmitDirect(uint32_t frf = 0) override;
649 
656  int16_t receiveDirect() override;
657 
663  int16_t packetMode();
664 
665  // interrupt methods
666 
672  void setDio0Action(void (*func)(void));
673 
677  void clearDio0Action();
678 
684  void setDio1Action(void (*func)(void));
685 
689  void clearDio1Action();
690 
702  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
703 
713  int16_t startReceive(uint8_t len = 0, uint8_t mode = SX127X_RXCONTINUOUS);
714 
724  int16_t readData(uint8_t* data, size_t len) override;
725 
726 
727  // configuration methods
728 
736  int16_t setSyncWord(uint8_t syncWord);
737 
745  int16_t setCurrentLimit(uint8_t currentLimit);
746 
754  int16_t setPreambleLength(uint16_t preambleLength);
755 
763  float getFrequencyError(bool autoCorrect = false);
764 
770  float getSNR();
771 
777  float getDataRate() const;
778 
786  int16_t setBitRate(float br);
787 
795  int16_t setFrequencyDeviation(float freqDev) override;
796 
804  int16_t setRxBandwidth(float rxBw);
805 
815  int16_t setSyncWord(uint8_t* syncWord, size_t len);
816 
824  int16_t setNodeAddress(uint8_t nodeAddr);
825 
833  int16_t setBroadcastAddress(uint8_t broadAddr);
834 
840  int16_t disableAddressFiltering();
841 
849  int16_t setOOK(bool enableOOK);
850 
858  size_t getPacketLength(bool update = true) override;
859 
867  int16_t fixedPacketLengthMode(uint8_t len = SX127X_MAX_PACKET_LENGTH_FSK);
868 
876  int16_t variablePacketLengthMode(uint8_t maxLen = SX127X_MAX_PACKET_LENGTH_FSK);
877 
888  int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset = 0);
889 
898  int16_t setEncoding(uint8_t encoding) override;
899 
907  uint16_t getIRQFlags();
908 
914  uint8_t getModemStatus();
915 
922  int8_t getTempRaw();
923 
932  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
933 
939  uint8_t random();
940 
946  int16_t getChipVersion();
947 
948 #ifndef RADIOLIB_GODMODE
949  protected:
950 #endif
951  Module* _mod;
952 
953  float _freq = 0;
954  float _bw = 0;
955  uint8_t _sf = 0;
956  uint8_t _cr = 0;
957  float _br = 0;
958  float _rxBw = 0;
959  bool _ook = false;
960  bool _crcEnabled = false;
961 
962  int16_t setFrequencyRaw(float newFreq);
963  int16_t config();
964  int16_t configFSK();
965  int16_t getActiveModem();
966  int16_t directMode();
967  int16_t setPacketMode(uint8_t mode, uint8_t len);
968 
969 #ifndef RADIOLIB_GODMODE
970  private:
971 #endif
972  float _dataRate = 0;
973  size_t _packetLength = 0;
974  bool _packetLengthQueried = false; // FSK packet length is the first byte in FIFO, length can only be queried once
975  uint8_t _packetLengthConfig = SX127X_PACKET_VARIABLE;
976 
977  bool findChip(uint8_t ver);
978  int16_t setMode(uint8_t mode);
979  int16_t setActiveModem(uint8_t modem);
980  void clearIRQFlags();
981  void clearFIFO(size_t count); // used mostly to clear remaining bytes in FIFO after a packet read
982 };
983 
984 #endif
985 
986 #endif
SX127x::setRSSIConfig
int16_t setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)
Sets RSSI measurement configuration in FSK mode.
Definition: SX127x.cpp:897
SX127x
Base class for SX127x series. All derived classes for SX127x (e.g. SX1278 or SX1272) inherit from thi...
Definition: SX127x.h:536
SX127x::getPacketLength
size_t getPacketLength(bool update=true) override
Query modem for the packet length of received payload.
Definition: SX127x.cpp:861
SX127x::readData
int16_t readData(uint8_t *data, size_t len) override
Reads data that was received after calling startReceive method. This method reads len characters...
Definition: SX127x.cpp:480
@@ -108,6 +108,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x::startReceive
int16_t startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)
Interrupt-driven receive method. DIO0 will be activated when full valid packet is received...
Definition: SX127x.cpp:353
SX127x::setDio0Action
void setDio0Action(void(*func)(void))
Set interrupt service routine function to call when DIO0 activates.
Definition: SX127x.cpp:397
SX127x::clearDio1Action
void clearDio1Action()
Clears interrupt service routine to call when DIO1 activates.
Definition: SX127x.cpp:412
+
SX127x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if ...
Definition: SX127x.cpp:993
Module
Implements all common low-level SPI/UART/I2C methods to control the wireless module. Every module class contains one private instance of this class.
Definition: Module.h:17
PhysicalLayer::transmit
int16_t transmit(__FlashStringHelper *fstr, uint8_t addr=0)
Arduino Flash String transmit method.
Definition: PhysicalLayer.cpp:8
SX127x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode on pins DIO1 (clock) and DIO2 (data). While in direct mode...
Definition: SX127x.cpp:314
@@ -120,7 +121,7 @@ $(document).ready(function(){initNavTree('_s_x127x_8h_source.html','');});
SX127x::beginFSK
int16_t beginFSK(uint8_t chipVersion, float br, float freqDev, float rxBw, uint16_t preambleLength, bool enableOOK)
Initialization method for FSK modem. Will be called with appropriate parameters when calling FSK init...
Definition: SX127x.cpp:52
SX127x::getIRQFlags
uint16_t getIRQFlags()
Reads currently active IRQ flags, can be used to check which event caused an interrupt. In LoRa mode, this is the content of SX127X_REG_IRQ_FLAGS register. In FSK mode, this is the contents of SX127X_REG_IRQ_FLAGS_2 (MSB) and SX127X_REG_IRQ_FLAGS_1 (LSB) registers.
Definition: SX127x.cpp:939
PhysicalLayer
Provides common interface for protocols that run on LoRa/FSK modules, such as RTTY or LoRaWAN...
Definition: PhysicalLayer.h:13
-
SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:993
+
SX127x::getTempRaw
int8_t getTempRaw()
Reads uncalibrated temperature value. This function will change operating mode and should not be call...
Definition: SX127x.cpp:997
SX127x::scanChannel
int16_t scanChannel()
Performs scan for valid LoRa preamble in the current channel.
Definition: SX127x.cpp:233
SX127x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: SX127x.cpp:964
SX127x::packetMode
int16_t packetMode()
Disables direct mode and enables packet mode, allowing the module to receive packets. Can only be activated in FSK mode.
Definition: SX127x.cpp:344
diff --git a/_si443x_8h_source.html b/_si443x_8h_source.html index 768b97e4..2a9c276f 100644 --- a/_si443x_8h_source.html +++ b/_si443x_8h_source.html @@ -84,10 +84,11 @@ $(document).ready(function(){initNavTree('_si443x_8h_source.html','');});
Si443x.h
-
1 #if !defined(_RADIOLIB_SI443X_H)
2 #define _RADIOLIB_SI443X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SI443X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // Si443x physical layer properties
13 #define SI443X_FREQUENCY_STEP_SIZE 156.25
14 #define SI443X_MAX_PACKET_LENGTH 64
15 
16 // Si443x series common registers
17 #define SI443X_REG_DEVICE_TYPE 0x00
18 #define SI443X_REG_DEVICE_VERSION 0x01
19 #define SI443X_REG_DEVICE_STATUS 0x02
20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03
21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04
22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05
23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06
24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07
25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08
26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09
27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A
28 #define SI443X_REG_GPIO0_CONFIG 0x0B
29 #define SI443X_REG_GPIO1_CONFIG 0x0C
30 #define SI443X_REG_GPIO2_CONFIG 0x0D
31 #define SI443X_REG_IO_PORT_CONFIG 0x0E
32 #define SI443X_REG_ADC_CONFIG 0x0F
33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10
34 #define SI443X_REG_ADC_VALUE 0x11
35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12
36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13
37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14
38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15
39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16
40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17
41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18
42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19
43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A
44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B
45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C
46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D
47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E
48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F
49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20
50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21
51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22
52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23
53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24
54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25
55 #define SI443X_REG_RSSI 0x26
56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27
57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28
58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29
59 #define SI443X_REG_AFC_LIMITER 0x2A
60 #define SI443X_REG_AFC_CORRECTION 0x2B
61 #define SI443X_REG_OOK_COUNTER_1 0x2C
62 #define SI443X_REG_OOK_COUNTER_2 0x2D
63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E
64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30
65 #define SI443X_REG_EZMAC_STATUS 0x31
66 #define SI443X_REG_HEADER_CONTROL_1 0x32
67 #define SI443X_REG_HEADER_CONTROL_2 0x33
68 #define SI443X_REG_PREAMBLE_LENGTH 0x34
69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35
70 #define SI443X_REG_SYNC_WORD_3 0x36
71 #define SI443X_REG_SYNC_WORD_2 0x37
72 #define SI443X_REG_SYNC_WORD_1 0x38
73 #define SI443X_REG_SYNC_WORD_0 0x39
74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A
75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B
76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C
77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D
78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E
79 #define SI443X_REG_CHECK_HEADER_3 0x3F
80 #define SI443X_REG_CHECK_HEADER_2 0x40
81 #define SI443X_REG_CHECK_HEADER_1 0x41
82 #define SI443X_REG_CHECK_HEADER_0 0x42
83 #define SI443X_REG_HEADER_ENABLE_3 0x43
84 #define SI443X_REG_HEADER_ENABLE_2 0x44
85 #define SI443X_REG_HEADER_ENABLE_1 0x45
86 #define SI443X_REG_HEADER_ENABLE_0 0x46
87 #define SI443X_REG_RECEIVED_HEADER_3 0x47
88 #define SI443X_REG_RECEIVED_HEADER_2 0x48
89 #define SI443X_REG_RECEIVED_HEADER_1 0x49
90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A
91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B
92 #define SI443X_REG_ADC8_CONTROL 0x4F
93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60
94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62
95 #define SI443X_REG_AGC_OVERRIDE_1 0x69
96 #define SI443X_REG_TX_POWER 0x6D
97 #define SI443X_REG_TX_DATA_RATE_1 0x6E
98 #define SI443X_REG_TX_DATA_RATE_0 0x6F
99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70
100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71
101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72
102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73
103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74
104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75
105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76
106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77
107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79
108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A
109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C
110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D
111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E
112 #define SI443X_REG_FIFO_ACCESS 0x7F
113 
114 // SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION
115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register
116 
117 // SI443X_REG_DEVICE_VERSION
118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register
119 
120 // SI443X_REG_DEVICE_STATUS
121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag
122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag
123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag
124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag
125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range)
126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx
127 #define SI443X_RX 0b00000001 // 1 0 Rx
128 #define SI443X_IDLE 0b00000000 // 1 0 idle
129 
130 // SI443X_REG_INTERRUPT_STATUS_1
131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow
132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full
133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty
134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full
135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx
136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done
137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received
138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed
139 
140 // SI443X_REG_INTERRUPT_STATUS_2
141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected
142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected
143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected
144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold
145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired
146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected
147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected
148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected
149 
150 // SI443X_REG_INTERRUPT_ENABLE_1
151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled
152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled
153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled
154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled
155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled
156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled
157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled
158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled
159 
160 // SI443X_REG_INTERRUPT_ENABLE_2
161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled
162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled
163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled
164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled
165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled
166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled
167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled
168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled
169 
170 // SI443X_REG_OP_FUNC_CONTROL_1
171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values
172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection
173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer
174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default)
175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator
176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode
177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode
178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode)
179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode)
180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode)
181 
182 // SI443X_REG_OP_FUNC_CONTROL_2
183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default)
184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low
185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high
186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high
187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low
188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high
189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low
190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high
191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default)
192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled
193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default)
194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled
195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default)
196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled
197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first)
198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second)
199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first)
200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second)
201 
202 // SI443X_REG_XOSC_LOAD_CAPACITANCE
203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration:
204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT
205 
206 // SI443X_REG_MCU_OUTPUT_CLOCK
207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default)
208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128
209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256
210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512
211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default)
212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled
213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz
214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz
215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz
216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz
217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz
218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz
219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default)
220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz
221 
222 // SI443X_REG_GPIO0_CONFIG + SI443X_REG_GPIO1_CONFIG + SI443X_REG_GPIO2_CONFIG
223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive)
224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default)
225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled
226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default)
227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default)
228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default)
229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output
230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output
231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output
232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge
233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge
234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change
235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input
236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input
237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input
238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input
239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output
240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output
241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output
242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output
243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode
244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode
245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input
246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output
247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output
248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output
249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output
250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output
251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1
252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2
253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output
254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output
255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output
256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output
257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD
258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND
259 
260 // SI443X_REG_IO_PORT_CONFIG
261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2
262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1
263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0
264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default)
265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled
266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2
267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1
268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0
269 
270 // SI443X_REG_ADC_CONFIG
271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement
272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress
273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done
274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default)
275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0
276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1
277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2
278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-)
279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-)
280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-)
281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND
282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default)
283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3
284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2
285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain
286 
287 // SI443X_REG_ADC_SENSOR_AMP_OFFSET
288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset
289 
290 // SI443X_REG_TEMP_SENSOR_CONTROL
291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default)
292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution
293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution
294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution
295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled
296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default)
297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default)
298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled
299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value
300 
301 // SI443X_REG_WAKEUP_TIMER_PERIOD_1
302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent
303 
304 // SI443X_REG_WAKEUP_TIMER_PERIOD_2 + SI443X_REG_WAKEUP_TIMER_PERIOD_3
305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value:
306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
307 
308 // SI443X_REG_LOW_DC_MODE_DURATION
309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
310 
311 // SI443X_REG_LOW_BATT_DET_THRESHOLD
312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V)
313 
314 // SI443X_REG_IF_FILTER_BANDWIDTH
315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default)
316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled
317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate
318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection
319 
320 // SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE
321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default)
322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled
323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled
324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default)
325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting
326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default)
327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB
328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb
329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default)
330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default)
331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases
332 
333 // SI443X_REG_AFC_TIMING_CONTROL
334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching
335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction
336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time
337 
338 // SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE
339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value
340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value
341 
342 // SI443X_REG_CLOCK_REC_OVERSAMP_RATIO
343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit
344 
345 // SI443X_REG_CLOCK_REC_OFFSET_2
346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit
347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold
348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB
349 
350 // SI443X_REG_CLOCK_REC_OFFSET_1
351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID
352 
353 // SI443X_REG_CLOCK_REC_OFFSET_0
354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB
355 
356 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1
357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default)
358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled
359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default)
360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled
361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB
362 
363 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0
364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB
365 
366 // SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD
367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold
368 
369 // SI443X_REG_AFC_LIMITER
370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value
371 
372 // SI443X_REG_OOK_COUNTER_1
373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default)
374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled
375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled
376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default)
377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled
378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default)
379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB
380 
381 // SI443X_REG_OOK_COUNTER_2
382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB
383 
384 // SI443X_REG_SLICER_PEAK_HOLD
385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time
386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time
387 
388 // SI443X_REG_DATA_ACCESS_CONTROL
389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled
390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default)
391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default)
392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled
393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default)
394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled
395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default)
396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled
397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled
398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default)
399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled
400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default)
401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT
402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default)
403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16
404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva
405 
406 // SI443X_REG_EZMAC_STATUS
407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones
408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet
409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet
410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received
411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed
412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet
413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent
414 
415 // SI443X_REG_HEADER_CONTROL_1
416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default)
417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0
418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1
419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2
420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3
421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none
422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0
423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1
424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default)
425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default)
426 
427 // SI443X_REG_HEADER_CONTROL_2
428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default)
429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled
430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none
431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3
432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2
433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default)
434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0
435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default)
436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled
437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3
438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default)
439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1
440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0
441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB
442 
443 // SI443X_REG_PREAMBLE_LENGTH
444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits
445 
446 // SI443X_REG_PREAMBLE_DET_CONTROL
447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits
448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB
449 
450 // SI443X_REG_SYNC_WORD_3 - SI443X_REG_SYNC_WORD_0
451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB)
452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte
453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte
454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB)
455 
456 // SI443X_REG_CHANNEL_FILTER_COEFF
457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles
458 
459 // SI443X_REG_XOSC_CONTROL_TEST
460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power
461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready
462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune
463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx
464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx
465 
466 // SI443X_REG_AGC_OVERRIDE_1
467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default)
468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled
469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled
470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default)
471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default)
472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB
473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB
474 
475 // SI443X_REG_TX_POWER
476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled
477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default)
478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max
479 
480 // SI443X_REG_TX_DATA_RATE_1 + SI443X_REG_TX_DATA_RATE_0
481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or
482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps)
483 
484 // SI443X_REG_MODULATION_MODE_CONTROL_1
485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default)
486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps
487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default)
488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled
489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low
490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default)
491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled
492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default)
493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default)
494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled
495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default)
496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled
497 
498 // SI443X_REG_MODULATION_MODE_CONTROL_2
499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default)
500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin
501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin
502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin
503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default)
504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin
505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO
506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal
507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default)
508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled
509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB
510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default)
511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK
512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK
513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK
514 
515 // SI443X_REG_FREQUENCY_DEVIATION
516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz
517 
518 // SI443X_REG_FREQUENCY_OFFSET_1 + SI443X_REG_FREQUENCY_OFFSET_2
519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset:
520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz
521 
522 // SI443X_REG_FREQUENCY_BAND_SELECT
523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default)
524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency
525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz
526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default)
527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select
528 
529 // SI443X_REG_NOM_CARRIER_FREQUENCY_1 + SI443X_REG_NOM_CARRIER_FREQUENCY_0
530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency:
531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz]
532 
533 // SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL
534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number
535 
536 // SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE
537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size
538 
539 // SI443X_REG_TX_FIFO_CONTROL_1
540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold
541 
542 // SI443X_REG_TX_FIFO_CONTROL_2
543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold
544 
545 // SI443X_REG_RX_FIFO_CONTROL
546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold
547 
554 class Si443x: public PhysicalLayer {
555  public:
556  // introduce PhysicalLayer overloads
557  using PhysicalLayer::transmit;
558  using PhysicalLayer::receive;
559  using PhysicalLayer::startTransmit;
560  using PhysicalLayer::readData;
561 
562  // constructor
563 
569  Si443x(Module* mod);
570 
571  // basic methods
572 
586  int16_t begin(float br, float freqDev, float rxBw, uint8_t preambleLen);
587 
591  void reset();
592 
605  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
606 
617  int16_t receive(uint8_t* data, size_t len) override;
618 
625  int16_t sleep();
626 
632  int16_t standby() override;
633 
641  int16_t transmitDirect(uint32_t frf = 0) override;
642 
648  int16_t receiveDirect() override;
649 
655  int16_t packetMode();
656 
657  // interrupt methods
658 
664  void setIrqAction(void (*func)(void));
665 
669  void clearIrqAction();
670 
682  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
683 
689  int16_t startReceive();
690 
700  int16_t readData(uint8_t* data, size_t len) override;
701 
702  // configuration methods
703 
711  int16_t setBitRate(float br);
712 
720  int16_t setFrequencyDeviation(float freqDev) override;
721 
729  int16_t setRxBandwidth(float rxBw);
730 
738  int16_t setSyncWord(uint8_t* syncWord, size_t len);
739 
747  int16_t setPreambleLength(uint8_t preambleLen);
748 
756  size_t getPacketLength(bool update = true) override;
757 
766  int16_t setEncoding(uint8_t encoding) override;
767 
776  int16_t setDataShaping(uint8_t sh) override;
777 
786  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
787 
793  uint8_t random();
794 
795 #ifndef RADIOLIB_GODMODE
796  protected:
797 #endif
798  Module* _mod;
799 
800  float _br = 0;
801  float _freqDev = 0;
802  float _freq = 0;
803 
804  size_t _packetLength = 0;
805  bool _packetLengthQueried = false;
806 
807  int16_t setFrequencyRaw(float newFreq);
808 
809 #ifndef RADIOLIB_GODMODE
810  private:
811 #endif
812  bool findChip();
813  void clearIRQFlags();
814  int16_t config();
815  int16_t updateClockRecovery();
816  int16_t directMode();
817 };
818 
819 #endif
820 
821 #endif
Si443x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:364
+
1 #if !defined(_RADIOLIB_SI443X_H)
2 #define _RADIOLIB_SI443X_H
3 
4 #include "../../TypeDef.h"
5 
6 #if !defined(RADIOLIB_EXCLUDE_SI443X)
7 
8 #include "../../Module.h"
9 
10 #include "../../protocols/PhysicalLayer/PhysicalLayer.h"
11 
12 // Si443x physical layer properties
13 #define SI443X_FREQUENCY_STEP_SIZE 156.25
14 #define SI443X_MAX_PACKET_LENGTH 64
15 
16 // Si443x series common registers
17 #define SI443X_REG_DEVICE_TYPE 0x00
18 #define SI443X_REG_DEVICE_VERSION 0x01
19 #define SI443X_REG_DEVICE_STATUS 0x02
20 #define SI443X_REG_INTERRUPT_STATUS_1 0x03
21 #define SI443X_REG_INTERRUPT_STATUS_2 0x04
22 #define SI443X_REG_INTERRUPT_ENABLE_1 0x05
23 #define SI443X_REG_INTERRUPT_ENABLE_2 0x06
24 #define SI443X_REG_OP_FUNC_CONTROL_1 0x07
25 #define SI443X_REG_OP_FUNC_CONTROL_2 0x08
26 #define SI443X_REG_XOSC_LOAD_CAPACITANCE 0x09
27 #define SI443X_REG_MCU_OUTPUT_CLOCK 0x0A
28 #define SI443X_REG_GPIO0_CONFIG 0x0B
29 #define SI443X_REG_GPIO1_CONFIG 0x0C
30 #define SI443X_REG_GPIO2_CONFIG 0x0D
31 #define SI443X_REG_IO_PORT_CONFIG 0x0E
32 #define SI443X_REG_ADC_CONFIG 0x0F
33 #define SI443X_REG_ADC_SENSOR_AMP_OFFSET 0x10
34 #define SI443X_REG_ADC_VALUE 0x11
35 #define SI443X_REG_TEMP_SENSOR_CONTROL 0x12
36 #define SI443X_REG_TEMP_VALUE_OFFSET 0x13
37 #define SI443X_REG_WAKEUP_TIMER_PERIOD_1 0x14
38 #define SI443X_REG_WAKEUP_TIMER_PERIOD_2 0x15
39 #define SI443X_REG_WAKEUP_TIMER_PERIOD_3 0x16
40 #define SI443X_REG_WAKEUP_TIMER_VALUE_1 0x17
41 #define SI443X_REG_WAKEUP_TIMER_VALUE_2 0x18
42 #define SI443X_REG_LOW_DC_MODE_DURATION 0x19
43 #define SI443X_REG_LOW_BATT_DET_THRESHOLD 0x1A
44 #define SI443X_REG_BATT_VOLTAGE_LEVEL 0x1B
45 #define SI443X_REG_IF_FILTER_BANDWIDTH 0x1C
46 #define SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D
47 #define SI443X_REG_AFC_TIMING_CONTROL 0x1E
48 #define SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE 0x1F
49 #define SI443X_REG_CLOCK_REC_OVERSAMP_RATIO 0x20
50 #define SI443X_REG_CLOCK_REC_OFFSET_2 0x21
51 #define SI443X_REG_CLOCK_REC_OFFSET_1 0x22
52 #define SI443X_REG_CLOCK_REC_OFFSET_0 0x23
53 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1 0x24
54 #define SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0 0x25
55 #define SI443X_REG_RSSI 0x26
56 #define SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD 0x27
57 #define SI443X_REG_ANTENNA_DIVERSITY_1 0x28
58 #define SI443X_REG_ANTENNA_DIVERSITY_2 0x29
59 #define SI443X_REG_AFC_LIMITER 0x2A
60 #define SI443X_REG_AFC_CORRECTION 0x2B
61 #define SI443X_REG_OOK_COUNTER_1 0x2C
62 #define SI443X_REG_OOK_COUNTER_2 0x2D
63 #define SI443X_REG_SLICER_PEAK_HOLD 0x2E
64 #define SI443X_REG_DATA_ACCESS_CONTROL 0x30
65 #define SI443X_REG_EZMAC_STATUS 0x31
66 #define SI443X_REG_HEADER_CONTROL_1 0x32
67 #define SI443X_REG_HEADER_CONTROL_2 0x33
68 #define SI443X_REG_PREAMBLE_LENGTH 0x34
69 #define SI443X_REG_PREAMBLE_DET_CONTROL 0x35
70 #define SI443X_REG_SYNC_WORD_3 0x36
71 #define SI443X_REG_SYNC_WORD_2 0x37
72 #define SI443X_REG_SYNC_WORD_1 0x38
73 #define SI443X_REG_SYNC_WORD_0 0x39
74 #define SI443X_REG_TRANSMIT_HEADER_3 0x3A
75 #define SI443X_REG_TRANSMIT_HEADER_2 0x3B
76 #define SI443X_REG_TRANSMIT_HEADER_1 0x3C
77 #define SI443X_REG_TRANSMIT_HEADER_0 0x3D
78 #define SI443X_REG_TRANSMIT_PACKET_LENGTH 0x3E
79 #define SI443X_REG_CHECK_HEADER_3 0x3F
80 #define SI443X_REG_CHECK_HEADER_2 0x40
81 #define SI443X_REG_CHECK_HEADER_1 0x41
82 #define SI443X_REG_CHECK_HEADER_0 0x42
83 #define SI443X_REG_HEADER_ENABLE_3 0x43
84 #define SI443X_REG_HEADER_ENABLE_2 0x44
85 #define SI443X_REG_HEADER_ENABLE_1 0x45
86 #define SI443X_REG_HEADER_ENABLE_0 0x46
87 #define SI443X_REG_RECEIVED_HEADER_3 0x47
88 #define SI443X_REG_RECEIVED_HEADER_2 0x48
89 #define SI443X_REG_RECEIVED_HEADER_1 0x49
90 #define SI443X_REG_RECEIVED_HEADER_0 0x4A
91 #define SI443X_REG_RECEIVED_PACKET_LENGTH 0x4B
92 #define SI443X_REG_ADC8_CONTROL 0x4F
93 #define SI443X_REG_CHANNEL_FILTER_COEFF 0x60
94 #define SI443X_REG_XOSC_CONTROL_TEST 0x62
95 #define SI443X_REG_AGC_OVERRIDE_1 0x69
96 #define SI443X_REG_TX_POWER 0x6D
97 #define SI443X_REG_TX_DATA_RATE_1 0x6E
98 #define SI443X_REG_TX_DATA_RATE_0 0x6F
99 #define SI443X_REG_MODULATION_MODE_CONTROL_1 0x70
100 #define SI443X_REG_MODULATION_MODE_CONTROL_2 0x71
101 #define SI443X_REG_FREQUENCY_DEVIATION 0x72
102 #define SI443X_REG_FREQUENCY_OFFSET_1 0x73
103 #define SI443X_REG_FREQUENCY_OFFSET_2 0x74
104 #define SI443X_REG_FREQUENCY_BAND_SELECT 0x75
105 #define SI443X_REG_NOM_CARRIER_FREQUENCY_1 0x76
106 #define SI443X_REG_NOM_CARRIER_FREQUENCY_0 0x77
107 #define SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL 0x79
108 #define SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE 0x7A
109 #define SI443X_REG_TX_FIFO_CONTROL_1 0x7C
110 #define SI443X_REG_TX_FIFO_CONTROL_2 0x7D
111 #define SI443X_REG_RX_FIFO_CONTROL 0x7E
112 #define SI443X_REG_FIFO_ACCESS 0x7F
113 
114 // SI443X_REG_DEVICE_TYPE MSB LSB DESCRIPTION
115 #define SI443X_DEVICE_TYPE 0x08 // 4 0 device identification register
116 
117 // SI443X_REG_DEVICE_VERSION
118 #define SI443X_DEVICE_VERSION 0x06 // 4 0 chip version register
119 
120 // SI443X_REG_DEVICE_STATUS
121 #define SI443X_RX_TX_FIFO_OVERFLOW 0b10000000 // 7 7 Rx/Tx FIFO overflow flag
122 #define SI443X_RX_TX_FIFO_UNDERFLOW 0b01000000 // 6 6 Rx/Tx FIFO underflow flag
123 #define SI443X_RX_FIFO_EMPTY 0b00100000 // 5 5 Rx FIFO empty flag
124 #define SI443X_HEADER_ERROR 0b00010000 // 4 4 header error flag
125 #define SI443X_FREQUENCY_ERROR 0b00001000 // 3 3 frequency error flag (frequency outside allowed range)
126 #define SI443X_TX 0b00000010 // 1 0 power state: Tx
127 #define SI443X_RX 0b00000001 // 1 0 Rx
128 #define SI443X_IDLE 0b00000000 // 1 0 idle
129 
130 // SI443X_REG_INTERRUPT_STATUS_1
131 #define SI443X_FIFO_LEVEL_ERROR_INTERRUPT 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow
132 #define SI443X_TX_FIFO_ALMOST_FULL_INTERRUPT 0b01000000 // 6 6 Tx FIFO almost full
133 #define SI443X_TX_FIFO_ALMOST_EMPTY_INTERRUPT 0b00100000 // 5 5 Tx FIFO almost empty
134 #define SI443X_RX_FIFO_ALMOST_FULL_INTERRUPT 0b00010000 // 4 4 Rx FIFO almost full
135 #define SI443X_EXTERNAL_INTERRUPT 0b00001000 // 3 3 external interrupt occurred on GPIOx
136 #define SI443X_PACKET_SENT_INTERRUPT 0b00000100 // 2 2 packet transmission done
137 #define SI443X_VALID_PACKET_RECEIVED_INTERRUPT 0b00000010 // 1 1 valid packet has been received
138 #define SI443X_CRC_ERROR_INTERRUPT 0b00000001 // 0 0 CRC failed
139 
140 // SI443X_REG_INTERRUPT_STATUS_2
141 #define SI443X_SYNC_WORD_DETECTED_INTERRUPT 0b10000000 // 7 7 sync word has been detected
142 #define SI443X_VALID_PREAMBLE_DETECTED_INTERRUPT 0b01000000 // 6 6 valid preamble has been detected
143 #define SI443X_INVALID_PREAMBLE_DETECTED_INTERRUPT 0b00100000 // 5 5 invalid preamble has been detected
144 #define SI443X_RSSI_INTERRUPT 0b00010000 // 4 4 RSSI exceeded programmed threshold
145 #define SI443X_WAKEUP_TIMER_INTERRUPT 0b00001000 // 3 3 wake-up timer expired
146 #define SI443X_LOW_BATTERY_INTERRUPT 0b00000100 // 2 2 low battery detected
147 #define SI443X_CHIP_READY_INTERRUPT 0b00000010 // 1 1 chip ready event detected
148 #define SI443X_POWER_ON_RESET_INTERRUPT 0b00000001 // 0 0 power-on-reset detected
149 
150 // SI443X_REG_INTERRUPT_ENABLE_1
151 #define SI443X_FIFO_LEVEL_ERROR_ENABLED 0b10000000 // 7 7 Tx/Rx FIFO overflow or underflow interrupt enabled
152 #define SI443X_TX_FIFO_ALMOST_FULL_ENABLED 0b01000000 // 6 6 Tx FIFO almost full interrupt enabled
153 #define SI443X_TX_FIFO_ALMOST_EMPTY_ENABLED 0b00100000 // 5 5 Tx FIFO almost empty interrupt enabled
154 #define SI443X_RX_FIFO_ALMOST_FULL_ENABLED 0b00010000 // 4 4 Rx FIFO almost full interrupt enabled
155 #define SI443X_EXTERNAL_ENABLED 0b00001000 // 3 3 external interrupt interrupt enabled
156 #define SI443X_PACKET_SENT_ENABLED 0b00000100 // 2 2 packet transmission done interrupt enabled
157 #define SI443X_VALID_PACKET_RECEIVED_ENABLED 0b00000010 // 1 1 valid packet received interrupt enabled
158 #define SI443X_CRC_ERROR_ENABLED 0b00000001 // 0 0 CRC failed interrupt enabled
159 
160 // SI443X_REG_INTERRUPT_ENABLE_2
161 #define SI443X_SYNC_WORD_DETECTED_ENABLED 0b10000000 // 7 7 sync word interrupt enabled
162 #define SI443X_VALID_PREAMBLE_DETECTED_ENABLED 0b01000000 // 6 6 valid preamble interrupt enabled
163 #define SI443X_INVALID_PREAMBLE_DETECTED_ENABLED 0b00100000 // 5 5 invalid preamble interrupt enabled
164 #define SI443X_RSSI_ENABLED 0b00010000 // 4 4 RSSI exceeded programmed threshold interrupt enabled
165 #define SI443X_WAKEUP_TIMER_ENABLED 0b00001000 // 3 3 wake-up timer interrupt enabled
166 #define SI443X_LOW_BATTERY_ENABLED 0b00000100 // 2 2 low battery interrupt enabled
167 #define SI443X_CHIP_READY_ENABLED 0b00000010 // 1 1 chip ready event interrupt enabled
168 #define SI443X_POWER_ON_RESET_ENABLED 0b00000001 // 0 0 power-on-reset interrupt enabled
169 
170 // SI443X_REG_OP_FUNC_CONTROL_1
171 #define SI443X_SOFTWARE_RESET 0b10000000 // 7 7 reset all registers to default values
172 #define SI443X_ENABLE_LOW_BATTERY_DETECT 0b01000000 // 6 6 enable low battery detection
173 #define SI443X_ENABLE_WAKEUP_TIMER 0b00100000 // 5 5 enable wakeup timer
174 #define SI443X_32_KHZ_RC 0b00000000 // 4 4 32.768 kHz source: RC oscillator (default)
175 #define SI443X_32_KHZ_XOSC 0b00010000 // 4 4 crystal oscillator
176 #define SI443X_TX_ON 0b00001000 // 3 3 Tx on in manual transmit mode
177 #define SI443X_RX_ON 0b00000100 // 2 2 Rx on in manual receive mode
178 #define SI443X_PLL_ON 0b00000010 // 1 1 PLL on (tune mode)
179 #define SI443X_XTAL_OFF 0b00000000 // 0 0 crystal oscillator: off (standby mode)
180 #define SI443X_XTAL_ON 0b00000001 // 0 0 on (ready mode)
181 
182 // SI443X_REG_OP_FUNC_CONTROL_2
183 #define SI443X_ANT_DIV_TR_HL_IDLE_L 0b00000000 // 7 5 GPIO1/2 states: Tx/Rx GPIO1 H, GPIO2 L; idle low (default)
184 #define SI443X_ANT_DIV_TR_LH_IDLE_L 0b00100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle low
185 #define SI443X_ANT_DIV_TR_HL_IDLE_H 0b01000000 // 7 5 Tx/Rx GPIO1 H, GPIO2 L; idle high
186 #define SI443X_ANT_DIV_TR_LH_IDLE_H 0b01100000 // 7 5 Tx/Rx GPIO1 L, GPIO2 H; idle high
187 #define SI443X_ANT_DIV_TR_ALG_IDLE_L 0b10000000 // 7 5 Tx/Rx diversity algorithm; idle low
188 #define SI443X_ANT_DIV_TR_ALG_IDLE_H 0b10100000 // 7 5 Tx/Rx diversity algorithm; idle high
189 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_L 0b11000000 // 7 5 Tx/Rx diversity algorithm (beacon); idle low
190 #define SI443X_ANT_DIV_TR_ALG_BEACON_IDLE_H 0b11100000 // 7 5 Tx/Rx diversity algorithm (beacon); idle high
191 #define SI443X_RX_MULTIPACKET_OFF 0b00000000 // 4 4 Rx multipacket: disabled (default)
192 #define SI443X_RX_MULTIPACKET_ON 0b00010000 // 4 4 enabled
193 #define SI443X_AUTO_TX_OFF 0b00000000 // 3 3 Tx autotransmit on FIFO almost full: disabled (default)
194 #define SI443X_AUTO_TX_ON 0b00001000 // 3 3 enabled
195 #define SI443X_LOW_DUTY_CYCLE_OFF 0b00000000 // 2 2 low duty cycle mode: disabled (default)
196 #define SI443X_LOW_DUTY_CYCLE_ON 0b00000100 // 2 2 enabled
197 #define SI443X_RX_FIFO_RESET 0b00000010 // 1 1 Rx FIFO reset/clear: reset (call first)
198 #define SI443X_RX_FIFO_CLEAR 0b00000000 // 1 1 clear (call second)
199 #define SI443X_TX_FIFO_RESET 0b00000001 // 0 0 Tx FIFO reset/clear: reset (call first)
200 #define SI443X_TX_FIFO_CLEAR 0b00000000 // 0 0 clear (call second)
201 
202 // SI443X_REG_XOSC_LOAD_CAPACITANCE
203 #define SI443X_XTAL_SHIFT 0b00000000 // 7 7 crystal capacitance configuration:
204 #define SI443X_XTAL_LOAD_CAPACITANCE 0b01111111 // 6 0 C_int = 1.8 pF + 0.085 pF * SI443X_XTAL_LOAD_CAPACITANCE + 3.7 pF * SI443X_XTAL_SHIFT
205 
206 // SI443X_REG_MCU_OUTPUT_CLOCK
207 #define SI443X_CLOCK_TAIL_CYCLES_OFF 0b00000000 // 5 4 additional clock cycles: none (default)
208 #define SI443X_CLOCK_TAIL_CYCLES_128 0b00010000 // 5 4 128
209 #define SI443X_CLOCK_TAIL_CYCLES_256 0b00100000 // 5 4 256
210 #define SI443X_CLOCK_TAIL_CYCLES_512 0b00110000 // 5 4 512
211 #define SI443X_LOW_FREQ_CLOCK_OFF 0b00000000 // 3 3 32.768 kHz clock output: disabled (default)
212 #define SI443X_LOW_FREQ_CLOCK_ON 0b00001000 // 3 3 enabled
213 #define SI443X_MCU_CLOCK_30_MHZ 0b00000000 // 2 0 GPIO clock output: 30 MHz
214 #define SI443X_MCU_CLOCK_15_MHZ 0b00000001 // 2 0 15 MHz
215 #define SI443X_MCU_CLOCK_10_MHZ 0b00000010 // 2 0 10 MHz
216 #define SI443X_MCU_CLOCK_4_MHZ 0b00000011 // 2 0 4 MHz
217 #define SI443X_MCU_CLOCK_3_MHZ 0b00000100 // 2 0 3 MHz
218 #define SI443X_MCU_CLOCK_2_MHZ 0b00000101 // 2 0 2 MHz
219 #define SI443X_MCU_CLOCK_1_MHZ 0b00000110 // 2 0 1 MHz (default)
220 #define SI443X_MCU_CLOCK_32_KHZ 0b00000111 // 2 0 32.768 kHz
221 
222 // SI443X_REG_GPIO0_CONFIG + SI443X_REG_GPIO1_CONFIG + SI443X_REG_GPIO2_CONFIG
223 #define SI443X_GPIOX_DRIVE_STRENGTH 0b00000000 // 7 6 GPIOx drive strength (higher number = stronger drive)
224 #define SI443X_GPIOX_PULLUP_OFF 0b00000000 // 5 5 GPIOx internal 200k pullup: disabled (default)
225 #define SI443X_GPIOX_PULLUP_ON 0b00100000 // 5 5 enabled
226 #define SI443X_GPIO0_POWER_ON_RESET_OUT 0b00000000 // 4 0 GPIOx function: power-on-reset output (GPIO0 only, default)
227 #define SI443X_GPIO1_POWER_ON_RESET_INV_OUT 0b00000000 // 4 0 inverted power-on-reset output (GPIO1 only, default)
228 #define SI443X_GPIO2_MCU_CLOCK_OUT 0b00000000 // 4 0 MCU clock output (GPIO2 only, default)
229 #define SI443X_GPIOX_WAKEUP_OUT 0b00000001 // 4 0 wakeup timer expired output
230 #define SI443X_GPIOX_LOW_BATTERY_OUT 0b00000010 // 4 0 low battery detect output
231 #define SI443X_GPIOX_DIGITAL_OUT 0b00000011 // 4 0 direct digital output
232 #define SI443X_GPIOX_EXT_INT_FALLING_IN 0b00000100 // 4 0 external interrupt, falling edge
233 #define SI443X_GPIOX_EXT_INT_RISING_IN 0b00000101 // 4 0 external interrupt, rising edge
234 #define SI443X_GPIOX_EXT_INT_CHANGE_IN 0b00000110 // 4 0 external interrupt, state change
235 #define SI443X_GPIOX_ADC_IN 0b00000111 // 4 0 ADC analog input
236 #define SI443X_GPIOX_ANALOG_TEST_N_IN 0b00001000 // 4 0 analog test N input
237 #define SI443X_GPIOX_ANALOG_TEST_P_IN 0b00001001 // 4 0 analog test P input
238 #define SI443X_GPIOX_DIGITAL_IN 0b00001010 // 4 0 direct digital input
239 #define SI443X_GPIOX_DIGITAL_TEST_OUT 0b00001011 // 4 0 digital test output
240 #define SI443X_GPIOX_ANALOG_TEST_N_OUT 0b00001100 // 4 0 analog test N output
241 #define SI443X_GPIOX_ANALOG_TEST_P_OUT 0b00001101 // 4 0 analog test P output
242 #define SI443X_GPIOX_REFERENCE_VOLTAGE_OUT 0b00001110 // 4 0 reference voltage output
243 #define SI443X_GPIOX_TX_RX_DATA_CLK_OUT 0b00001111 // 4 0 Tx/Rx clock output in direct mode
244 #define SI443X_GPIOX_TX_DATA_IN 0b00010000 // 4 0 Tx data input direct mode
245 #define SI443X_GPIOX_EXT_RETRANSMIT_REQUEST_IN 0b00010001 // 4 0 external retransmission request input
246 #define SI443X_GPIOX_TX_STATE_OUT 0b00010010 // 4 0 Tx state output
247 #define SI443X_GPIOX_TX_FIFO_ALMOST_FULL_OUT 0b00010011 // 4 0 Tx FIFO almost full output
248 #define SI443X_GPIOX_RX_DATA_OUT 0b00010100 // 4 0 Rx data output
249 #define SI443X_GPIOX_RX_STATE_OUT 0b00010101 // 4 0 Rx state output
250 #define SI443X_GPIOX_RX_FIFO_ALMOST_FULL_OUT 0b00010110 // 4 0 Rx FIFO almost full output
251 #define SI443X_GPIOX_ANT_DIV_1_OUT 0b00010111 // 4 0 antenna diversity output 1
252 #define SI443X_GPIOX_ANT_DIV_2_OUT 0b00011000 // 4 0 antenna diversity output 2
253 #define SI443X_GPIOX_VALID_PREAMBLE_OUT 0b00011001 // 4 0 valid preamble detected output
254 #define SI443X_GPIOX_INVALID_PREAMBLE_OUT 0b00011010 // 4 0 invalid preamble detected output
255 #define SI443X_GPIOX_SYNC_WORD_DETECTED_OUT 0b00011011 // 4 0 sync word detected output
256 #define SI443X_GPIOX_CLEAR_CHANNEL_OUT 0b00011100 // 4 0 clear channel assessment output
257 #define SI443X_GPIOX_VDD 0b00011101 // 4 0 VDD
258 #define SI443X_GPIOX_GND 0b00011110 // 4 0 GND
259 
260 // SI443X_REG_IO_PORT_CONFIG
261 #define SI443X_GPIO2_EXT_INT_STATE_MASK 0b01000000 // 6 6 external interrupt state mask for: GPIO2
262 #define SI443X_GPIO1_EXT_INT_STATE_MASK 0b00100000 // 5 5 GPIO1
263 #define SI443X_GPIO0_EXT_INT_STATE_MASK 0b00010000 // 4 4 GPIO0
264 #define SI443X_IRQ_BY_SDO_OFF 0b00000000 // 3 3 output IRQ state on SDO pin: disabled (default)
265 #define SI443X_IRQ_BY_SDO_ON 0b00001000 // 3 3 enabled
266 #define SI443X_GPIO2_DIGITAL_STATE_MASK 0b00000100 // 2 2 digital state mask for: GPIO2
267 #define SI443X_GPIO1_DIGITAL_STATE_MASK 0b00000010 // 1 1 GPIO1
268 #define SI443X_GPIO0_DIGITAL_STATE_MASK 0b00000001 // 0 0 GPIO0
269 
270 // SI443X_REG_ADC_CONFIG
271 #define SI443X_ADC_START 0b10000000 // 7 7 ADC control: start measurement
272 #define SI443X_ADC_RUNNING 0b00000000 // 7 7 measurement in progress
273 #define SI443X_ADC_DONE 0b10000000 // 7 7 done
274 #define SI443X_ADC_SOURCE_TEMPERATURE 0b00000000 // 6 4 ADC source: internal temperature sensor (default)
275 #define SI443X_ADC_SOURCE_GPIO0_SINGLE 0b00010000 // 6 4 single-ended on GPIO0
276 #define SI443X_ADC_SOURCE_GPIO1_SINGLE 0b00100000 // 6 4 single-ended on GPIO1
277 #define SI443X_ADC_SOURCE_GPIO2_SINGLE 0b00110000 // 6 4 single-ended on GPIO2
278 #define SI443X_ADC_SOURCE_GPIO01_DIFF 0b01000000 // 6 4 differential on GPIO0 (+) and GPIO1 (-)
279 #define SI443X_ADC_SOURCE_GPIO12_DIFF 0b01010000 // 6 4 differential on GPIO1 (+) and GPIO2 (-)
280 #define SI443X_ADC_SOURCE_GPIO02_DIFF 0b01100000 // 6 4 differential on GPIO0 (+) and GPIO2 (-)
281 #define SI443X_ADC_SOURCE_GND 0b01110000 // 6 4 GND
282 #define SI443X_ADC_REFERNCE_BAND_GAP 0b00000000 // 3 2 ADC reference: internal bandgap 1.2 V (default)
283 #define SI443X_ADC_REFERNCE_VDD_3 0b00001000 // 3 2 VDD/3
284 #define SI443X_ADC_REFERNCE_VDD_2 0b00001100 // 3 2 VDD/2
285 #define SI443X_ADC_GAIN 0b00000000 // 1 0 ADC amplifier gain
286 
287 // SI443X_REG_ADC_SENSOR_AMP_OFFSET
288 #define SI443X_ADC_OFFSET 0b00000000 // 3 0 ADC offset
289 
290 // SI443X_REG_TEMP_SENSOR_CONTROL
291 #define SI443X_TEMP_SENSOR_RANGE_64_TO_64_C 0b00000000 // 7 6 temperature sensor range: -64 to 64 deg. C, 0.5 deg. C resolution (default)
292 #define SI443X_TEMP_SENSOR_RANGE_64_TO_192_C 0b01000000 // 7 6 -64 to 192 deg. C, 1.0 deg. C resolution
293 #define SI443X_TEMP_SENSOR_RANGE_0_TO_128_C 0b11000000 // 7 6 0 to 128 deg. C, 0.5 deg. C resolution
294 #define SI443X_TEMP_SENSOR_RANGE_40_TO_216_F 0b10000000 // 7 6 -40 to 216 deg. F, 1.0 deg. F resolution
295 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_OFF 0b00000000 // 5 5 Kelvin to Celsius offset: disabled
296 #define SI443X_TEMP_SENSOR_KELVIN_TO_CELSIUS_ON 0b00100000 // 5 5 enabled (default)
297 #define SI443X_TEMP_SENSOR_TRIM_OFF 0b00000000 // 4 4 temperature sensor trim: disabled (default)
298 #define SI443X_TEMP_SENSOR_TRIM_ON 0b00010000 // 4 4 enabled
299 #define SI443X_TEMP_SENSOR_TRIM_VALUE 0b00000000 // 3 0 temperature sensor trim value
300 
301 // SI443X_REG_WAKEUP_TIMER_PERIOD_1
302 #define SI443X_WAKEUP_TIMER_EXPONENT 0b00000011 // 4 0 wakeup timer value exponent
303 
304 // SI443X_REG_WAKEUP_TIMER_PERIOD_2 + SI443X_REG_WAKEUP_TIMER_PERIOD_3
305 #define SI443X_WAKEUP_TIMER_MANTISSA_MSB 0x00 // 7 0 wakeup timer value:
306 #define SI443X_WAKEUP_TIMER_MANTISSA_LSB 0x01 // 7 0 T = (4 * SI443X_WAKEUP_TIMER_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
307 
308 // SI443X_REG_LOW_DC_MODE_DURATION
309 #define SI443X_LOW_DC_MODE_DURATION_MANTISSA 0x01 // 7 0 low duty cycle mode duration: T = (4 * SI443X_LOW_DC_MODE_DURATION_MANTISSA * 2 ^ SI443X_WAKEUP_TIMER_EXPONENT) / 32.768 ms
310 
311 // SI443X_REG_LOW_BATT_DET_THRESHOLD
312 #define SI443X_LOW_BATT_DET_THRESHOLD 0b00010100 // 4 0 low battery detection threshold: Vth = 1.7 + SI443X_LOW_BATT_DET_THRESHOLD * 0.05 V (defaults to 2.7 V)
313 
314 // SI443X_REG_IF_FILTER_BANDWIDTH
315 #define SI443X_BYPASS_DEC_BY_3_OFF 0b00000000 // 7 7 bypass decimate-by-3 stage: disabled (default)
316 #define SI443X_BYPASS_DEC_BY_3_ON 0b10000000 // 7 7 enabled
317 #define SI443X_IF_FILTER_DEC_RATE 0b00000000 // 6 4 IF filter decimation rate
318 #define SI443X_IF_FILTER_COEFF_SET 0b00000001 // 3 0 IF filter coefficient set selection
319 
320 // SI443X_REG_AFC_LOOP_GEARSHIFT_OVERRIDE
321 #define SI443X_AFC_WIDEBAND_OFF 0b00000000 // 7 7 AFC wideband: disabled (default)
322 #define SI443X_AFC_WIDEBAND_ON 0b10000000 // 7 7 enabled
323 #define SI443X_AFC_OFF 0b00000000 // 6 6 AFC: disabled
324 #define SI443X_AFC_ON 0b01000000 // 6 6 enabled (default)
325 #define SI443X_AFC_HIGH_GEAR_SETTING 0b00000000 // 5 3 AFC high gear setting
326 #define SI443X_SECOND_PHASE_BIAS_0_DB 0b00000100 // 2 2 second phase antenna selection bias: 0 dB (default)
327 #define SI443X_SECOND_PHASE_BIAS_1_5_DB 0b00000000 // 2 2 1.5 dB
328 #define SI443X_MOVING_AVERAGE_TAP_8 0b00000010 // 1 1 moving average filter tap length: 8*Tb
329 #define SI443X_MOVING_AVERAGE_TAP_4 0b00000000 // 1 1 4*Tb after first preamble (default)
330 #define SI443X_ZERO_PHASE_RESET_5 0b00000000 // 0 0 reset preamble detector after: 5 zero phases (default)
331 #define SI443X_ZERO_PHASE_RESET_2 0b00000001 // 0 0 3 zero phases
332 
333 // SI443X_REG_AFC_TIMING_CONTROL
334 #define SI443X_SW_ANT_TIMER 0b00000000 // 7 6 number of periods to wait for RSSI to stabilize during antenna switching
335 #define SI443X_SHORT_WAIT 0b00001000 // 5 3 period to wait after AFC correction
336 #define SI443X_ANTENNA_SWITCH_WAIT 0b00000010 // 2 0 antenna switching wait time
337 
338 // SI443X_REG_CLOCK_REC_GEARSHIFT_OVERRIDE
339 #define SI443X_CLOCK_RECOVER_FAST_GEARSHIFT 0b00000000 // 5 3 clock recovery fast gearshift value
340 #define SI443X_CLOCK_RECOVER_SLOW_GEARSHIFT 0b00000011 // 2 0 clock recovery slow gearshift value
341 
342 // SI443X_REG_CLOCK_REC_OVERSAMP_RATIO
343 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_LSB 0b01100100 // 7 0 oversampling rate LSB, defaults to 12.5 clock cycles per bit
344 
345 // SI443X_REG_CLOCK_REC_OFFSET_2
346 #define SI443X_CLOCK_REC_OVERSAMP_RATIO_MSB 0b00000000 // 7 5 oversampling rate MSB, defaults to 12.5 clock cycles per bit
347 #define SI443X_SECOND_PHASE_SKIP_THRESHOLD 0b00000000 // 4 4 skip seconds phase antenna diversity threshold
348 #define SI443X_NCO_OFFSET_MSB 0b00000001 // 3 0 NCO offset MSB
349 
350 // SI443X_REG_CLOCK_REC_OFFSET_1
351 #define SI443X_NCO_OFFSET_MID 0b01000111 // 7 0 NCO offset MID
352 
353 // SI443X_REG_CLOCK_REC_OFFSET_0
354 #define SI443X_NCO_OFFSET_LSB 0b10101110 // 7 0 NCO offset LSB
355 
356 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_1
357 #define SI443X_RX_COMPENSATION_OFF 0b00000000 // 4 4 Rx compensation for high data rate: disabled (default)
358 #define SI443X_RX_COMPENSATION_ON 0b00010000 // 4 4 enabled
359 #define SI443X_CLOCK_REC_GAIN_DOUBLE_OFF 0b00000000 // 3 3 clock recovery gain doubling: disabled (default)
360 #define SI443X_CLOCK_REC_GAIN_DOUBLE_ON 0b00001000 // 3 3 enabled
361 #define SI443X_CLOCK_REC_LOOP_GAIN_MSB 0b00000010 // 2 0 clock recovery timing loop gain MSB
362 
363 // SI443X_REG_CLOCK_REC_TIMING_LOOP_GAIN_0
364 #define SI443X_CLOCK_REC_LOOP_GAIN_LSB 0b10001111 // 7 0 clock recovery timing loop gain LSB
365 
366 // SI443X_REG_RSSI_CLEAR_CHANNEL_THRESHOLD
367 #define SI443X_RSSI_CLEAR_CHANNEL_THRESHOLD 0b00011110 // 7 0 RSSI clear channel interrupt threshold
368 
369 // SI443X_REG_AFC_LIMITER
370 #define SI443X_AFC_LIMITER 0x00 // 7 0 AFC limiter value
371 
372 // SI443X_REG_OOK_COUNTER_1
373 #define SI443X_OOK_FREEZE_OFF 0b00000000 // 5 5 OOK moving average detector freeze: disabled (default)
374 #define SI443X_OOK_FREEZE_ON 0b00100000 // 5 5 enabled
375 #define SI443X_PEAK_DETECTOR_OFF 0b00000000 // 4 4 peak detector: disabled
376 #define SI443X_PEAK_DETECTOR_ON 0b00010000 // 4 4 enabled (default)
377 #define SI443X_OOK_MOVING_AVERAGE_OFF 0b00000000 // 3 3 OOK moving average: disabled
378 #define SI443X_OOK_MOVING_AVERAGE_ON 0b00001000 // 3 3 enabled (default)
379 #define SI443X_OOK_COUNTER_MSB 0b00000000 // 2 0 OOK counter MSB
380 
381 // SI443X_REG_OOK_COUNTER_2
382 #define SI443X_OOK_COUNTER_LSB 0b10111100 // 7 0 OOK counter LSB
383 
384 // SI443X_REG_SLICER_PEAK_HOLD
385 #define SI443X_PEAK_DETECTOR_ATTACK 0b00010000 // 6 4 OOK peak detector attach time
386 #define SI443X_PEAK_DETECTOR_DECAY 0b00001100 // 3 0 OOK peak detector decay time
387 
388 // SI443X_REG_DATA_ACCESS_CONTROL
389 #define SI443X_PACKET_RX_HANDLING_OFF 0b00000000 // 7 7 packet Rx handling: disabled
390 #define SI443X_PACKET_RX_HANDLING_ON 0b10000000 // 7 7 enabled (default)
391 #define SI443X_LSB_FIRST_OFF 0b00000000 // 6 6 LSB first transmission: disabled (default)
392 #define SI443X_LSB_FIRST_ON 0b01000000 // 6 6 enabled
393 #define SI443X_CRC_DATA_ONLY_OFF 0b00000000 // 5 5 CRC calculated only from data fields: disabled (default)
394 #define SI443X_CRC_DATA_ONLY_ON 0b00100000 // 5 5 enabled
395 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_OFF 0b00000000 // 4 4 skip second phase of preamble detection: disabled (default)
396 #define SI443X_SKIP_SECOND_PHASE_PREAMBLE_DET_ON 0b00010000 // 4 4 enabled
397 #define SI443X_PACKET_TX_HANDLING_OFF 0b00000000 // 3 3 packet Tx handling: disabled
398 #define SI443X_PACKET_TX_HANDLING_ON 0b00001000 // 3 3 enabled (default)
399 #define SI443X_CRC_OFF 0b00000000 // 2 2 CRC: disabled
400 #define SI443X_CRC_ON 0b00000100 // 2 2 enabled (default)
401 #define SI443X_CRC_CCITT 0b00000000 // 1 0 CRC type: CCITT
402 #define SI443X_CRC_IBM_CRC16 0b00000001 // 1 0 IBM CRC-16 (default)
403 #define SI443X_CRC_IEC16 0b00000010 // 1 0 IEC-16
404 #define SI443X_CRC_BIACHEVA 0b00000011 // 1 0 Biacheva
405 
406 // SI443X_REG_EZMAC_STATUS
407 #define SI443X_CRC_ALL_ONE 0b01000000 // 6 6 last received CRC was all ones
408 #define SI443X_PACKET_SEARCHING 0b00100000 // 5 5 radio is searching for a valid packet
409 #define SI443X_PACKET_RECEIVING 0b00010000 // 4 4 radio is currently receiving packet
410 #define SI443X_VALID_PACKET_RECEIVED 0b00001000 // 3 3 valid packet was received
411 #define SI443X_CRC_ERROR 0b00000100 // 2 2 CRC check failed
412 #define SI443X_PACKET_TRANSMITTING 0b00000010 // 1 1 radio is currently transmitting packet
413 #define SI443X_PACKET_SENT 0b00000001 // 0 0 packet sent
414 
415 // SI443X_REG_HEADER_CONTROL_1
416 #define SI443X_BROADCAST_ADDR_CHECK_NONE 0b00000000 // 7 4 broadcast address check: none (default)
417 #define SI443X_BROADCAST_ADDR_CHECK_BYTE0 0b00010000 // 7 4 on byte 0
418 #define SI443X_BROADCAST_ADDR_CHECK_BYTE1 0b00100000 // 7 4 on byte 1
419 #define SI443X_BROADCAST_ADDR_CHECK_BYTE2 0b01000000 // 7 4 on byte 2
420 #define SI443X_BROADCAST_ADDR_CHECK_BYTE3 0b10000000 // 7 4 on byte 3
421 #define SI443X_RECEIVED_HEADER_CHECK_NONE 0b00000000 // 3 0 received header check: none
422 #define SI443X_RECEIVED_HEADER_CHECK_BYTE0 0b00000001 // 3 0 on byte 0
423 #define SI443X_RECEIVED_HEADER_CHECK_BYTE1 0b00000010 // 3 0 on byte 1
424 #define SI443X_RECEIVED_HEADER_CHECK_BYTE2 0b00000100 // 3 0 on byte 2 (default)
425 #define SI443X_RECEIVED_HEADER_CHECK_BYTE3 0b00001000 // 3 0 on byte 3 (default)
426 
427 // SI443X_REG_HEADER_CONTROL_2
428 #define SI443X_SYNC_WORD_TIMEOUT_OFF 0b00000000 // 7 7 ignore timeout period when searching for sync word: disabled (default)
429 #define SI443X_SYNC_WORD_TIMEOUT_ON 0b10000000 // 7 7 enabled
430 #define SI443X_HEADER_LENGTH_HEADER_NONE 0b00000000 // 6 4 header length: none
431 #define SI443X_HEADER_LENGTH_HEADER_3 0b00010000 // 6 4 header 3
432 #define SI443X_HEADER_LENGTH_HEADER_32 0b00100000 // 6 4 header 3 and 2
433 #define SI443X_HEADER_LENGTH_HEADER_321 0b00110000 // 6 4 header 3, 2 and 1 (default)
434 #define SI443X_HEADER_LENGTH_HEADER_3210 0b01000000 // 6 4 header 3, 2, 1, and 0
435 #define SI443X_FIXED_PACKET_LENGTH_OFF 0b00000000 // 3 3 fixed packet length mode: disabled (default)
436 #define SI443X_FIXED_PACKET_LENGTH_ON 0b00001000 // 3 3 enabled
437 #define SI443X_SYNC_LENGTH_SYNC_3 0b00000000 // 2 1 sync word length: sync 3
438 #define SI443X_SYNC_LENGTH_SYNC_32 0b00000010 // 2 1 sync 3 and 2 (default)
439 #define SI443X_SYNC_LENGTH_SYNC_321 0b00000100 // 2 1 sync 3, 2 and 1
440 #define SI443X_SYNC_LENGTH_SYNC_3210 0b00000110 // 2 1 sync 3, 2, 1 and 0
441 #define SI443X_PREAMBLE_LENGTH_MSB 0b00000000 // 0 0 preamble length MSB
442 
443 // SI443X_REG_PREAMBLE_LENGTH
444 #define SI443X_PREAMBLE_LENGTH_LSB 0b00001000 // 0 0 preamble length LSB, defaults to 32 bits
445 
446 // SI443X_REG_PREAMBLE_DET_CONTROL
447 #define SI443X_PREAMBLE_DET_THRESHOLD 0b00101000 // 7 3 number of 4-bit nibbles in valid preamble, defaults to 20 bits
448 #define SI443X_RSSI_OFFSET 0b00000010 // 2 0 RSSI calculation offset, defaults to +8 dB
449 
450 // SI443X_REG_SYNC_WORD_3 - SI443X_REG_SYNC_WORD_0
451 #define SI443X_SYNC_WORD_3 0x2D // 7 0 sync word: 4th byte (MSB)
452 #define SI443X_SYNC_WORD_2 0xD4 // 7 0 3rd byte
453 #define SI443X_SYNC_WORD_1 0x00 // 7 0 2nd byte
454 #define SI443X_SYNC_WORD_0 0x00 // 7 0 1st byte (LSB)
455 
456 // SI443X_REG_CHANNEL_FILTER_COEFF
457 #define SI443X_INVALID_PREAMBLE_THRESHOLD 0b00000000 // 7 4 invalid preamble threshold in nibbles
458 
459 // SI443X_REG_XOSC_CONTROL_TEST
460 #define SI443X_STATE_LOW_POWER 0b00000000 // 7 5 chip power state: low power
461 #define SI443X_STATE_READY 0b00100000 // 7 5 ready
462 #define SI443X_STATE_TUNE 0b01100000 // 7 5 tune
463 #define SI443X_STATE_TX 0b01000000 // 7 5 Tx
464 #define SI443X_STATE_RX 0b11100000 // 7 5 Rx
465 
466 // SI443X_REG_AGC_OVERRIDE_1
467 #define SI443X_AGC_GAIN_INCREASE_OFF 0b00000000 // 6 6 AGC gain increase override: disabled (default)
468 #define SI443X_AGC_GAIN_INCREASE_ON 0b01000000 // 6 6 enabled
469 #define SI443X_AGC_OFF 0b00000000 // 5 5 AGC loop: disabled
470 #define SI443X_AGC_ON 0b00100000 // 5 5 enabled (default)
471 #define SI443X_LNA_GAIN_MIN 0b00000000 // 4 4 LNA gain select: 5 dB (default)
472 #define SI443X_LNA_GAIN_MAX 0b00010000 // 4 4 25 dB
473 #define SI443X_PGA_GAIN_OVERRIDE 0b00000000 // 3 0 PGA gain override, gain = SI443X_PGA_GAIN_OVERRIDE * 3 dB
474 
475 // SI443X_REG_TX_POWER
476 #define SI443X_LNA_SWITCH_OFF 0b00000000 // 3 3 LNA switch control: disabled
477 #define SI443X_LNA_SWITCH_ON 0b00001000 // 3 3 enabled (default)
478 #define SI443X_OUTPUT_POWER 0b00000000 // 2 0 output power in 3 dB steps, 0 is chip min, 7 is chip max
479 
480 // SI443X_REG_TX_DATA_RATE_1 + SI443X_REG_TX_DATA_RATE_0
481 #define SI443X_DATA_RATE_MSB 0x0A // 7 0 data rate: DR = 10^6 * (SI443X_DATA_RATE / 2^16) in high data rate mode or
482 #define SI443X_DATA_RATE_LSB 0x3D // 7 0 DR = 10^6 * (SI443X_DATA_RATE / 2^21) in low data rate mode (defaults to 40 kbps)
483 
484 // SI443X_REG_MODULATION_MODE_CONTROL_1
485 #define SI443X_HIGH_DATA_RATE_MODE 0b00000000 // 5 5 data rate: above 30 kbps (default)
486 #define SI443X_LOW_DATA_RATE_MODE 0b00100000 // 5 5 below 30 kbps
487 #define SI443X_PACKET_HANDLER_POWER_DOWN_OFF 0b00000000 // 4 4 power off packet handler in low power mode: disabled (default)
488 #define SI443X_PACKET_HANDLER_POWER_DOWN_ON 0b00010000 // 4 4 enabled
489 #define SI443X_MANCHESTER_PREAMBLE_POL_LOW 0b00000000 // 3 3 preamble polarity in Manchester mode: low
490 #define SI443X_MANCHESTER_PREAMBLE_POL_HIGH 0b00001000 // 3 3 high (default)
491 #define SI443X_MANCHESTER_INVERTED_OFF 0b00000000 // 2 2 inverted Manchester encoding: disabled
492 #define SI443X_MANCHESTER_INVERTED_ON 0b00000100 // 2 2 enabled (default)
493 #define SI443X_MANCHESTER_OFF 0b00000000 // 1 1 Manchester encoding: disabled (default)
494 #define SI443X_MANCHESTER_ON 0b00000010 // 1 1 enabled
495 #define SI443X_WHITENING_OFF 0b00000000 // 0 0 data whitening: disabled (default)
496 #define SI443X_WHITENING_ON 0b00000001 // 0 0 enabled
497 
498 // SI443X_REG_MODULATION_MODE_CONTROL_2
499 #define SI443X_TX_DATA_CLOCK_NONE 0b00000000 // 7 6 Tx data clock: disabled (default)
500 #define SI443X_TX_DATA_CLOCK_GPIO 0b01000000 // 7 6 GPIO pin
501 #define SI443X_TX_DATA_CLOCK_SDI 0b10000000 // 7 6 SDI pin
502 #define SI443X_TX_DATA_CLOCK_NIRQ 0b11000000 // 7 6 nIRQ pin
503 #define SI443X_TX_DATA_SOURCE_GPIO 0b00000000 // 5 4 Tx data source in direct mode: GPIO pin (default)
504 #define SI443X_TX_DATA_SOURCE_SDI 0b00010000 // 5 4 SDI pin
505 #define SI443X_TX_DATA_SOURCE_FIFO 0b00100000 // 5 4 FIFO
506 #define SI443X_TX_DATA_SOURCE_PN9 0b00110000 // 5 4 PN9 internal
507 #define SI443X_TX_RX_INVERTED_OFF 0b00000000 // 3 3 Tx/Rx data inverted: disabled (default)
508 #define SI443X_TX_RX_INVERTED_ON 0b00001000 // 3 3 enabled
509 #define SI443X_FREQUENCY_DEVIATION_MSB 0b00000000 // 2 2 frequency deviation MSB
510 #define SI443X_MODULATION_NONE 0b00000000 // 1 0 modulation type: unmodulated carrier (default)
511 #define SI443X_MODULATION_OOK 0b00000001 // 1 0 OOK
512 #define SI443X_MODULATION_FSK 0b00000010 // 1 0 FSK
513 #define SI443X_MODULATION_GFSK 0b00000011 // 1 0 GFSK
514 
515 // SI443X_REG_FREQUENCY_DEVIATION
516 #define SI443X_FREQUENCY_DEVIATION_LSB 0b00100000 // 7 0 frequency deviation LSB, Fd = 625 Hz * SI443X_FREQUENCY_DEVIATION, defaults to 20 kHz
517 
518 // SI443X_REG_FREQUENCY_OFFSET_1 + SI443X_REG_FREQUENCY_OFFSET_2
519 #define SI443X_FREQUENCY_OFFSET_MSB 0x00 // 7 0 frequency offset:
520 #define SI443X_FREQUENCY_OFFSET_LSB 0x00 // 1 0 Foff = 156.25 Hz * (SI443X_BAND_SELECT + 1) * SI443X_FREQUENCY_OFFSET, defaults to 156.25 Hz
521 
522 // SI443X_REG_FREQUENCY_BAND_SELECT
523 #define SI443X_SIDE_BAND_SELECT_LOW 0b00000000 // 6 6 Rx LO tuning: below channel frequency (default)
524 #define SI443X_SIDE_BAND_SELECT_HIGH 0b01000000 // 6 6 above channel frequency
525 #define SI443X_BAND_SELECT_LOW 0b00000000 // 5 5 band select: low, 240 - 479.9 MHz
526 #define SI443X_BAND_SELECT_HIGH 0b00100000 // 5 5 high, 480 - 960 MHz (default)
527 #define SI443X_FREQUENCY_BAND_SELECT 0b00010101 // 4 0 frequency band select
528 
529 // SI443X_REG_NOM_CARRIER_FREQUENCY_1 + SI443X_REG_NOM_CARRIER_FREQUENCY_0
530 #define SI443X_NOM_CARRIER_FREQUENCY_MSB 0b10111011 // 7 0 nominal carrier frequency:
531 #define SI443X_NOM_CARRIER_FREQUENCY_LSB 0b10000000 // 7 0 Fc = (SI443X_BAND_SELECT + 1)*10*(SI443X_FREQUENCY_BAND_SELECT + 24) + (SI443X_NOM_CARRIER_FREQUENCY - SI443X_FREQUENCY_OFFSET)/6400 [MHz]
532 
533 // SI443X_REG_FREQUENCY_HOPPING_CHANNEL_SEL
534 #define SI443X_FREQUENCY_HOPPING_CHANNEL 0x00 // 7 0 frequency hopping channel number
535 
536 // SI443X_REG_FREQUENCY_HOPPING_STEP_SIZE
537 #define SI443X_FREQUENCY_HOPPING_STEP_SIZE 0x00 // 7 0 frequency hopping step size
538 
539 // SI443X_REG_TX_FIFO_CONTROL_1
540 #define SI443X_TX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Tx FIFO almost full threshold
541 
542 // SI443X_REG_TX_FIFO_CONTROL_2
543 #define SI443X_TX_FIFO_ALMOST_EMPTY_THRESHOLD 0x04 // 5 0 Tx FIFO almost full threshold
544 
545 // SI443X_REG_RX_FIFO_CONTROL
546 #define SI443X_RX_FIFO_ALMOST_FULL_THRESHOLD 0x37 // 5 0 Rx FIFO almost full threshold
547 
554 class Si443x: public PhysicalLayer {
555  public:
556  // introduce PhysicalLayer overloads
557  using PhysicalLayer::transmit;
558  using PhysicalLayer::receive;
559  using PhysicalLayer::startTransmit;
560  using PhysicalLayer::readData;
561 
562  // constructor
563 
569  Si443x(Module* mod);
570 
571  // basic methods
572 
586  int16_t begin(float br, float freqDev, float rxBw, uint8_t preambleLen);
587 
591  void reset();
592 
605  int16_t transmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
606 
617  int16_t receive(uint8_t* data, size_t len) override;
618 
625  int16_t sleep();
626 
632  int16_t standby() override;
633 
641  int16_t transmitDirect(uint32_t frf = 0) override;
642 
648  int16_t receiveDirect() override;
649 
655  int16_t packetMode();
656 
657  // interrupt methods
658 
664  void setIrqAction(void (*func)(void));
665 
669  void clearIrqAction();
670 
682  int16_t startTransmit(uint8_t* data, size_t len, uint8_t addr = 0) override;
683 
689  int16_t startReceive();
690 
700  int16_t readData(uint8_t* data, size_t len) override;
701 
702  // configuration methods
703 
711  int16_t setBitRate(float br);
712 
720  int16_t setFrequencyDeviation(float freqDev) override;
721 
729  int16_t setRxBandwidth(float rxBw);
730 
738  int16_t setSyncWord(uint8_t* syncWord, size_t len);
739 
747  int16_t setPreambleLength(uint8_t preambleLen);
748 
756  size_t getPacketLength(bool update = true) override;
757 
766  int16_t setEncoding(uint8_t encoding) override;
767 
776  int16_t setDataShaping(uint8_t sh) override;
777 
786  void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn);
787 
793  uint8_t random();
794 
800  int16_t getChipVersion();
801 
802 #ifndef RADIOLIB_GODMODE
803  protected:
804 #endif
805  Module* _mod;
806 
807  float _br = 0;
808  float _freqDev = 0;
809  float _freq = 0;
810 
811  size_t _packetLength = 0;
812  bool _packetLengthQueried = false;
813 
814  int16_t setFrequencyRaw(float newFreq);
815 
816 #ifndef RADIOLIB_GODMODE
817  private:
818 #endif
819  bool findChip();
820  void clearIRQFlags();
821  int16_t config();
822  int16_t updateClockRecovery();
823  int16_t directMode();
824 };
825 
826 #endif
827 
828 #endif
Si443x::setRxBandwidth
int16_t setRxBandwidth(float rxBw)
Sets receiver bandwidth. Allowed values range from 2.6 to 620.7 kHz.
Definition: Si443x.cpp:364
Si443x::startReceive
int16_t startReceive()
Interrupt-driven receive method. IRQ will be activated when full valid packet is received.
Definition: Si443x.cpp:254
Si443x::setDataShaping
int16_t setDataShaping(uint8_t sh) override
Sets Gaussian filter bandwidth-time product that will be used for data shaping. Only available in FSK...
Definition: Si443x.cpp:533
PhysicalLayer::startTransmit
int16_t startTransmit(String &str, uint8_t addr=0)
Interrupt-driven Arduino String transmit method. Unlike the standard transmit method, this one is non-blocking. Interrupt pin will be activated when transmission finishes.
Definition: PhysicalLayer.cpp:49
+
Si443x::getChipVersion
int16_t getChipVersion()
Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and work...
Definition: Si443x.cpp:575
Si443x::setRfSwitchPins
void setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)
Some modules contain external RF switch controlled by two pins. This function gives RadioLib control ...
Definition: Si443x.cpp:552
Si443x::setSyncWord
int16_t setSyncWord(uint8_t *syncWord, size_t len)
Sets sync word. Up to 4 bytes can be set as sync word.
Definition: Si443x.cpp:471
Si443x::receiveDirect
int16_t receiveDirect() override
Enables direct reception mode. While in direct mode, the module will not be able to transmit or recei...
Definition: Si443x.cpp:189
diff --git a/class_c_c1101-members.html b/class_c_c1101-members.html index a6a8c8bf..e9291403 100644 --- a/class_c_c1101-members.html +++ b/class_c_c1101-members.html @@ -95,48 +95,49 @@ $(document).ready(function(){initNavTree('class_c_c1101.html','');}); disableSyncWordFiltering(bool requireCarrierSense=false)CC1101 enableSyncWordFiltering(uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 fixedPacketLengthMode(uint8_t len=CC1101_MAX_PACKET_LENGTH)CC1101 - getFreqStep() constPhysicalLayer - getLQI() constCC1101 - getPacketLength(bool update=true) overrideCC1101virtual - getRSSI() constCC1101 - packetMode()CC1101 - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()CC1101virtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideCC1101virtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideCC1101virtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideCC1101virtual - setBitRate(float br)CC1101 - setCrcFiltering(bool crcOn=true)CC1101 - setDataShaping(uint8_t sh) overrideCC1101virtual - setEncoding(uint8_t encoding) overrideCC1101virtual - setFrequency(float freq)CC1101 - setFrequencyDeviation(float freqDev) overrideCC1101virtual - setGdo0Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)CC1101 - setGdo2Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)CC1101 - setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs=0)CC1101 - setOOK(bool enableOOK)CC1101 - setOutputPower(int8_t power)CC1101 - setPreambleLength(uint8_t preambleLength)CC1101 - setPromiscuousMode(bool promiscuous=true)CC1101 - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)CC1101 - setRxBandwidth(float rxBw)CC1101 - setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 - setSyncWord(uint8_t *syncWord, uint8_t len, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 - standby() overrideCC1101virtual - startReceive()CC1101 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideCC1101virtual - variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)CC1101 + getChipVersion()CC1101 + getFreqStep() constPhysicalLayer + getLQI() constCC1101 + getPacketLength(bool update=true) overrideCC1101virtual + getRSSI() constCC1101 + packetMode()CC1101 + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()CC1101virtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideCC1101virtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideCC1101virtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideCC1101virtual + setBitRate(float br)CC1101 + setCrcFiltering(bool crcOn=true)CC1101 + setDataShaping(uint8_t sh) overrideCC1101virtual + setEncoding(uint8_t encoding) overrideCC1101virtual + setFrequency(float freq)CC1101 + setFrequencyDeviation(float freqDev) overrideCC1101virtual + setGdo0Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)CC1101 + setGdo2Action(void(*func)(void), RADIOLIB_INTERRUPT_STATUS dir=FALLING)CC1101 + setNodeAddress(uint8_t nodeAddr, uint8_t numBroadcastAddrs=0)CC1101 + setOOK(bool enableOOK)CC1101 + setOutputPower(int8_t power)CC1101 + setPreambleLength(uint8_t preambleLength)CC1101 + setPromiscuousMode(bool promiscuous=true)CC1101 + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)CC1101 + setRxBandwidth(float rxBw)CC1101 + setSyncWord(uint8_t syncH, uint8_t syncL, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 + setSyncWord(uint8_t *syncWord, uint8_t len, uint8_t maxErrBits=0, bool requireCarrierSense=false)CC1101 + standby() overrideCC1101virtual + startReceive()CC1101 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideCC1101virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideCC1101virtual + variablePacketLengthMode(uint8_t maxLen=CC1101_MAX_PACKET_LENGTH)CC1101
diff --git a/class_c_c1101.html b/class_c_c1101.html index f734af5d..2d0c0d57 100644 --- a/class_c_c1101.html +++ b/class_c_c1101.html @@ -224,6 +224,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return CC1101_VERSION_LEGACY (0x04) or CC1101_VERSION_CURRENT (0x14) if CC1101 is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
@@ -465,6 +468,26 @@ void 
Returns
Status Codes
+
+
+ +

◆ getChipVersion()

+ +
+
+ + + + + + + +
int16_t CC1101::getChipVersion ()
+
+ +

Read version SPI register. Should return CC1101_VERSION_LEGACY (0x04) or CC1101_VERSION_CURRENT (0x14) if CC1101 is connected and working.

+
Returns
Version register contents or Status Codes
+
diff --git a/class_c_c1101.js b/class_c_c1101.js index 2979f88e..dedde23b 100644 --- a/class_c_c1101.js +++ b/class_c_c1101.js @@ -8,6 +8,7 @@ var class_c_c1101 = [ "disableSyncWordFiltering", "class_c_c1101.html#a4f2dc4176b62a0636636088e31b8e85b", null ], [ "enableSyncWordFiltering", "class_c_c1101.html#a6fe55d0217bf5218865198ef8d6fdab4", null ], [ "fixedPacketLengthMode", "class_c_c1101.html#a9335f1d5ccab7aab2357449002203810", null ], + [ "getChipVersion", "class_c_c1101.html#a2a4c6e622dffd2788d8ac52d708b0705", null ], [ "getLQI", "class_c_c1101.html#a59ca9e8956e308159949638bf327e5fb", null ], [ "getPacketLength", "class_c_c1101.html#a122281f6a915b77ee9dafc9926e731a0", null ], [ "getRSSI", "class_c_c1101.html#a48fd0452d6f7d7d51ea7d23b2dbe1551", null ], diff --git a/class_r_f69-members.html b/class_r_f69-members.html index 9739c683..c994414f 100644 --- a/class_r_f69-members.html +++ b/class_r_f69-members.html @@ -96,52 +96,53 @@ $(document).ready(function(){initNavTree('class_r_f69.html','');}); enableAES()RF69 enableSyncWordFiltering(uint8_t maxErrBits=0)RF69 fixedPacketLengthMode(uint8_t len=RF69_MAX_PACKET_LENGTH)RF69 - getFreqStep() constPhysicalLayer - getPacketLength(bool update=true) overrideRF69virtual - getRSSI()RF69 - getTemperature()RF69 - packetMode()RF69 - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()RF69virtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideRF69virtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideRF69virtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideRF69virtual - reset()RF69 - RF69(Module *module)RF69 - setAESKey(uint8_t *key)RF69 - setAmbientTemperature(int16_t tempAmbient)RF69 - setBitRate(float br)RF69 - setBroadcastAddress(uint8_t broadAddr)RF69 - setCrcFiltering(bool crcOn=true)RF69 - setDataShaping(uint8_t sh) overrideRF69virtual - setDio0Action(void(*func)(void))RF69 - setDio1Action(void(*func)(void))RF69 - setEncoding(uint8_t encoding) overrideRF69virtual - setFrequency(float freq)RF69 - setFrequencyDeviation(float freqDev) overrideRF69virtual - setNodeAddress(uint8_t nodeAddr)RF69 - setOutputPower(int8_t power, bool highPower=false)RF69 - setPreambleLength(uint8_t preambleLen)RF69 - setPromiscuousMode(bool promiscuous=true)RF69 - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)RF69 - setRxBandwidth(float rxBw)RF69 - setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 - sleep()RF69 - standby() overrideRF69virtual - startReceive()RF69 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideRF69virtual - variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 + getChipVersion()RF69 + getFreqStep() constPhysicalLayer + getPacketLength(bool update=true) overrideRF69virtual + getRSSI()RF69 + getTemperature()RF69 + packetMode()RF69 + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()RF69virtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideRF69virtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideRF69virtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideRF69virtual + reset()RF69 + RF69(Module *module)RF69 + setAESKey(uint8_t *key)RF69 + setAmbientTemperature(int16_t tempAmbient)RF69 + setBitRate(float br)RF69 + setBroadcastAddress(uint8_t broadAddr)RF69 + setCrcFiltering(bool crcOn=true)RF69 + setDataShaping(uint8_t sh) overrideRF69virtual + setDio0Action(void(*func)(void))RF69 + setDio1Action(void(*func)(void))RF69 + setEncoding(uint8_t encoding) overrideRF69virtual + setFrequency(float freq)RF69 + setFrequencyDeviation(float freqDev) overrideRF69virtual + setNodeAddress(uint8_t nodeAddr)RF69 + setOutputPower(int8_t power, bool highPower=false)RF69 + setPreambleLength(uint8_t preambleLen)RF69 + setPromiscuousMode(bool promiscuous=true)RF69 + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)RF69 + setRxBandwidth(float rxBw)RF69 + setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 + sleep()RF69 + standby() overrideRF69virtual + startReceive()RF69 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideRF69virtual + variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69
diff --git a/class_r_f69.html b/class_r_f69.html index 507e0850..9a37097a 100644 --- a/class_r_f69.html +++ b/class_r_f69.html @@ -241,6 +241,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
@@ -504,6 +507,26 @@ void 
Returns
Status Codes
+
+ + +

◆ getChipVersion()

+ +
+
+ + + + + + + +
int16_t RF69::getChipVersion ()
+
+ +

Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working.

+
Returns
Version register contents or Status Codes
+
diff --git a/class_r_f69.js b/class_r_f69.js index 54746162..2e1f2470 100644 --- a/class_r_f69.js +++ b/class_r_f69.js @@ -10,6 +10,7 @@ var class_r_f69 = [ "enableAES", "class_r_f69.html#a1fd4609f419d8b0213ee39b05dd40b69", null ], [ "enableSyncWordFiltering", "class_r_f69.html#a643a711bcb4b7771a7ab1f457e61a417", null ], [ "fixedPacketLengthMode", "class_r_f69.html#a4c9dcbd7e44bc5e46d9f10ae276a0c5f", null ], + [ "getChipVersion", "class_r_f69.html#a0c30202b2d52eb32f43066bc0f938638", null ], [ "getPacketLength", "class_r_f69.html#a86a080086c0228d23e2cb77d2b1915c1", null ], [ "getRSSI", "class_r_f69.html#ac4fc3f2b178ef08caec3a9f548f44cd7", null ], [ "getTemperature", "class_r_f69.html#a0526ce6ea3722fd258f96d9677a60853", null ], diff --git a/class_r_f_m95-members.html b/class_r_f_m95-members.html index 0a9b456e..af2636f4 100644 --- a/class_r_f_m95-members.html +++ b/class_r_f_m95-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_r_f_m95.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - RFM95(Module *mod)RFM95 - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)RFM95 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1278 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + RFM95(Module *mod)RFM95 + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)RFM95 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1278 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_r_f_m95.html b/class_r_f_m95.html index 65114ec3..a50d4a9b 100644 --- a/class_r_f_m95.html +++ b/class_r_f_m95.html @@ -295,6 +295,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_r_f_m96-members.html b/class_r_f_m96-members.html index a98e0590..49f6c062 100644 --- a/class_r_f_m96-members.html +++ b/class_r_f_m96-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_r_f_m96.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - RFM96(Module *mod)RFM96 - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)RFM96 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1278 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + RFM96(Module *mod)RFM96 + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)RFM96 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1278 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_r_f_m96.html b/class_r_f_m96.html index 2c7fada3..3be04d57 100644 --- a/class_r_f_m96.html +++ b/class_r_f_m96.html @@ -294,6 +294,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_r_f_m97-members.html b/class_r_f_m97-members.html index 94e102c9..88e0658a 100644 --- a/class_r_f_m97-members.html +++ b/class_r_f_m97-members.html @@ -97,67 +97,68 @@ $(document).ready(function(){initNavTree('class_r_f_m97.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - RFM95(Module *mod)RFM95 - RFM97(Module *mod)RFM97 - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)RFM95 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)RFM97 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + RFM95(Module *mod)RFM95 + RFM97(Module *mod)RFM97 + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)RFM95 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)RFM97 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_r_f_m97.html b/class_r_f_m97.html index f18064c9..750a4010 100644 --- a/class_r_f_m97.html +++ b/class_r_f_m97.html @@ -302,6 +302,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1231-members.html b/class_s_x1231-members.html index 4edfde76..6d8b163b 100644 --- a/class_s_x1231-members.html +++ b/class_s_x1231-members.html @@ -96,53 +96,54 @@ $(document).ready(function(){initNavTree('class_s_x1231.html','');}); enableAES()RF69 enableSyncWordFiltering(uint8_t maxErrBits=0)RF69 fixedPacketLengthMode(uint8_t len=RF69_MAX_PACKET_LENGTH)RF69 - getFreqStep() constPhysicalLayer - getPacketLength(bool update=true) overrideRF69virtual - getRSSI()RF69 - getTemperature()RF69 - packetMode()RF69 - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()RF69virtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideRF69virtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideRF69virtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideRF69virtual - reset()RF69 - RF69(Module *module)RF69 - setAESKey(uint8_t *key)RF69 - setAmbientTemperature(int16_t tempAmbient)RF69 - setBitRate(float br)RF69 - setBroadcastAddress(uint8_t broadAddr)RF69 - setCrcFiltering(bool crcOn=true)RF69 - setDataShaping(uint8_t sh) overrideRF69virtual - setDio0Action(void(*func)(void))RF69 - setDio1Action(void(*func)(void))RF69 - setEncoding(uint8_t encoding) overrideRF69virtual - setFrequency(float freq)RF69 - setFrequencyDeviation(float freqDev) overrideRF69virtual - setNodeAddress(uint8_t nodeAddr)RF69 - setOutputPower(int8_t power, bool highPower=false)RF69 - setPreambleLength(uint8_t preambleLen)RF69 - setPromiscuousMode(bool promiscuous=true)RF69 - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)RF69 - setRxBandwidth(float rxBw)RF69 - setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 - sleep()RF69 - standby() overrideRF69virtual - startReceive()RF69 - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1231(Module *mod)SX1231 - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideRF69virtual - variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 + getChipVersion()RF69 + getFreqStep() constPhysicalLayer + getPacketLength(bool update=true) overrideRF69virtual + getRSSI()RF69 + getTemperature()RF69 + packetMode()RF69 + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()RF69virtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideRF69virtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideRF69virtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideRF69virtual + reset()RF69 + RF69(Module *module)RF69 + setAESKey(uint8_t *key)RF69 + setAmbientTemperature(int16_t tempAmbient)RF69 + setBitRate(float br)RF69 + setBroadcastAddress(uint8_t broadAddr)RF69 + setCrcFiltering(bool crcOn=true)RF69 + setDataShaping(uint8_t sh) overrideRF69virtual + setDio0Action(void(*func)(void))RF69 + setDio1Action(void(*func)(void))RF69 + setEncoding(uint8_t encoding) overrideRF69virtual + setFrequency(float freq)RF69 + setFrequencyDeviation(float freqDev) overrideRF69virtual + setNodeAddress(uint8_t nodeAddr)RF69 + setOutputPower(int8_t power, bool highPower=false)RF69 + setPreambleLength(uint8_t preambleLen)RF69 + setPromiscuousMode(bool promiscuous=true)RF69 + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)RF69 + setRxBandwidth(float rxBw)RF69 + setSyncWord(uint8_t *syncWord, size_t len, uint8_t maxErrBits=0)RF69 + sleep()RF69 + standby() overrideRF69virtual + startReceive()RF69 + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1231(Module *mod)SX1231 + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideRF69virtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideRF69virtual + variablePacketLengthMode(uint8_t maxLen=RF69_MAX_PACKET_LENGTH)RF69 diff --git a/class_s_x1231.html b/class_s_x1231.html index 849432d9..92e25aa9 100644 --- a/class_s_x1231.html +++ b/class_s_x1231.html @@ -248,6 +248,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return RF69_CHIP_VERSION (0x24) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1272-members.html b/class_s_x1272-members.html index 2f0d8542..1cae2f1b 100644 --- a/class_s_x1272-members.html +++ b/class_s_x1272-members.html @@ -97,65 +97,66 @@ $(document).ready(function(){initNavTree('class_s_x1272.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1272 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1272 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1272virtual - scanChannel()SX127x - setBandwidth(float bw)SX1272 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1272 - setCRC(bool enableCRC)SX1272 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1272virtual - setDataShapingOOK(uint8_t sh)SX1272 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1272 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1272 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1272 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1272 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1272(Module *mod)SX1272 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1272 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1272virtual + scanChannel()SX127x + setBandwidth(float bw)SX1272 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1272 + setCRC(bool enableCRC)SX1272 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1272virtual + setDataShapingOOK(uint8_t sh)SX1272 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1272 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1272 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1272 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1272 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1272(Module *mod)SX1272 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1272.html b/class_s_x1272.html index 2e39c832..f3caac06 100644 --- a/class_s_x1272.html +++ b/class_s_x1272.html @@ -284,6 +284,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1273-members.html b/class_s_x1273-members.html index 003162ff..f8199683 100644 --- a/class_s_x1273-members.html +++ b/class_s_x1273-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_s_x1273.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1272 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1272 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1272virtual - scanChannel()SX127x - setBandwidth(float bw)SX1272 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1272 - setCRC(bool enableCRC)SX1272 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1272virtual - setDataShapingOOK(uint8_t sh)SX1272 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1272 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1272 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1272 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1273 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1272(Module *mod)SX1272 - SX1273(Module *mod)SX1273 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1272 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1272virtual + scanChannel()SX127x + setBandwidth(float bw)SX1272 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1272 + setCRC(bool enableCRC)SX1272 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1272virtual + setDataShapingOOK(uint8_t sh)SX1272 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1272 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1272 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1272 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1273 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1272(Module *mod)SX1272 + SX1273(Module *mod)SX1273 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1273.html b/class_s_x1273.html index 8a0acd15..d10fbeed 100644 --- a/class_s_x1273.html +++ b/class_s_x1273.html @@ -294,6 +294,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1276-members.html b/class_s_x1276-members.html index c684109f..4cc6e49c 100644 --- a/class_s_x1276-members.html +++ b/class_s_x1276-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_s_x1276.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1276 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1278 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1276(Module *mod)SX1276 - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1276 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1278 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1276(Module *mod)SX1276 + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1276.html b/class_s_x1276.html index c7308e55..fca98228 100644 --- a/class_s_x1276.html +++ b/class_s_x1276.html @@ -297,6 +297,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1277-members.html b/class_s_x1277-members.html index 336b344b..d9a21dc0 100644 --- a/class_s_x1277-members.html +++ b/class_s_x1277-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_s_x1277.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1277 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1277 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1277(Module *mod)SX1277 - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1277 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1277 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1277(Module *mod)SX1277 + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1277.html b/class_s_x1277.html index 99de6587..16c71941 100644 --- a/class_s_x1277.html +++ b/class_s_x1277.html @@ -300,6 +300,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1278-members.html b/class_s_x1278-members.html index eae65475..bcf39526 100644 --- a/class_s_x1278-members.html +++ b/class_s_x1278-members.html @@ -97,65 +97,66 @@ $(document).ready(function(){initNavTree('class_s_x1278.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1278 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1278 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1278 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1278 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1278.html b/class_s_x1278.html index a1e9933c..d190f1fc 100644 --- a/class_s_x1278.html +++ b/class_s_x1278.html @@ -289,6 +289,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x1279-members.html b/class_s_x1279-members.html index 15586228..ee19d22f 100644 --- a/class_s_x1279-members.html +++ b/class_s_x1279-members.html @@ -97,66 +97,67 @@ $(document).ready(function(){initNavTree('class_s_x1279.html','');}); disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x forceLDRO(bool enable)SX1278 - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getRSSI()SX1278 - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset() overrideSX1278virtual - scanChannel()SX127x - setBandwidth(float bw)SX1278 - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCodingRate(uint8_t cr)SX1278 - setCRC(bool enableCRC)SX1278 - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh) overrideSX1278virtual - setDataShapingOOK(uint8_t sh)SX1278 - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequency(float freq)SX1279 - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setGain(uint8_t gain)SX1278 - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setOutputPower(int8_t power)SX1278 - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSpreadingFactor(uint8_t sf)SX1278 - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX1278(Module *mod)SX1278 - SX1279(Module *mod)SX1279 - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getRSSI()SX1278 + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset() overrideSX1278virtual + scanChannel()SX127x + setBandwidth(float bw)SX1278 + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCodingRate(uint8_t cr)SX1278 + setCRC(bool enableCRC)SX1278 + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh) overrideSX1278virtual + setDataShapingOOK(uint8_t sh)SX1278 + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequency(float freq)SX1279 + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setGain(uint8_t gain)SX1278 + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setOutputPower(int8_t power)SX1278 + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSpreadingFactor(uint8_t sf)SX1278 + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX1278(Module *mod)SX1278 + SX1279(Module *mod)SX1279 + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x1279.html b/class_s_x1279.html index 7c992687..728eee9a 100644 --- a/class_s_x1279.html +++ b/class_s_x1279.html @@ -297,6 +297,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_s_x127x-members.html b/class_s_x127x-members.html index 822e8f19..abb32437 100644 --- a/class_s_x127x-members.html +++ b/class_s_x127x-members.html @@ -93,55 +93,56 @@ $(document).ready(function(){initNavTree('class_s_x127x.html','');}); clearDio1Action()SX127x disableAddressFiltering()SX127x fixedPacketLengthMode(uint8_t len=SX127X_MAX_PACKET_LENGTH_FSK)SX127x - getDataRate() constSX127x - getFreqStep() constPhysicalLayer - getFrequencyError(bool autoCorrect=false)SX127x - getIRQFlags()SX127x - getModemStatus()SX127x - getPacketLength(bool update=true) overrideSX127xvirtual - getSNR()SX127x - getTempRaw()SX127x - packetMode()SX127x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()SX127xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSX127xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSX127xvirtual - reset()=0SX127xpure virtual - scanChannel()SX127x - setBitRate(float br)SX127x - setBroadcastAddress(uint8_t broadAddr)SX127x - setCurrentLimit(uint8_t currentLimit)SX127x - setDataShaping(uint8_t sh)=0PhysicalLayerpure virtual - setDio0Action(void(*func)(void))SX127x - setDio1Action(void(*func)(void))SX127x - setEncoding(uint8_t encoding) overrideSX127xvirtual - setFrequencyDeviation(float freqDev) overrideSX127xvirtual - setNodeAddress(uint8_t nodeAddr)SX127x - setOOK(bool enableOOK)SX127x - setPreambleLength(uint16_t preambleLength)SX127x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x - setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x - setRxBandwidth(float rxBw)SX127x - setSyncWord(uint8_t syncWord)SX127x - setSyncWord(uint8_t *syncWord, size_t len)SX127x - sleep()SX127x - standby() overrideSX127xvirtual - startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - SX127x(Module *mod)SX127x - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSX127xvirtual - variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x + getChipVersion()SX127x + getDataRate() constSX127x + getFreqStep() constPhysicalLayer + getFrequencyError(bool autoCorrect=false)SX127x + getIRQFlags()SX127x + getModemStatus()SX127x + getPacketLength(bool update=true) overrideSX127xvirtual + getSNR()SX127x + getTempRaw()SX127x + packetMode()SX127x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()SX127xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSX127xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSX127xvirtual + reset()=0SX127xpure virtual + scanChannel()SX127x + setBitRate(float br)SX127x + setBroadcastAddress(uint8_t broadAddr)SX127x + setCurrentLimit(uint8_t currentLimit)SX127x + setDataShaping(uint8_t sh)=0PhysicalLayerpure virtual + setDio0Action(void(*func)(void))SX127x + setDio1Action(void(*func)(void))SX127x + setEncoding(uint8_t encoding) overrideSX127xvirtual + setFrequencyDeviation(float freqDev) overrideSX127xvirtual + setNodeAddress(uint8_t nodeAddr)SX127x + setOOK(bool enableOOK)SX127x + setPreambleLength(uint16_t preambleLength)SX127x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)SX127x + setRSSIConfig(uint8_t smoothingSamples, int8_t offset=0)SX127x + setRxBandwidth(float rxBw)SX127x + setSyncWord(uint8_t syncWord)SX127x + setSyncWord(uint8_t *syncWord, size_t len)SX127x + sleep()SX127x + standby() overrideSX127xvirtual + startReceive(uint8_t len=0, uint8_t mode=SX127X_RXCONTINUOUS)SX127x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + SX127x(Module *mod)SX127x + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSX127xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSX127xvirtual + variablePacketLengthMode(uint8_t maxLen=SX127X_MAX_PACKET_LENGTH_FSK)SX127x diff --git a/class_s_x127x.html b/class_s_x127x.html index 80490525..162620ab 100644 --- a/class_s_x127x.html +++ b/class_s_x127x.html @@ -245,6 +245,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
@@ -469,6 +472,26 @@ void 
Returns
Status Codes
+ + + +

◆ getChipVersion()

+ +
+
+ + + + + + + +
int16_t SX127x::getChipVersion ()
+
+ +

Read version SPI register. Should return SX1278_CHIP_VERSION (0x12) or SX1272_CHIP_VERSION (0x22) if SX127x is connected and working.

+
Returns
Version register contents or Status Codes
+
diff --git a/class_s_x127x.js b/class_s_x127x.js index ab9c5e20..73b63455 100644 --- a/class_s_x127x.js +++ b/class_s_x127x.js @@ -7,6 +7,7 @@ var class_s_x127x = [ "clearDio1Action", "class_s_x127x.html#a9b6532a25e1730973ac08146008adca5", null ], [ "disableAddressFiltering", "class_s_x127x.html#afe6e9bbfd75f9cad26f9f72c34c4ada5", null ], [ "fixedPacketLengthMode", "class_s_x127x.html#aaf8ce9f09d0f46a76a5e251786b6de7f", null ], + [ "getChipVersion", "class_s_x127x.html#aee5324d7d854e7a2f6768221d4f362cd", null ], [ "getDataRate", "class_s_x127x.html#adc25b685de0859b799488bf7729350b6", null ], [ "getFrequencyError", "class_s_x127x.html#af6aa854a2668d70f4d3a374a49440362", null ], [ "getIRQFlags", "class_s_x127x.html#ac5d2ddb517e474a699b4539653b3754d", null ], diff --git a/class_si4430-members.html b/class_si4430-members.html index 0b0e8e9f..25513ad3 100644 --- a/class_si4430-members.html +++ b/class_si4430-members.html @@ -90,44 +90,45 @@ $(document).ready(function(){initNavTree('class_si4430.html','');}); begin(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=181.1, int8_t power=10, uint8_t preambleLen=16)Si4430 Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen)Si443x clearIrqAction()Si443x - getFreqStep() constPhysicalLayer - getPacketLength(bool update=true) overrideSi443xvirtual - packetMode()Si443x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()Si443xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSi443xvirtual - reset()Si443x - setBitRate(float br)Si443x - setDataShaping(uint8_t sh) overrideSi443xvirtual - setEncoding(uint8_t encoding) overrideSi443xvirtual - setFrequency(float freq)Si4430 - setFrequencyDeviation(float freqDev) overrideSi443xvirtual - setIrqAction(void(*func)(void))Si443x - setOutputPower(int8_t power)Si4430 - setPreambleLength(uint8_t preambleLen)Si443x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x - setRxBandwidth(float rxBw)Si443x - setSyncWord(uint8_t *syncWord, size_t len)Si443x - Si4430(Module *mod)Si4430 - Si4432(Module *mod)Si4432 - Si443x(Module *mod)Si443x - sleep()Si443x - standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + getChipVersion()Si443x + getFreqStep() constPhysicalLayer + getPacketLength(bool update=true) overrideSi443xvirtual + packetMode()Si443x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()Si443xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSi443xvirtual + reset()Si443x + setBitRate(float br)Si443x + setDataShaping(uint8_t sh) overrideSi443xvirtual + setEncoding(uint8_t encoding) overrideSi443xvirtual + setFrequency(float freq)Si4430 + setFrequencyDeviation(float freqDev) overrideSi443xvirtual + setIrqAction(void(*func)(void))Si443x + setOutputPower(int8_t power)Si4430 + setPreambleLength(uint8_t preambleLen)Si443x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x + setRxBandwidth(float rxBw)Si443x + setSyncWord(uint8_t *syncWord, size_t len)Si443x + Si4430(Module *mod)Si4430 + Si4432(Module *mod)Si4432 + Si443x(Module *mod)Si443x + sleep()Si443x + standby() overrideSi443xvirtual + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual diff --git a/class_si4430.html b/class_si4430.html index 9d5985ab..af82b73a 100644 --- a/class_si4430.html +++ b/class_si4430.html @@ -209,6 +209,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_si4431-members.html b/class_si4431-members.html index ce201818..429e7e99 100644 --- a/class_si4431-members.html +++ b/class_si4431-members.html @@ -90,44 +90,45 @@ $(document).ready(function(){initNavTree('class_si4431.html','');}); begin(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=181.1, int8_t power=10, uint8_t preambleLen=16)Si4431 Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen)Si443x clearIrqAction()Si443x - getFreqStep() constPhysicalLayer - getPacketLength(bool update=true) overrideSi443xvirtual - packetMode()Si443x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()Si443xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSi443xvirtual - reset()Si443x - setBitRate(float br)Si443x - setDataShaping(uint8_t sh) overrideSi443xvirtual - setEncoding(uint8_t encoding) overrideSi443xvirtual - setFrequency(float freq)Si4432 - setFrequencyDeviation(float freqDev) overrideSi443xvirtual - setIrqAction(void(*func)(void))Si443x - setOutputPower(int8_t power)Si4431 - setPreambleLength(uint8_t preambleLen)Si443x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x - setRxBandwidth(float rxBw)Si443x - setSyncWord(uint8_t *syncWord, size_t len)Si443x - Si4431(Module *mod)Si4431 - Si4432(Module *mod)Si4432 - Si443x(Module *mod)Si443x - sleep()Si443x - standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + getChipVersion()Si443x + getFreqStep() constPhysicalLayer + getPacketLength(bool update=true) overrideSi443xvirtual + packetMode()Si443x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()Si443xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSi443xvirtual + reset()Si443x + setBitRate(float br)Si443x + setDataShaping(uint8_t sh) overrideSi443xvirtual + setEncoding(uint8_t encoding) overrideSi443xvirtual + setFrequency(float freq)Si4432 + setFrequencyDeviation(float freqDev) overrideSi443xvirtual + setIrqAction(void(*func)(void))Si443x + setOutputPower(int8_t power)Si4431 + setPreambleLength(uint8_t preambleLen)Si443x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x + setRxBandwidth(float rxBw)Si443x + setSyncWord(uint8_t *syncWord, size_t len)Si443x + Si4431(Module *mod)Si4431 + Si4432(Module *mod)Si4432 + Si443x(Module *mod)Si443x + sleep()Si443x + standby() overrideSi443xvirtual + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual diff --git a/class_si4431.html b/class_si4431.html index e70ab7f4..a0b95c4f 100644 --- a/class_si4431.html +++ b/class_si4431.html @@ -206,6 +206,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_si4432-members.html b/class_si4432-members.html index 66d20648..c6df4975 100644 --- a/class_si4432-members.html +++ b/class_si4432-members.html @@ -90,43 +90,44 @@ $(document).ready(function(){initNavTree('class_si4432.html','');}); begin(float freq=434.0, float br=48.0, float freqDev=50.0, float rxBw=181.1, int8_t power=10, uint8_t preambleLen=16)Si4432 Si443x::begin(float br, float freqDev, float rxBw, uint8_t preambleLen)Si443x clearIrqAction()Si443x - getFreqStep() constPhysicalLayer - getPacketLength(bool update=true) overrideSi443xvirtual - packetMode()Si443x - PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer - random()Si443xvirtual - PhysicalLayer::random(int32_t max)PhysicalLayer - PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer - readData(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer - receive(uint8_t *data, size_t len) overrideSi443xvirtual - PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer - receiveDirect() overrideSi443xvirtual - reset()Si443x - setBitRate(float br)Si443x - setDataShaping(uint8_t sh) overrideSi443xvirtual - setEncoding(uint8_t encoding) overrideSi443xvirtual - setFrequency(float freq)Si4432 - setFrequencyDeviation(float freqDev) overrideSi443xvirtual - setIrqAction(void(*func)(void))Si443x - setOutputPower(int8_t power)Si4432 - setPreambleLength(uint8_t preambleLen)Si443x - setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x - setRxBandwidth(float rxBw)Si443x - setSyncWord(uint8_t *syncWord, size_t len)Si443x - Si4432(Module *mod)Si4432 - Si443x(Module *mod)Si443x - sleep()Si443x - standby() overrideSi443xvirtual - startReceive()Si443x - startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer - transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual - PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer - PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer - transmitDirect(uint32_t frf=0) overrideSi443xvirtual + getChipVersion()Si443x + getFreqStep() constPhysicalLayer + getPacketLength(bool update=true) overrideSi443xvirtual + packetMode()Si443x + PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer + random()Si443xvirtual + PhysicalLayer::random(int32_t max)PhysicalLayer + PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer + readData(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer + receive(uint8_t *data, size_t len) overrideSi443xvirtual + PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer + receiveDirect() overrideSi443xvirtual + reset()Si443x + setBitRate(float br)Si443x + setDataShaping(uint8_t sh) overrideSi443xvirtual + setEncoding(uint8_t encoding) overrideSi443xvirtual + setFrequency(float freq)Si4432 + setFrequencyDeviation(float freqDev) overrideSi443xvirtual + setIrqAction(void(*func)(void))Si443x + setOutputPower(int8_t power)Si4432 + setPreambleLength(uint8_t preambleLen)Si443x + setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x + setRxBandwidth(float rxBw)Si443x + setSyncWord(uint8_t *syncWord, size_t len)Si443x + Si4432(Module *mod)Si4432 + Si443x(Module *mod)Si443x + sleep()Si443x + standby() overrideSi443xvirtual + startReceive()Si443x + startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer + transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual + PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer + PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer + transmitDirect(uint32_t frf=0) overrideSi443xvirtual diff --git a/class_si4432.html b/class_si4432.html index a6214c8e..41f8793d 100644 --- a/class_si4432.html +++ b/class_si4432.html @@ -197,6 +197,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
diff --git a/class_si443x-members.html b/class_si443x-members.html index 35db074f..5d1eabbe 100644 --- a/class_si443x-members.html +++ b/class_si443x-members.html @@ -89,40 +89,41 @@ $(document).ready(function(){initNavTree('class_si443x.html','');}); - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
begin(float br, float freqDev, float rxBw, uint8_t preambleLen)Si443x
clearIrqAction()Si443x
getFreqStep() constPhysicalLayer
getPacketLength(bool update=true) overrideSi443xvirtual
packetMode()Si443x
PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer
random()Si443xvirtual
PhysicalLayer::random(int32_t max)PhysicalLayer
PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer
readData(uint8_t *data, size_t len) overrideSi443xvirtual
PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer
receive(uint8_t *data, size_t len) overrideSi443xvirtual
PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer
receiveDirect() overrideSi443xvirtual
reset()Si443x
setBitRate(float br)Si443x
setDataShaping(uint8_t sh) overrideSi443xvirtual
setEncoding(uint8_t encoding) overrideSi443xvirtual
setFrequencyDeviation(float freqDev) overrideSi443xvirtual
setIrqAction(void(*func)(void))Si443x
setPreambleLength(uint8_t preambleLen)Si443x
setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x
setRxBandwidth(float rxBw)Si443x
setSyncWord(uint8_t *syncWord, size_t len)Si443x
Si443x(Module *mod)Si443x
sleep()Si443x
standby() overrideSi443xvirtual
startReceive()Si443x
startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual
PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer
PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer
transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual
PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer
PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer
PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer
transmitDirect(uint32_t frf=0) overrideSi443xvirtual
getChipVersion()Si443x
getFreqStep() constPhysicalLayer
getPacketLength(bool update=true) overrideSi443xvirtual
packetMode()Si443x
PhysicalLayer(float freqStep, size_t maxPacketLength)PhysicalLayer
random()Si443xvirtual
PhysicalLayer::random(int32_t max)PhysicalLayer
PhysicalLayer::random(int32_t min, int32_t max)PhysicalLayer
readData(uint8_t *data, size_t len) overrideSi443xvirtual
PhysicalLayer::readData(String &str, size_t len=0)PhysicalLayer
receive(uint8_t *data, size_t len) overrideSi443xvirtual
PhysicalLayer::receive(String &str, size_t len=0)PhysicalLayer
receiveDirect() overrideSi443xvirtual
reset()Si443x
setBitRate(float br)Si443x
setDataShaping(uint8_t sh) overrideSi443xvirtual
setEncoding(uint8_t encoding) overrideSi443xvirtual
setFrequencyDeviation(float freqDev) overrideSi443xvirtual
setIrqAction(void(*func)(void))Si443x
setPreambleLength(uint8_t preambleLen)Si443x
setRfSwitchPins(RADIOLIB_PIN_TYPE rxEn, RADIOLIB_PIN_TYPE txEn)Si443x
setRxBandwidth(float rxBw)Si443x
setSyncWord(uint8_t *syncWord, size_t len)Si443x
Si443x(Module *mod)Si443x
sleep()Si443x
standby() overrideSi443xvirtual
startReceive()Si443x
startTransmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual
PhysicalLayer::startTransmit(String &str, uint8_t addr=0)PhysicalLayer
PhysicalLayer::startTransmit(const char *str, uint8_t addr=0)PhysicalLayer
transmit(uint8_t *data, size_t len, uint8_t addr=0) overrideSi443xvirtual
PhysicalLayer::transmit(__FlashStringHelper *fstr, uint8_t addr=0)PhysicalLayer
PhysicalLayer::transmit(String &str, uint8_t addr=0)PhysicalLayer
PhysicalLayer::transmit(const char *str, uint8_t addr=0)PhysicalLayer
transmitDirect(uint32_t frf=0) overrideSi443xvirtual
diff --git a/class_si443x.html b/class_si443x.html index 88d64ea5..75eb9d8a 100644 --- a/class_si443x.html +++ b/class_si443x.html @@ -184,6 +184,9 @@ void uint8_t random ()  Get one truly random byte from RSSI noise. More...
  +int16_t getChipVersion () + Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working. More...
+  - Public Member Functions inherited from PhysicalLayer  PhysicalLayer (float freqStep, size_t maxPacketLength)  Default constructor. More...
@@ -299,6 +302,26 @@ void 
Returns
Status Codes
+ + + +

◆ getChipVersion()

+ +
+
+ + + + + + + +
int16_t Si443x::getChipVersion ()
+
+ +

Read version SPI register. Should return SI443X_DEVICE_VERSION (0x06) if Si443x is connected and working.

+
Returns
Version register contents or Status Codes
+
diff --git a/class_si443x.js b/class_si443x.js index f7d02865..5df032b2 100644 --- a/class_si443x.js +++ b/class_si443x.js @@ -3,6 +3,7 @@ var class_si443x = [ "Si443x", "class_si443x.html#ae7cfff2efebfa01c8a50a5cbbe8775b9", null ], [ "begin", "class_si443x.html#a453eda5436dc4dfe0dad676dc3977752", null ], [ "clearIrqAction", "class_si443x.html#a8d019f58551346c3f3bd8b72d2486109", null ], + [ "getChipVersion", "class_si443x.html#a55252bda74e8c67636a8c1fa0e9f58d3", null ], [ "getPacketLength", "class_si443x.html#a2d944669dc69ccd47f9e6c360f2ffd10", null ], [ "packetMode", "class_si443x.html#a616eb24c4b11c5d39caaade160be8092", null ], [ "random", "class_si443x.html#ad371b44fc0c4ddd3ed39e2595e85b5df", null ], diff --git a/functions_func_g.html b/functions_func_g.html index 97a33617..db353ca6 100644 --- a/functions_func_g.html +++ b/functions_func_g.html @@ -86,6 +86,12 @@ $(document).ready(function(){initNavTree('functions_func_g.html','');});
  • get() : HTTPClient
    • +
  • getChipVersion() +: CC1101 +, RF69 +, Si443x +, SX127x +
  • getCs() : Module
    • diff --git a/functions_g.html b/functions_g.html index 8eb15dd5..f2bf15dc 100644 --- a/functions_g.html +++ b/functions_g.html @@ -86,6 +86,12 @@ $(document).ready(function(){initNavTree('functions_g.html','');});
  • get() : HTTPClient
    • +
  • getChipVersion() +: CC1101 +, RF69 +, Si443x +, SX127x +
  • getCs() : Module
    • diff --git a/navtreedata.js b/navtreedata.js index 6a1328fb..f115f606 100644 --- a/navtreedata.js +++ b/navtreedata.js @@ -23,9 +23,9 @@ var NAVTREE = var NAVTREEINDEX = [ "_a_f_s_k_8h_source.html", -"class_module.html#ad7ca9ae5a22cdacdf9437ca9cd37c9b4", -"class_s_x1272.html#ae1c57ad5e8496dc28cd3ba9852809852", -"dir_c14921ab4918e015c91d11c846a1924a.html" +"class_module.html#ad5767216ba9340ae6d86915b12e89bd6", +"class_s_x1272.html#aaa5a787164fb216c12b8dea4d810f7f3", +"dir_7b8feacc70eb38d5fd56f060c649a59c.html" ]; var SYNCONMSG = 'click to disable panel synchronisation'; diff --git a/navtreeindex0.js b/navtreeindex0.js index 0c120f74..e7a61756 100644 --- a/navtreeindex0.js +++ b/navtreeindex0.js @@ -86,45 +86,46 @@ var NAVTREEINDEX0 = "class_a_x25_frame.html#adce5294af25f09df752997d33ac0e87f":[3,0,2,16], "class_a_x25_frame.html#af62935e56dc24bca5d2e2aeb932b63f8":[3,0,2,11], "class_c_c1101.html":[3,0,3], -"class_c_c1101.html#a0d69713b9f20c9de354c13c3167b18b3":[3,0,3,21], -"class_c_c1101.html#a0df2938e2509a8f2746b20ae0558d4ea":[3,0,3,35], -"class_c_c1101.html#a122281f6a915b77ee9dafc9926e731a0":[3,0,3,9], -"class_c_c1101.html#a240eef8fa7d838d76f3c11086dc50e46":[3,0,3,37], -"class_c_c1101.html#a2911d49d1c293542f7a374c9af60df0e":[3,0,3,28], -"class_c_c1101.html#a381d0059d7a0ccd8a2f54d7d3376f9b6":[3,0,3,30], -"class_c_c1101.html#a38f6978c757b0dd73e3ef98164a735a2":[3,0,3,11], -"class_c_c1101.html#a433f1a40b33be6c84d3665a1b4cd57d6":[3,0,3,31], -"class_c_c1101.html#a45ab4e3f4f9db367185333d36ba21ed2":[3,0,3,29], -"class_c_c1101.html#a48fd0452d6f7d7d51ea7d23b2dbe1551":[3,0,3,10], +"class_c_c1101.html#a0d69713b9f20c9de354c13c3167b18b3":[3,0,3,22], +"class_c_c1101.html#a0df2938e2509a8f2746b20ae0558d4ea":[3,0,3,36], +"class_c_c1101.html#a122281f6a915b77ee9dafc9926e731a0":[3,0,3,10], +"class_c_c1101.html#a240eef8fa7d838d76f3c11086dc50e46":[3,0,3,38], +"class_c_c1101.html#a2911d49d1c293542f7a374c9af60df0e":[3,0,3,29], +"class_c_c1101.html#a2a4c6e622dffd2788d8ac52d708b0705":[3,0,3,8], +"class_c_c1101.html#a381d0059d7a0ccd8a2f54d7d3376f9b6":[3,0,3,31], +"class_c_c1101.html#a38f6978c757b0dd73e3ef98164a735a2":[3,0,3,12], +"class_c_c1101.html#a433f1a40b33be6c84d3665a1b4cd57d6":[3,0,3,32], +"class_c_c1101.html#a45ab4e3f4f9db367185333d36ba21ed2":[3,0,3,30], +"class_c_c1101.html#a48fd0452d6f7d7d51ea7d23b2dbe1551":[3,0,3,11], "class_c_c1101.html#a4f2dc4176b62a0636636088e31b8e85b":[3,0,3,5], -"class_c_c1101.html#a59ca9e8956e308159949638bf327e5fb":[3,0,3,8], +"class_c_c1101.html#a59ca9e8956e308159949638bf327e5fb":[3,0,3,9], "class_c_c1101.html#a6807e4254c4b55fa8d393b2bf8f2db3e":[3,0,3,0], -"class_c_c1101.html#a6dfd6a57cdbb3196ad021b152b0c65ed":[3,0,3,22], -"class_c_c1101.html#a6e62914790f132816134fc68c2bb5eb8":[3,0,3,24], +"class_c_c1101.html#a6dfd6a57cdbb3196ad021b152b0c65ed":[3,0,3,23], +"class_c_c1101.html#a6e62914790f132816134fc68c2bb5eb8":[3,0,3,25], "class_c_c1101.html#a6fe55d0217bf5218865198ef8d6fdab4":[3,0,3,6], -"class_c_c1101.html#a7612bf81e48086004c62548de2682266":[3,0,3,33], -"class_c_c1101.html#a7cb99a9200b21829b50e3fc3878573f4":[3,0,3,36], -"class_c_c1101.html#a881122ec3457c5f95760859f8e0297c7":[3,0,3,38], -"class_c_c1101.html#a8c79975a7bbe8a37f8214ecd1f69ba22":[3,0,3,13], +"class_c_c1101.html#a7612bf81e48086004c62548de2682266":[3,0,3,34], +"class_c_c1101.html#a7cb99a9200b21829b50e3fc3878573f4":[3,0,3,37], +"class_c_c1101.html#a881122ec3457c5f95760859f8e0297c7":[3,0,3,39], +"class_c_c1101.html#a8c79975a7bbe8a37f8214ecd1f69ba22":[3,0,3,14], "class_c_c1101.html#a9335f1d5ccab7aab2357449002203810":[3,0,3,7], -"class_c_c1101.html#a9592c023556c38c2b8066a23da96ae5e":[3,0,3,20], +"class_c_c1101.html#a9592c023556c38c2b8066a23da96ae5e":[3,0,3,21], "class_c_c1101.html#a9aee5df428d30b9c80b8a8700609a883":[3,0,3,4], -"class_c_c1101.html#aa53427cabcda0778f287ed1d850bbe37":[3,0,3,16], -"class_c_c1101.html#aafac40359c4a1bb01aae12da6b03be26":[3,0,3,17], -"class_c_c1101.html#ab053c185330519d58f364790108d29ac":[3,0,3,15], -"class_c_c1101.html#ab4b98eb6af33d006306bb7514ed216ea":[3,0,3,19], +"class_c_c1101.html#aa53427cabcda0778f287ed1d850bbe37":[3,0,3,17], +"class_c_c1101.html#aafac40359c4a1bb01aae12da6b03be26":[3,0,3,18], +"class_c_c1101.html#ab053c185330519d58f364790108d29ac":[3,0,3,16], +"class_c_c1101.html#ab4b98eb6af33d006306bb7514ed216ea":[3,0,3,20], "class_c_c1101.html#ab5e6b3745f80cf61e1ced33303311df8":[3,0,3,2], -"class_c_c1101.html#ab89b0932dbacadc34d049a2bd2292001":[3,0,3,32], -"class_c_c1101.html#ac3ff8051af5ca50c349e02257f1a3bda":[3,0,3,26], -"class_c_c1101.html#ac6338c2f5c937a12dac06069944ffb77":[3,0,3,23], +"class_c_c1101.html#ab89b0932dbacadc34d049a2bd2292001":[3,0,3,33], +"class_c_c1101.html#ac3ff8051af5ca50c349e02257f1a3bda":[3,0,3,27], +"class_c_c1101.html#ac6338c2f5c937a12dac06069944ffb77":[3,0,3,24], "class_c_c1101.html#ac7a8b1fe7d08dc6db20cf1569b0d37b4":[3,0,3,3], -"class_c_c1101.html#acbfa80f431f335d5597500319f0affa8":[3,0,3,27], +"class_c_c1101.html#acbfa80f431f335d5597500319f0affa8":[3,0,3,28], "class_c_c1101.html#adcf6b5c4e1a066d6b9be326a9ee04284":[3,0,3,1], -"class_c_c1101.html#adf96e77f25b7e256891601bef04f35a6":[3,0,3,18], -"class_c_c1101.html#aedc1067d0334bb69ed5316146014097d":[3,0,3,14], -"class_c_c1101.html#aeea507b71f1a3dfab5be4c3a1606b8fd":[3,0,3,12], -"class_c_c1101.html#af727750d05be0bcef4bb8ac260d110e3":[3,0,3,34], -"class_c_c1101.html#afa64d1ad4789d3146b38d14437234756":[3,0,3,25], +"class_c_c1101.html#adf96e77f25b7e256891601bef04f35a6":[3,0,3,19], +"class_c_c1101.html#aedc1067d0334bb69ed5316146014097d":[3,0,3,15], +"class_c_c1101.html#aeea507b71f1a3dfab5be4c3a1606b8fd":[3,0,3,13], +"class_c_c1101.html#af727750d05be0bcef4bb8ac260d110e3":[3,0,3,35], +"class_c_c1101.html#afa64d1ad4789d3146b38d14437234756":[3,0,3,26], "class_e_s_p8266.html":[3,0,4], "class_e_s_p8266.html#a1caaa537edd52d1c2b7a0a25ef69c1c9":[3,0,4,8], "class_e_s_p8266.html#a2f34474953b7dbe4d057c8e3f65e0dc4":[3,0,4,9], @@ -248,6 +249,5 @@ var NAVTREEINDEX0 = "class_module.html#a9d8ab2ff353bad5d0e7568d300a48ba0":[3,0,11,31], "class_module.html#ab814614ddd34b57f5a612a20f5fe4c57":[3,0,11,28], "class_module.html#ac65f3d9e022b3284134ced1c20bcff09":[3,0,11,3], -"class_module.html#ad1aadc2b52eea2bf9d26591091eec3f1":[3,0,11,8], -"class_module.html#ad5767216ba9340ae6d86915b12e89bd6":[3,0,11,7] +"class_module.html#ad1aadc2b52eea2bf9d26591091eec3f1":[3,0,11,8] }; diff --git a/navtreeindex1.js b/navtreeindex1.js index ed4fac78..907501fa 100644 --- a/navtreeindex1.js +++ b/navtreeindex1.js @@ -1,5 +1,6 @@ var NAVTREEINDEX1 = { +"class_module.html#ad5767216ba9340ae6d86915b12e89bd6":[3,0,11,7], "class_module.html#ad7ca9ae5a22cdacdf9437ca9cd37c9b4":[3,0,11,23], "class_module.html#adb22d89bc5f532f1d056d9a9f3a6589c":[3,0,11,19], "class_module.html#ae352c7a7b997fc1b17189c1312a8347f":[3,0,11,14], @@ -65,49 +66,50 @@ var NAVTREEINDEX1 = "class_physical_layer.html#af81565ee82ef9a7de9c5663c745f4ef7":[3,0,15,21], "class_physical_layer.html#afb1b090348d9091bfa3a0b5ba3d85b36":[3,0,15,8], "class_r_f69.html":[3,0,16], -"class_r_f69.html#a0526ce6ea3722fd258f96d9677a60853":[3,0,16,12], -"class_r_f69.html#a09ba80f60ee7974011a4b4f6c18c6847":[3,0,16,41], +"class_r_f69.html#a0526ce6ea3722fd258f96d9677a60853":[3,0,16,13], +"class_r_f69.html#a09ba80f60ee7974011a4b4f6c18c6847":[3,0,16,42], +"class_r_f69.html#a0c30202b2d52eb32f43066bc0f938638":[3,0,16,10], "class_r_f69.html#a15fafb6c24a8b5721623be447628bbaa":[3,0,16,5], -"class_r_f69.html#a1b7598b87ffaabdbe733c47317fa91d8":[3,0,16,22], +"class_r_f69.html#a1b7598b87ffaabdbe733c47317fa91d8":[3,0,16,23], "class_r_f69.html#a1fd4609f419d8b0213ee39b05dd40b69":[3,0,16,7], -"class_r_f69.html#a20242499eb926ff7b7da6e3f74a9ece1":[3,0,16,38], -"class_r_f69.html#a222682569338abb49d6952430b6eebdd":[3,0,16,42], -"class_r_f69.html#a26667d50ec845c28e17236c69c886561":[3,0,16,36], -"class_r_f69.html#a3983b66c83818b4082805bcafc712f00":[3,0,16,15], +"class_r_f69.html#a20242499eb926ff7b7da6e3f74a9ece1":[3,0,16,39], +"class_r_f69.html#a222682569338abb49d6952430b6eebdd":[3,0,16,43], +"class_r_f69.html#a26667d50ec845c28e17236c69c886561":[3,0,16,37], +"class_r_f69.html#a3983b66c83818b4082805bcafc712f00":[3,0,16,16], "class_r_f69.html#a400bb57d2353b57c29cf41a6d9497c80":[3,0,16,6], -"class_r_f69.html#a42b99e437454e92c6932c3b7acc1fc4a":[3,0,16,24], -"class_r_f69.html#a472a04041551cb38d2223fb34f71d8eb":[3,0,16,37], +"class_r_f69.html#a42b99e437454e92c6932c3b7acc1fc4a":[3,0,16,25], +"class_r_f69.html#a472a04041551cb38d2223fb34f71d8eb":[3,0,16,38], "class_r_f69.html#a4c9dcbd7e44bc5e46d9f10ae276a0c5f":[3,0,16,9], "class_r_f69.html#a4d0dea965aba1017a660c9478ec57560":[3,0,16,1], -"class_r_f69.html#a54cd7be92e166659b50bd6ed4433db4c":[3,0,16,14], +"class_r_f69.html#a54cd7be92e166659b50bd6ed4433db4c":[3,0,16,15], "class_r_f69.html#a5996fc1751e7542baafa0d6c0a6c78ee":[3,0,16,4], "class_r_f69.html#a643a711bcb4b7771a7ab1f457e61a417":[3,0,16,8], -"class_r_f69.html#a6a67dd698b3cc6afcaf18c3710ad5f0f":[3,0,16,13], -"class_r_f69.html#a6d90ad1d455de045c53c5758babd876c":[3,0,16,33], -"class_r_f69.html#a735d8f22095a7e69471d73ca021b9d1a":[3,0,16,35], -"class_r_f69.html#a7c84b3f881cad6e05b0f4f68c24496d9":[3,0,16,32], -"class_r_f69.html#a855dc194947b095b821ec1524ba6814c":[3,0,16,40], -"class_r_f69.html#a86a080086c0228d23e2cb77d2b1915c1":[3,0,16,10], +"class_r_f69.html#a6a67dd698b3cc6afcaf18c3710ad5f0f":[3,0,16,14], +"class_r_f69.html#a6d90ad1d455de045c53c5758babd876c":[3,0,16,34], +"class_r_f69.html#a735d8f22095a7e69471d73ca021b9d1a":[3,0,16,36], +"class_r_f69.html#a7c84b3f881cad6e05b0f4f68c24496d9":[3,0,16,33], +"class_r_f69.html#a855dc194947b095b821ec1524ba6814c":[3,0,16,41], +"class_r_f69.html#a86a080086c0228d23e2cb77d2b1915c1":[3,0,16,11], "class_r_f69.html#a9721d2a3ed9fa8dd878575d71d5a4942":[3,0,16,2], -"class_r_f69.html#a998ddd21fc152d835c6f1b8d31b02fcc":[3,0,16,31], -"class_r_f69.html#a9e50a1183d13ff9984f8438a7e9e4a77":[3,0,16,25], -"class_r_f69.html#aa72ad2ac5238bd87886684064b7494cf":[3,0,16,26], -"class_r_f69.html#aada7c48828b950cdfd260594d502b03d":[3,0,16,34], -"class_r_f69.html#aae828ce8dda16da4e54d2f18b1fb8af2":[3,0,16,27], -"class_r_f69.html#ab467f0fc318e651d0cdfbc0399d4c34b":[3,0,16,28], -"class_r_f69.html#ab9c217d5ece259950780a05c6e41f75c":[3,0,16,30], -"class_r_f69.html#abd556b0f455f9510213b17588a4baf1b":[3,0,16,17], -"class_r_f69.html#abe5b378d7cc274fd8b75881e7d604bf3":[3,0,16,19], -"class_r_f69.html#ac205bc487833dc4eae4bb0069c0c4d1e":[3,0,16,23], -"class_r_f69.html#ac37d9ddee2adcc8876a182b8ebc3e703":[3,0,16,20], -"class_r_f69.html#ac4fc3f2b178ef08caec3a9f548f44cd7":[3,0,16,11], -"class_r_f69.html#ad7f8132912a5dbf38c5cf676ac167d13":[3,0,16,21], -"class_r_f69.html#adb9fbfedf95f34ac537815870b98a9be":[3,0,16,29], +"class_r_f69.html#a998ddd21fc152d835c6f1b8d31b02fcc":[3,0,16,32], +"class_r_f69.html#a9e50a1183d13ff9984f8438a7e9e4a77":[3,0,16,26], +"class_r_f69.html#aa72ad2ac5238bd87886684064b7494cf":[3,0,16,27], +"class_r_f69.html#aada7c48828b950cdfd260594d502b03d":[3,0,16,35], +"class_r_f69.html#aae828ce8dda16da4e54d2f18b1fb8af2":[3,0,16,28], +"class_r_f69.html#ab467f0fc318e651d0cdfbc0399d4c34b":[3,0,16,29], +"class_r_f69.html#ab9c217d5ece259950780a05c6e41f75c":[3,0,16,31], +"class_r_f69.html#abd556b0f455f9510213b17588a4baf1b":[3,0,16,18], +"class_r_f69.html#abe5b378d7cc274fd8b75881e7d604bf3":[3,0,16,20], +"class_r_f69.html#ac205bc487833dc4eae4bb0069c0c4d1e":[3,0,16,24], +"class_r_f69.html#ac37d9ddee2adcc8876a182b8ebc3e703":[3,0,16,21], +"class_r_f69.html#ac4fc3f2b178ef08caec3a9f548f44cd7":[3,0,16,12], +"class_r_f69.html#ad7f8132912a5dbf38c5cf676ac167d13":[3,0,16,22], +"class_r_f69.html#adb9fbfedf95f34ac537815870b98a9be":[3,0,16,30], "class_r_f69.html#ade1f9a7a603d712c480ed5e9a8d1bf51":[3,0,16,3], -"class_r_f69.html#ae36e8e6042245621a182b29526fe2245":[3,0,16,16], -"class_r_f69.html#af62ebde1ea34a394b9781a21ae348c39":[3,0,16,43], -"class_r_f69.html#af953ee17aca5392f1e62ea4fe690550a":[3,0,16,18], -"class_r_f69.html#afae38fa64242043de34096bf497725f1":[3,0,16,39], +"class_r_f69.html#ae36e8e6042245621a182b29526fe2245":[3,0,16,17], +"class_r_f69.html#af62ebde1ea34a394b9781a21ae348c39":[3,0,16,44], +"class_r_f69.html#af953ee17aca5392f1e62ea4fe690550a":[3,0,16,19], +"class_r_f69.html#afae38fa64242043de34096bf497725f1":[3,0,16,40], "class_r_f69.html#afbc84d4f91502bcbe12ddda2fde51448":[3,0,16,0], "class_r_f_m22.html":[3,0,17], "class_r_f_m23.html":[3,0,18], @@ -247,7 +249,5 @@ var NAVTREEINDEX1 = "class_s_x1272.html#a82084ac58502c83d2ada998410307490":[3,0,35,15], "class_s_x1272.html#a91aca64124321c07a67f26b3c6934aea":[3,0,35,10], "class_s_x1272.html#a960913438feccad4c1913a9222384a5f":[3,0,35,8], -"class_s_x1272.html#a9ffe467a6baaeaa079e02c3f1f43f626":[3,0,35,0], -"class_s_x1272.html#aaa5a787164fb216c12b8dea4d810f7f3":[3,0,35,2], -"class_s_x1272.html#abb4bbfe8acc6026c833d267d78417b63":[3,0,35,1] +"class_s_x1272.html#a9ffe467a6baaeaa079e02c3f1f43f626":[3,0,35,0] }; diff --git a/navtreeindex2.js b/navtreeindex2.js index 5b8283e9..b60fb3cf 100644 --- a/navtreeindex2.js +++ b/navtreeindex2.js @@ -1,5 +1,7 @@ var NAVTREEINDEX2 = { +"class_s_x1272.html#aaa5a787164fb216c12b8dea4d810f7f3":[3,0,35,2], +"class_s_x1272.html#abb4bbfe8acc6026c833d267d78417b63":[3,0,35,1], "class_s_x1272.html#ae1c57ad5e8496dc28cd3ba9852809852":[3,0,35,13], "class_s_x1272.html#ae3596f303714509f552d98321bdfce5c":[3,0,35,14], "class_s_x1272.html#af409f50e51042cf9357c0a8267f762f8":[3,0,35,12], @@ -42,49 +44,50 @@ var NAVTREEINDEX2 = "class_s_x1279.html#abc606ad06ee77b6830dab4331793d22a":[3,0,40,0], "class_s_x1279.html#acf9b2087f5b661f06e9512bad36b3817":[3,0,40,3], "class_s_x127x.html":[3,0,41], -"class_s_x127x.html#a0995088d37689a3c240a1af791df6cf1":[3,0,41,14], -"class_s_x127x.html#a24ef0af19a6b8954f956a3c3ad4286ee":[3,0,41,29], -"class_s_x127x.html#a2cc53b9f9d90647c5709cb974779cf53":[3,0,41,33], -"class_s_x127x.html#a2cf6a5bd8f3257f98ee4f250cbdf8bdc":[3,0,41,10], -"class_s_x127x.html#a3321ac4a7f65e73004202486db9b1d68":[3,0,41,19], -"class_s_x127x.html#a400575e3d83977bd250c5cb382fc7002":[3,0,41,23], -"class_s_x127x.html#a44501ec8f8ac6084467b94516b1337df":[3,0,41,36], -"class_s_x127x.html#a448ea8a6a6011a9cdddd4e09bd6c9679":[3,0,41,27], -"class_s_x127x.html#a462fa74275e67c296328a01f361892d5":[3,0,41,11], +"class_s_x127x.html#a0995088d37689a3c240a1af791df6cf1":[3,0,41,15], +"class_s_x127x.html#a24ef0af19a6b8954f956a3c3ad4286ee":[3,0,41,30], +"class_s_x127x.html#a2cc53b9f9d90647c5709cb974779cf53":[3,0,41,34], +"class_s_x127x.html#a2cf6a5bd8f3257f98ee4f250cbdf8bdc":[3,0,41,11], +"class_s_x127x.html#a3321ac4a7f65e73004202486db9b1d68":[3,0,41,20], +"class_s_x127x.html#a400575e3d83977bd250c5cb382fc7002":[3,0,41,24], +"class_s_x127x.html#a44501ec8f8ac6084467b94516b1337df":[3,0,41,37], +"class_s_x127x.html#a448ea8a6a6011a9cdddd4e09bd6c9679":[3,0,41,28], +"class_s_x127x.html#a462fa74275e67c296328a01f361892d5":[3,0,41,12], "class_s_x127x.html#a5da8218f69e3bf52df389a0480f8b430":[3,0,41,1], -"class_s_x127x.html#a606d839b3a992c681ac9ad7ca6020022":[3,0,41,21], -"class_s_x127x.html#a6a03da620f9fb532c879900ba05732de":[3,0,41,15], +"class_s_x127x.html#a606d839b3a992c681ac9ad7ca6020022":[3,0,41,22], +"class_s_x127x.html#a6a03da620f9fb532c879900ba05732de":[3,0,41,16], "class_s_x127x.html#a729b4f3f36096b5b15bae19c7876e823":[3,0,41,3], -"class_s_x127x.html#a760b8c5103128f122fbe489c6529ce41":[3,0,41,37], -"class_s_x127x.html#a95bc32a555675879ad9e2a9e399dc6c1":[3,0,41,13], +"class_s_x127x.html#a760b8c5103128f122fbe489c6529ce41":[3,0,41,38], +"class_s_x127x.html#a95bc32a555675879ad9e2a9e399dc6c1":[3,0,41,14], "class_s_x127x.html#a9b6532a25e1730973ac08146008adca5":[3,0,41,4], -"class_s_x127x.html#a9b7afe338fd5b81122c369ecaf0c3ebc":[3,0,41,35], -"class_s_x127x.html#a9c4ea3285922bf01cebd2c8a706d9a29":[3,0,41,40], -"class_s_x127x.html#a9f753c0857e7b8b4b9f7f6e91c77f0fd":[3,0,41,42], -"class_s_x127x.html#aa7ac558d537c6364c4bc82c8f33e398f":[3,0,41,18], +"class_s_x127x.html#a9b7afe338fd5b81122c369ecaf0c3ebc":[3,0,41,36], +"class_s_x127x.html#a9c4ea3285922bf01cebd2c8a706d9a29":[3,0,41,41], +"class_s_x127x.html#a9f753c0857e7b8b4b9f7f6e91c77f0fd":[3,0,41,43], +"class_s_x127x.html#aa7ac558d537c6364c4bc82c8f33e398f":[3,0,41,19], "class_s_x127x.html#aaf8ce9f09d0f46a76a5e251786b6de7f":[3,0,41,6], -"class_s_x127x.html#ab608c45e0dcc44280df29580dc0a31ed":[3,0,41,30], -"class_s_x127x.html#ab99630d50672b43fc7162ba8f3293f95":[3,0,41,28], -"class_s_x127x.html#abad2d455012bd28d304589c8164390eb":[3,0,41,26], -"class_s_x127x.html#abc5069b39dc31b637ee561d5745e1deb":[3,0,41,12], -"class_s_x127x.html#abc51ce6718153e4963128f25bb5aab40":[3,0,41,22], -"class_s_x127x.html#abfc840e8d6fe5e222f0143be17876745":[3,0,41,16], -"class_s_x127x.html#ac5c7f4584352a12390594395d9c29bde":[3,0,41,34], -"class_s_x127x.html#ac5d2ddb517e474a699b4539653b3754d":[3,0,41,9], +"class_s_x127x.html#ab608c45e0dcc44280df29580dc0a31ed":[3,0,41,31], +"class_s_x127x.html#ab99630d50672b43fc7162ba8f3293f95":[3,0,41,29], +"class_s_x127x.html#abad2d455012bd28d304589c8164390eb":[3,0,41,27], +"class_s_x127x.html#abc5069b39dc31b637ee561d5745e1deb":[3,0,41,13], +"class_s_x127x.html#abc51ce6718153e4963128f25bb5aab40":[3,0,41,23], +"class_s_x127x.html#abfc840e8d6fe5e222f0143be17876745":[3,0,41,17], +"class_s_x127x.html#ac5c7f4584352a12390594395d9c29bde":[3,0,41,35], +"class_s_x127x.html#ac5d2ddb517e474a699b4539653b3754d":[3,0,41,10], "class_s_x127x.html#ac74c5914ca429a3892c66b9d98e3ea6c":[3,0,41,0], -"class_s_x127x.html#ad3955f85f456edae772a51025a19029b":[3,0,41,32], -"class_s_x127x.html#ada007b90821258fe8c6ca7f8ae3efed5":[3,0,41,20], -"class_s_x127x.html#ada53419d65f207f352124da7747c5960":[3,0,41,24], -"class_s_x127x.html#adc25b685de0859b799488bf7729350b6":[3,0,41,7], -"class_s_x127x.html#adc2f1379573b7a7b5ee8125ea3752083":[3,0,41,39], +"class_s_x127x.html#ad3955f85f456edae772a51025a19029b":[3,0,41,33], +"class_s_x127x.html#ada007b90821258fe8c6ca7f8ae3efed5":[3,0,41,21], +"class_s_x127x.html#ada53419d65f207f352124da7747c5960":[3,0,41,25], +"class_s_x127x.html#adc25b685de0859b799488bf7729350b6":[3,0,41,8], +"class_s_x127x.html#adc2f1379573b7a7b5ee8125ea3752083":[3,0,41,40], "class_s_x127x.html#add78edb65673d9e88931a55b0672a9f3":[3,0,41,2], -"class_s_x127x.html#adfe0d3f033a23ec2f3c2a407285d357c":[3,0,41,17], -"class_s_x127x.html#ae9781180418c1ec9c365b74acbc98d8a":[3,0,41,31], -"class_s_x127x.html#aefeeb9f7192e11a75b5dfb1ab8488e84":[3,0,41,41], -"class_s_x127x.html#af6aa854a2668d70f4d3a374a49440362":[3,0,41,8], -"class_s_x127x.html#afc844f7f3530f4076c8ea5f684c1b123":[3,0,41,25], +"class_s_x127x.html#adfe0d3f033a23ec2f3c2a407285d357c":[3,0,41,18], +"class_s_x127x.html#ae9781180418c1ec9c365b74acbc98d8a":[3,0,41,32], +"class_s_x127x.html#aee5324d7d854e7a2f6768221d4f362cd":[3,0,41,7], +"class_s_x127x.html#aefeeb9f7192e11a75b5dfb1ab8488e84":[3,0,41,42], +"class_s_x127x.html#af6aa854a2668d70f4d3a374a49440362":[3,0,41,9], +"class_s_x127x.html#afc844f7f3530f4076c8ea5f684c1b123":[3,0,41,26], "class_s_x127x.html#afe6e9bbfd75f9cad26f9f72c34c4ada5":[3,0,41,5], -"class_s_x127x.html#afe8456d0f9abbce4d743f256f3e1e6c6":[3,0,41,38], +"class_s_x127x.html#afe8456d0f9abbce4d743f256f3e1e6c6":[3,0,41,39], "class_s_x1280.html":[3,0,42], "class_s_x1280.html#a0356199b89860e15cda4979cd9dc13eb":[3,0,42,0], "class_s_x1280.html#a812e289084b2f78977b254c28f0fff7c":[3,0,42,2], @@ -151,30 +154,31 @@ var NAVTREEINDEX2 = "class_si4432.html#aa0cdb6cb53bb0176803d5115356a8e84":[3,0,26,2], "class_si4432.html#afb1f1ae46d04788aa42f6276efd231ac":[3,0,26,0], "class_si443x.html":[3,0,27], -"class_si443x.html#a10f886fc534a85bbf8c1aeb9b5ffe4f2":[3,0,27,21], -"class_si443x.html#a1382fc3b68f447e381613e6670747128":[3,0,27,12], -"class_si443x.html#a178b471527813a608c04db7d3c9648d6":[3,0,27,8], -"class_si443x.html#a2d944669dc69ccd47f9e6c360f2ffd10":[3,0,27,3], -"class_si443x.html#a402b4f5f11ba79e9cd4fb6ac0bfd9314":[3,0,27,22], +"class_si443x.html#a10f886fc534a85bbf8c1aeb9b5ffe4f2":[3,0,27,22], +"class_si443x.html#a1382fc3b68f447e381613e6670747128":[3,0,27,13], +"class_si443x.html#a178b471527813a608c04db7d3c9648d6":[3,0,27,9], +"class_si443x.html#a2d944669dc69ccd47f9e6c360f2ffd10":[3,0,27,4], +"class_si443x.html#a402b4f5f11ba79e9cd4fb6ac0bfd9314":[3,0,27,23], "class_si443x.html#a453eda5436dc4dfe0dad676dc3977752":[3,0,27,1], -"class_si443x.html#a4821a6141caf16141074615c976ecd91":[3,0,27,15], -"class_si443x.html#a4ed0da298c2418db4a88a19ef8938e0a":[3,0,27,18], -"class_si443x.html#a51e6b7c677e82042224798114f311175":[3,0,27,17], -"class_si443x.html#a5a86a2032c4b876c1c8e4a7cf4730c99":[3,0,27,24], -"class_si443x.html#a616eb24c4b11c5d39caaade160be8092":[3,0,27,4], -"class_si443x.html#a782748025e19ec6e597293afb6570bff":[3,0,27,23], -"class_si443x.html#a7c4e6caa95e5622f6f515ba0339a1c66":[3,0,27,13], -"class_si443x.html#a801b51059e61f93d4e01ae6ba8eb0726":[3,0,27,14], +"class_si443x.html#a4821a6141caf16141074615c976ecd91":[3,0,27,16], +"class_si443x.html#a4ed0da298c2418db4a88a19ef8938e0a":[3,0,27,19], +"class_si443x.html#a51e6b7c677e82042224798114f311175":[3,0,27,18], +"class_si443x.html#a55252bda74e8c67636a8c1fa0e9f58d3":[3,0,27,3], +"class_si443x.html#a5a86a2032c4b876c1c8e4a7cf4730c99":[3,0,27,25], +"class_si443x.html#a616eb24c4b11c5d39caaade160be8092":[3,0,27,5], +"class_si443x.html#a782748025e19ec6e597293afb6570bff":[3,0,27,24], +"class_si443x.html#a7c4e6caa95e5622f6f515ba0339a1c66":[3,0,27,14], +"class_si443x.html#a801b51059e61f93d4e01ae6ba8eb0726":[3,0,27,15], "class_si443x.html#a8d019f58551346c3f3bd8b72d2486109":[3,0,27,2], -"class_si443x.html#aabca3ba8eda212938febab1df2e764b4":[3,0,27,7], -"class_si443x.html#ac45d2776df3ff338db154ead143fb7b8":[3,0,27,20], -"class_si443x.html#ad00ff8b58c68118ad74fee82028aa71e":[3,0,27,6], -"class_si443x.html#ad371b44fc0c4ddd3ed39e2595e85b5df":[3,0,27,5], -"class_si443x.html#ad43575e731dd7e66d5ad9e6dccd27170":[3,0,27,10], -"class_si443x.html#ada90718aeb67d7f0e9899da534de9695":[3,0,27,19], -"class_si443x.html#ade08c79074c7e4414d34eefa25cee168":[3,0,27,11], -"class_si443x.html#ae365087803b88b29932b5c793edff1d4":[3,0,27,16], -"class_si443x.html#ae782ee06e2c463c24f22f5d4c3dd8d97":[3,0,27,9], +"class_si443x.html#aabca3ba8eda212938febab1df2e764b4":[3,0,27,8], +"class_si443x.html#ac45d2776df3ff338db154ead143fb7b8":[3,0,27,21], +"class_si443x.html#ad00ff8b58c68118ad74fee82028aa71e":[3,0,27,7], +"class_si443x.html#ad371b44fc0c4ddd3ed39e2595e85b5df":[3,0,27,6], +"class_si443x.html#ad43575e731dd7e66d5ad9e6dccd27170":[3,0,27,11], +"class_si443x.html#ada90718aeb67d7f0e9899da534de9695":[3,0,27,20], +"class_si443x.html#ade08c79074c7e4414d34eefa25cee168":[3,0,27,12], +"class_si443x.html#ae365087803b88b29932b5c793edff1d4":[3,0,27,17], +"class_si443x.html#ae782ee06e2c463c24f22f5d4c3dd8d97":[3,0,27,10], "class_si443x.html#ae7cfff2efebfa01c8a50a5cbbe8775b9":[3,0,27,0], "class_transport_layer.html":[3,0,47], "class_transport_layer.html#a1d9cb76640868aa0338b52808e4f022d":[3,0,47,4], @@ -245,9 +249,5 @@ var NAVTREEINDEX2 = "dir_6baa7f88a31cf8c1ad1b651eaa1fd5b9.html":[4,0,0,0,7], "dir_70c194bd40717a4946dbd8bc35f09b17.html":[4,0,0,1,0], "dir_747c20e84f9dfe1cc835713177129efc.html":[4,0,0,0,10], -"dir_79690749eba542503bb1a9a3dbb495e1.html":[4,0,0,1], -"dir_7b8feacc70eb38d5fd56f060c649a59c.html":[4,0,0,0,13], -"dir_8d5439df06ea2679013aa8390703d116.html":[4,0,0,0,4], -"dir_a6b6d785787649e9a3efd5036a39108c.html":[4,0,0,1,5], -"dir_a758e8e29d8436beff5e1f16d5ed2d65.html":[4,0,0,0,9] +"dir_79690749eba542503bb1a9a3dbb495e1.html":[4,0,0,1] }; diff --git a/navtreeindex3.js b/navtreeindex3.js index 23d20420..ed482682 100644 --- a/navtreeindex3.js +++ b/navtreeindex3.js @@ -1,5 +1,9 @@ var NAVTREEINDEX3 = { +"dir_7b8feacc70eb38d5fd56f060c649a59c.html":[4,0,0,0,13], +"dir_8d5439df06ea2679013aa8390703d116.html":[4,0,0,0,4], +"dir_a6b6d785787649e9a3efd5036a39108c.html":[4,0,0,1,5], +"dir_a758e8e29d8436beff5e1f16d5ed2d65.html":[4,0,0,0,9], "dir_c14921ab4918e015c91d11c846a1924a.html":[4,0,0,1,2], "dir_d916eb25599dc82f14db514c97a6ae6d.html":[4,0,0,1,4], "dir_ddb4d7e95cc2d6c8e1ade10a20d7247d.html":[4,0,0,0], @@ -9,8 +13,8 @@ var NAVTREEINDEX3 = "dir_ed12d23d857ca7061030f8751e72e77c.html":[4,0,0,0,12], "dir_f980efad9544c0545d0fa50a84ff12f2.html":[4,0,0,0,11], "files.html":[4,0], -"functions.html":[3,3,0], "functions.html":[3,3,0,0], +"functions.html":[3,3,0], "functions_0x7e.html":[3,3,0,23], "functions_b.html":[3,3,0,1], "functions_c.html":[3,3,0,2], @@ -158,8 +162,8 @@ var NAVTREEINDEX3 = "group__uart__config.html#gad418f0922126e27279d1a374fc63e036":[2,1,8], "group__uart__config.html#gae077d53c5c120a989b1f285f183f1b78":[2,1,3], "hierarchy.html":[3,2], -"index.html":[0], "index.html":[], +"index.html":[0], "modules.html":[2], "n_r_f24_8h_source.html":[4,0,0,0,4,0], "pages.html":[], diff --git a/search/all_6.js b/search/all_6.js index 7ee3df16..bb4f0160 100644 --- a/search/all_6.js +++ b/search/all_6.js @@ -1,6 +1,7 @@ var searchData= [ ['get',['get',['../class_h_t_t_p_client.html#abc505d06d29fdc774d27c163e0be7ff8',1,'HTTPClient::get(String &url, String &response)'],['../class_h_t_t_p_client.html#a7ae493bf7db12ca2201cd6cead54c64f',1,'HTTPClient::get(const char *url, String &response)']]], + ['getchipversion',['getChipVersion',['../class_c_c1101.html#a2a4c6e622dffd2788d8ac52d708b0705',1,'CC1101::getChipVersion()'],['../class_r_f69.html#a0c30202b2d52eb32f43066bc0f938638',1,'RF69::getChipVersion()'],['../class_si443x.html#a55252bda74e8c67636a8c1fa0e9f58d3',1,'Si443x::getChipVersion()'],['../class_s_x127x.html#aee5324d7d854e7a2f6768221d4f362cd',1,'SX127x::getChipVersion()']]], ['getcs',['getCs',['../class_module.html#ae53e355a77f2b7ce6473c62ac5f37334',1,'Module']]], ['getcurrentlimit',['getCurrentLimit',['../class_s_x126x.html#aa668babb0bd129b2facee9fd280525ab',1,'SX126x']]], ['getdatarate',['getDataRate',['../class_s_x126x.html#acbe2d75b1e2df8bcc58c4fd9d8e6e4f9',1,'SX126x::getDataRate()'],['../class_s_x127x.html#adc25b685de0859b799488bf7729350b6',1,'SX127x::getDataRate()']]], diff --git a/search/functions_6.js b/search/functions_6.js index 7ee3df16..bb4f0160 100644 --- a/search/functions_6.js +++ b/search/functions_6.js @@ -1,6 +1,7 @@ var searchData= [ ['get',['get',['../class_h_t_t_p_client.html#abc505d06d29fdc774d27c163e0be7ff8',1,'HTTPClient::get(String &url, String &response)'],['../class_h_t_t_p_client.html#a7ae493bf7db12ca2201cd6cead54c64f',1,'HTTPClient::get(const char *url, String &response)']]], + ['getchipversion',['getChipVersion',['../class_c_c1101.html#a2a4c6e622dffd2788d8ac52d708b0705',1,'CC1101::getChipVersion()'],['../class_r_f69.html#a0c30202b2d52eb32f43066bc0f938638',1,'RF69::getChipVersion()'],['../class_si443x.html#a55252bda74e8c67636a8c1fa0e9f58d3',1,'Si443x::getChipVersion()'],['../class_s_x127x.html#aee5324d7d854e7a2f6768221d4f362cd',1,'SX127x::getChipVersion()']]], ['getcs',['getCs',['../class_module.html#ae53e355a77f2b7ce6473c62ac5f37334',1,'Module']]], ['getcurrentlimit',['getCurrentLimit',['../class_s_x126x.html#aa668babb0bd129b2facee9fd280525ab',1,'SX126x']]], ['getdatarate',['getDataRate',['../class_s_x126x.html#acbe2d75b1e2df8bcc58c4fd9d8e6e4f9',1,'SX126x::getDataRate()'],['../class_s_x127x.html#adc25b685de0859b799488bf7729350b6',1,'SX127x::getDataRate()']]],