[SX128x] Added Module overrides for all Arduino core functions
This commit is contained in:
parent
6ff84d7b23
commit
2aeffd914f
2 changed files with 36 additions and 36 deletions
|
@ -11,10 +11,10 @@ int16_t SX1280::range(bool master, uint32_t addr) {
|
||||||
RADIOLIB_ASSERT(state);
|
RADIOLIB_ASSERT(state);
|
||||||
|
|
||||||
// wait until ranging is finished
|
// wait until ranging is finished
|
||||||
uint32_t start = millis();
|
uint32_t start = Module::millis();
|
||||||
while(!digitalRead(_mod->getIrq())) {
|
while(!Module::digitalRead(_mod->getIrq())) {
|
||||||
yield();
|
Module::yield();
|
||||||
if(millis() - start > 10000) {
|
if(Module::millis() - start > 10000) {
|
||||||
clearIrqStatus();
|
clearIrqStatus();
|
||||||
standby();
|
standby();
|
||||||
return(ERR_RANGING_TIMEOUT);
|
return(ERR_RANGING_TIMEOUT);
|
||||||
|
|
|
@ -228,7 +228,7 @@ int16_t SX128x::reset(bool verify) {
|
||||||
// run the reset sequence - same as SX126x, as SX128x docs don't seem to mention this
|
// run the reset sequence - same as SX126x, as SX128x docs don't seem to mention this
|
||||||
Module::pinMode(_mod->getRst(), OUTPUT);
|
Module::pinMode(_mod->getRst(), OUTPUT);
|
||||||
Module::digitalWrite(_mod->getRst(), LOW);
|
Module::digitalWrite(_mod->getRst(), LOW);
|
||||||
delay(1);
|
Module::delay(1);
|
||||||
Module::digitalWrite(_mod->getRst(), HIGH);
|
Module::digitalWrite(_mod->getRst(), HIGH);
|
||||||
|
|
||||||
// return immediately when verification is disabled
|
// return immediately when verification is disabled
|
||||||
|
@ -237,7 +237,7 @@ int16_t SX128x::reset(bool verify) {
|
||||||
}
|
}
|
||||||
|
|
||||||
// set mode to standby
|
// set mode to standby
|
||||||
uint32_t start = millis();
|
uint32_t start = Module::millis();
|
||||||
while(true) {
|
while(true) {
|
||||||
// try to set mode to standby
|
// try to set mode to standby
|
||||||
int16_t state = standby();
|
int16_t state = standby();
|
||||||
|
@ -247,13 +247,13 @@ int16_t SX128x::reset(bool verify) {
|
||||||
}
|
}
|
||||||
|
|
||||||
// standby command failed, check timeout and try again
|
// standby command failed, check timeout and try again
|
||||||
if(millis() - start >= 3000) {
|
if(Module::millis() - start >= 3000) {
|
||||||
// timed out, possibly incorrect wiring
|
// timed out, possibly incorrect wiring
|
||||||
return(state);
|
return(state);
|
||||||
}
|
}
|
||||||
|
|
||||||
// wait a bit to not spam the module
|
// wait a bit to not spam the module
|
||||||
delay(10);
|
Module::delay(10);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -285,10 +285,10 @@ int16_t SX128x::transmit(uint8_t* data, size_t len, uint8_t addr) {
|
||||||
RADIOLIB_ASSERT(state);
|
RADIOLIB_ASSERT(state);
|
||||||
|
|
||||||
// wait for packet transmission or timeout
|
// wait for packet transmission or timeout
|
||||||
uint32_t start = micros();
|
uint32_t start = Module::micros();
|
||||||
while(!digitalRead(_mod->getIrq())) {
|
while(!Module::digitalRead(_mod->getIrq())) {
|
||||||
yield();
|
Module::yield();
|
||||||
if(micros() - start > timeout) {
|
if(Module::micros() - start > timeout) {
|
||||||
clearIrqStatus();
|
clearIrqStatus();
|
||||||
standby();
|
standby();
|
||||||
return(ERR_TX_TIMEOUT);
|
return(ERR_TX_TIMEOUT);
|
||||||
|
@ -329,10 +329,10 @@ int16_t SX128x::receive(uint8_t* data, size_t len) {
|
||||||
RADIOLIB_ASSERT(state);
|
RADIOLIB_ASSERT(state);
|
||||||
|
|
||||||
// wait for packet reception or timeout
|
// wait for packet reception or timeout
|
||||||
uint32_t start = micros();
|
uint32_t start = Module::micros();
|
||||||
while(!digitalRead(_mod->getIrq())) {
|
while(!Module::digitalRead(_mod->getIrq())) {
|
||||||
yield();
|
Module::yield();
|
||||||
if(micros() - start > timeout) {
|
if(Module::micros() - start > timeout) {
|
||||||
clearIrqStatus();
|
clearIrqStatus();
|
||||||
standby();
|
standby();
|
||||||
return(ERR_RX_TIMEOUT);
|
return(ERR_RX_TIMEOUT);
|
||||||
|
@ -392,8 +392,8 @@ int16_t SX128x::scanChannel() {
|
||||||
RADIOLIB_ASSERT(state);
|
RADIOLIB_ASSERT(state);
|
||||||
|
|
||||||
// wait for channel activity detected or timeout
|
// wait for channel activity detected or timeout
|
||||||
while(!digitalRead(_mod->getIrq())) {
|
while(!Module::digitalRead(_mod->getIrq())) {
|
||||||
yield();
|
Module::yield();
|
||||||
}
|
}
|
||||||
|
|
||||||
// check CAD result
|
// check CAD result
|
||||||
|
@ -422,7 +422,7 @@ int16_t SX128x::sleep(bool retainConfig) {
|
||||||
int16_t state = SPIwriteCommand(SX128X_CMD_SET_SLEEP, &sleepConfig, 1, false);
|
int16_t state = SPIwriteCommand(SX128X_CMD_SET_SLEEP, &sleepConfig, 1, false);
|
||||||
|
|
||||||
// wait for SX128x to safely enter sleep mode
|
// wait for SX128x to safely enter sleep mode
|
||||||
delay(1);
|
Module::delay(1);
|
||||||
|
|
||||||
return(state);
|
return(state);
|
||||||
}
|
}
|
||||||
|
@ -440,11 +440,11 @@ int16_t SX128x::standby(uint8_t mode) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void SX128x::setDio1Action(void (*func)(void)) {
|
void SX128x::setDio1Action(void (*func)(void)) {
|
||||||
attachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()), func, RISING);
|
Module::attachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()), func, RISING);
|
||||||
}
|
}
|
||||||
|
|
||||||
void SX128x::clearDio1Action() {
|
void SX128x::clearDio1Action() {
|
||||||
detachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()));
|
Module::detachInterrupt(RADIOLIB_DIGITAL_PIN_TO_INTERRUPT(_mod->getIrq()));
|
||||||
}
|
}
|
||||||
|
|
||||||
int16_t SX128x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
|
int16_t SX128x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
|
||||||
|
@ -504,8 +504,8 @@ int16_t SX128x::startTransmit(uint8_t* data, size_t len, uint8_t addr) {
|
||||||
RADIOLIB_ASSERT(state);
|
RADIOLIB_ASSERT(state);
|
||||||
|
|
||||||
// wait for BUSY to go low (= PA ramp up done)
|
// wait for BUSY to go low (= PA ramp up done)
|
||||||
while(digitalRead(_mod->getGpio())) {
|
while(Module::digitalRead(_mod->getGpio())) {
|
||||||
yield();
|
Module::yield();
|
||||||
}
|
}
|
||||||
|
|
||||||
return(state);
|
return(state);
|
||||||
|
@ -1295,17 +1295,17 @@ int16_t SX128x::SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* d
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// ensure BUSY is low (state machine ready)
|
// ensure BUSY is low (state machine ready)
|
||||||
uint32_t start = millis();
|
uint32_t start = Module::millis();
|
||||||
while(digitalRead(_mod->getGpio())) {
|
while(Module::digitalRead(_mod->getGpio())) {
|
||||||
yield();
|
Module::yield();
|
||||||
if(millis() - start >= timeout) {
|
if(Module::millis() - start >= timeout) {
|
||||||
digitalWrite(_mod->getCs(), HIGH);
|
Module::digitalWrite(_mod->getCs(), HIGH);
|
||||||
return(ERR_SPI_CMD_TIMEOUT);
|
return(ERR_SPI_CMD_TIMEOUT);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// pull NSS low
|
// pull NSS low
|
||||||
digitalWrite(_mod->getCs(), LOW);
|
Module::digitalWrite(_mod->getCs(), LOW);
|
||||||
|
|
||||||
// start transfer
|
// start transfer
|
||||||
spi->beginTransaction(spiSettings);
|
spi->beginTransaction(spiSettings);
|
||||||
|
@ -1362,15 +1362,15 @@ int16_t SX128x::SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* d
|
||||||
|
|
||||||
// stop transfer
|
// stop transfer
|
||||||
spi->endTransaction();
|
spi->endTransaction();
|
||||||
digitalWrite(_mod->getCs(), HIGH);
|
Module::digitalWrite(_mod->getCs(), HIGH);
|
||||||
|
|
||||||
// wait for BUSY to go high and then low
|
// wait for BUSY to go high and then low
|
||||||
if(waitForBusy) {
|
if(waitForBusy) {
|
||||||
delayMicroseconds(1);
|
Module::delayMicroseconds(1);
|
||||||
start = millis();
|
start = Module::millis();
|
||||||
while(digitalRead(_mod->getGpio())) {
|
while(Module::digitalRead(_mod->getGpio())) {
|
||||||
yield();
|
Module::yield();
|
||||||
if(millis() - start >= timeout) {
|
if(Module::millis() - start >= timeout) {
|
||||||
status = SX128X_STATUS_CMD_TIMEOUT;
|
status = SX128X_STATUS_CMD_TIMEOUT;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -1420,7 +1420,7 @@ int16_t SX128x::SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* d
|
||||||
// not sure why, but it seems that long enough SPI transaction
|
// not sure why, but it seems that long enough SPI transaction
|
||||||
// (e.g. setPacketParams for GFSK) will fail without it
|
// (e.g. setPacketParams for GFSK) will fail without it
|
||||||
#if defined(ARDUINO_ARCH_STM32) || defined(SAMD_SERIES)
|
#if defined(ARDUINO_ARCH_STM32) || defined(SAMD_SERIES)
|
||||||
delay(1);
|
Module::delay(1);
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue