Add timeouts for both MARC state checks

This commit is contained in:
Crsarmv7l 2025-02-11 19:47:06 +01:00 committed by GitHub
parent eda1067a71
commit 19b85ee75e
No known key found for this signature in database
GPG key ID: B5690EEEBB952194

View file

@ -240,7 +240,13 @@ int16_t CC1101::startTransmit(const uint8_t* data, size_t len, uint8_t addr) {
SPIsendCommand(RADIOLIB_CC1101_CMD_FSTXON);
// Check MARCSTATE and wait until ready to tx
while(SPIgetRegValue(RADIOLIB_CC1101_REG_MARCSTATE, 4, 0) != 0x12) {};
RadioLibTime_T start = this->mod->hal->micros();
while(SPIgetRegValue(RADIOLIB_CC1101_REG_MARCSTATE, 4, 0) != 0x12) {
if(this->mod->hal->micros() - start > 724) {
standby();
return(RADIOLIB_ERR_TX_TIMEOUT);
}
}
// set GDO0 mapping
int16_t state = SPIsetRegValue(RADIOLIB_CC1101_REG_IOCFG2, RADIOLIB_CC1101_GDOX_SYNC_WORD_SENT_OR_PKT_RECEIVED, 5, 0);
@ -301,8 +307,14 @@ int16_t CC1101::finishTransmit() {
// set mode to standby to disable transmitter/RF switch
// Check MARCSTATE for Idle
while(SPIgetRegValue(RADIOLIB_CC1101_REG_MARCSTATE, 4, 0) != 0x01) {};
//TODO: Timeout
// Timeout is 2x FIFO transmit time
RadioLibTime_T timeout = (1.0f/(this->bitRate))*(RADIOLIB_CC1101_FIFO_SIZE*2.0f);
RadioLibTime_T start = this->mod->hal->millis();
while(SPIgetRegValue(RADIOLIB_CC1101_REG_MARCSTATE, 4, 0) != 0x01) {
if(this->mod->hal->millis() - start > timeout) {
return(RADIOLIB_ERR_TX_TIMEOUT);
}
}
int16_t state = standby();
RADIOLIB_ASSERT(state);