From 098e611eae99a59e07afd4e7bd7f41dbcf3e1d2a Mon Sep 17 00:00:00 2001 From: jgromes Date: Fri, 5 Feb 2021 20:02:54 +0100 Subject: [PATCH] Updated SparkFun Apollo3 core (SparkFun:apollo3:sfe_artemis) --- .github/workflows/main.yml | 2 +- examples/RTTY/RTTY_Transmit/RTTY_Transmit.ino | 1 + .../Si443x/Si443x_Receive/Si443x_Receive.ino | 2 +- .../Si443x_Receive_Interrupt.ino | 12 +- .../Si443x_Transmit/Si443x_Transmit.ino | 3 +- src/modules/AX5243/AX5243.cpp | 12 + src/modules/AX5243/AX5243.h | 263 ++++++++++++++++++ src/modules/Si443x/Si443x.cpp | 17 +- 8 files changed, 301 insertions(+), 11 deletions(-) create mode 100644 src/modules/AX5243/AX5243.cpp create mode 100644 src/modules/AX5243/AX5243.h diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 7ec52c01..445282cd 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -108,7 +108,7 @@ jobs: elif [[ "${{ contains(matrix.board, 'SparkFun:apollo3') }}" == "true" ]]; then # SparkFun Apollo - echo "::set-output name=index-url::--additional-urls https://raw.githubusercontent.com/sparkfun/Arduino_Boards/master/IDE_Board_Manager/package_sparkfun_index.json" + echo "::set-output name=index-url::--additional-urls https://raw.githubusercontent.com/sparkfun/Arduino_Apollo3/master/package_sparkfun_apollo3_index.json" echo "::set-output name=warnings::'none'" elif [[ "${{ contains(matrix.board, 'STM32:stm32') }}" == "true" ]]; then diff --git a/examples/RTTY/RTTY_Transmit/RTTY_Transmit.ino b/examples/RTTY/RTTY_Transmit/RTTY_Transmit.ino index 80c3c67f..32f0a18f 100644 --- a/examples/RTTY/RTTY_Transmit/RTTY_Transmit.ino +++ b/examples/RTTY/RTTY_Transmit/RTTY_Transmit.ino @@ -40,6 +40,7 @@ RTTYClient rtty(&radio); void setup() { Serial.begin(9600); + while(!Serial); // initialize SX1278 with default settings Serial.print(F("[SX1278] Initializing ... ")); diff --git a/examples/Si443x/Si443x_Receive/Si443x_Receive.ino b/examples/Si443x/Si443x_Receive/Si443x_Receive.ino index 846e46e3..5265ffff 100644 --- a/examples/Si443x/Si443x_Receive/Si443x_Receive.ino +++ b/examples/Si443x/Si443x_Receive/Si443x_Receive.ino @@ -25,7 +25,7 @@ // nSEL pin: 10 // nIRQ pin: 2 // SDN pin: 9 -Si4432 radio = new Module(10, 2, 9); +Si4432 radio = new Module(D8, D2, D0); // or using RadioShield // https://github.com/jgromes/RadioShield diff --git a/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino b/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino index e890b08d..dc5fb89c 100644 --- a/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino +++ b/examples/Si443x/Si443x_Receive_Interrupt/Si443x_Receive_Interrupt.ino @@ -21,14 +21,14 @@ // nSEL pin: 10 // nIRQ pin: 2 // SDN pin: 9 -Si4432 radio = new Module(10, 2, 9); +Si4432 radio = new Module(D8, D2, D0); // or using RadioShield // https://github.com/jgromes/RadioShield //Si4432 radio = RadioShield.ModuleA; void setup() { - Serial.begin(9600); + Serial.begin(115200); // initialize Si4432 with default settings Serial.print(F("[Si4432] Initializing ... ")); @@ -76,7 +76,7 @@ volatile bool enableInterrupt = true; // is received by the module // IMPORTANT: this function MUST be 'void' type // and MUST NOT have any arguments! -void setFlag(void) { +IRAM_ATTR void setFlag(void) { // check if the interrupt is enabled if(!enableInterrupt) { return; @@ -87,6 +87,12 @@ void setFlag(void) { } void loop() { + Serial.print(radio._mod->SPIreadRegister(SI443X_REG_DEVICE_STATUS), HEX); + Serial.print('\t'); + Serial.print(radio._mod->SPIreadRegister(SI443X_REG_INTERRUPT_STATUS_1), HEX); + Serial.print('\t'); + Serial.println(radio._mod->SPIreadRegister(SI443X_REG_INTERRUPT_STATUS_2), HEX); + // check if the flag is set if(receivedFlag) { // disable the interrupt service routine while diff --git a/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino b/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino index ca267624..4aec648d 100644 --- a/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino +++ b/examples/Si443x/Si443x_Transmit/Si443x_Transmit.ino @@ -23,7 +23,8 @@ // nSEL pin: 10 // nIRQ pin: 2 // SDN pin: 9 -Si4432 radio = new Module(10, 2, 9); +//Si4432 radio = new Module(5, 26, 25); +Si4432 radio = new Module(D8, D2, D0); // or using RadioShield // https://github.com/jgromes/RadioShield diff --git a/src/modules/AX5243/AX5243.cpp b/src/modules/AX5243/AX5243.cpp new file mode 100644 index 00000000..cbafa5ef --- /dev/null +++ b/src/modules/AX5243/AX5243.cpp @@ -0,0 +1,12 @@ +#include "AX5243.h" +#if !defined(RADIOLIB_EXCLUDE_AX5243) + +AX5243::AX5243(Module* module) : PhysicalLayer(AX5243_FREQUENCY_STEP_SIZE, AX5243_MAX_PACKET_LENGTH) { + _mod = module; +} + +int16_t AX5243::begin() { + return(ERR_NONE); +} + +#endif diff --git a/src/modules/AX5243/AX5243.h b/src/modules/AX5243/AX5243.h new file mode 100644 index 00000000..985d4108 --- /dev/null +++ b/src/modules/AX5243/AX5243.h @@ -0,0 +1,263 @@ +#if !defined(_RADIOLIB_AX5243_H) && !defined(RADIOLIB_EXCLUDE_AX5243) +#define _RADIOLIB_AX5243_H + +#include "../../TypeDef.h" +#include "../../Module.h" + +#include "../../protocols/PhysicalLayer/PhysicalLayer.h" + +// AX5243 physical layer properties +#define AX5243_FREQUENCY_STEP_SIZE (0.98) +#define AX5243_MAX_PACKET_LENGTH (256) + +// AX5243 register map +#define AX5243_REG_REVISION (0x0000) +#define AX5243_REG_SCRATCH (0x0001) +#define AX5243_REG_PWR_MODE (0x0002) +#define AX5243_REG_POW_STAT (0x0003) +#define AX5243_REG_POW_STICKY_STAT (0x0004) +#define AX5243_REG_POW_IRQ_MASK (0x0005) +#define AX5243_REG_IRQ_MASK_1 (0x0006) +#define AX5243_REG_IRQ_MASK_0 (0x0007) +#define AX5243_REG_RADIO_EVENTS_MASK_1 (0x0008) +#define AX5243_REG_RADIO_EVENTS_MASK_0 (0x0009) +#define AX5243_REG_IRQ_INVERSION_1 (0x000A) +#define AX5243_REG_IRQ_INVERSION_0 (0x000B) +#define AX5243_REG_IRQ_REQUEST_1 (0x000C) +#define AX5243_REG_IRQ_REQUEST_0 (0x000D) +#define AX5243_REG_RADIO_EVENT_REQ_1 (0x000E) +#define AX5243_REG_RADIO_EVENT_REQ_0 (0x000F) +#define AX5243_REG_MODULATION (0x0010) +#define AX5243_REG_ENCODING (0x0011) +#define AX5243_REG_FRAMING (0x0012) +#define AX5243_REG_CRC_INIT_3 (0x0014) +#define AX5243_REG_CRC_INIT_2 (0x0015) +#define AX5243_REG_CRC_INIT_1 (0x0016) +#define AX5243_REG_CRC_INIT_0 (0x0017) +#define AX5243_REG_FEC (0x0018) +#define AX5243_REG_FEC_SYNC (0x0019) +#define AX5243_REG_FEC_STATUS (0x001A) +#define AX5243_REG_RADIO_STATE (0x001C) +#define AX5243_REG_XTAL_STATUS (0x001D) +#define AX5243_REG_PIN_STATE (0x0020) +#define AX5243_REG_PIN_FUNC_SYSCLK (0x0021) +#define AX5243_REG_PIN_FUNC_DCLK (0x0022) +#define AX5243_REG_PIN_FUNC_DATA (0x0023) +#define AX5243_REG_PIN_FUNC_IRQ (0x0024) +#define AX5243_REG_PIN_FUNC_ANTSEL (0x0025) +#define AX5243_REG_PIN_FUNC_PWRAMP (0x0026) +#define AX5243_REG_PWRAMP (0x0027) +#define AX5243_REG_FIFO_STAT (0x0028) +#define AX5243_REG_FIFO_DATA (0x0029) +#define AX5243_REG_FIFO_COUNT_1 (0x002A) +#define AX5243_REG_FIFO_COUNT_0 (0x002B) +#define AX5243_REG_FIFO_FREE_1 (0x002C) +#define AX5243_REG_FIFO_FREE_0 (0x002D) +#define AX5243_REG_FIFO_THRESH_1 (0x002E) +#define AX5243_REG_FIFO_THRESH_0 (0x002F) +#define AX5243_REG_PLL_LOOP (0x0030) +#define AX5243_REG_PLL_CPI (0x0031) +#define AX5243_REG_PLL_VCO_DIV (0x0032) +#define AX5243_REG_PLL_RANGING_A (0x0033) +#define AX5243_REG_FREQ_A_3 (0x0034) +#define AX5243_REG_FREQ_A_2 (0x0035) +#define AX5243_REG_FREQ_A_1 (0x0036) +#define AX5243_REG_FREQ_A_0 (0x0037) +#define AX5243_REG_PLL_LOOP_BOOST (0x0038) +#define AX5243_REG_PLL_CPI_BOOST (0x0039) +#define AX5243_REG_PLL_RANGING_B (0x003B) +#define AX5243_REG_FREQ_B_3 (0x003C) +#define AX5243_REG_FREQ_B_2 (0x003D) +#define AX5243_REG_FREQ_B_1 (0x003E) +#define AX5243_REG_FREQ_B_0 (0x003F) +#define AX5243_REG_RSSI (0x0040) +#define AX5243_REG_BGND_RSSI (0x0041) +#define AX5243_REG_DIVERSITY (0x0042) +#define AX5243_REG_AGC_COUNTER (0x0043) +#define AX5243_REG_TRK_DATARATE_2 (0x0045) +#define AX5243_REG_TRK_DATARATE_1 (0x0046) +#define AX5243_REG_TRK_DATARATE_0 (0x0047) +#define AX5243_REG_TRK_AMPL_1 (0x0048) +#define AX5243_REG_TRK_AMPL_0 (0x0049) +#define AX5243_REG_TRK_PHASE_1 (0x004A) +#define AX5243_REG_TRK_PHASE_0 (0x004B) +#define AX5243_REG_TRK_RF_FREQ_2 (0x004D) +#define AX5243_REG_TRK_RF_FREQ_1 (0x004E) +#define AX5243_REG_TRK_RF_FREQ_0 (0x004F) +#define AX5243_REG_TRK_FREQ_2 (0x0050) +#define AX5243_REG_TRK_FREQ_1 (0x0051) +#define AX5243_REG_TRK_FSK_DEMOD_1 (0x0052) +#define AX5243_REG_TRK_FSK_DEMOD_0 (0x0053) +#define AX5243_REG_TIMER_2 (0x0059) +#define AX5243_REG_TIMER_1 (0x005A) +#define AX5243_REG_TIMER_0 (0x005B) +#define AX5243_REG_WAKEUP_TIMER_1 (0x0068) +#define AX5243_REG_WAKEUP_TIMER_0 (0x0069) +#define AX5243_REG_WAKEUP_1 (0x006A) +#define AX5243_REG_WAKEUP_0 (0x006B) +#define AX5243_REG_WAKEUP_FREQ_1 (0x006C) +#define AX5243_REG_WAKEUP_FREQ_0 (0x006D) +#define AX5243_REG_WAKEUP_XO_EARLY (0x006E) +#define AX5243_REG_IF_FREQ_1 (0x0100) +#define AX5243_REG_IF_FREQ_0 (0x0101) +#define AX5243_REG_DECIMATION (0x0102) +#define AX5243_REG_RX_DATA_RATE_2 (0x0103) +#define AX5243_REG_RX_DATA_RATE_1 (0x0104) +#define AX5243_REG_RX_DATA_RATE_0 (0x0105) +#define AX5243_REG_MAX_DR_OFFSET_2 (0x0106) +#define AX5243_REG_MAX_DR_OFFSET_1 (0x0107) +#define AX5243_REG_MAX_DR_OFFSET_0 (0x0108) +#define AX5243_REG_MAX_RF_OFFSET_2 (0x0109) +#define AX5243_REG_MAX_RF_OFFSET_1 (0x010A) +#define AX5243_REG_MAX_RF_OFFSET_0 (0x010B) +#define AX5243_REG_FSK_DMAX_1 (0x010C) +#define AX5243_REG_FSK_DMAX_0 (0x010D) +#define AX5243_REG_FSK_DMIN_1 (0x010E) +#define AX5243_REG_FSK_DMIN_0 (0x010F) +#define AX5243_REG_AFSK_SPACE_1 (0x0110) +#define AX5243_REG_AFSK_SPACE_0 (0x0111) +#define AX5243_REG_AFSK_MARK_1 (0x0112) +#define AX5243_REG_AFSK_MARK_0 (0x0113) +#define AX5243_REG_AFSK_CTRL (0x0114) +#define AX5243_REG_AMPL_FILTER (0x0115) +#define AX5243_REG_FREQUENCY_LEAK (0x0116) +#define AX5243_REG_RX_PARAM_SETS (0x0117) +#define AX5243_REG_RX_PARAM_CUR_SET (0x0118) +#define AX5243_REG_RX_PARAM_SET_0 (0x0120) +#define AX5243_REG_RX_PARAM_SET_1 (0x0130) +#define AX5243_REG_RX_PARAM_SET_2 (0x0140) +#define AX5243_REG_RX_PARAM_SET_3 (0x0150) +#define AX5243_REG_RXPAR_AGC_GAIN (0x0000) +#define AX5243_REG_RXPAR_AGC_TARGET (0x0001) +#define AX5243_REG_RXPAR_AGC_HYST (0x0002) +#define AX5243_REG_RXPAR_AGC_MIN_MAX (0x0003) +#define AX5243_REG_RXPAR_TIME_GAIN (0x0004) +#define AX5243_REG_RXPAR_DR_GAIN (0x0005) +#define AX5243_REG_RXPAR_PHASE_GAIN (0x0006) +#define AX5243_REG_RXPAR_FREQ_GAIN_A (0x0007) +#define AX5243_REG_RXPAR_FREQ_GAIN_B (0x0008) +#define AX5243_REG_RXPAR_FREQ_GAIN_C (0x0009) +#define AX5243_REG_RXPAR_FREQ_GAIN_D (0x000A) +#define AX5243_REG_RXPAR_AMPL_GAIN (0x000B) +#define AX5243_REG_RXPAR_FREQ_DEV_1 (0x000C) +#define AX5243_REG_RXPAR_FREQ_DEV_0 (0x000D) +#define AX5243_REG_RXPAR_FOUR_FSK (0x000E) +#define AX5243_REG_RXPAR_BB_OFFS_RES (0x000F) +#define AX5243_REG_MOD_CFG_F (0x0160) +#define AX5243_REG_FSK_DEV_2 (0x0161) +#define AX5243_REG_FSK_DEV_1 (0x0162) +#define AX5243_REG_FSK_DEV_0 (0x0163) +#define AX5243_REG_MOD_CFG_A (0x0164) +#define AX5243_REG_TX_RATE_2 (0x0165) +#define AX5243_REG_TX_RATE_1 (0x0166) +#define AX5243_REG_TX_RATE_0 (0x0167) +#define AX5243_REG_TX_PWR_COEFF_A_1 (0x0168) +#define AX5243_REG_TX_PWR_COEFF_A_0 (0x0169) +#define AX5243_REG_TX_PWR_COEFF_B_1 (0x016A) +#define AX5243_REG_TX_PWR_COEFF_B_0 (0x016B) +#define AX5243_REG_TX_PWR_COEFF_C_1 (0x016C) +#define AX5243_REG_TX_PWR_COEFF_C_0 (0x016D) +#define AX5243_REG_TX_PWR_COEFF_D_1 (0x016E) +#define AX5243_REG_TX_PWR_COEFF_D_0 (0x016F) +#define AX5243_REG_TX_PWR_COEFF_E_1 (0x0170) +#define AX5243_REG_TX_PWR_COEFF_E_0 (0x0171) +#define AX5243_REG_PLL_VCO_I (0x0180) +#define AX5243_REG_PLL_VCO_IR (0x0181) +#define AX5243_REG_PLL_LOCK_DET (0x0182) +#define AX5243_REG_PLL_RNG_CLK (0x0183) +#define AX5243_REG_XTAL_CAP (0x0184) +#define AX5243_REG_BB_TUNE (0x0188) +#define AX5243_REG_BB_OFFS_CAP (0x0189) +#define AX5243_REG_PKT_ADDR_CFG (0x0200) +#define AX5243_REG_PKT_LEN_CFG (0x0201) +#define AX5243_REG_PKT_LEN_OFFSET (0x0202) +#define AX5243_REG_PKT_MAX_LEN (0x0203) +#define AX5243_REG_PKT_ADDR_3 (0x0204) +#define AX5243_REG_PKT_ADDR_2 (0x0205) +#define AX5243_REG_PKT_ADDR_1 (0x0206) +#define AX5243_REG_PKT_ADDR_0 (0x0207) +#define AX5243_REG_PKT_ADDR_MASK_3 (0x0208) +#define AX5243_REG_PKT_ADDR_MASK_2 (0x0209) +#define AX5243_REG_PKT_ADDR_MASK_1 (0x020A) +#define AX5243_REG_PKT_ADDR_MASK_0 (0x020B) +#define AX5243_REG_MATCH_0_PAT_3 (0x0210) +#define AX5243_REG_MATCH_0_PAT_2 (0x0211) +#define AX5243_REG_MATCH_0_PAT_1 (0x0212) +#define AX5243_REG_MATCH_0_PAT_0 (0x0213) +#define AX5243_REG_MATCH_0_LEN (0x0214) +#define AX5243_REG_MATCH_0_MIN (0x0215) +#define AX5243_REG_MATCH_0_MAX (0x0216) +#define AX5243_REG_MATCH_1_PAT_1 (0x0218) +#define AX5243_REG_MATCH_1_PAT_0 (0x0219) +#define AX5243_REG_MATCH_1_LEN (0x021C) +#define AX5243_REG_MATCH_1_MIN (0x021D) +#define AX5243_REG_MATCH_1_MAX (0x021E) +#define AX5243_REG_TMG_TX_BOOST (0x0220) +#define AX5243_REG_TMG_TX_SETTLE (0x0221) +#define AX5243_REG_TMG_RX_BOOST (0x0223) +#define AX5243_REG_TMG_RX_SETTLE (0x0224) +#define AX5243_REG_TMG_RX_OFFS_ACQ (0x0225) +#define AX5243_REG_TMG_RX_COARSE_ACQ (0x0226) +#define AX5243_REG_TMG_RX_AGC (0x0227) +#define AX5243_REG_TMG_RX_RSSI (0x0228) +#define AX5243_REG_TMG_RX_PREAMBLE_1 (0x0229) +#define AX5243_REG_TMG_RX_PREAMBLE_2 (0x022A) +#define AX5243_REG_TMG_RX_PREAMBLE_3 (0x022B) +#define AX5243_REG_RSSI_REFERENCE (0x022C) +#define AX5243_REG_RSSI_ABS_THR (0x022D) +#define AX5243_REG_BGND_RSSI_GAIN (0x022E) +#define AX5243_REG_BGND_RSSI_THR (0x022F) +#define AX5243_REG_PKT_CHUNK_SIZE (0x0230) +#define AX5243_REG_PKT_MISC_FLAGS (0x0231) +#define AX5243_REG_PKT_STORE_FLAGS (0x0232) +#define AX5243_REG_PKT_ACCEPT_FLAGS (0x0233) +#define AX5243_REG_GP_ADC_CTRL (0x0300) +#define AX5243_REG_GP_ADC_PERIOD (0x0301) +#define AX5243_REG_GP_ADC_13_VALUE_1 (0x0308) +#define AX5243_REG_GP_ADC_13_VALUE_0 (0x0309) +#define AX5243_REG_LP_OSC_CONFIG (0x0310) +#define AX5243_REG_LP_OSC_STATUS (0x0311) +#define AX5243_REG_LP_OSC_FILTER_1 (0x0312) +#define AX5243_REG_LP_OSC_FILTER_0 (0x0313) +#define AX5243_REG_LP_OSC_REF_1 (0x0314) +#define AX5243_REG_LP_OSC_REF_0 (0x0315) +#define AX5243_REG_LP_OSC_FREQ_1 (0x0316) +#define AX5243_REG_LP_OSC_FREQ_0 (0x0317) +#define AX5243_REG_LP_OSC_PER_1 (0x0318) +#define AX5243_REG_LP_OSC_PER_0 (0x0319) +#define AX5243_REG_DAC_VALUE_1 (0x0330) +#define AX5243_REG_DAC_VALUE_0 (0x0331) +#define AX5243_REG_DAC_CONFIG (0x0332) + +/*! + \class AX5243 + + \brief Control class for %AX5243 module. +*/ +class AX5243: public PhysicalLayer { + public: + // introduce PhysicalLayer overloads + using PhysicalLayer::transmit; + using PhysicalLayer::receive; + using PhysicalLayer::startTransmit; + using PhysicalLayer::readData; + + /*! + \brief Default constructor. + + \param mod Instance of Module that will be used to communicate with the radio. + */ + AX5243(Module* module); + + // basic methods + + int16_t begin(); + +#ifndef RADIOLIB_GODMODE + private: +#endif + Module* _mod; + +}; + +#endif diff --git a/src/modules/Si443x/Si443x.cpp b/src/modules/Si443x/Si443x.cpp index fe1d15a6..a7eda1e3 100644 --- a/src/modules/Si443x/Si443x.cpp +++ b/src/modules/Si443x/Si443x.cpp @@ -267,11 +267,14 @@ int16_t Si443x::startReceive() { _mod->setRfSwitchState(HIGH, LOW); // set interrupt mapping - _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_1, SI443X_PACKET_SENT_ENABLED); + //_mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_1, SI443X_PACKET_SENT_ENABLED); + //_mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); + _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_1, SI443X_VALID_PACKET_RECEIVED_ENABLED | SI443X_CRC_ERROR_ENABLED); _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); // set mode to receive _mod->SPIwriteRegister(SI443X_REG_OP_FUNC_CONTROL_1, SI443X_RX_ON | SI443X_XTAL_ON); + _mod->SPIwriteRegister(SI443X_REG_INTERRUPT_ENABLE_2, 0x00); return(state); } @@ -572,10 +575,6 @@ uint8_t Si443x::random() { return(randByte); } -int16_t Si443x::getChipVersion() { - return(_mod->SPIgetRegValue(SI443X_REG_DEVICE_VERSION)); -} - int16_t Si443x::setFrequencyRaw(float newFreq) { // set mode to standby int16_t state = standby(); @@ -597,6 +596,7 @@ int16_t Si443x::setFrequencyRaw(float newFreq) { state = _mod->SPIsetRegValue(SI443X_REG_FREQUENCY_BAND_SELECT, bandSelect | freqBand, 5, 0); state |= _mod->SPIsetRegValue(SI443X_REG_NOM_CARRIER_FREQUENCY_1, (uint8_t)((freqCarrier & 0xFF00) >> 8)); state |= _mod->SPIsetRegValue(SI443X_REG_NOM_CARRIER_FREQUENCY_0, (uint8_t)(freqCarrier & 0xFF)); + //state |= _mod->SPIsetRegValue(SI443X_REG_AFC_LIMITER, 80); return(state); } @@ -647,10 +647,17 @@ int16_t Si443x::config() { // disable packet header state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_2, SI443X_SYNC_WORD_TIMEOUT_ON | SI443X_HEADER_LENGTH_HEADER_NONE, 7, 4); + //state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_2, SI443X_HEADER_LENGTH_HEADER_3210 | SI443X_FIXED_PACKET_LENGTH_OFF | SI443X_SYNC_LENGTH_SYNC_32, 6, 1); RADIOLIB_ASSERT(state); // disable packet header checking state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_1, SI443X_BROADCAST_ADDR_CHECK_NONE | SI443X_RECEIVED_HEADER_CHECK_NONE); + //state = _mod->SPIsetRegValue(SI443X_REG_HEADER_CONTROL_1, SI443X_BROADCAST_ADDR_CHECK_BYTE3 | SI443X_RECEIVED_HEADER_CHECK_BYTE3); + RADIOLIB_ASSERT(state); + + state = _mod->SPIsetRegValue(SI443X_REG_GPIO0_CONFIG, 0x12); + RADIOLIB_ASSERT(state); + state = _mod->SPIsetRegValue(SI443X_REG_GPIO1_CONFIG, 0x15); RADIOLIB_ASSERT(state); return(state);